Microelectronic FET device comprising large contact surfaces between the conduction channel and the source and drain regions

Abstract

A microelectronic FET device (100) comprising: - a semiconductor layer (120) of which a first region (122) forms a channel; - a gate (110) and a gate dielectric layer (112) or a ferroelectric memory layer, disposed against the first region; - dielectric spacers (114) disposed against flanks of the gate; - source (116) / drain (118) regions electrically coupled to the first region by second regions (124) of the active layer extending between the source / drain regions and the dielectric spacers; wherein the second regions form, with the first region, a continuous layer, and the first region forms a semiconductor portion such that the gate covers several distinct faces of the semiconductor portion. Figure for the abbreviation: Figure 7.

Description

Title of the invention: FET microelectronic device comprising large contact surfaces between the conduction channel and the source and drain regions technical field

[0001] The invention relates to the field of microelectronic devices applied to advanced CMOS technologies. The invention relates in particular to microelectronic devices of the FET type (“Field-Effect Transistor”), in particular of the FinFET type (“Fin Field-Effect Transistor”) or FeFET type (“Ferroelectric Field Effect Transistor”), in particular based on two-dimensional materials, or 2D materials, or semiconductor oxides, as well as the realization of such microelectronic devices. Prior art

[0002] The miniaturization of electronics is constantly increasing, but the industry is now approaching the scale limit for conventional materials such as silicon. Recently, 2D materials have emerged as promising candidates for use in miniaturized electronic and optoelectronic devices due to their unique properties and the very thin layers of these materials, which can consist of a single layer of atoms or molecules.

[0003] The document by KP O'Brien et al., "Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering," 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 7.1.1-7.1.4, proposes to fabricate a MOSFET transistor by integrating a MoS2 layer to form the conduction channel. This layer is connected to two metallic source and drain regions based on gold, palladium, TiN, tungsten, or nickel. The back gate is formed by a doped silicon layer positioned on the back side under a dielectric layer based on SiO2, HfO2, or Al2O3.

[0004] In order to overcome the constraints related to the deposition of metallic materials in the source and drain regions on the 2D material, it is possible to form these regions not on the upper face of the 2D material layer, but against the sides of the 2D material layer. This configuration, called "side contact", is however problematic because the contact surface between the 2D material layer and the regions of source and drain is low, which generates significant contact resistances at the interfaces between the 2D material layer and the source and drain regions.

[0005] US patent 2022 / 045176 A1 describes several methods for manufacturing gate-last FET transistors, in which portions of silicon serve as a support for the deposition of a 2D material layer. Besides the disadvantages related to the fact that the transistors produced have side-contact channel / source-drain interfaces, the silicon portions used to deposit the 2D material form a potential barrier at the interface with the 2D material, which is unfavorable because some of the charge transport may occur in these silicon portions and not in the 2D material. Description of the invention

[0006] An object of the present invention is to propose a FET type microelectronic device whose structure is compatible with any type of semiconductor material including 2D materials or other materials of the semiconductor oxide type, and not presenting the disadvantages of a "side contact" configuration.

[0007] To this end, the present invention proposes a FET microelectronic device comprising at least: - a substrate; - a semiconductor layer comprising at least a first zone forming a fin-shaped semiconductor portion and serving as an electrical conduction channel for the FET microelectronic device; - an electrostatic control grid; - a grid dielectric layer or a ferroelectric memory layer, disposed between the electrostatic control grid and the first zone of the semiconductor layer, covering several distinct faces of the first zone of the semiconductor layer; - dielectric spacers arranged against the sides of the electrostatic control grid; - fin-shaped source / drain regions, electrically coupled to the first zone of the semiconductor layer by second zones of the semiconductor layer, the second zones of the semiconductor layer extending between the source / drain regions and the dielectric spacers; and in which the second zones of the semiconductor layer are not arranged directly against the electrostatic control grid and form, with the first zone, a continuous layer.

[0008] The proposed microelectronic device is based on a FET-type architecture without a "side contact" type interface between the channel and the regions of Source / drain coupling is achieved through secondary zones of the semiconductor layer, which provide electrical coupling between the channel formed by the primary zone and the source / drain regions. These secondary zones, extending against at least part of the lateral walls of the source / drain regions, create a large contact area, thus reducing the contact resistance of the source / drain regions. Consequently, the electrical current flowing through the channel is not reduced by these contact resistances, and therefore the device's performance is not diminished.

[0009] Furthermore, with the proposed architecture, the semiconductor layer can be fabricated just before the fabrication of the source / drain regions or just before the metal deposition of the source / drain regions. Thus, the semiconductor layer, the first zone of which is intended to form the conduction channel, is not damaged by the steps involved in fabricating the source / drain regions. This is particularly advantageous when the semiconductor layer is made of a 2D material.

[0010] Furthermore, the realization of such a device does not require the preservation of portions of silicon to deposit the semiconductor layer intended to form the channel, thus eliminating the potential barrier problem at the interface with the semiconductor layer material.

[0011] When the device includes the gate dielectric layer, the device can be classified as a FinFET-type transistor. When the device includes the ferroelectric memory layer, the device can be classified as a FeFET-type memory device.

[0012] The semiconductor layer may comprise a two-dimensional material or any other semiconductor material deposited, for example, by MOCVD (Metal-Organic Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). In this case, the microelectronic device can be made with very small dimensions. The semiconductor layer may, in particular, comprise at least one 2D material and / or a semiconductor oxide material.

[0013] The electrostatic control grid and the grid dielectric layer, or the electrostatic control grid and the ferroelectric memory layer, can together cover several distinct faces of the semiconductor portion.

[0014] Advantageously, the FET microelectronic device can be such that: - each of the source / drain regions is disposed in a cavity comprising side walls formed at least by dielectric spacers and by an insulating dielectric material; - the second zones of the semiconductor layer cover at least one part, and preferably all, of the walls of the cavities in which the source / drain regions are arranged.

[0015] In the above configuration, the contact surfaces of the source / drain regions with the semiconductor layer are maximized by using the surface of the cavity walls, and advantageously the entire surface of the cavity walls, to form the contact between the second zones of the semiconductor layer and the source / drain regions, which allows for very low contact resistances of the source / drain regions, and therefore a higher current flowing through the conduction channel of the device.

[0016] The FET microelectronic device may further comprise at least one dielectric portion surrounded by the first zone of the semiconductor layer.

[0017] Alternatively, the first zone of the semiconductor layer may not surround a dielectric portion.

[0018] The semiconductor layer may comprise several first zones forming several distinct fin-shaped semiconductor portions, arranged on the substrate and such that the gate dielectric layer or the ferroelectric memory layer is disposed between the electrostatic control gate and each of the first zones of the semiconductor layer by covering together several distinct faces of each of the first zones of the semiconductor layer.

[0019] Advantageously, the invention can be applied to the realization of CMOS components for 5 nm and sub-5nm technology nodes.

[0020] The invention also relates to a method for making a FET microelectronic device, comprising at least: a) fabrication of at least one portion of temporary material on a substrate, then b) fabrication, at least on the portion of temporary material, of at least one electrostatic control grid and dielectric spacers arranged against flanks of the electrostatic control grid, the electrostatic control grid covering several distinct faces of the portion of temporary material, then c) engraving of the portion of temporary material, then (d) fabrication of a semiconductor layer comprising a two-dimensional material or any other semiconductor material deposited by MOCVD, CVD or ALD, the semiconductor layer comprising at least a first zone forming a fin-shaped semiconductor portion disposed on the substrate and configured to serve as an electrical conduction channel for the FET microelectronic device, disposed under the electrostatic control grid and the dielectric spacers in at least one location formed by etching the temporary material portion, and such that the semiconductor layer extends, without discontinuity with the first zone, to form second zones covering at least a portion of the flanks of the dielectric spacers and which are not arranged directly against the electrostatic control grid, then e) realization, on the substrate, of fin-shaped source / drain regions, electrically coupled to the first zone of the semiconductor layer by the second zones of the semiconductor layer, and such that the second zones of the semiconductor layer extend between the source / drain regions and the dielectric spacers.

[0021] The method may further comprise, before the implementation of step c), a deposition of an insulating dielectric material around the dielectric spacers, and then an etching of cavities in the insulating dielectric material such that the cavities comprise at least one side wall formed by one of the dielectric spacers, and wherein: - step d) is implemented such that the second zones of the semiconductor layer cover at least part of the lateral walls of the cavities; - step e) is implemented such that each of the source / drain regions is disposed in one of the cavities.

[0022] In an advantageous configuration: - step a) may involve the creation of several temporary portions of material on the substrate, and - step b) can be implemented such that the electrostatic control grid covers several distinct faces of each of the temporary material portions, and - step c) involves engraving all portions of temporary material, and - step d) can be implemented such that several first zones of the semiconductor layer are arranged in locations formed by etching temporary portions of material, the first zones of the semiconductor layer forming several semiconductor portions arranged on the substrate and such that the electrostatic control grid covers several distinct faces of each of the first zones of the semiconductor layer.

[0023] The process may further include a step of depositing a grid dielectric layer or a ferroelectric memory layer implemented: - between steps a) and b), on the portion of temporary material, the electrostatic control grid is then made on the grid dielectric layer or the ferroelectric memory layer, and / or - between steps c) and d), under the electrostatic control grid and the dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer being then made by covering the grid dielectric layer or the ferroelectric memory layer.

[0024] The invention also relates to a method for making a microelec- device FET electronics, including at least: a) fabrication of at least one portion of temporary material on a substrate, then b) fabrication, at least on the portion of temporary material, of at least one temporary grid and dielectric spacers arranged against flanks of the temporary grid, the temporary grid covering several distinct faces of the portion of temporary material, then c) engraving of the portion of temporary material, then d) fabrication of a semiconductor layer comprising a two-dimensional material or any other semiconductor material deposited by MOCVD, CVD or ALD, the semiconductor layer comprising at least a first zone forming a fin-shaped semiconductor portion disposed on the substrate and configured to serve as an electrical conduction channel for the FET microelectronic device, located under the temporary gate and dielectric spacers in at least one location formed by etching the portion of temporary material, and such that the semiconductor layer extends, without discontinuity with the first zone, to form second zones covering at least a portion of the flanks of the dielectric spacers and which are not disposed directly against the temporary gate, then e) etching of the temporary gate, and fabrication of at least one electrostatic control gate in place of the temporary gate, then f) realization, on the substrate, of fin-shaped source / drain regions, electrically coupled to the first zone of the semiconductor layer by the second zones of the semiconductor layer, and such that the second zones of the semiconductor layer extend between the source / drain regions and the dielectric spacers.

[0025] In this case, the method may further comprise, before the implementation of step c), a deposition of an insulating dielectric material around the dielectric spacers, and then an etching of cavities in the insulating dielectric material such that the cavities comprise at least one side wall formed by one of the dielectric spacers, and wherein: - step d) is implemented such that the second zones of the semiconductor layer cover at least part of the lateral walls of the cavities; - step f) is implemented such that each of the source / drain regions is disposed in one of the cavities.

[0026] Furthermore, the method may be such that: - Step a) involves creating several temporary portions of material on the substrate, and - step b) is implemented such that the temporary grid covers several distinct faces of each of the temporary material portions, and - step c) involves etching all the temporary material portions, and - step d) is implemented such that several first areas of the semiconductor layer are arranged in locations formed by etching the temporary material portions, the first areas of the semiconductor layer forming several semiconductor portions arranged on the substrate and such that the temporary grid covers several distinct faces of each of the first areas of the semiconductor layer.

[0027] The process may further include a step of depositing a grid dielectric layer or a ferroelectric memory layer implemented: - during step e), on the first area of ​​the semiconductor layer, the electrostatic control grid is then made on the gate dielectric layer or the ferroelectric memory layer, and / or - between steps c) and d), under the temporary grid and dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer being then made by covering the grid dielectric layer or the ferroelectric memory layer.

[0028] Throughout this document, the terms "on" and "under" are used without distinction as to the spatial orientation of the element to which the term refers. For example, in the feature "on a face of the first substrate," this face of the first substrate is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element should be understood as either having the first element directly against the second element, without any intermediate elements between the first and second elements, or having the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0029] Throughout this document, the term "layer" may refer to a single layer or a stack of several layers.

[0030] Throughout this document, the expression "electrically couple" is used to refer to an electrical connection that may be direct or indirect (i.e., made through one or more intermediate electrical elements). Brief description of the drawings

[0031] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which: - [Fig. 1] to [Fig. 6] schematically represent the steps of a re- process ization of the FET microelectronic device, the subject of the present invention, according to a particular embodiment; - [Fig.7] schematically represents a microelectronic device, the subject of the present invention, according to a variant of the particular embodiment.

[0032] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0033] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0034] The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with each other.

[0035] Detailed description of particular embodiments

[0036] An example of a method for making a FET 100 microelectronic device according to a particular embodiment, corresponding to a FinFET device, is described below in relation to figures 1 to 6. On each of these figures, the view on the left is a cross-sectional view in the (X,Z) plane, and the view on the right corresponds to a cross-sectional view along the AA' axis visible on the view on the left.

[0037] In the embodiment described in connection with these figures, the device 100 is made from a bulk-type substrate 102. The substrate 102 is etched from its upper face so as to form, on this face, one or more portions of temporary material 160 whose shape and volume correspond to those desired to form the active area of ​​the device 100. In [Fig. 1], three portions of temporary material 160 are shown.

[0038] Alternatively, the substrate 102 may correspond to an SOI substrate, i.e. comprising a surface layer of silicon disposed on a buried dielectric layer comprising for example SiO2, the buried dielectric layer being disposed on a support layer comprising for example silicon.

[0039] A grid dielectric layer 112 and an electrostatic control grid 110 are then made and cover several distinct faces of each portion of temporary material 160. The sides of the grid 110 are covered by the dielectric spacers 114. In addition, the portions 160 are electrically insulated by dielectric insulation regions 161 of the type STI (“Shallow Trench Isolation”) formed in the substrate 104.

[0040] Layer 112 comprises, for example, a high-K dielectric material (with high dielectric permittivity) such as HfO2. Alternatively, this layer 112 may comprise SiO2 or Al2O3 or any other suitable material or combination of materials.

[0041] The electrostatic control grid 110 is, for example, made by depositing one or more conductive materials onto the layer 112, for example a first deposit of a thin layer of TiN (thickness for example equal to 3 nm) on which is stacked a layer of tungsten of thickness equal to for example equal to 200 nm. Alternatively, the grid 110 can include one or more materials other than TiN and W, such as for example doped polysilicon or any other metal (Mo, etc.).

[0042] Furthermore, a suitable material for manufacturing the dielectric spacers 114 corresponds, for example, to SiN, SiCO₃, or SiBCN. The thickness of the layer deposited to manufacture the dielectric spacers 114 is, for example, between 5 nm and 15 nm.

[0043] The portions 160 are then etched anisotropically so as to retain only the parts of these portions covered by the grid 104 (see [Fig.2]). This etching is stopped at the isolation regions 161.

[0044] An insulating dielectric material 128, for example SiO2, is then deposited and subsequently planarized, stopping at the hard mask (not visible in the figures). The insulating dielectric material 128 is deposited to a significant thickness, and then planarization is carried out until the hard mask is reached. The hard mask is then removed, for example, by wet etching, for example, using a dilute H3PO4 solution at a temperature of 110°C. The structure obtained at this stage of the process is shown in [Fig. 3].

[0045] Cavities 150 are then etched into the insulating dielectric material 128 (see [Fig. 4]). These cavities 150 comprise side walls formed by the dielectric spacers 114 and remaining portions of the insulating dielectric material 128. These cavities 150 form locations for the source and drain regions of the device 100.

[0046] The temporary material portions 160 are then etched, and subsequently a semiconductor layer 120 is deposited (see [Fig. 5]). The first zones 122 of the semiconductor layer 120 form fin-shaped semiconductor portions arranged on the substrate 102 and occupying the spaces formed by the etching of the remaining portions of the temporary material portions 160 located under the grid 110. The second zones 124 of the semiconductor layer 120 cover the walls of the cavities 150.

[0047] The semiconductor layer 120 comprises at least one 2D semiconductor material, for example a transition metal dichalcogenide such as MoS2, or WSe2, or WS2, or MoTe2. It is also possible that the material of the semiconductor layer 120 corresponds to IGZO, ITn2O3, IWO, ITO, or an amorphous semiconductor oxide, or any other suitable semiconductor material deposited by CVD, MOCVD or ALD.

[0048] The fin-shaped source 116 and drain 118 regions are then formed in the cavities 150 by depositing, in the example described, one or more metallic materials in the cavities 150. Before this or these metallic deposits, it is possible to A layer of graphene is deposited in the cavities 150, and the metal(s) are then deposited onto the graphene layer. These source 116 and drain 118 regions, in [Fig. 6], are electrically coupled to the first zones 122 of the semiconductor layer 120 via the second zones 124 of the semiconductor layer 120, which extend between the source 116 / drain 118 regions and the dielectric spacers 114, as well as against the other walls of the source 116 / drain 118 regions located in the cavities 150. The material from these regions deposited outside the cavities 150 is removed by implementing planarization with a stop on the insulating dielectric material 128.

[0049] Advantageously, the source 116 / drain 118 regions comprise at least one metallic material such as gold, palladium, TiN, W, Ni, etc. According to one embodiment, each of the source 116 / drain 118 regions comprises a TiN layer on which a tungsten portion is formed. Different metals can be used to form the regions 116, 118 to promote low contact resistances, such as: S, Bi, Sn, Pd, Ru, Cu, Ni, Ti, TiN, W, Au, etc. These materials can also be modified subsequently (to improve their properties), for example by a doping step. The resulting device 100 is shown in [Fig. 6].

[0050] In the embodiment described above, the semiconductor layer 120 is such that the space previously occupied by the temporary portion(s) 160 is completely filled by the material of the semiconductor layer 120. Alternatively, it is possible that the semiconductor layer 120 does not completely fill the space(s) previously occupied by the temporary portion(s) 160. In this case, after the deposition of the semiconductor layer 120, the remaining space(s) are filled with dielectric material so as to form one or more dielectric portions 126 (visible in the example of [Fig. 7] described below) surrounded by the first zone 122 of the semiconductor layer 120.To form this or these portions 126, one or more dielectric layers, comprising for example Al2O3 (or HfO2) and / or SiO2 (or a low-k dielectric, or one with low dielectric permittivity), are deposited and then etched isotropically so as to retain only portions 126 located in the remaining spaces.

[0051] According to another embodiment, the substrate 102 can be of the semiconductor-on-insulator type, for example SOL. The temporary portions 160 are in this case made from the surface semiconductor layer of the substrate 102. The steps implemented to fabricate the device 100 are similar to those previously described in connection with Figures 1 to 6 (except for the insulation regions 161, which do not need to be fabricated in this embodiment). The device 100 obtained according to this embodiment is shown in [Fig. 7].

[0052] In the various examples described above, the second zones 124 of the semiconductor layer 120 cover all the sides and bottom walls of the source 116 and drain 118 regions. Generally, it is possible for the second zones 124 of the semiconductor layer 120 to extend between the source 116 and drain 118 regions and the dielectric spacers 114 and / or against walls of the source and drain regions other than those arranged against the dielectric spacers 114. Furthermore, the walls of the source 116 and drain 118 regions may be only partially covered by the second zones 124 of the semiconductor layer 120.

[0053] In the embodiments described above for the first and second embodiments, the gate dielectric layer 112 and the electrostatic control gate(s) 110 are fabricated on the temporary material portion(s) 160 before the semiconductor layer 120 is fabricated (the so-called "gate first" approach). Alternatively, instead of the gate dielectric layer 112 and the electrostatic control gate(s) 110, one or more temporary gates can be fabricated on the temporary material portion(s) 160, and then, after the semiconductor layer 120 is fabricated, the temporary gate(s) can be etched and the gate dielectric layer 112 and the electrostatic control gate(s) 110 can be fabricated in place of the etched temporary gate(s) (the so-called "gate last" approach).

[0054] In the embodiments described above, the gate dielectric layer 112 is formed just before the fabrication of the electrostatic control gate(s) 110, whether or not one or more temporary gates have been used. Alternatively, the electrostatic control gate(s) 110 may be fabricated without first fabricating the gate dielectric layer 112. In this case, the gate dielectric layer 112 can be deposited just before the semiconductor layer 120 is deposited, at least against the walls of the location(s) obtained by etching the portion(s) of temporary material 160. In this case, the layer 112 covers the various walls onto which the material of the semiconductor layer 120 is intended to be deposited, thus homogenizing the surfaces, and therefore the interfaces, against which the semiconductor layer 120 is subsequently deposited.

[0055] According to another embodiment, it is possible for the layer 112 to be deposited in two different stages: first, just before the formation of the grid 110 as previously described in connection with [Fig. 1], and then in the spaces formed by the etching of the portions 160 and in the cavities 150, just before the deposition of the semiconductor layer 120. In this case, the parts of the layer 112 located directly above the grid 110 are thicker than the other parts of the layer 112 because these parts combine the thicknesses of material deposited during the two deposition stages.

[0056] In the examples and variants described above, layer 112 comprises a dielectric material intended to form the gate dielectrics of the devices 100 produced, which correspond to FinFET transistors. Alternatively, layer 112 may comprise a ferroelectric material such as HfO2 or HfZrO2, in which case layer 112 corresponds to a ferroelectric memory layer. The devices 100 produced correspond to microelectronic devices having a FeFET-type memory function. The various embodiments of layer 112 described above also apply to a layer 112 comprising a ferroelectric material.Furthermore, when layer 112 contains a ferroelectric material, it is advantageous for layer 112 to be deposited in the spaces formed by the etching of portions 160 and in the cavities 150, just before the deposition of the semiconductor layer 120, or deposited in two separate steps as previously described. Thus, the surface area of ​​ferroelectric material formed by layer 112 is larger than if it were deposited only just before the fabrication of gate 110, thereby reducing memory variability in terms of performance.

Claims

Demands

1. A method for making a FET microelectronic device (100), comprising at least: a) making at least a portion of temporary material (160) on a substrate (102), then b) fabrication, at least on the portion of temporary material (160), of at least one grid, the grid being an electrostatic control grid (110) or a temporary grid, and dielectric spacers (114) arranged against flanks of the grid, the grid covering several distinct faces of the portion of temporary material (160), then c) engraving of the portion of temporary material (160), then (d) fabrication of a semiconductor layer (120) comprising a two-dimensional material or any other semiconductor material deposited by MOCVD, CVD or ALD, the semiconductor layer (120) comprising at least a first zone (122) forming a fin-shaped semiconductor portion disposed on the substrate (102) and configured to serve as an electrical conduction channel for the FET microelectronic device (100), disposed under the gate (110) and the dielectric spacers (114) in at least one location formed by the etching of the temporary material portion (160), and such that the semiconductor layer (120) extends, without discontinuity with the first zone (122), forming second zones (124) covering at least a portion of the flanks of the dielectric spacers (114) and which are not disposed directly against the gate (110), then e) realization, on the substrate (102), of fin-shaped source (116) / drain (118) regions, electrically coupled to the first zone (122) of the semiconductor layer (120) by the second zones (124) of the semiconductor layer (120), and such that the second zones (124) of the semiconductor layer (120) extend between the source (116) / drain (118) regions and the dielectric spacers (114), wherein the method further comprises realization of a gate dielectric layer or a ferroelectric memory layer such that it is disposed between the gate and the first zone of the semiconductor layer by covering several distinct faces of the first zone of the semiconductor layer.

2. A method according to claim 1, wherein the grid formed in step b) is an electrostatic control grid (130), the method further comprising, prior to the implementation of step c), a deposition of an insulating dielectric material (128) around the dielectric spacers (114), and then an etching of cavities (150) in the insulating dielectric material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), and in which: - step d) is implemented such that the second zones (124) of the semiconductor layer (120) cover at least a part of the side walls of the cavities (150); - step e) is implemented such that each of the source (116) / drain (118) regions is disposed in one of the cavities (150).

3. A method according to any one of claims 1 or 2, wherein the grid formed in step b) is an electrostatic control grid (130) and wherein: - step a) comprises the fabrication of several temporary material portions (160) on the substrate (102), and - step b) is implemented such that the electrostatic control grid (110) covers several distinct faces of each of the temporary material portions (160), and - step c) comprises the etching of all the temporary material portions (160), and - step d) is implemented such that several first zones (122) of the semiconductor layer (120) are arranged in locations formed by the etching of the temporary material portions (160),the first zones (122) of the semiconductor layer (120) forming several semiconductor portions arranged on the substrate (102) and such that the electrostatic control grid (110) covers several distinct faces of each of the first zones (122) of the semiconductor layer (120).

4. A method according to any one of claims 1 to 3, wherein the grid formed in step b) is an electrostatic control grid (130) further comprising a step of depositing a grid dielectric layer (112) or a ferroelectric memory layer (112) implemented: - between steps a) and b), on the portion of temporary material (160), the electrostatic control grid (110) then being formed on the grid dielectric layer (112) or the ferroelectric memory layer (112)

5.

6.

7. electric, and / or - between steps c) and d), under the electrostatic control grid (110) and the dielectric spacers (114), in at least one location formed by etching the portion of temporary material (160), the semiconductor layer (120) being then made by covering the grid dielectric layer (112) or the ferroelectric memory layer (112). Method of making a FET microelectronic device (100) according to claim 1, wherein the gate made in step b) is a temporary gate and wherein after step b) and before step e), the temporary gate is etched, and an electrostatic control gate (110) is made in place of the temporary gate. A method according to claim 5, further comprising, before the implementation of step c), the deposition of an insulating dielectric material (128) around the dielectric spacers (114), and then the etching of cavities (150) in the insulating dielectric material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), and in which: - step d) is implemented such that the second zones (124) of the semiconductor layer (120) cover at least part of the side walls of the cavities (150); - step e) is implemented such that each of the source (116) / drain (118) regions is disposed in one of the cavities (150). A method according to claim 5 or 6, wherein: - step a) involves the creation of several portions of temporary material (160) on the substrate (102), and - step b) is implemented such that the temporary grid covers several distinct faces of each of the portions of temporary material (160), and - step c) involves engraving all portions of temporary material (160), and - step d) is implemented such that several first zones (122) of the semiconductor layer (120) are arranged in locations formed by etching the temporary material portions (160), the first zones (122) of the semiconductor layer (120) forming several semiconductor portions arranged on the substrate (102) and such that the temporary grid covers several distinct faces of each of the first zones (122) of the semiconductor layer (120).

8. A method according to any one of claims 5 to 7, further comprising a step of depositing a layer (112) of grid dielectric or a layer (112) of ferroelectric memory implemented: - during step e), on the first area (122) of the semiconductor layer (120), the electrostatic control grid (110) is then made on the grid dielectric layer (112) or the ferroelectric memory layer (112), and / or - between steps c) and d), under the temporary grid and dielectric spacers (114), in at least one location formed by etching the portion of temporary material (160), the semiconductor layer (120) being then made by covering the grid dielectric layer (112) or the ferroelectric memory layer (112).

9. A method according to any one of claims 1 to 8, wherein: each of the source (116) / drain (118) regions formed in step e) is disposed in a cavity (150) comprising side walls formed at least by dielectric spacers (114) and by an insulating dielectric material (128); the second zones (124) of the semiconductor layer (120) completely covering the walls of the cavities (150) in which the source (116) / drain (118) regions are arranged.

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