STRUCTURE COMPRISING A SURFACE LAYER ATTACHED TO A SUBSTRATE EQUIPPED WITH A LAYER FOR TRAPPING CHARGES WITH LIMITED CONTAMINATION AND MANUFACTURING METHOD

Abstract

A device comprising a ferroelectric surface layer (20) containing lithium; a dielectric layer (16) comprising an oxide and disposed in contact with the ferroelectric surface layer; and a substrate (10) in contact with the dielectric layer, the substrate comprising a charge-trapping layer (14) disposed on a support (12), the charge-trapping layer (14) being disposed between the support (12) and the dielectric layer (16), the dielectric layer (16) having a thickness between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge-trapping layer (14) being such that the charge-trapping layer (14) has a lithium concentration of less than 5 x 10¹¹ at / cm². Figure to be published with the abbreviation: Fig. 1

Description

Title of the invention: STRUCTURE COMPRISING A SURFACE LAYER ATTACHED TO A SUBSTRATE EQUIPPED WITH A CHARGE-TRAPPING LAYER LIMITED CONTAMINATION AND MANUFACTURING PROCESS TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to a structure comprising a surface layer transferred onto a support having a charge-trapping layer, the structure being capable of limiting contamination of the charge-trapping layer by contaminants. The invention extends to a method for manufacturing this structure. TECHNOLOGICAL BACKGROUND

[0002] Integrated devices are usually fabricated on wafer-shaped substrates, which primarily serve as a support for their manufacture. However, increasing levels of integration and expected performance of these devices lead to a growing coupling between their performance and the characteristics of the substrate on which they are formed. This is particularly true for radio frequency (RF) devices, which process signals with frequencies ranging from approximately 3 kHz to 300 GHz and are used in applications such as telecommunications (telephony, Wi-Fi, Bluetooth, etc.).

[0003] As an example of device / substrate coupling, electromagnetic fields, arising from high-frequency signals propagating in devices, penetrate the depth of the substrate and interact with any electrical charge carriers present there. This results in unnecessary consumption of some of the signal energy due to insertion loss and possible crosstalk between components.

[0004] High-resistivity silicon-on-insulator (HR SOI) substrates are known, comprising a silicon support substrate with a resistivity greater than 1 kOhm.cm, a dielectric layer on the support substrate, and a silicon surface layer disposed on the dielectric layer. The support substrate may also include a charge-trapping layer disposed on the side of the dielectric layer, preferably in contact with it. The charge-trapping layer may comprise undoped polycrystalline silicon. The fabrication of this type of substrate is described, for example, in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656, or WO20211008742.

[0005] Surface acoustic wave (SAW) devices with composite structures integrating a surface layer of ferroelectric material and a charge-trapping layer are also known, forming a substrate similar to that described in the preceding paragraph, as detailed for example in document WO 2020 / 200986. These devices are used in many applications, and in particular in electronic applications where they form the central element of filters, oscillators, delay lines or transformers.

[0006] When an alternating electrical signal is applied to a transducer formed of one or more electrodes in contact with the ferroelectric material, in addition to an electrical wave as described above, a corresponding mechanical signal (i.e. an oscillation or a vibration) is generated at the level of this material: the electrical signal is translated into a mechanical signal exhibiting a frequency dependence with respect to the alternating electrical signal, a dependence which is a function of the characteristics of the electrode(s), the properties of the ferroelectric material and other factors including the characteristics of the semiconductor support of the device.

[0007] Elastic wave devices exploit this dependence to provide one or more frequency-dependent functions, and therefore dependent on the characteristics of the substrate. A dielectric layer interposed between the ferroelectric layer and its substrate improves the mechanical behavior of the transducer, and more specifically limits the occurrence of parasitic responses, induced losses related to substrate properties, and interface effects within the stack. Increasing the operating frequencies may necessitate thinning the dielectric layer for purely mechanical reasons.

[0008] Whether we consider semiconductor substrates or ferroelectric substrates, the problem is the same: The charge trapping layer, by capturing possible electric charge carriers, limits interactions with electromagnetic fields from high-frequency signals from devices formed on the substrate and allows these devices to achieve high levels of performance.

[0009] However, a continuing trend in the evolution of these devices is to employ increasingly higher operating frequencies, which require increasingly thinner dielectric layers, interposed between the surface layer and the trapping layer.

[0010] However, the thinning of the dielectric layers promotes the diffusion towards the trapping layer of charges of contaminating species such as hydrogen originally included in the surface layer or brought in during the manufacture of the devices or lithium in the case of ferroelectric surface layers made of lithium niobate or lithium tantalate.

[0011] By diffusion through the dielectric layer, these contaminating species occupy the electrical charge trapping sites of the trapping layer, reducing the efficiency of the latter and compromising the overall performance of the devices. Description of the invention

[0012] The present invention aims to address, at least in part, the problem of contamination of the electrical charge trapping layer, which is exacerbated by the thinness of the dielectric layer. More particularly, it aims to provide a structure comprising a surface layer transferred onto a support equipped with an electrical charge trapping layer that limits contamination of the latter, as well as a method for manufacturing such a structure.

[0013] For the purpose of achieving this goal, the object of the invention is a device comprising a ferroelectric surface layer containing lithium; a dielectric layer comprising an oxide and disposed in contact with the ferroelectric surface layer; and a substrate in contact with the dielectric layer, the substrate comprising a charge-trapping layer disposed on a support, the charge-trapping layer being disposed between the support and the dielectric layer, a device in which the dielectric layer has a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer and a surface roughness of the charge-trapping layer are such that the charge-trapping layer has a lithium dose of less than 5.1011 at / cm2.

[0014] An advantage of the structure according to the invention is to maintain the effectiveness of the charge trapping function of the electrical charge trapping layer even when the dielectric layer separating the charge trapping layer from the surface layer is thinned, by avoiding its contamination by chemical species likely to passivate the charge trapping sites, in particular hydrogen and lithium present in the surface layer.

[0015] Consequently, the structure according to the invention makes it possible to provide substrates for the manufacture of components comprising piezoelectric layers and designed to operate at high frequencies and exhibiting excellent performance.

[0016] According to additional, non-limiting features of the first aspect of the invention, considered individually or in any technically feasible combination: - the nitrogen concentration of the dielectric layer can be between 5 x 10²⁰ at / cm³ and 10²² at / cm³; and the surface roughness of the trapping layer can be less than 800 nm, measured peak-to-valley, preferably less than 400 nm, and even more preferentially less than 100 nm;

[0017] - the dielectric layer may have a thickness between 150 nm and 250 nm;

[0018] - the nitrogen concentration of the dielectric layer can be between 1021 at / cm3 and 6.1021 at / cm3;

[0019] - the dielectric layer can be a silicon oxide layer and a the hydrogen concentration of the dielectric layer can be strictly less than the nitrogen concentration of the dielectric layer;

[0020] - a hydrogen concentration of the dielectric layer (16) can be at least three times lower than the nitrogen concentration of the dielectric layer;

[0021] - a hydrogen concentration in the dielectric layer may be less than 10 22 at / cm3;

[0022] - the lithium dose in the charge trapping layer may be less than 1011 at / cm2;

[0023] - the ferroelectric surface layer may comprise lithium niobate or lithium tantalate;

[0024] - the charge trapping layer may include polycrystalline silicon;

[0025] - the ferroelectric surface layer can be made of a mono-material crystalline.

[0026] A second aspect of the invention relates to a method for manufacturing a device comprising a ferroelectric layer, comprising the steps of forming a charge-trapping layer on a support to form a substrate; smoothing an exposed surface of the trapping layer so as to reduce the roughness of this exposed surface below a threshold roughness; forming a dielectric layer at least on the smoothed charge-trapping layer and optionally on a donor substrate comprising a ferroelectric material, the dielectric layer having a thickness of between 150 nm and 500 nm; joining the donor substrate and the substrate via the dielectric layer;removing part of the donor substrate to form a ferroelectric surface layer, the threshold roughness and a nitrogen concentration in an oxide layer included in the dielectric layer being chosen so that the lithium dose in the charge trapping layer is less than 5.1011 at / cm2 at the end of the manufacturing process. ;

[0027] According to additional, non-limiting features of the second aspect of the invention, considered individually or in any technically feasible combination:

[0028] - the nitrogen concentration of the dielectric layer can be between 5.1020 at / cm3 and 1022 at / cm3; and the surface roughness of the trapping layer can be less than 800 nm in peak-valley measurement, preferably less than 400 nm, and even more preferentially less than 100 nm;

[0029] - the smoothing step may include the mechano-chemical polishing of the layer of charge trapping;

[0030] - the charge trapping layer may include polycrystalline silicon;

[0031] - the manufacturing process may include the formation of a brittle plane by implanting lightweight species into the donor substrate to define the surface layer, and the step of removing part of the donor substrate may include detaching the surface layer at the weakening plane. BRIEF DESCRIPTION OF THE FIGURES

[0032] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0033] [Fig. 1] Fig. 1 represents a structure which is the subject of this description;

[0034] [Fig. 2] Fig. 2 illustrates a manufacturing process for the structure shown in [Fig.l];

[0035] [Fig.3] Fig.3 schematically illustrates a mechanism for the diffusion of chemical species and the peak-valley measurement concept in the structure according to the invention;

[0036] [Fig.4] Fig.4 represents a graph indicating a required thickness oxide in the structure of the [Fig.l]. DETAILED DESCRIPTION OF THE INVENTION

[0037] Fig. 1 represents a structure 1 comprising a substrate 10 integrating a support 12 and a layer 14 for trapping electrical charges on the support, a surface layer 20 disposed on the substrate 10, and a dielectric layer 16 interposed between the surface layer 20 and the substrate 10, preferably in direct contact with the surface layer 20 and the charge-trapping layer 14.

[0038] The surface layer 20 is a layer enabling the provision of functions, for example piezoelectric, to a device developed on or in the structure 1.

[0039] Conventionally, structure 1 can be in the form of a circular plate whose diameter can be 100, 200, 300 or even 450mm.

[0040] As presented in the prior art documents presented in the preamble, structure 1 can be fabricated in multiple ways. Most generally, structure 1 can be fabricated by a manufacturing process comprising assembling the substrate 10 and a donor substrate, with the dielectric layer 16 interposed between these two elements, followed by a step of removing part of the donor substrate to form the surface layer 20. The step of removing part of the donor substrate can be carried out by chemical thinning of this substrate. However, structure 1 is preferably fabricated by applying Smart Cut™ technology, according to which a layer intended to form the super layer The artificial layer 20 is delimited by means of a weakening plane formed by the implantation of light species such as hydrogen in the donor substrate. This layer is then separated from the donor substrate bonded to the support via the dielectric layer 16, by fracture at the level of the weakening plane, the surface layer 20 remaining fixed to the substrate 10 equipped with the trapping layer 14, with the dielectric layer 16 interposed between them.

[0041] The fabrication of such a structure leads to the introduction of hydrogen into the layers due, for example, to hydrogen implantation during the Smart Cut process and hydrogen production during the bonding between the surface layer and the substrate via the dielectric layer. Furthermore, when the surface layer is a ferroelectric layer containing lithium niobate or lithium titanate, lithium is also present in the layers. These two elements, hydrogen and lithium, can diffuse into the trapping layer, occupy the charge-trapping sites, and thus passivate them, potentially drastically reducing the effectiveness of the trapping layer.

[0042] The substrate 10 typically has a thickness of several hundred microns. Preferably, the substrate has a high resistivity, greater than 1000 ohm-cm, and even more preferably, greater than 2000 ohm-cm. This limits the density of charges, holes or electrons, that are likely to move within the substrate. However, the invention is not limited to a substrate 10 with such a high resistivity, and it also provides RF performance advantages when the substrate has a more compliant resistivity, on the order of a few hundred ohm-cm, for example, less than 1000 ohm-cm, or 500 ohm-cm, or even 10 ohm-cm.

[0043] For reasons of availability and cost, the support 12 is preferably made of monocrystalline silicon. For example, it may be a CZ silicon substrate with a low interstitial oxygen content of between 6 and 10 ppm, or an FZ silicon substrate, which in particular has a naturally very low interstitial oxygen content. It may also be a CZ silicon substrate with a high interstitial oxygen content (designated by the expression "High Oi") greater than 26 ppm. Alternatively, the support 12 may be made of another material: for example, sapphire, glass, quartz, silicon carbide, etc. Under certain circumstances, and in particular when the trapping layer 14 has a sufficient thickness, for example greater than 30 microns, the support 12 may have a standard resistivity of less than 1 kΩ·cm.

[0044] The trapping layer 14 can be of very diverse natures, as reported in the prior art documents. Generally, it is a non-crystalline layer exhibiting structural defects such as dislocations, Grain boundaries, amorphous zones, interstices, inclusions, pores... These structural defects trap charges that may circulate within the material, for example, at incomplete or dangling chemical bonds. This prevents or limits conduction in the trapping layer, which consequently exhibits high resistivity.

[0045] Advantageously, and for reasons of ease of implementation, this trapping layer 14 is formed of a polycrystalline silicon layer. Its thickness, particularly when formed on a resistive support 12, can be between 0.3 and 3 µm. However, other thicknesses less than or greater than this range are perfectly feasible, depending on the expected RF performance level of the structure 1.

[0046] In order to preserve the polycrystalline quality of this layer during the heat treatments that the structure 1 may undergo, an amorphous layer, in silicon dioxide for example, can advantageously be provided on the support 12 before the deposition of the charge trapping layer 14.

[0047] Alternatively, the trapping layer 14 can be formed by implanting a heavy species, such as argon, into a surface layer of the support 12, in order to create the structural defects constituting the electrical traps. This layer 14 can also be formed by porosification of a surface layer of the support 12.

[0048] The dielectric layer is usually made of silicon oxide and preferably contains nitrogen, which is favorable for forming a barrier layer preventing the diffusion of species, in particular hydrogen and lithium mentioned above.

[0049] The surface layer 20 can be of any suitable material. It is most preferably made of a single-crystal material. When the structure 1 is intended to receive integrated semiconductor components, the surface layer 20 can thus be composed of single-crystal silicon, or any other semiconductor material. In such a case, lithium contamination may originate from the equipment used to manufacture the structure. When the structure 1 is intended to receive surface acoustic wave filters, the surface layer 20 can be composed of a piezoelectric and / or ferroelectric material, such as lithium tantalate or lithium niobate. In this case, in addition to possible external contamination, lithium contamination may also originate from the surface layer itself.The surface layer 20 may also include finished or semi-finished integrated components, formed on the donor substrate and transferred to the substrate 10 during the fabrication step of the structure 1. In general, the thin layer may have a thickness between 10 nm and 10 pm.

[0050] A method for manufacturing a structure conforming to that shown in [Fig. 1] is now presented by way of illustration only, using [Fig. 2], in of which the surface layer 20 is a ferroelectric layer.

[0051] According to this process, a charge-trapping layer 14 of polycrystalline silicon is formed by deposition on a silicon support 12, for example using an LPCVD technique conducted between 600°C and 650°C. The trapping layer 14 has a thickness of approximately 500 nm, or even 1 micron.

[0052] The trapping layer 14 is then polished by a chemical-mechanical polishing (CMP) step, resulting in the removal of approximately 100 to 200 nanometers of the trapping layer, yielding a layer with a thickness between 500 and 1000 nanometers and exhibiting a surface roughness of less than 300 nm, preferably less than 140 nm, or even more preferably less than 100 nm, in peak-valley measurement. Notwithstanding, a peak-valley roughness of 800 nm can be obtained with a polycrystalline silicon filler trapping layer several microns (approximately 4 pm) thick.Such roughness could help avoid parasitic modes, particularly present in a POI (Piezoelectric-On-Insulator) type structure with a piezoelectric layer thickness greater than the wavelength used, due to the radiation of these volume modes into the volume and their interaction with the interfaces.

[0053] Preferably, in order to reduce the hydrogen content of the trapping layer, a first annealing of this layer can be carried out in a hydrogen-poor atmosphere (i.e., less than 5 ppm) at a temperature between the deposition temperature and 1000°C. Advantageously, the temperature of the first annealing is above 620°C and preferably below 900°C, for at least one hour and preferably for several hours. Under these preferred annealing conditions, the hydrogen present in the trapping layer 3 is efficiently exodiffused to reduce its concentration below the threshold of 10¹⁸ at / cm³, preferably 10¹⁷ at / cm³, without altering the polycrystalline nature of the trapping layer, by recrystallization.

[0054] A dielectric layer 16, consisting of a 300 nm to 1000 nm thick layer of silicon oxide containing nitrogen, is deposited onto the trapping layer 14, for example by a PECVD technique conducted at a temperature between 600°C and 800°C. This dielectric layer forms the dielectric layer 16 of structure 1. The layer is then polished by a chemical-mechanical polishing (CMP) step, resulting in the removal of approximately 200 to 800 nanometers of the oxide to provide a surface with a roughness of less than 0.3 nm RMS, for example, over a 5 x 5 micron field or a 30 x 30 micron field, as measured by atomic force microscopy. The dimensions of the measurement field are adjusted by the practitioner to obtain a representative characterization of the layer in question. Here, the dielectric layer 16 has a thickness between 150 nm and 500 nm, preferably between 150 nm and 250 nm, and a significant hydrogen concentration of more than 1020 at / cm 3 but preferably remaining below a nitrogen concentration in the dielectric layer 16.

[0055] To reduce this concentration, a second annealing, called a "densification" anneal, similar to the first annealing described above, can be applied. This involves annealing under a low-hydrogen atmosphere (i.e., less than 5 ppm) and exposing the dielectric layer 16 to a temperature above its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is above 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodiffuse the hydrogen from the dielectric layer 16, and possibly from the trapping layer 14. At the end of this densification annealing, the dielectric layer 16 has a hydrogen concentration of less than 1020 at / cm3 and the trapping layer 14 has a hydrogen concentration of less than 1018 at / cm3, preferably 1017 at / cm3.

[0056] The presence of nitrogen in a silicon oxide layer improves its barrier effect against the diffusion of chemical species such as lithium and hydrogen. The applicant has estimated through simulations and confirmed through experiments that a decrease in the roughness of the trapping layer is accompanied by a decrease in the nitrogen content required to obtain a satisfactory barrier effect. Thus, a nitrogen concentration between 5 x 10²⁰ at / cm³ and 10²² at / cm³, preferably between 10²¹ at / cm³ and 6 x 10²¹ at / cm³, in combination with a trapping layer with a roughness of less than 800 nm, preferably less than 400 nm, preferably less than 100 nm, in peak-valley measurement, makes it possible to obtain a sufficient barrier effect of the dielectric layer to fabricate devices on the substrate thus obtained that are capable of operating at high frequencies.The upper values ​​of the above ranges do not constitute an upper limit to the nitrogen concentration required to achieve a barrier effect, but ensure a sufficiently low nitrogen concentration to allow the structure according to the invention to be applied to known devices without risking a negative impact on their performance.

[0057] The importance of minimizing roughness in peak-valley measurement is explained empirically by means of [Fig.3]: each roughness peak 310 of the trapping layer 14 creates one or more preferred paths (represented by straight arrows) for the migration of species through the dielectric layer 16 due to a local thinning of the dielectric layer 16 at the level of these peaks 310. [Fig.3] is only a schematic representation used for explanatory purposes and in no way a realistic representation of the layers in a real device.

[0058] As illustrated by [Fig. 3], a peak-valley measurement consists of measuring the sum The sum of a maximum depth SI of a trough (the deepest valley) in a given surface Surf and a maximum height S2 of a peak (the highest protrusion) of that surface, the depth and height being measured relative to a mean altitude Moy of that surface, for example, over a given area of ​​the sample. In the case of an atomic force microscopy measurement, one could, for example, consider an observation area corresponding to a square with sides of 30 pm, but one could alternatively consider a square with sides of 5 pm or more to establish the peak-valley measurement.

[0059] The thickness of the oxide layer forming the dielectric layer 16 can be minimized as a function of its nitrogen concentration and a maximum dose of lithium considered acceptable in the charge-trapping layer. The minimum thickness of the oxide layer is thus estimated as the sum of half the peak-valley roughness and a minimum oxide thickness dependent on its nitrogen concentration, this minimum thickness decreasing with increasing nitrogen concentration. The thickness of the dielectric layer 16 is measured between the average depth of the charge-trapping layer and the surface of the oxide layer.

[0060] The term dose refers to the quantity of atoms of a given chemical species over the thickness of the layer, that is, the quantity contained in a volume defined by a given surface area of ​​the layer and the projection of this surface perpendicular to the layer. A dose can be expressed as the number of atoms per unit area of ​​the layer.

[0061] The graph illustrated in [Fig. 4] summarizes the situation. The x-axis represents the thickness Tk of the oxide layer expressed in nanometers, and the y-axis represents the peak-to-valley roughness of the charge-trapping layer indicated by PV, also expressed in nanometers. For this graph, the curves identified by [N]i, [N]2, [N]3, and [N]4 represent the minimum thicknesses of the oxide layer according to PV to obtain a maximum acceptable lithium dose of 5 x 10¹¹ lithium atoms per square centimeter in the charge-trapping layer, respectively, for nitrogen concentrations of approximately 10²⁰, 1 x 10²¹, 3 x 10²¹, and 10²² at / cm³, respectively. A PV value of 0 corresponds to a perfectly smooth charge trapping layer, which gives the minimum oxide thickness to be deposited to sufficiently limit the diffusion of chemical species in the layer, lithium in particular, for a given nitrogen concentration of this oxide.

[0062] Preferably, the oxide layer forming the dielectric layer 16 has a proportion between the concentrations of nitrogen and hydrogen that is favorable to blocking the diffusion of hydrogen, with an excess of nitrogen relative to the amount of hydrogen, that is to say a ratio between the concentrations of nitrogen and hydrogen that The concentration must be strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, for concentrations measured by a SIMS (Secondary Ion Mass Spectrometry) method. Thus, the hydrogen concentration in the dielectric layer is preferably less than approximately 1022 at / cm³, more preferably less than approximately 1021 at / cm³, and even more preferably less than approximately 1020 at / cm³.

[0063] It should be noted that, when the dielectric layer 16 is formed on the trapping layer 14, and these two layers have been deposited at a relatively low temperature as just described, it is not necessary to apply the first and second annealing respectively after each deposition step. It is possible to perform a single annealing, under conditions similar to the first and second annealing, after the formation of the dielectric layer 16 at low temperature on the trapping layer 14. In other words, it is not necessary in this case to apply a specific annealing to the trapping layer 14 before the deposition of the dielectric layer 16.

[0064] As illustrated by this embodiment, it is generally preferable to place the dielectric layer 16 on the support 12 (via the trapping layer 14) rather than on the donor substrate 200. Indeed, it is generally possible to heat-treat this support 12 at the temperature of the first and / or second annealing, which is not always the case for the donor substrate 200. For example, this donor substrate may have a plane of embrittlement, or be composed of a ferroelectric material with a relatively low Curie temperature, or contain components, which, in each of these cases, limits the applicable heat budget to a few hundred degrees for a relatively short time, less than 1 hour. However, the invention does not preclude the possibility that, in certain favorable cases, the dielectric layer 16 may be formed at least partially on the donor substrate 200.

[0065] The structure obtained at this stage is illustrated in (a) of [Fig.2].

[0066] In parallel with the preparation of the substrate 10, hydrogen ions are implanted into a ferroelectric lithium tantalate donor substrate 200 through a first face 210 of its faces in order to form a buried embrittlement plane 220. A surface layer 20 is thus defined between this embrittlement plane 220 and the first face 210 of the donor substrate, and a complementary layer 22 comprises the remainder of the donor substrate.

[0067] The donor substrate obtained at this stage is illustrated in (b) of [Fig.2].

[0068] The donor substrate 200 is assembled with the silicon oxide layer 16 disposed on the support 12 as illustrated in (c) of [Fig. 2], and the donor substrate 200 is then fractured at the embrittlement plane 220 using a moderate heat treatment of approximately 400°C. The complementary layer 22 of the substrate is then released. donor to expose a free face 230 of this layer which can then be prepared to improve its crystalline quality and surface finish. This preparation includes a step of thinning the first layer by chemical polishing and a heat treatment step at 500°C in a neutral atmosphere for 1h. The resulting structure, shown in (d) of [Fig.2], is that of [Fig.1].

[0069] The process described above is applied to a ferroelectric lithium tantalate layer used as a surface layer 20, but other types of ferroelectric or piezoelectric materials such as lithium niobate could be used. Furthermore, as an alternative to a ferroelectric surface layer, a semiconducting surface layer such as a silicon layer or one comprising silicon such as monocrystalline silicon could be used.

[0070] The manufacturing process detailed above thus makes it possible to obtain a structure in which the contamination of the trapping layer by harmful species, in particular hydrogen and lithium, remains sufficiently limited to allow the development of devices capable of operating satisfactorily at high frequencies. Indeed, for example, the combination of a nitrogen content between 5 x 10²⁰ at / cm³ and 10²² at / cm³ for an oxide layer of sufficient thickness deposited directly on a trapping layer 14 surface with a peak-valley roughness of less than 300 nm results in the trapping layer retaining lithium dose charges 14 at less than 5 x 10¹¹ at / cm², and hydrogen concentrations at less than 10²⁰ at / cm³, preferably less than 10¹⁹ at / cm³, and even more preferably less than 10¹⁸ at / cm³.

[0071] Of course the invention is not limited to the modes of implementation described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Demands

1. A device comprising: - a ferroelectric surface layer (20) containing lithium; - a dielectric layer (16) comprising an oxide and disposed in contact with the ferroelectric surface layer; and - a substrate (10) in contact with the dielectric layer, the substrate comprising a charge-trapping layer (14) disposed on a support (12), the charge-trapping layer (14) being disposed between the support (12) and the dielectric layer (16), the device being characterized in that: the dielectric layer (16) has a thickness between 150 nm and 500 nm, preferably between 150 nm and 300 nm; a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge-trapping layer (14) are such that the charge-trapping layer (14) has a lithium dose of less than 5.1011 at / cm2; the nitrogen concentration of the dielectric layer is between 5.1020 at / cm3 and 1022 at / cm3; and the surface roughness of the trapping layer (14) is less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm.

2. The device according to claim 1, wherein the dielectric layer (16) has a thickness between 150 nm and 250 nm.

3. The device according to claim 1 or 2, wherein the nitrogen concentration of the dielectric layer (16) is between 1021 at / cm3 and 6.1021 at / cm3.

4. The device according to any one of claims 1 to 3, wherein the dielectric layer is a silicon oxide layer and a hydrogen concentration of the dielectric layer (16) is strictly less than the nitrogen concentration of the dielectric layer (16).

5. The device according to claim 4, wherein a hydrogen concentration of the dielectric layer (16) is at least three times lower than the nitrogen concentration of the dielectric layer (16).

6. The device according to any one of claims 1 to 5, wherein a hydrogen concentration in the dielectric layer (16) is less than 1022 at / cm3.

7. The device according to any one of claims 1 to 6, wherein the lithium dose in the charge trapping layer (14) is less than 1011 at / cm2.

8. The device according to any one of claims 1 to 7, wherein the ferroelectric surface layer (20) comprises lithium niobate or lithium tantalate.

9. The device according to any one of the preceding claims 1 to 8 wherein the charge-trapping layer (14) comprises polycrystalline silicon.

10. The device according to any one of the preceding claims in which the ferroelectric surface layer (20) is made of a single-crystal material.

11. A method for manufacturing a device comprising the following steps: - forming a charge-trapping layer (14) on a support (12) to form a substrate (10); - smoothing an exposed surface of the trapping layer (14) so ​​as to reduce the roughness of this exposed surface below a threshold roughness; - forming a dielectric layer (16) at least on the smoothed charge-trapping layer (14) and optionally on a donor substrate (200) comprising a ferroelectric material containing lithium, the dielectric layer (16) having a thickness between 150 nm and 500 nm; - joining the donor substrate (200) and the substrate (10) via the dielectric layer (16);- removing part of the donor substrate to form a surface ferroelectric layer (20) containing lithium, the threshold roughness and a nitrogen concentration in an oxide layer included in the dielectric layer (16) being chosen so that the lithium dose in the charge trapping layer is less than 5.1011 at / cm2 at the end of the manufacturing process; wherein: - the nitrogen concentration of the dielectric layer is between 5.1020 at / cm3 and 1022 at / cm3; and - the surface roughness of the trapping layer (14) is less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm.;

12. A manufacturing method according to claim 11, wherein the smoothing step includes the mechano-chemical polishing of the charge trapping layer (14).

13. A manufacturing method according to claim 11 or 12, wherein the charge-trapping layer (14) comprises polycrystalline silicon.

14. A manufacturing method according to any one of the preceding claims 11 to 13, comprising the formation of a weakening plane (220) by implanting light species in the donor substrate (200) to define the surface layer (20), and the step of removing part of the donor substrate includes the detachment of the surface layer (20) at the level of the weakening plane (220).

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