Quadrature oscillators

Abstract

Quadrature Oscillators The present description relates to a device comprising two oscillators (LO) coupled to each other so as to operate in quadrature, each oscillator comprising an inductance (L) and a capacitance (C) with a value selectable from at least two values ​​each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductance (L) is lower than the quality factor of its capacitance (C). Figure for abstract: Fig. 1

Description

Title of the invention: Quadrature oscillators Technical field

[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, in these electronic circuits, to devices for generating two periodic radiofrequency signals in quadrature with respect to each other. Prior art

[0002] Many known electronic circuits, for example wireless transmitters and / or receivers, include devices known for generating periodic signals in quadrature with respect to each other.

[0003] Some of these known devices use a polyphase filter to generate the two quadrature signals.

[0004] Other known devices use an oscillator providing a first periodic signal from which the two quadrature signals are generated by frequency division, the first signal then having to have a frequency twice as high as that targeted for the two quadrature signals.

[0005] Still other known devices use two oscillators interconnected to each other so as to provide the two signals in quadrature, these two interconnected oscillators being said to be in quadrature. An example of such a device with quadrature oscillators is for example described in relation to figure numbered l(b) of the article "A 900MHz CMOS LC-Oscillator with Quadrature Outputs" by A. Rofougaran et. al, published in 1996 in ISSCC.

[0006] However, the known devices described above have drawbacks. For example, these known devices do not allow quadrature signals to be obtained whose frequency is selectable (or adjustable) from several high values, for example greater than 5 GHz, extending over a wide frequency range, for example a frequency range from 5 to 10 GHz. For example, these known devices are not suitable for implementation in an Ultra Wide Band (UWB) radiofrequency transmission and / or reception circuit. Summary of the invention

[0007] There is a need to overcome all or part of the disadvantages of known devices for generating two quadrature signals.

[0008] For example, there is a need for a device for generating two quadrature signals with a frequency whose value is greater than 5 GHz and selectable over a wide frequency band ranging for example from 5 GHz to 10 GHz.

[0009] One embodiment overcomes all or part of the drawbacks of known devices for generating two quadrature signals.

[0010] One embodiment provides a device comprising two oscillators coupled to each other so as to operate in quadrature, each oscillator comprising an inductance and a capacitance with a value selectable from at least two values ​​each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductance is lower than the quality factor of its capacitance.

[0011] According to one embodiment, in each oscillator: the inductor comprises identical first and second windings; the first winding has a first end coupled to a first node for applying a supply potential and a second end coupled to a second output node of the oscillator; the second winding has a first end coupled to the first node and a second end coupled to a third output node of the oscillator; and a first electrode of the capacitor is connected to the second node and a second electrode of the capacitor is connected to the third node.

[0012] According to one embodiment, in each oscillator, the inductance comprises a first resistor connected in series with the first winding between the first and second nodes, and a second resistor connected in series with the second winding between the first and third nodes, the first and second resistors having the same resistance value.

[0013] According to one embodiment, each of the first and second resistors has a resistance value of between 0.5 and 5 ohms, said at least two values ​​of the capacitance being for example between 0.5 and 2.0 pF and the inductance having for example a value of between 300 and 700 pH.

[0014] According to one embodiment, in each oscillator, each of the first and second resistors is implemented by at least one portion of polycrystalline silicon, preferably undoped.

[0015] According to one embodiment, each of the first and second resistors comprises: a first conductive portion of a first metal level of an interconnect structure, the first conductive portion corresponding to a first terminal of the resistor; a second conductive portion of the first metal level corresponding to a second terminal of the resistor; at least a third conductive portion of a second metal level of the interconnection structure; at least a fourth conductive portion of the second metal level; first conductive vias electrically coupling the first portion to said at least one third portion and the second portion to said at least one fourth portion; and second conductive vias electrically coupling said at least one portion of polycrystalline silicon to said at least one third portion and to said at least one fourth portion.

[0016] According to one embodiment, in each of the oscillators, the capacitance comprises a plurality of capacitances associated with switches configured so that each of the at least two values ​​corresponds to a given combination of open and closed states of said switches.

[0017] According to one embodiment, in each of the oscillators, the selectable value capacitor further comprises varicap diodes.

[0018] According to one embodiment, each of the oscillators further comprises: a first MOS transistor and a second MOS transistor each having a first conduction terminal connected to the second node and a second conduction terminal coupled to a fifth node for applying a reference potential, the first transistor having its gate coupled to the third node; a third MOS transistor and a fourth MOS transistor each having a first conduction terminal connected to the third node and a second conduction terminal coupled to the fifth node, the third transistor having its gate coupled to the second node.

[0019] According to one embodiment: the second transistor of a first of the two oscillators has its gate coupled to the second node of a second of the two oscillators; the fourth transistor of the first oscillator has its gate coupled to the third node of the second oscillator; the second transistor of the second oscillator has its gate coupled to the third node of the first oscillator; and the fourth transistor of the second oscillator has its gate coupled to the second node of the first oscillator.

[0020] According to one embodiment, each of the oscillators comprises: a first current source having a first terminal connected to the second conduction terminals of the first and third transistors of the oscillator, and a second terminal connected to the fifth node; and a second current source having a first terminal connected to the second conduction terminals of the second and fourth transistors of the oscillator, and a second terminal connected to the fifth node.

[0021] According to one embodiment, each operating frequency value belongs to a range from 5 GHz to 10 GHz.

[0022] According to one embodiment, the operating frequency values ​​comprise a first value between 5 and 6.5 Ghz and a second value between 8.5 and 10 Ghz.

[0023] According to one embodiment, each of the operating frequency values ​​is separated from the other operating frequency values ​​by at least 0.5 GHz. Brief Description of the Drawings

[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0025] [Fig.l] represents an embodiment of an oscillator;

[0026] [Fig.2] represents in the form of blocks an embodiment of a device comprising two quadrature oscillators identical to that of [Fig.l];

[0027] [Fig. 3] represents, by a schematic top view, an example of an embodiment of a resistance of the oscillators of figures 1 and 2;

[0028] [Fig.4] represents a schematic sectional view of the resistor of [Fig.3]. Description of the embodiments

[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the usual electronic circuits, for example integrated, and the usual applications in which a device for generating two quadrature signals can be provided have not been detailed, the embodiments described being compatible with these usual circuits and applications.

[0031] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0032] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., are referred to, unless otherwise specified, the orientation of the figures.

[0033] Unless otherwise indicated, the value of a parameter is said to be selectable from several values ​​when the value of the parameter is controllable and can take each of said several values ​​depending on its control. For example, the value of a capacitor is said to be selectable from several values ​​when the capacitor can take each of these several values, for example under the control of one or more control signals. As another example, the value of an operating frequency is said to be selectable from several values ​​when the frequency can take each of these several values, for example under the control of one or more control signals.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] Among the known devices presented previously, quadrature oscillators make it possible to generate quadrature signals having frequencies greater than 1 GHz, for example a frequency of the order of 5 GHz. However, the quadrature oscillators can switch between two operating modes corresponding respectively to two different frequency values ​​for the quadrature signals generated by the device. More particularly, in a first of the two operating modes, the operating frequency of the quadrature oscillators is greater than the operating frequency of these oscillators not interconnected to each other, and, in a second of the two operating modes, the operating frequency of the quadrature oscillators is lower than the operating frequency of these oscillators not interconnected to each other.Forcing the device's oscillators to operate in only one of the two modes ensures that the frequency of the quadrature signals is the desired one. To achieve this, it has been proposed to add phase shifters in the connections between the two quadrature oscillators. However, in a device with quadrature oscillators interconnected to each other via phase shifters, the phase shifters are sized for a given operating frequency, i.e. a given frequency of the quadrature signals provided by the device. As a result, switching between the two operating modes is not controlled over the entire operating range of the device, which poses a problem.For example, such a device is not suitable for generating quadrature signals having a frequency whose value is selectable from several values ​​in a range from 5 GHz to 10 GHz, for example a frequency whose value is selectable from at least a first frequency value between 5 and 6.5 GHz and a second frequency value between 8.5 and 10 GHz and / or a frequency whose value is selectable. selectable among several values ​​separated from each other by at least 0.5 GHz.

[0036] A device is proposed here comprising two quadrature oscillators, i.e. two oscillators coupled to each other so as to operate in quadrature, in which each oscillator comprises a load ("tank" in English) of LC type in parallel and is configured so that, at each selectable value of operating frequency of the oscillators of the device, the quality factor of the inductance L of the LC load is lower than the quality factor of the capacitance C of the LC load. In practice, in such a device, each LC load comprises a capacitance having a selectable (or controllable) value from among several values, each of these selectable capacitance values ​​each corresponding to a different operating frequency of the device.

[0037] The provision of an inductance L with a lower quality factor than that of the capacitance C leads to greater losses compared to the case where the inductance L would have a higher quality factor, for example higher than that of the capacitance C. This goes against the usual practices which consist, in the LC load of an oscillator, of having an inductance L whose quality factor is as high as possible and therefore generally higher than that of the capacitance C of the LC load. Indeed, an LC load having an inductance L with the highest possible quality factor, and, in particular, higher than that of the capacitance C of the load, makes it possible to limit consumption and to optimize (for example reduce) phase noise.

[0038] However, the provision, for each selectable value of operating frequency of the device, of an inductance L with a quality factor lower than that of the capacitance allows that, for each of these values ​​of operating frequency, the device is always in the same operating mode among the two operating modes between which quadrature oscillators can switch.

[0039] In order to ensure that, for each selectable value of operating frequency of the device, the device is always in the same operating mode among the two operating modes between which quadrature oscillators can switch, one could have thought of configuring the LC load so that, at each selectable value of operating frequency, the quality factor of the inductance L of the LC load is higher than the quality factor of the capacitance C of the LC load. However, the device would then be maintained in the operating mode where the frequency of the quadrature signals that it provides is lower than the operating frequency of each of the oscillators not interconnected to each other.Conversely, when for each selectable value of operating frequency of the device, the quality factor of the inductance L of the LC load is lower than the quality factor of the capacitance C of the LC load, the . device is maintained in the operating mode where the frequency of the quadrature signals it provides is higher than the operating frequency of the oscillators not interconnected to each other, which is advantageous when aiming for operating frequencies above 5 GHz including for example an operating frequency between 8.5 and 10 GHz.

[0040] According to one embodiment, to ensure that, for each selectable operating frequency value, the quality factor of the inductance L is lower than that of the capacitance C, the inductance L of each oscillator comprises at least one resistor, despite this resistor increasing the losses in the inductance. By way of example, this resistor is configured to limit the increase in consumption, phase noise and capacitances resulting from the introduction of this resistor, while ensuring that, for each of the selectable operating frequency values ​​of the device, the device is maintained in the same operating mode, namely that where the quality factor of the inductance is lower than that of the capacitance. Preferably, the value of the resistor is chosen to be the smallest possible among the resistance values ​​making it possible to ensure the above operation.

[0041] According to one embodiment, the at least one resistance of the inductance L is implemented by a portion of intrinsic polycrystalline silicon (i.e. not intentionally doped), rather than by a conductive portion of a metal level of an interconnection structure of the integrated circuit of the device. Indeed, polycrystalline silicon does not suffer from the electromigration problems suffered by a portion of a metal layer of a metal level.

[0042] Embodiments and variants of such a device will now be described.

[0043] In the remainder of the description, by way of example, the device described is configured to have an operating frequency whose value is selectable from at least two values ​​belonging to a frequency range from 5 GHz to 10 GHz, for example from at least two values ​​comprising a first value between 5 and 6.5 GHz and a second value between 8.5 and 10 GHz. Preferably, each of the selectable frequency values ​​is separated from the other selectable frequency values ​​by at least 0.5 GHz. However, the person skilled in the art is able, from the functional indications given in the present description, to modify the frequency range to which the selectable frequency values ​​and / or the selectable frequency values ​​belong.For example, the person skilled in the art is able, from the present description, to adapt the selectable values ​​of the capacitance C so that all or part of the operating frequencies of the oscillators of the device are less than 5 GHz. Indeed, the device described here is adapted to provide quadrature signals at frequencies in . below 5 GHz although it is, for example, particularly advantageous for operating frequencies above 5 GHz.

[0044] [Fig.l] represents an embodiment of an LO oscillator, and [Fig.2] represents, in the form of blocks, an embodiment of a device 2 comprising two LO oscillators in quadrature, that is to say interconnected to each other so as to operate in quadrature or, in other words, so as to provide two signals in quadrature.

[0045] As seen in [Fig.l], the LO oscillator comprises a load 100 ("tank" in English) of parallel LC type. The load 100 comprises a capacitor C and an inductance L. The capacitor C has a selectable (controllable) value from at least two values ​​each corresponding to an operating frequency of the LO oscillators of the device 2.

[0046] In device 2, the two quadrature LO oscillators, referenced respectively 200 and 202 in [Fig.2], are each configured so that, for each operating frequency of the LO oscillators of device 2, the quality factor of the inductance L of the oscillator is lower than that of its capacitance C.

[0047] According to one embodiment, to obtain this relationship between the quality factors of the inductance L and the controllable capacitance C of the oscillator LO, the capacitance C is optimized so that its quality factor is as high as possible, and the inductance L is chosen with a low quality factor which is lower than that of the capacitance C.

[0048] According to one embodiment, the inductance L comprises at least one resistor. This makes it possible to reduce the quality factor of the inductance L compared to the case where the resistor is omitted, so that the quality factor of the inductance L is lower than that of the capacitance C.

[0049] In each LO oscillator, the load 100 is connected between two output nodes A and B of the LO oscillator. For example, the inductor L is connected between the two nodes A and B and the capacitor C is connected between the two nodes A and B, in parallel with the inductor L. More particularly, the capacitor C has an electrode connected to the node A and an electrode connected to the node B.

[0050] Although not shown in [Fig.l], the capacitor C comprises, according to one embodiment, a bank of selectable capacitors, i.e. several capacitors and several switches associated with these capacitors and configured so that each selectable value of the capacitor C corresponds to a given combination of the open and closed states of these switches. In this case, the control signals of the switches are control signals of the capacitor C.

[0051] According to one embodiment, the capacitor C further comprises varicap diodes (varactors), a varicap diode being a diode behaving like a capacitor whose the value varies with the reverse voltage applied to its terminals. In such an embodiment, the capacitor bank allows coarse adjustment of the value of the capacitor C and the varicap diodes allow fine adjustment of the value of the capacitor C. In this case, the signal(s) for selecting or controlling the value of the reverse voltage applied to the terminals of each varicap diode are, in addition to the control signals of the switches of the capacitor bank, control signals of the capacitor C.

[0052] The implementation of capacity C is within the reach of the person skilled in the art from the functional indications given in the present description.

[0053] According to one embodiment, the inductance L of each oscillator LO comprises a first winding L1 and a second winding L2 identical to the winding LL. The windings are connected in series between the nodes A and B of the oscillator LO. More particularly, winding L1 has an end 102 coupled, preferably connected, to a node 112 itself coupled to a node 104 configured to receive a supply potential VDD, and an end 106 coupled to node A, winding L2 having an end 108 coupled, preferably connected, to node 112 and an end 110 coupled to node B. In the example of [Fig.l], ends 102 and 108 of the respective windings L1 and L2 are connected to node 112. Furthermore, in the example of [Fig.l], node 112 is connected to node 104.

[0054] In the example of [Fig.l], the potential VDD is positive and referenced relative to a reference potential GND, for example ground.

[0055] In an embodiment not illustrated, the inductance L is devoid of resistance and only comprises windings, for example the windings L1 and L2. In such an embodiment, the inductance L and the capacitance C remain however configured so that, for each of the operating frequencies of the device 2, the quality factor of the inductance L is lower than that of the capacitance C.

[0056] However, depending on the number and / or the values ​​of the operating frequencies of the device 2, it is difficult or even impossible to have an inductance L whose quality factor is lower than that of the capacitance for each operating frequency of the device 2.

[0057] Thus, according to another embodiment, as indicated previously, the inductance L comprises at least one resistor so as to reduce its quality factor. More particularly, as illustrated in [Fig.l], the inductance L comprises a resistor RI connected in series with the winding L1 between the nodes 112 and A, and a resistor R2 connected in series with the winding L2 between the nodes 112 and B. The resistors RI and R2 have the same resistance value, for example between 0.5 and 5 ohms. By way of example, as shown in [Fig.l], the resistor RI is connected between the end 106 of the winding L1 and the node A, resistor R2 being connected between end 110 of winding L2 and node B.

[0058] According to one embodiment, each resistor RI, R2 is implemented by at least one portion of undoped polycrystalline silicon, i.e., not intentionally doped. For example, in each resistor RI, R2, each portion of polycrystalline silicon of the resistor rests on a semiconductor substrate. By way of example, an insulating layer disposed between the polycrystalline silicon and the substrate to separate the polycrystalline silicon of the resistor from the semiconductor of the substrate, although in other examples this insulating layer may be omitted.For example, in each resistor RI, R2, each polycrystalline silicon portion of the resistor has one end (or one side) electrically coupled to the same portion of conductive layer of a metal level of an interconnection structure resting on the substrate, this conductive portion corresponding, for example, to a first terminal of the resistor, and a second end electrically coupled to the same other portion of conductive layer of this metal level, this other conductive portion corresponding, for example, to a second terminal of the resistor.

[0059] In alternative embodiments, the resistors RI and R2 may each be implemented by a portion of metallic conductive layer of a metal level of an interconnection structure. However, this portion of metallic conductive layer will be subject to electromigration phenomena, which is not the case with polycrystalline silicon.

[0060] Each LO oscillator further comprises transistors T1, T2, T3 and T4. Transistors T1 to T4 are MOS (Metal Oxide Semiconductor) transistors.

[0061] Transistors T1 and T2 each have a first conduction terminal coupled, preferably connected, to node A, and a second conduction terminal coupled to a node 114 configured to receive the reference potential GND. Transistors T3 and T4 each have a first conduction terminal coupled, preferably connected, to node B, and a second conduction terminal coupled to node 114. The first conduction terminal of each transistor T1, T2, T3, T4 corresponds, for example, to the drain of this transistor, its second conduction terminal then corresponding to its source.

[0062] Transistor T1 has its gate coupled, for example connected, to node B, transistor T3 having its gate coupled, for example connected, to node A.

[0063] In the remainder of the description, in each LO oscillator, the gate of transistor T2 is referenced G2 and the gate of transistor T4 is referenced G4. In each LO oscillator, nodes A and B are, for example, outputs of the oscillator, and terminals G2 and G4 are inputs of the oscillator.

[0064] The interconnection of two quadrature oscillators is, for example, illustrated by the figure numbered l(d) of the article "A 900MHz CMOS LC-Oscillator with Quadrature Outputs", and applies to the two oscillators 200 and 202 of the device 2.

[0065] More particularly, as seen in [Fig.2] where the oscillators LO 200 and 202 are each represented by a block comprising two outputs A and B and two inputs G2 and G4, in the device 2: - the input G2 of the oscillator 200 is coupled, for example connected, to the output A of the oscillator 202; - input G4 of oscillator 200 is coupled, for example connected, to output B of oscillator 202; - the input G2 of the oscillator 202 is coupled, for example connected, to the output B of the oscillator 200; and - input G4 of oscillator 202 is coupled, for example connected, to output A of oscillator 200.

[0066] In the example of [Fig.l] where the potential VDD is positive with respect to the potential GND, the transistors T1 to T4 are N-channel MOS transistors or NMOS. In another example not shown where the potential VDD is negative with respect to the potential GND, the transistors T1 to T4 are P-channel MOS transistors, or PMOS.

[0067] For example, transistors T1 and T3 are identical to each other, and transistors T2 and T4 are identical to each other.

[0068] In examples, all transistors T1 to T4 are identical, i.e. they have the same dimensions.

[0069] In other examples, the ratio between the dimensions of the identical transistors T1 and T3 and those of the identical transistors T2 and T4 is determined by a target coupling coefficient between the two oscillators 200 and 202.

[0070] According to one embodiment, the node 112 is connected to the node 104, the ends 102 and 108 of the respective windings L1 and L2 then being, for example, connected to the node 104. Furthermore, the second conduction terminals of the transistors T1 to T4 are coupled to the node 114 by at least one current source. By way of example, in such an embodiment, in each oscillator LO, the gate of the transistor T1 is connected to the node B of the oscillator, the gate of the transistor T3 being connected to the node A of the oscillator. Still by way of example, in such an embodiment, the input G2 of the oscillator 200 is connected to the output A of the oscillator 202, the input G4 of the oscillator 200 is connected to the output B of the oscillator 202, the input G2 of the oscillator 202 is connected to the output B of the oscillator 200, and the input G4 of the oscillator 202 is connected to the output A of the oscillator 200.

[0071] As an example, in an embodiment where the second conduction terminals of transistors T1 to T4 are coupled to node 114 by at least one current source, as illustrated in [Fig.l], in each oscillator LO, a current source 116 is connected between the second conduction terminals of transistors T1 and T3 and node 114, and another current source 118 is connected between the second conduction terminals of transistors T2 and T4 and node 114. The current source 116 has, for example, one terminal connected to the second conduction terminals of transistors T1 and T3 and another terminal connected to node 114, the current source 116 having, for example, one terminal connected to the second conduction terminals of transistors T2 and T4 and another terminal connected to node 114.

[0072] The provision of two current sources 116 and 118 for biasing the transistors T1 and T3, and T2 and T4 respectively, allows the parameter gm of the transistors T1 and T3 to be different from the parameter gm of the transistors T2 and T4.

[0073] As an alternative example not illustrated, in an embodiment where the second conduction terminals of transistors T1 to T4 are coupled to node 114 by at least one current source, in each oscillator LO, a single current source is connected between the second conduction terminals of transistors T1 to T4 and node 114, this current source having, for example, a terminal connected to the second conduction terminal of each of transistors T1 to T4 and another conduction terminal connected to node 114.

[0074] In a non-illustrated alternative embodiment, the second conduction terminals of transistors T1 to T4 are all connected to node 114 and node 112 is coupled to node 104 by a current source, the current source having, for example, a terminal connected to node 112 and a terminal connected to node 104. By way of example, in such an alternative embodiment, in each oscillator LO, the gate of transistor T1 is connected to node B of the oscillator, the gate of transistor T3 being connected to node A of the oscillator. Still by way of example, in such an alternative embodiment, the input G2 of the oscillator 200 is connected to the output A of the oscillator 202, the input G4 of the oscillator 200 is connected to the output B of the oscillator 202, the input G2 of the oscillator 202 is connected to the output B of the oscillator 200, and the input G4 of the oscillator 202 is connected to the output A of the oscillator 200.

[0075] In another alternative embodiment not shown, the second conduction terminals of transistors T1 to T4 are all connected to node 114, and node 112 is connected to node 104. For example, in such an alternative embodiment, in each oscillator LO, the gate of transistor T1 is coupled to node B of the oscillator by a capacitor, the gate of transistor T3 is coupled to node A of the oscillator by a capacitor, the input G2 of oscillator 200 is coupled to output A of oscillator 202 by a capacitor, the input G4 of oscillator 200 is coupled to output B of oscillator 202 by a capacitor, the input G2 of oscillator 202 is coupled to output B of oscillator 200 by a capacitor, and the input G4 of oscillator 202 is coupled to output A of oscillator 200 by a capacitor.

[0076] The device 2 described above makes it possible to obtain a first periodic signal on the output B of the oscillator 200, a second periodic signal on the output A of the oscillator 200, the second signal having the same frequency as the first signal but being phase-shifted by 180° relative to the first signal, a third periodic signal on the output B of the oscillator 202, the third signal having the same frequency as the first signal but being phase-shifted by 90° relative to the first signal, and a fourth periodic signal on the output A of the oscillator 202, the fourth signal having the same frequency as the first signal but being phase-shifted by 270° relative to the first signal. Thus, the signals from the outputs A and B of the oscillator 202 are in quadrature with the signals from the respective outputs A and B of the oscillator 200.

[0077] As an example, the device 2 of [Fig.2] makes it possible to generate two periodic quadrature signals at a frequency selectable from among five frequency values ​​equal respectively to 6.4896 GHz; 7.1136 GHz; 7.7376 GHz; 8.3616 GHz and 8.9856 GHz, while maintaining the oscillators in the same operating mode for each of these values, which was not possible with known quadrature oscillator devices.

[0078] Taking the example above, the value of the resistors RI and R2 is, for example, between 0.5 and 5 ohms, the value of the inductance L, that is to say of the set of the two windings L1 and L2, is, for example, between 300 and 700 pH (pico henry) and each of the values ​​that the capacitance C can take is, for example, between 0.5 and 2 pF (pico farad).

[0079] The person skilled in the art will be able, from the functional description given above, to predict other operating frequency values, and to adapt the values ​​of the inductance L and the variable capacitance C accordingly.

[0080] [Fig. 3] represents, by a schematic top view, an example of an embodiment of the resistors RI and R2 of the oscillators of figures 1 and 2, [Fig. 4] being a sectional view taken in the plane AA of [Fig. 3]. In figures 3 and 4, only the resistor R2 is represented, it being understood that the resistor RI is identical or similar to the resistor R2. In this embodiment, the resistor R2 is implemented by at least one portion of undoped polycrystalline silicon.

[0081] For example, in [Fig. 3] and 4, the resistor R2 is implemented by two portions 300 and 302 of polycrystalline silicon. The provision of two portions 300 and 302 of polycrystalline silicon rather than a single one may result, for example, from constraints of integrated circuit designs in a given manufacturing technology. However, each resistor RI, R2 may also be implemented by a single portion of polycrystalline silicon or by more than two portions of polycrystalline silicon.

[0082] Each portion 300, 302 of polycrystalline silicon of the resistor R2 rests on a semiconductor substrate 304, for example made of monocrystalline silicon.

[0083] In the example shown, the polycrystalline silicon of the portions 300 and 302 rests directly on the substrate 304.

[0084] However, in other examples not illustrated, each portion 300, 302 is separated from the substrate 304 by an insulating layer disposed between the polycrystalline silicon and the substrate. For example, in this case, the insulating layer has a first face in contact with the substrate 304 and a second face in contact with the polycrystalline silicon, the second face being opposite the first face.

[0085] Each portion 300, 302 has an end or a side (at the top in [Fig.3] and on the right in [Fig.4]) which is electrically coupled to the same portion 308 of a conductive layer of a metal level Mtop of an interconnection structure IT resting on the substrate 304. Thus, in the example of FIGS. 3 and 4 where the resistor R2 comprises two portions 300 and 302 of polycrystalline silicon, these two portions are electrically coupled to the portion 308 of the metal level Mtop. The portion 308 of the metal level Mtop corresponds, for example, to a first terminal of the resistor R2, for example connected to the end 110 of the winding L2 of the inductor L ([Fig.l]).

[0086] Symmetrically, each portion 300, 302 has another end or another side (at the bottom in [Fig.3] and on the left in [Fig.4]) which is electrically coupled to the same portion 310 of a conductive layer of the metal level Mtop. Thus, in the example of FIGS. 3 and 4 where the resistor R2 comprises two portions 300 and 302 of polycrystalline silicon, these two portions are electrically coupled to the portion 310 of the metal level Mtop. The portion 310 of the metal level Mtop corresponds, for example, to a second terminal of the resistor R2, for example connected to the node B ([Fig.l]).

[0087] By way of example, each portion 300, 302 is electrically coupled to the portion 308, respectively 310, of the metal level Mtop by means of conductive vias and, for example, one or more portions of conductive layers of one or more metal levels of the IT structure which are arranged between the polycrystalline silicon and the metal level Mtop.

[0088] Preferably, the Mtop level corresponds to the least resistive metal level of the IT structure, that is to say, for example, to the metal level which is the furthest from the substrate.

[0089] In the example of Figures 3 and 4, one end of each of the portions 300 and 302 (at the top in [Fig.3] and on the right in [Fig.4]) is coupled by conductive vias 312 to a corresponding portion 314, 316 of a metal level Mlow of the IT structure, this portion 314, 316 being coupled by conductive vias 318 to the portion 308 of the metal level Mtop. The metal level Mlow is disposed between the substrate 304 and the metal level Mtop. Furthermore, another end of each of the portions 300 and 302 (bottom in [Fig.3] and left in [Fig.4]) is coupled by other conductive vias 312 to a corresponding portion 320, 322 of the metal level Mlow, this portion 320, 322 being coupled by conductive vias 318 to the portion 310 of the metal level Mtop.

[0090] Preferably, the metal level Mlow is the least resistive metal level of the IT structure from which vias 312 can extend to the polycrystalline silicon of the resistor, i.e. the polycrystalline silicon of the portions 300 and 302 in this example. In other words, preferably, the metal level Mlow is the least resistive metal level among all the metal levels of the IT structure from which vias can be formed to the polycrystalline silicon of the resistor.

[0091] Furthermore, although this is not detailed in Figures 3 and 4, the IT interconnection structure generally comprises intermediate metal levels arranged between the Mtop level and the Mlow level. Although this is not detailed in Figures 3 and 4, one or more metal levels may be provided between the Mlow level and the substrate.

[0092] For example, as illustrated in Figures 3 and 4, vias 312 extend from one end of portion 300 to portion 314 of the metal level Mlow, other vias 312 extend from another end of portion 300 to portion 320 of the metal level Mlow, still other vias 312 extend from one end of portion 302 to portion 316 of the metal level Mlow, and still other vias 312 extend from another end of portion 302 to portion 322 of the metal level Mlow. Further, vias 318 extend from each of portions 314 and 316 of the Mlow metal level to portion 308 of the Mtop metal level, and further vias 318 extend from each of portions 320 and 322 of the Mlow metal level to portion 310 of the Mtop metal level.

[0093] An advantage of providing coupling of portions 300 and 302 with the metal level Mtop via vias 318, the metal level Mlow and vias 312 is that the integration density of vias 312 is greater than that of vias 318, which makes it possible to reduce the resistance of the electrical connection between the metal level Mtop and the polycrystalline silicon.

[0094] Although in the above example, the polycrystalline silicon portion 300 is coupled by vias 112 to portions 314 and 320 of the metal level Mlow and the polycrystalline silicon portion 302 is coupled by vias 112 to portions 316 and 322 distinct from the respective portions 314 and 320, this choice is for example linked to design rules of the integrated circuit. Thus, in other examples not illustrated, the portion 314 and the portion 318 of the metal level Mlow form a single and same portion of this metal level, and, similarly, the portion 314 and the portion 318 of the metal level Mlow form a single portion of this metal level.

[0095] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0096] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Device (200) comprising two oscillators (LO; 200, 202) coupled to each other so as to operate in quadrature, each oscillator comprising an inductance (L) and a capacitance (C) with a value selectable from at least two values ​​each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductance (L) is lower than the quality factor of its capacitance (C).

2. Device according to claim 1 wherein, in each oscillator: the inductance (L) comprises first and second identical windings (L1, L2); the first winding (L1) has a first end (102) coupled to a first node (104) for applying a supply potential (VDD) and a second end (106) coupled to a second output node (A) of the oscillator; the second winding (L2) has a first end (108) coupled to the first node (104) and a second end (110) coupled to a third output node (B) of the oscillator; and a first electrode of the capacitor (C) is connected to the second node (A) and a second electrode of the capacitor is connected to the third node (B).

3. Device according to claim 2, wherein, in each oscillator (200, 202), the inductance (L) comprises a first resistor (RI) connected in series with the first winding (L1) between the first and second nodes (104, A), and a second resistor (R2) connected in series with the second winding (L2) between the first and third nodes (104, B), the first and second resistors (RI, R2) having the same resistance value.

4. Device according to claim 3, wherein each of the first and second resistors (RI, R2) has a resistance value between 0.5 and 5 ohms, said at least two values ​​of the capacitance (C) being for example between 0.5 and 2.0 pF and the inductance (L) having for example a value between 300 and 700 pH.

5. Device according to claim 3 or 4, wherein, in each oscillator (200, 202), each of the first and second resistors (RI, R2) is implemented by at least one portion of poly-silicon crystalline (300, 302), preferably undoped.

6. The device of claim 5, wherein each of the first and second resistors (RI, R2) comprises: a first conductive portion (308) of a first metal level (Mtop) of an interconnection structure (IT), the first conductive portion (308) corresponding to a first terminal of the resistor; a second conductive portion (310) of the first metal level (Mtop) corresponding to a second terminal of the resistor; at least a third conductive portion (314, 316) of a second metal level (Mlow) of the interconnection structure (IT); at least a fourth conductive portion (320, 322) of the second metal level (Mlow); first conductive vias (318) electrically coupling the first portion (308) to said at least one third portion (314, 316) and the second portion (310) to said at least one fourth portion (320, 322);and second conductive vias (312) electrically coupling said at least one polycrystalline silicon portion (300, 302) to said at least one third portion (314, 316) and to said at least one fourth portion (320, 322).;

7. Device according to any one of claims 2 to 6, wherein, in each of the oscillators (200, 202), the capacitance (C) comprises a plurality of capacitances associated with switches configured so that each of the at least two values ​​corresponds to a given combination of open and closed states of said switches.

8. The device of claim 7, wherein in each of the oscillators (200, 202), the selectable value capacitor further comprises varicap diodes.

9. A device according to any one of claims 2 to 8, wherein each of the oscillators further comprises: a first MOS transistor (T1) and a second MOS transistor (T2) each having a first conduction terminal connected to the second node (A) and a second conduction terminal coupled to a fifth node (114) for applying a reference potential (GND), the first transistor (T1) having its gate coupled to the third node (B); a third MOS transistor (T3) and a fourth MOS transistor (T4) each having a first conduction terminal connected to the third node (B) and a second conduction terminal coupled to the fifth node (114), the third transistor (T3) having its gate coupled to the second node (A).

10. The device of claim 9, wherein: the second transistor (T2) of a first (200) of the two oscillators (200, 202) has its gate coupled to the second node (A) of a second (202) of the two oscillators (200, 202); the fourth transistor (T4) of the first oscillator (200) has its gate coupled to the third node (B) of the second oscillator (202); the second transistor (T2) of the second oscillator (202) has its gate coupled to the third node (B) of the first oscillator (200); and the fourth transistor (T4) of the second oscillator (202) has its gate coupled to the second node (A) of the first oscillator (200).

11. The device of claim 9 or 10, wherein each of the oscillators comprises: a first current source (116) having a first terminal connected to the second conduction terminals of the first and third transistors (T1, T3) of the oscillator, and a second terminal connected to the fifth node (114); and a second current source (118) having a first terminal connected to the second conduction terminals of the second and fourth transistors (T2, T4) of the oscillator, and a second terminal connected to the fifth node (114).

12. A device according to any one of claims 1 to 11, wherein each operating frequency value falls within a range of 5 GHz to 10 GHz.

13. A device according to any one of claims 1 to 12, wherein the operating frequency values ​​comprise a first value between 5 and 6.5 Ghz and a second value between 8.5 and 10 Ghz.

14. A device according to any one of claims 1 to 13, wherein each of the operating frequency values ​​is separated from the other operating frequency values ​​by at least 0.5 GHz.

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