POLYCRYSTALLINE SILICON CARBIDE SUPPORT FOR A SUBSTRATE INTENDED TO RECEIVE POWER SEMICONDUCTOR DEVICES AND SUBSTRATE COMPRISING SUCH A SUPPORT.

Abstract

The invention relates to a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support has a first face, designated the "front face," and a second face, designated the "back face," and comprises a first surface layer disposed directly under the front face and having a resistivity greater than or equal to 1 ohm.cm, and a second surface layer disposed directly under the back face and having a resistivity strictly less than 1 ohm.cm. Figure 3

Description

Title of the invention: POLYCRYSTALLINE SILICON CARBIDE SUPPORT FOR A SUBSTRATE INTENDED TO RECEIVE POWER SEMICONDUCTOR DEVICES AND SUBSTRATE COMPRISING SUCH A SUPPORT. FIELD OF INVENTION

[0001] The present invention relates to substrates for receiving semiconductor devices, particularly devices used in applications requiring high electrical power. These devices may be based on ILN materials, such as gallium nitride. The invention also relates to a support particularly suited for forming such a substrate. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Transistors based on IILN materials, of the HEMT type ("High Electron Mobility Transistor" according to Anglo-Saxon terminology or high electron mobility transistor) find some of their applications in the field of managing significant electrical power, for example as switches in power converters.

[0003] As schematically represented in [Fig. 1], such a component 1 puts conventionally implemented: - a substrate 2 which can typically be a silicon, sapphire or silicon carbide wafer; - a buffer layer 3, usually doped to be semi-insulating, formed on substrate 2; - a heterojunction consisting of a GaN channel layer 5 and a layer barrier 6 of AlGaN formed successively on the buffer layer; - source electrode structures S, drain electrode structure D and gate electrode structure G on / in the heterojunction. - A metallic foil M in ohmic contact with the back face of the substrate 2. The foil M may be the copper lead frame (often referred to in Anglo-Saxon terminology in this field) of a semiconductor chip package. An adhesion layer B, for example a sintered silver paste, may be used to reliably bond the back face of the substrate 2 to the metallic foil M.

[0004] The metallic foil M helps to facilitate the dissipation of heat produced at the heterojunction during the operation of the device. Generally, the source electrode S is electrically connected to the substrate 2, so as to prevent that The potential of this substrate does not remain floating. The electrically conducting state of the transistor between the source S and the drain D is controlled by the voltage applied to the gate G. In the case of power application, the voltage VDS applied across the source S and drain D electrodes can reach several hundred volts to several thousand volts at the transistor's cutoff point. The leakage current flowing between the source S and the drain D in the cutoff state is low, on the order of a few nanoamperes. In contrast, in the conducting state, several amperes can flow between the source S and the drain D. Furthermore, the switching between the conducting and cutting states is very fast, on the order of a few nanoseconds.

[0005] Several problems, however, limit the diffusion of this technology.

[0006] As we have seen, in the blocking state, a high voltage is applied across the terminals of the source electrode S and the drain electrode D. This leads to the formation of an electric field whose lines penetrate very deeply into the buffer layer 3 and the substrate 2. An electric field then develops between the drain electrode D and the substrate 2, particularly in the thickness of the buffer layer 3, and between the source S and the drain D. In order to prevent the intensity of this field from exceeding the critical value (called the breakdown field) beyond which the material can no longer withstand it, the drain D and the source S must be separated by a sufficient distance d so that, for a given voltage VDs, the intensity of the field E = VDs / d is less than the breakdown field.Similarly, a buffer layer 3 of sufficient thickness can be provided so that the value of the electric field at the interface between the buffer layer 3 and the substrate 2 is less than the permissible limit for the materials in question.

[0007] It is relatively easy to choose the distance d separating the drain electrode D from the source S during the design of the transistor. Thus, for a VDS voltage on the order of 400 V to 2000 V, a distance d on the order of 5 to 20 microns can be chosen. However, increasing this distance has its limits, as it tends to increase the size of the HEMT device and therefore make it more expensive and less compact.

[0008] Providing a device 1 with a sufficiently thick buffer layer 3 made of IILN material (on the order of 3 microns or more) is, however, much more difficult, particularly when the substrate 2 is chosen to be made of large silicon (200 mm in diameter) rather than sapphire, for reasons of availability and cost. This is mainly due to the difference between the coefficient of thermal expansion of silicon and that of the IILN material that forms the buffer layer. This layer is produced by high-temperature deposition on the silicon substrate, and the return to ambient temperature puts this layer under very high stresses, which can lead to cracking, or even breakage of the substrate, if the stresses are too great. It is generally difficult to provide a buffer layer thicker than 3 microns on a silicon substrate in the form of a 200 mm wafer.

[0009] One could naturally seek to replace the silicon substrate with a substrate having a coefficient of thermal expansion closer to that of the buffer layer material in order to overcome this constraint. For example, a silicon carbide substrate could be used. However, besides the fact that this material in its crystalline form is particularly scarce and expensive, it must also be metallized and treated to form an ohmic contact with the metal sheet M. The document "Ohmic contacts to SiC" International Journal of High Speed ​​Electronics and Systems, Vol. 15, No. 04, pp. 781-820 (2005) notes that a metal-SiC layer contact is generally non-ohmic immediately after the metal layer is depositioned.It is then necessary to thermally treat this interface, for example with a laser, to promote the formation of silicides, carbides, or ternary phases, thus making the contact effectively ohmic. Simplifying the device's housing would be desirable. SUBJECT OF THE INVENTION

[0010] One object of the invention is to provide a support for a substrate intended to receive a power semiconductor device that addresses, at least in part, these problems. More particularly, one object of the invention is to provide a support for a substrate capable of receiving a relatively thick buffer layer, preferably with a thickness greater than or equal to 5 microns, and which can be easily integrated into a package without requiring heat treatment on the surface receiving the adhesion layer. Another object of the invention is to provide a substrate that utilizes such a support and a semiconductor component formed on / in such a substrate. BRIEF DESCRIPTION OF THE INVENTION

[0011] To achieve one of these objectives, the object of the invention provides a polycrystalline silicon carbide support for a substrate intended to receive a power semiconductor device. The support comprises a first face, designated the "front face," and a second face opposite the first, designated the "rear face." The support comprises: - a first surface layer positioned directly under the front face and having a resistivity greater than or equal to 1 ohm.cm and; - a second surface layer arranged directly under the back face and having a resistivity strictly less than 1 ohm.cm.

[0012] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: the second layer has a minimum thickness of 10 micrometers or more; • the second layer having a concentration of n-type dopants, such as nitrogen, greater than 10A20 at / cmA3; • the concentration of n-type dopant increases monotonically from the front face to the second surface layer; • the first layer is not intentionally doped or has a vanadium concentration greater than 10A15 at / cmA3; • the support has a total thickness, between the first face and the second face, of between 200 micrometers and 1 mm; • The support is in the form of a circular plate, advantageously 200 mm in diameter

[0013] According to another aspect, the object of the invention provides a substrate for receiving a semiconductor device comprising a support as described above and a seed layer, located on the front face of the support

[0014] According to other advantageous and non-limiting features of this aspect of the invention, taken alone or in any technically feasible combination: - the seed layer is made of gallium nitride, silicon carbide, sapphire or silicon (1,1,1); - the substrate includes a dielectric bonding layer disposed between, and in contact with, the support and the seed layer, preferably a silicon nitride dielectric bonding layer; - the germ layer makes direct contact with the support; - a buffer layer based on gallium nitride, preferably semi-insulating, is placed on the seed layer; - the buffer layer has a thickness greater than 3 microns, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers; - the substrate includes a heterojunction disposed on the buffer layer, the heterojunction comprising a channel layer and a barrier layer and being capable of forming a 2D electron gas.

[0015] According to yet another aspect, the invention proposes a semiconductor component comprising a substrate as described above and a source structure, a drain structure and a gate structure disposed on the heterojunction.

[0016] Advantageously, a metal foil is disposed under the rear face of the support, in ohmic contact with a metal layer deposited on the second surface layer. An adhesion layer, such as a layer of sintered silver paste, can be disposed between the metal foil and the metal layer deposited on the second surface layer. Brief description of the drawings

[0017] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0018] [Fig.1]

[0019] Fig. 1 represents a substrate equipped with a HEMT transistor according to the prior art;

[0020] [Fig.2a][Fig.2b]

[0021] Figures 2a, 2b represent two substrates intended to receive semiconductor devices according to the invention;

[0022] [Fig.3]

[0023] Figure [Fig. 3] represents a semiconductor component formed from a substrate according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] For the sake of simplicity in the following description, the same references are used for identical elements or elements performing the same function in the different modes of implementation of the invention or in the presentation of the prior art.

[0025] Figures 2a and 2b show two embodiments of a substrate 2 intended to receive a power semiconductor device, which is the subject of this description. As briefly explained in the introduction to this application, this substrate 2 is intended to receive at least one device comprising a buffer layer of IILN material several microns thick, a heterojunction comprising a channel layer and a barrier layer on the buffer layer, and source, drain, and grid structures arranged on the heterojunction.

[0026] The substrate 2, when still free of devices, advantageously takes the form of a circular wafer, the diameter of which is standardized so that it can be handled by standard equipment in the semiconductor industry. Advantageously, a diameter of 200 mm is chosen.

[0027] After the device formation and individualization steps, chips are formed, as is well known, which are intended to be integrated into packages to form a semiconductor component. The substrate 2, when incorporated into a chip, then takes the form of a rectangular parallelepiped with sides on the order of mm or cm. General presentation of substrate 2

[0028] Whatever form the substrate 2 takes, it generally comprises a support 2a and a seed layer 2c transferred onto the support 2a. In the embodiment of [Fig. 2a], a dielectric bonding layer 2b is disposed between, and in contact with, the support 2a and the seed layer 2c. In the embodiment of In the [Fig.2b] configuration, substrate 2 is devoid of a dielectric bonding layer and the seed layer 2c is transferred directly onto the support 2a, in contact with this support 2a.

[0029] The support 2a is made entirely of polycrystalline silicon carbide. It comprises a first face, designated the "front face," and a second face opposite the first, designated the "back face." The seed layer is transferred to the front face of the support, either directly or via the bonding dielectric layer 2c. The main function of the support 2a is to mechanically support the rest of the stack, which leads to the formation of a functional semiconductor component, as will be explained in a later section of this detailed description. To this end, it has a relatively large thickness, measured between its front and back faces, typically between 200 micrometers and 1 mm.

[0030] The seed layer 2c, for its part, serves to provide an exposed surface of the support 2 suitable for receiving the buffer layer 3 of the device. The nature of this layer is therefore chosen to offer a lattice parameter adapted to that of the IILN material forming the buffer layer 3, typically gallium nitride, in order to facilitate its growth by epitaxy on the support 2. It can therefore be gallium nitride, silicon carbide, sapphire, or silicon (1,1,1), in all cases in their single-crystal form. This seed layer 2c does not need to be thick, since only its surface properties are exploited, and a relatively small thickness, less than 2 micrometers, will therefore be chosen.

[0031] The dielectric bonding layer 2c serves to facilitate the fabrication of the substrate 2, as will be explained later. A dielectric material with a good thermal diffusion coefficient, such as silicon nitride, is preferred, and its thickness is minimized, preferably less than 1 micrometer, so as not to affect the thermal properties of the substrate 2, as will be explained later.

[0032] It is noted that the seed layer 2c is significantly thinner than the thickness of the support 2a. Consequently, and due to compliance, it undergoes the deformations imposed on it by the support 2a, for example when the substrate 2 is exposed to significant temperature variations of several hundred degrees, as is the case during the epitaxial formation of the buffer layer 3. In other words, the deformation of the substrate 2 caused by its exposure to a significant temperature variation is dictated by the behavior of the support 2a. It is to promote this compliance effect that the thickness of the seed layer is chosen to be relatively small, less than 2 micrometers, as already mentioned.

[0033] It is also noted that the polycrystalline silicon carbide from which support 2a is formed has a coefficient of thermal expansion close to that of the material 1ILN from which it is The buffer layer 3 is composed of a specific material, particularly when this buffer layer 3 is made of gallium nitride. Furthermore, after the formation of buffer layer 3 by high-temperature epitaxy, and when the substrate 2 bearing this layer is cooled to room temperature, few stresses develop in the structure. It is therefore possible to form a buffer layer 3 much thicker than that achievable on a prior art silicon substrate. Specifically, a buffer layer 3 can be formed with a thickness of at least 3 micrometers, preferably greater than 5 micrometers, and even more preferably between 5 and 10 micrometers.

[0034] Finally, the polycrystalline silicon carbide from which support 2a is formed (which represents the major part of substrate 2) possesses thermal diffusion properties that allow for efficient dissipation of the heat generated within the device. It should be noted that since this device is preferably intended for processing significant electrical power, it tends to heat up, and it is necessary to dissipate the heat generated to avoid affecting its proper operation. Thus, the thermal diffusion coefficient of polycrystalline silicon carbide is approximately three times greater than that of the silicon used in a prior art substrate. By improving the thermal conductivity of substrate 2 compared to a prior art substrate, the power density processed within the device can also be increased.

[0035] According to an important feature of the support 2a, it comprises a first surface layer Cl, located directly beneath the front face, which has a resistivity greater than or equal to 1 ohm.cm, and advantageously greater than 10A³ ohm.cm. In the presence of a strong electric field whose lines extend into the depth of the substrate 2, and particularly into this first surface layer Cl of the support, the resistive nature of this first surface layer Cl allows the breakdown voltage to rise. The device can therefore withstand high drain-source voltages, exceeding 1000V, without risk of damage to the device.

[0036] To obtain these resistivity values, the first Cl layer is intrinsic in nature, that is to say, it is not intentionally doped. Alternatively, it can be doped with vanadium at a concentration greater than 1OA15 at / cmA3, in order to further increase its resistivity.

[0037] The support 2a also includes a second surface layer C2, this time disposed directly under the rear face. This second surface layer C2 has a resistivity strictly less than 1 ohm.cm, and can be less than 50 milliohm.cm or 10 milliohm.cm. This low resistivity, which can be obtained by n-type doping in a dopant concentration (for example, nitrogen) greater than 10A20 at / cmA3, allows the back face of the substrate to have an almost metallic behavior, and therefore to receive a layer of metal or metal alloys, by deposition, without the need for heat treatment before applying an assembly process of this face to a metal sheet, during the boxing stage.

[0038] It is not necessary for this second surface layer C2 to be very thick, it nevertheless has a thickness greater than 10 micrometers.

[0039] Preferably, the first Cl layer extends through the depth of support 2 to the second, heavily doped layer C2. A transition zone may, of course, exist between these two Cl and C2 layers to control the doping gradient necessary for this transition. In particular, the concentration of n-type dopant in support 2a may be considered to increase monotonically from the front face to the second surface layer C2.

[0040] But in all cases, and regardless of how the dopants are distributed within the thickness of the support 2a, the latter has a first surface layer C1 disposed directly under the front face, as close as possible to the device, which is resistive or highly resistive to counteract the effects of electric fields that may develop there. The support 2a also has a second surface layer C2, disposed directly under the rear face, which is very weakly resistive to give it a metallic behavior that promotes its robust bonding to a metal foil during the packaging of the device.

[0041] Fabrication of the support in crystalline silicon carbide

[0042] The manufacture of a polycrystalline silicon carbide support according to the invention, and therefore having the first and second surface layers C1,C2, employs a chemical vapor deposition (CVD) technique. This technique involves a gaseous mixture comprising at least one silicon precursor gas (such as a silane or a chlor-rosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyl trichlororosilane, abbreviated MTCS) to form the bulk part of the support 2a.

[0043] It also involves at least one n-type dopant gas to, at a minimum, form the second surface layer C2. In the case of nitrogen doping of this second surface layer C2, the dopant gas could, for example, be NH3, N2H4, or N2.

[0044] For vanadium doping of the first surface layer Cl, in the case where such doping is planned, a vanadium chloride dopant gas (VC12, for example) may be used.

[0045] These gases can be diluted in a carrier gas, which can be a reducing gas such as hydrogen and / or an inert gas such as argon. From this gaseous mixture, the A layer of polycrystalline silicon carbide forms on a substrate called a "growth substrate".

[0046] The gas mixture is admitted into a reactor at high temperature where the precursor gases are decomposed and react on the surface of the growth substrate, preferably fine-grained purified isostatic graphite, to form a layer of polycrystalline silicon carbide, for example polytype 3C, whose mechanical and thermal resistance properties, coefficient of thermal expansion and purity are perfectly suited for its use as support 2a of substrate 2. Polytype 3C can, moreover, be doped with nitrogen up to very high levels, on the order of 1020 atoms / cm3, and thus exhibit a resistivity of less than 10 μΩ·cm.

[0047] The reactor temperature during CVD deposition of silicon carbide must be between approximately 1000°C and approximately 1600°C, preferably between approximately 1100°C and approximately 1400°C, or even between approximately 1200°C and approximately 1400°C. Within this temperature range, deposition rates can vary considerably, from micrometers / h to more than 100 micrometers / h. Advantageously, the total pressure in the reactor does not exceed 350 mbar, or even 300 mbar.

[0048] To form a support 2a according to the invention, the flow of n-type dopant gas is controlled to form, at the beginning of the growth process, possibly after the formation of a seed layer on the graphite surface, a sufficiently thick layer of doped polycrystalline silicon carbide to ultimately constitute, after all the finishing steps described below, the second surface layer C2 of the support 2a. This may involve forming an n-type doped layer during this growth, which is 2 to 10 times thicker than the expected thickness in this support, which, it should be noted, is typically greater than 10 micrometers after possible thinning of the substrate.

[0049] During this deposition phase, after forming the heavily doped thickness n, the flow of n-type dopant gas can either be interrupted to form the remainder of the thickness in intrinsic, unintentionally undoped polycrystalline silicon carbide. Alternatively, a vanadium-based dopant gas flow can be circulated to further increase the resistivity of the material intended to form the first surface layer CL

[0050] Following this deposition phase, the graphite growth substrate, coated with a layer of polycrystalline silicon carbide, is machined and then oxidized in air, typically at 900°C, to remove any graphite residue and provide a raw polycrystalline silicon carbide disc. It should be noted that the graphite removal could also be achieved using purely mechanical machining techniques or primarily by burning / oxidation.

[0051] It is noted that it is possible to form, during the deposition phase, a very thick layer of polycrystalline silicon carbide to constitute a material ingot. Slices can then be taken from this ingot by cutting, each slice forming a raw silicon carbide disc. In this approach, care will be taken to insert, during the growth of the ingot, highly doped interlayers (which will be intended to form second surface layers C2) between intrinsic or vanadium-based doped layers (which will be intended to form first surface layers Cl). The ingot will be cut in positions allowing, after all the finishing steps described below, the formation of supports according to the invention.

[0052] In any event, a raw polycrystalline silicon carbide disc resulting from the deposition phase is then mechanically and thermally treated to form the support 2a with the chosen dimensions. This may involve thinning steps by coarse and then fine grinding. These may be followed by a polishing step to provide a satisfactory surface finish in terms of roughness. These grinding or polishing steps, known in the prior art, aim in particular to remove sufficient thickness from the side of the disc face that was in contact with the graphite, in order to eliminate the initial crystal growth zone, which generates high stresses.They also allow, by removing material from both sides of the raw disc, obtaining a polycrystalline silicon carbide support 2a which is in the form of a wafer, for example a wafer with a diameter of 200 mm and a thickness typically between 350 micrometers and 500 micrometers, but which can extend for example between 200 nm and 1 mm. Fabrication of substrate 2.

[0053] Very generally, substrate 2 can be produced by a manufacturing process involving the transfer of a seed layer onto support 2a, the preparation of which has just been described. Such a transfer process comprises: - the assembly, possibly via a dielectric bonding layer 2b, of the first face of the support 2a and a main face of a donor substrate in order to constitute an intermediate structure; - the removal of part of the donor substrate of the intermediate structure to define the seed layer 2c, transferred onto the support 2a.

[0054] The bonding dielectric layer 2b can be formed, by deposition and prior to the assembly step, on the donor substrate or on the front face of the support 2a or partly on both of these two elements. The bonding dielectric layer 2b can thus be produced according to an LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Poly- Saxon "Plasma Enhanced Chemical Vapor Deposition" or plasma-enhanced chemical vapor deposition). As already mentioned, this layer is advantageously made of silicon nitride, for reasons of thermal diffusivity.

[0055] The term "donor substrate" refers to a substrate made of the material of the seed layer 2c, or comprising a surface layer of this material. For example, the donor substrate may be formed from a bulk substrate of single-crystal gallium nitride, single-crystal (1,1,1) silicon, sapphire, or single-crystal silicon carbide. As a further example, it may be in the form of a composite substrate consisting of a first substrate on which rests a layer (at least equal to that of the seed layer 2c) of the material whose seed layer is to be formed. This may, in particular, be a layer of a III-N material such as gallium nitride formed on a silicon (1,1,1) substrate.

[0056] The assembly step of the layer transfer manufacturing process is advantageously implemented by molecular adhesion. As is well known, during a molecular adhesion process, the first face of the support 2a and one face of the donor substrate (possibly coated with a dielectric layer to form the bonding dielectric layer 2b), perfectly clean, flat, and smooth, are brought into intimate contact to promote the development of molecular bonds, for example, van der Waals or covalent bonds. The two bodies are then joined without the use of an adhesive. These bonds can be strengthened by applying a heat treatment to the intermediate structure thus formed.When it is desired to form a substrate 2 without a dielectric bonding layer, the first face of the support 2a and the face of the donor substrate are not provided with a dielectric layer, and are brought into direct intimate contact with each other.

[0057] The step of removing part of the donor substrate can be carried out by mechano-chemical thinning of this substrate.

[0058] Preferably, however, substrate 2 is manufactured by applying Smart Cut™ technology, whereby a layer intended to form the seed layer 2c is delimited by means of a weakening plane formed by implanting so-called "light" species (typically hydrogen and / or helium) into the donor substrate. After the assembly step, this layer is removed from the donor substrate by fracturing at the weakening plane and thus transferred to support 2a.

[0059] Whether the removal of part of the thickness of the donor substrate is carried out by thinning or by fracturing, any type of finishing treatment can be applied to the substrate thus formed to conform the germ layer 2c to specifications of thickness, uniformity of thickness, roughness or any other type of specifications.

[0060] In the substrate 2 thus formed, the rear face of the support 2, beneath which the second surface layer C2 is disposed, also forms the rear face of the substrate. The first surface layer Cl is disposed directly beneath the seed layer 2c (or directly beneath the bonding dielectric layer 2b, when this layer is present).

[0061] It should be noted that when the donor substrate material is polar, it is necessary to perform a double transfer of the seed layer 2c taken from it, first transferring this seed layer 2c onto an intermediate substrate and then, in a second transfer, onto the polycrystalline silicon carbide support 2a. In this way, the seed layer 2c exhibits its initial polarity on this support 2a. This is particularly the case when the donor substrate comprises gallium nitride, this material having, in its most readily available form, a gallium face, which is generally desired to be exposed, and a nitrogen face. Semiconductor component manufacturing

[0062] The substrate 2, in the form of a wafer, is used to form at least one semiconductor component. Thus, as explained in a previous passage and illustrated in [Fig. 3], a buffer layer 3 based on IILN material is formed by epitaxy on the exposed face of the seed layer 2c of substrate 2. Preferably, the main layer 3 is doped to make it semi-insulating. This could be, for example, carbon doping with a concentration in the main layer ranging from 5.10A18 to 5.10A19 at / cmA3. It could also be another p-type doping, for example with iron or magnesium.

[0063] It is possible to position one or more interlayers, for example AlGaN or more generally AlInGaN, within the buffer layer 3, which is primarily made of gallium nitride. In all cases, the lattice parameter of the seed layer 2c and the coefficient of thermal expansion of the polycrystalline silicon carbide support 2a are particularly well-suited to the nature of the buffer layer 3 material, which is IILN. Consequently, it is possible to form a relatively large thickness of this buffer layer 3 on the substrate 2, for example, a thickness greater than 3 micrometers, preferably greater than 5 micrometers, and even more preferably between 5 and 10 micrometers.

[0064] In a subsequent step of preparing the semiconductor component 1, a heterojunction is formed on the buffer layer 3. As is well known, such a heterojunction combines at least one channel layer 5 (for example, in GaN) and a barrier layer 6 (for example, in AlGaN). A 2D electron gas is likely to develop at the interface of these two layers. Then, a source structure S, a drain structure D, and a gate structure G are arranged on the heterojunction 5.

[0065] In some cases, it is possible to thin the substrate 2 by removing a thickness of support 2a on the side of the second surface layer C2. Care will be taken, however, to preserve a sufficient thickness of this layer C2, greater than or equal to 10 microns.

[0066] In a subsequent step, a metallic layer is formed on the rear face of the support 2a, in contact with the second surface layer C2. This metallic layer can be of any suitable material, for example titanium, aluminum, nickel, gold, or a stack of these materials. Due to the high doping of the second surface layer C2 and its low resistivity, the contact with the metallic layer is ohmic, without the need for heat treatment of this interface, which constitutes a particularly advantageous characteristic of a support according to the invention.

[0067] A large number of devices are usually formed collectively on the substrate 2 in the form of wafers. These devices are then isolated by cutting the wafer on which they rest, to form semiconductor chips. These chips are packaged to form semiconductor components 1, which are assembled to a metallic foil M using an adhesive, such as a sintered silver paste, forming a particularly reliable adhesion layer B for a power component.

[0068] Of course the invention is not limited to the modes of implementation described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Claims

1. Support (2a) made of polycrystalline silicon carbide for a substrate (2) intended to receive a power semiconductor device, the support comprising a first face, designated "front face" and a second face opposite the first and designated "rear face", the support comprising: - a first surface layer (Cl) arranged directly under the front face and having a resistivity greater than or equal to 1 ohm.cm and; - a second surface layer (C2) arranged directly under the rear face and having a resistivity strictly less than 1 ohm.cm.

2. Polycrystalline silicon carbide support (2a) according to the preceding claim in which the second surface layer (C2) has a thickness of 10 micrometers or more.

3. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in which the second surface layer (C2) has a concentration of n-type dopants, such as nitrogen, greater than 10A20 at / cmA3.

4. Support (2a) made of polycrystalline silicon carbide according to the preceding claim in which the concentration of n-type dopant increases monotonically from the front face to the second surface layer (C2).

5. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in which the first surface layer (Cl) is not intentionally doped or has a vanadium concentration greater than 10A15 at / cmA3.

6. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims having a total thickness, between the first face and the second face, of between 200 micrometers and 1 mm.

7. Support (2a) made of polycrystalline silicon carbide according to one of the preceding claims in the form of a circular plate, advantageously 200 mm in diameter.

8. Substrate (2) intended to receive a semiconductor device comprising a support (2a) according to one of the preceding claims and a seed layer (2c) transferred to the front face of the support (2a).

9. Substrate (2) according to the preceding claim in which the seed layer (2c) is made of gallium nitride, silicon carbide, sapphire or silicon (1,1,1).

10. Substrate (2) according to one of the two preceding claims comprising a dielectric bonding layer (2b) arranged between, and in contact with, the support (2a) and the seed layer (2c), preferably a dielectric bonding layer (2b) made of silicon nitride.

11. Substrate (2) according to claim 8 or 9, wherein the seed layer (2c) directly contacts the support (2a).

12. Substrate (2) according to one of claims 8 to 11 comprising a buffer layer (3) based on gallium nitride, preferably semi-insulating, arranged on the seed layer (2c).

13. Substrate (2) according to the preceding claim in which the buffer layer (3) has a thickness greater than 3 microns, preferably greater than 5 micrometers and even more preferably between 5 micrometers and 10 micrometers.

14. Substrate (2) according to one of claims 12 and 13 comprising a heterojunction arranged on the buffer layer (3), the heterojunction comprising a channel layer (5) and a barrier layer (6) and being capable of forming a 2D gas of electrons.

15. Semiconductor component (1) comprising a substrate (2) according to the preceding claim and a source structure (S), a drain structure (D) and a gate structure (G) arranged on the heterojunction.

16. Semiconductor component (1) according to the preceding claim comprising a metal sheet (M) arranged under the rear face of the support, in ohmic contact with the second surface layer (C2).

17. Semiconductor component (1) according to the preceding claim comprising an adhesion layer (B), such as a sintered silver paste layer, arranged between the metal sheet (M) and the second surface layer (C2).

18. Semiconductor component (1) according to one of the two preceding claims comprising a metal layer arranged against the second surface layer (C2).

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