Method for producing a stress state in a semiconductor layer

Abstract

Title: Method for producing a stress state in a semiconductor layer The invention relates to a method for producing a uniaxial stress state (C3, C3') in a semiconductor layer (13), said method comprising: - A provision of a stack comprising a support (10), the semiconductor layer (13) and an intercalated fusible layer (11), - A formation of a stress-donor layer (14) on the semiconductor layer (13), - A partial alteration of the stress-donor layer (14), modifying a first stress state (C1) of the layer (14) to obtain a second stress state (C2) in a single direction (y), - A melting of the fusible layer (11f), so that the stress-donor layer (14) transfers by relaxation the second stress state (C2, C2') into the semiconductor layer (13). Figure for abstract: Fig. 7

Description

Title of the invention: Method for producing a stress state in a semiconductor layer Technical field

[0001] The present invention relates to the field of microelectronics and, more particularly, to that of methods for mechanically deforming or constraining a semiconductor layer. A particular application concerns the production of Complementary Metal-Oxide-Semiconductor CMOS transistors (acronym for "Complementary Metal-Oxide-Semiconductor") on a fully depleted silicon-on-insulator (FDSOI) type substrate (acronym for "Fully Depleted Silicon On Insulator"). STATE OF THE ART

[0002] In this field, it is desirable to increase the mobility of charge carriers to achieve the best compromises between performance and energy consumption.

[0003] The mobility of electrons can typically be increased (respectively decreased) by a mechanical stress in tension (respectively in compression) of the semiconductor material in which they transit, whereas the mobility of holes can conversely be increased (respectively decreased) when the semiconductor is in compression (respectively in tension).

[0004] Thus, to improve the performance of the transistors, it is possible to provide for their channel region to be made of a semiconductor material having a mechanical stress in tension or compression. Typically, for transistors whose channel is made of silicon and of type N (the majority carriers are electrons), the most favorable configurations are a channel in biaxial tension or in uniaxial tension following the direction of electronic transport if the uniaxial stress is greater than or equal to 1.4 GPa. For transistors whose channel is made of silicon-germanium and of type P (the majority carriers are holes), the most favorable configuration is a channel in uniaxial compression following the direction of electronic transport.

[0005] Document FR3120738 A1 discloses an indirect method for modifying a stress state of a semiconductor layer. This method is based on the use of a fusible layer interposed between the semiconductor layer to be deformed and the support. A stress donor layer is furthermore deposited on the semiconductor layer to be deformed. A heat treatment is then carried out to melt the fusible layer. The stress donor layer then imposes a biaxial deformation on the semiconductor layer. This biaxial deformation of the semiconductor layer remains after solidification of the fusible layer and removal of the stress-donor layer. To obtain uniaxial stress, the semiconductor layer is then typically cut into strips so that the stress relaxes along the width of the strips. Only the stress along the length of the strips remains.

[0006] This cutting into strips consumes material. This loss of material results in a reduced integration density.

[0007] An objective of the present invention is to overcome the limitations of this known method.

[0008] In particular, an object of the present invention is to provide a method of rea lization of a uniaxial stress state in a semiconductor layer, allowing a higher integration density. SUMMARY

[0009] To achieve this objective, according to one embodiment, a method is provided for producing a uniaxial stress state in a semiconductor layer, said method comprising at least: • A supply of a stack comprising a support, the semi-conductor layer and a so-called fusible layer interposed between the support and the semi-conductor layer, • Formation of a stress-giving layer on the semiconductor layer, • A definition of patterns after formation of the stress donor layer, • A formation, from said patterns, of regions surrounded by trenches extending into the semiconductor layer, • A partial alteration of the stress donor layer at said regions, configured to modify a first stress state of said stress donor layer so as to obtain a second stress state mainly in a determined direction, • At least partial melting of the fusible layer, so that the stress-donor layer transfers at least in part, by relaxation, the second stress state into the semiconductor layer, so that the semiconductor layer has a uniaxial stress state along said determined direction.

[0010] Thus, unlike the known method mentioned above, the transformation of an initial stress state, in this case the first stress state, which is typically a biaxial stress state, into a uniaxial stress state, in this case the second stress state, is done prior to the melting of the fusible layer, upstream of the transfer of the stress state into the semiconductor layer. The stress state transferred from the stress-donor layer, during melting, is thus directly a uniaxial stress state. There is no need to implement further stress state modification steps in the semiconductor layer after this transfer. In particular, the material-intensive cutting steps of the semiconductor layer are eliminated.

[0011] The transfer of a uniaxial stress state according to the invention also makes it possible to increase the thickness of the semiconductor layer free of crystal defects. In the known method, the transferred stress state is a biaxial stress state. For a given stress intensity, the critical thickness of the material (from which plastic relaxation of the stress generating crystal defects is observed) is higher when the stress is uniaxial than when it is biaxial. Directly transferring a uniaxial stress state into the semiconductor layer thus makes it possible to produce a semiconductor layer without crystal defects that is thicker than that achievable by the known method.

[0012] Furthermore, modifying the stress state upstream of the transfer offers more possibilities in terms of stress state engineering. The modification can typically be configured to produce a uniaxial compressive stress state or a uniaxial tensile stress state, which is no longer possible after transfer by simple cutting of the semiconductor layer as in the prior art.

[0013] The modification of the first stress state into a second uniaxial stress state is done by partial alteration of the stress donor layer. This alteration can advantageously be carried out by usual steps of microelectronics, such as localized implantation or etching of trenches in the stress donor layer.

[0014] Consequently and advantageously, the method for producing a uniaxial stress state in a semiconductor layer according to the present invention allows in particular a saving of material and better versatility with respect to the known method previously described. By implementing the method according to the present invention, the integration density can be advantageously increased.

[0015] Another aspect of the invention relates to a method of manufacturing a transistor comprising implementing the method of producing a uniaxial stress state according to the invention. According to this manufacturing method, the transistor comprises a channel region produced in the semiconductor layer having the uniaxial stress state.

[0016] Other objects, features and advantages of the present invention will become apparent from a consideration of the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0017] In particular, the aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of at least one embodiment thereof which is illustrated by the following accompanying drawings in which:

[0018] [Fig.l] [Fig.l] illustrates in section a stack according to an embodiment of the present invention.

[0019] [Fig.2] [Fig.2] illustrates in top view the stack illustrated in [Fig.l], according to an embodiment of the present invention.

[0020] [Fig.3] [Fig.3] illustrates in section a method step (formation of isolation trenches and regions) according to an embodiment of the present invention.

[0021] [Fig.4] [Fig.4] illustrates in top view the method step (formation of isolation trenches and regions) illustrated in [Fig.3], according to an embodiment of the present invention.

[0022] [Fig.5] [Fig.5] illustrates in section a process step (formation of bands implanted in the stress donor layer) according to an embodiment of the present invention.

[0023] [Fig.6] [Fig.6] illustrates in top view the method step (formation of implanted bands in the stress donor layer) illustrated in [Fig.5], according to an embodiment of the present invention.

[0024] [Fig.7] [Fig.7] illustrates in section a process step (partial melting of the fusible layer) according to an embodiment of the present invention.

[0025] [Fig.8] [Fig.8] illustrates in top view the process step (partial melting of the fusible layer) illustrated in [Fig.7], according to an embodiment of the present invention.

[0026] [Fig.9] [Fig.9] illustrates in section a process step (removal of the stress donor layer) according to an embodiment of the present invention.

[0027] [Fig. 10] [Fig. 10] illustrates in top view the process step (removal of the stress donor layer) illustrated in [Fig.9], according to an embodiment of the present invention.

[0028] [Fig. 11] [Fig. 11] illustrates in section a process step (formation of relaxation trenches in the stress donor layer) according to another embodiment of the present invention.

[0029] [Fig. 12] [Fig. 12] illustrates in top view the method step (formation of relaxation trenches in the stress donor layer) illustrated in [Fig.l 1], according to another embodiment of the present invention.

[0030] [Fig. 13] [Fig. 13] illustrates in section a process step (filling the isolation trenches) according to another embodiment of the present invention.

[0031] [Fig. 14] [Fig. 14] illustrates in top view the process step (filling of the isolation trenches) illustrated in [Fig. 13], according to another embodiment of the present invention.

[0032] [Fig. 15] [Fig. 15] illustrates in section a process step (removal of the stress donor layer) according to another embodiment of the present invention.

[0033] [Fig. 16] [Fig. 16] illustrates in top view the process step (removal of the stress donor layer) illustrated in [Fig. 15], according to another embodiment of the present invention.

[0034] [Fig. 17] [Fig. 17] illustrates the dependence of the strain obtained in a 10 nm silicon film on 20 nm buried oxide as a function of the Young's modulus and the strain of a 100 nm thick strain donor layer, according to an embodiment of the present invention.

[0035] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular the thicknesses of the different layers and the dimensions of the different patterns which are illustrated by diagrams which are not representative of reality. DETAILED DESCRIPTION

[0036] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

[0037] According to one example, the method further comprises filling the trenches to form isolation trenches, after melting of the fusible layer and before removal of the stress donor layer. This makes it possible to confine certain regions of the semiconductor layer between the isolation trenches to avoid relaxation, typically along the uniaxial stress direction y, of the semiconductor layer regions after removal of the stress donor layer. This makes it possible, for example, to increase the uniaxial stress state. This makes it possible, for example, to limit stress losses during the transfer of the stress state in the semiconductor layer.

[0038] According to one example, the partial alteration comprises an implantation of ions in a portion of the stress donor layer forming implanted bands oriented in the determined direction, said implanted bands extending over an entire dimension of the stress donor layer in the determined direction. This implantation is typically carried out along the entire thickness of the stress donor layer. The width of the implanted bands is preferably less than or equal to half the thickness of the stress donor layer. Typically, if the bands implanted bands aim to relax the stress donor layer in an x direction, the width along x of the implanted bands is preferably chosen to be as small as possible (this minimum width is typically set by the resolution of the lithography equipment used to produce the mask defining the bands to be implanted). If the implanted bands aim to induce a state of uniaxial compression along y in the stress donor layer, the width along x of the implanted bands can be chosen to be of the order of half the thickness of the stress donor layer, or even of the order of one third of the thickness of the stress donor layer. The length along y of the implanted bands is typically much greater, i.e. at least ten times greater, than the thickness of the stress donor layer. This limits or avoids relaxation of the stress donor layer along y.

[0039] According to one example, the regions have a dimension in the determined direction significantly greater than the thickness of the stress-donor layer, typically at least six times greater than the thickness of the stress-donor layer. This makes it possible to optimize the uniaxial stress transfer in the determined direction in the semiconductor layer.

[0040] According to one example, the implanted ions are argon-based. The stress state of the stress donor layer is thus modified without exposing the underlying semiconductor layer. The semiconductor layer therefore remains protected from other process steps, typically during the formation, filling and planarization of the isolation trenches.

[0041] According to one example, the first stress state is substantially zero and the second stress state corresponds to uniaxial compression. The stress donor layer may be initially relaxed, before alteration. Implantation of argon in strips oriented in the determined direction typically makes it possible to generate such uniaxial compression in a SiN-based stress donor layer, for example.

[0042] According to one example, the first stress state corresponds to a biaxial tension and the second stress state corresponds to a uniaxial tension. The stress-donating layer, for example based on SiN, may initially be in biaxial tension, before alteration. Implanting argon in bands oriented in the determined direction typically makes it possible to relax the stress in these bands. The stress-donating layer then has relaxed bands and a residual stress state in uniaxial tension between the relaxed bands.

[0043] According to one example, the partial alteration comprises a formation of relaxation trenches in the stress-donor layer, oriented in the determined direction. It is thus possible to pass from a state of biaxial stress to a state of uniaxial stress by forming relaxation trenches in the stress-donor layer, preferably throughout the thickness of the stress-donor layer.

[0044] According to one example, the relaxation trenches are separated by strips of stress donor layer having a width approximately equal to one half of the thickness of the stress donor layer.

[0045] According to one example, the partial alteration comprises a formation of relaxation trenches in the stress donor layer of certain regions, and an implantation of ions in bands of the stress donor layer for other regions. The two types of partial alteration can thus coexist for different regions of the same plate or wafer.

[0046] According to one example, the stack comprises an insulating layer between the semiconductor layer and the fusible layer. According to one example, the insulating layer is silica-based. It preferably has a thickness of between 10 nm and 25 nm. This architecture typically corresponds to FDSOI technology. The low stiffness of the silica, which has a Young's modulus E of the order of 50 GPa, and the limited thickness promote the transmission of a stress state between the stress-giving layer and the semiconductor layer.

[0047] According to one example, the stress donor layer is based on silicon nitride. This material has the advantage of being transparent in the UV, in a range of wavelengths suitable for melting the fusible layer. It can also be advantageously used for filling isolation trenches, typically shallow STI (acronym for "Shallow Trench Isolation") trenches implemented for lateral isolation in FDSOI technology. The steps of filling the isolation trenches and depositing the stress donor layer can thus be carried out simultaneously, at least in part. This reduces the number of steps and the cost of the process.

[0048] According to a preferred possibility, the melting is carried out by thermal annealing of the rapid thermal annealing type, typically over the entire extent of the fusible layer, i.e. over the entire wafer. The use of rapid thermal annealing allows collective heating of the regions formed in the semiconductor layer, independently of the dimensions of said regions. According to another example, this thermal annealing is carried out using a nanosecond laser, typically by scanning the wafer with the laser beam. The use of a laser allows rapid and localized thermal elevation of the stack of layers to a predetermined temperature allowing the melting of the fusible layer while avoiding untimely diffusion of atoms in the stack. The thermal budget thus remains limited.According to one example, the laser is a pulsed laser having pulses whose duration is less than one microsecond and preferably between 10 ns and 1000 ns, advantageously between . 20 ns and 500 ns. The laser has a wavelength typically between 100 nm and 550 nm, and preferably between 250 nm and 400 nm.

[0049] According to one example, the fusible layer is amorphous. This makes it possible to lower the melting point of the fusible layer, compared to a fusible layer based on the same material in crystalline form. For example, a fusible layer based on SiGe in crystalline form containing 65% Ge melts around 1100°C, while a fusible layer based on SiGe in amorphous form containing 65% Ge melts below 1000°C.

[0050] According to one example, the amorphous fusible layer is formed by epitaxy before being amorphized by implantation. This makes it possible to obtain an amorphous fusible layer that is not very rough and contains little hydrogen.

[0051] In one example, the semiconductor layer is based on silicon or silicon-germanium and the fusible layer is based on silicon-germanium or germanium and has a higher germanium content than the semiconductor layer. The higher the germanium content, the lower the melting point. Advantageously, the fusible layer melts while the semiconductor layer remains in the solid state. The relative compositions of the fusible and semiconductor layers are typically chosen for this purpose. In one example, the semiconductor layer is based on silicon-germanium or germanium and the fusible layer is based on silicon-germanium and tin or germanium and tin. Tin further lowers the melting point of the germanium-based alloys.

[0052] Unless incompatibility exists, technical features described in detail for a given embodiment may be combined with technical features described in the context of other embodiments described by way of example and not limitation. In particular, elements described or illustrated for certain embodiments of the method may be combined so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0053] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0054] A layer may also be composed of several sub-layers of the same material or of different materials.

[0055] A substrate, a stack, a layer, “based” on a material A, is understood to mean a substrate, a stack, a layer comprising this material A only or this material A and possibly other materials, for example alloying elements and / or doping elements. Thus, a silicon-based layer is understood to mean, for example, a Si, n-doped Si, p-doped Si layer.

[0056] The present invention notably allows the production of a uniaxial stress state in a semiconductor layer. This semiconductor layer typically corresponds to the upper layer, called "topSi", of a silicon on insulator (SOI) substrate. The invention can be implemented for the production of various microelectronic devices or components according to architectures of the FDSOI, FinFET (field effect transistor whose channel is formed in the shape of a fin or a fin, "fin" in English) or even "nanosheet" (stack of thin layers forming the active layers of the transistors) type. The invention can also be implemented for the production of various optoelectronic devices or components, for example lasers, birefringent waveguides or amplifiers.The invention can be implemented more widely for the production of any device comprising a thin semiconductor layer having a uniaxial stress state.

[0057] Several embodiments of the invention implementing successive steps of the production method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0058] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0059] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of phases of the process.

[0060] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0061] In the present patent application, the thickness of a layer is taken along a direction normal to the main extension plane of the layer. The height of a device or the depth of a pattern, for example a trench, are taken along the z direction. Thus, a layer typically has a thickness along z and a trench typically has a depth along z. The related terms "on", "overlies", "under", "underlying" refer to positions taken along the z direction.

[0062] The terms "vertical", "vertically" refer to a direction along z. The terms "horizontal", "horizontally" refer to a direction in the xy plane. The term "lateral" refers to an xz or yz plane. Thus, the lateral flanks of the isolation trenches extend parallel to a yz and / or xz plane. Unless explicitly stated, the thickness, height and depth are measured along z.

[0063] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

[0064] The method comprises a definition of patterns after formation of the stress donor layer, and a formation of regions in the semiconductor layer from said patterns. These patterns and regions are not comparable to a partial alteration of the stress donor layer. These patterns and regions are intended to structure the stack, in particular with a view to integration within functional devices such as transistors. The dimensions of these patterns, in particular along y and / or along x, are much greater than the dimensions of the implanted strips or relaxation trenches, in particular much greater than their thickness or their height.

[0065] A state of mechanical stress is generally described by a tensor. In the context of the present invention, only the diagonal components of the tensor, and in particular the components in the xy plane, are considered.

[0066] By mechanical deformation of a semiconductor layer we mean that its material has its crystal lattice parameter(s) lengthened or shortened.

[0067] In the case where the deformed mesh parameter is greater than the so-called "natural" parameter of a crystalline material, it is said to be in tension deformation. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be in compressive deformation or compression.

[0068] These states of mechanical deformation are associated with states of mechanical stress. However, it is also common to refer to these states of deformation as states of mechanical stress. In the remainder of this application, this notion of deformation (“strain” according to English terminology) will be referred to generically by the term “constraint”, or “stress” in English.

[0069] The stress-giving layer is also called a “stressor” according to English terminology.

[0070] Fusion is understood to mean the transition, in a transient manner, of at least a given thickness of the fusible layer from a solid state to a liquid state. Advantageously, the fusible layer material has a melting or liquidus temperature lower than the melting or liquidus temperature of the semiconductor material of the semiconductor layer.

[0071] In the following, the term "absorption" or its equivalents refers to the phenomenon by which the energy of an electromagnetic wave is transformed into another form of energy, for example in the form of heat. In the present description, a material is considered to be absorbent when it absorbs at least 50% of light radiation, preferably at least 75% and advantageously at least 90%. It can be characterized by an absorption factor of between 0 and 1.

[0072] Furthermore, a layer is said to be transparent when it has a transmission coefficient greater than or equal to 50%, preferably 75%, or even 90% for a central wavelength of the spectral range of the incident electromagnetic radiation.

[0073] To determine the composition and stress state of the different layers, electron microscopy analyses can be carried out, in particular Scanning Electron Microscopy (SEM) or Transmission Electron Microscopy (TEM or TEM).

[0074] The chemical compositions of the different layers or regions can be determined using the well-known EDX or X-EDS method, an acronym for "energy dispersive x-ray spectroscopy" which means "energy dispersive analysis of X-ray photons".

[0075] This method is well suited for analyzing the composition of thin layers such as the semiconductor layer and the stress donor layer. It can be implemented on metallurgical sections within an SEM or a TEM.

[0076] Precessional electron diffraction (PED) can be implemented within a TEM to determine the stress state of thin layers such as the semiconductor layer. Other electron microscopy or diffraction techniques are also conceivable. Optical spectroscopy techniques, for example Raman spectroscopy, can also be implemented.

[0077] These techniques make it possible in particular to determine the state of stress of the semiconductor layer, and the arrangement and composition of the different layers within the stack.

[0078] A semiconductor layer in uniaxial tension above a “solidified” layer based on silicon-germanium (corresponding to a fusible layer), may be indications of implementation of the method according to the present invention.

[0079] [Fig.l] illustrates a stack comprising a support 10, a fusible layer 11, an insulating layer 12, a semiconducting layer 13 and a donor layer of constraint or stressor 14.

[0080] The support 10 typically corresponds to a massive substrate, called “bulk”, made of monocrystalline silicon. The support 10 typically has a resistivity of the order of 20 Q.cm. For certain applications, for example for RF applications, the support 10 may have a resistivity greater than or equal to 100 Q.cm. The stack may comprise other layers, typically between the substrate 10 and the fusible layer 11. A layer of porous silicon or a layer comprising a zone capable of trapping a large quantity of mobile charges (generally referred to as “trap rich”) may for example be intercalated between the substrate 10 and the fusible layer 11.

[0081] The fusible layer 11 is preferably based on a monocrystalline or polycrystalline SiGe alloy whose Ge content is chosen so that the liquidus of the alloy is notably lower than that of the rest of the stack, and in particular lower than the liquidus or the melting point of the semiconductor layer 13. A difference in melting / liquidus temperature between the semiconductor layer 13 and the fusible layer 11 greater than or equal to 50°C, and preferably greater than or equal to 80°C, is typically required. Thus, the choice of the composition of the fusible layer 11 is made relative to the composition of the semiconductor layer 13.

[0082] For example, when the semiconductor layer 13 is made of silicon, the fusible layer 11 may have a germanium content of between 30% at and 99% at, advantageously between 40% at and 70% at.

[0083] If the semiconductor layer 13 contains germanium, the fusible layer 11 may contain tin. This helps to maintain an acceptable melting / liquidus temperature difference between the semiconductor layer 13 and the fusible layer 11.

[0084] The fusible layer 11 can be formed by epitaxy or by chemical vapor deposition (CVD) on the support 10. The fusible layer 11 typically has a thickness of between 5 nm and 20 nm.

[0085] When the semiconductor layer 13 is formed directly in contact with the fusible layer 11, by epitaxy, the fusible layer 11 is preferably monocrystalline. The thickness of the fusible layer 11 is preferably less than its critical thickness for plastic relaxation (see for example, in the case of a fusible layer 11 based on SiGe on a support 10 based on Si, the document “Critical thickness for plastic relaxation of SiGe on Si(001) revisited” by JM Hartmann et al. published in Journal of Applied Physics 110, 083529 (2011)). This avoids the formation of dislocations in the semiconductor layer 13 during the growth of the semiconductor layer 13 on the fusible layer 11.

[0086] According to one possibility, the fusible layer 11 is amorphous. This makes it possible to lower the melting point of the fusible layer 11, in comparison with a crystalline fusible layer 11 of the same chemical composition. For example, a fusible layer with SiGe-based layer in crystalline form with a Ge concentration of 65%at melts around 1100°C, while a fusible layer based on SiGe in amorphous form with the same Ge concentration of 65%at melts below 1000°C.

[0087] The amorphous fusible layer 11 can be formed in two steps. A first step consists of epitaxying the fusible layer 11 in crystalline form on the support 10. A second step consists of amorphizing the fusible layer 11 by ion implantation. This makes it possible to obtain an amorphous fusible layer that is not very rough and contains little hydrogen.

[0088] The implantation conditions for the amorphization of at least a portion of the thickness of the fusible layer 11 may be defined using a simulation tool, for example using C-TRIM type software (CTRIM for “Crystal Transport of Ions in Matter”) using algorithms based on the Monte Carlo method. For the specific case of a Si semiconductor layer 13 and a SiGe fusible layer 11, Si ions may be used for example. The implanted dose is calculated so as to cause the amorphization of the SiGe fusible layer. A typical dose range for SiGe may be between 1.5el4 and 3el4 at / cm2. The amorphization depth preferably extends along the entire thickness ε of the fusible layer 11.

[0089] The insulating layer 12 is optional. It can be of the “buried oxide” or “BOX” type (meaning “Burried Oxide” in English) in an SOI (“Silicon On Insulator”) architecture. It is preferably based on silica, and has a thickness e^ typically between 10 nm and 25 nm. The low stiffness of the silica, which has a Young’s modulus E of the order of 50 GPa, and the limited thickness promote the transmission of a stress state between the stress-donating layer 14 and the semiconductor layer 13. This configuration is favorable in the case of an FDSOI architecture. For certain applications, for example in the case of a structure with high vertical capacitance, the insulating layer 12 can alternatively be based on a material with high permittivity. In this case, the insulating layer 12 can be based on alumina A12O3 or a silicon-hafnium oxynitride HfSiON with thicknesses e^ between 5 nm and 25 nm.

[0090] The semiconductor layer 13 is typically intended to form one or more active zones of a microelectronic device. The semiconductor layer 13 is based on a doped or intrinsic semiconductor material. It may have P-type or N-type doping, depending on the applications.

[0091] According to one example, the semiconductor layer 13 is made of monocrystalline silicon and has a thickness of between 5 nm and 20 nm. To produce the corresponding SOI substrate, a low-temperature manufacturing sequence can be advantageously used, for example as disclosed in document FR3116940 A1 or in document FR3125631 A1, incorporated here by reference. Such a low-temperature manufacturing sequence makes it possible to remain below the liquidus temperature of the fusible layer 11 during the formation of the semiconductor layer 13. Such a low-temperature manufacturing sequence can be implemented in particular when the fusible layer 11 contains more than 60% Ge, or when it is desirable for it to remain amorphous before melting and transfer of the stress state into the semiconductor layer 13.

[0092] According to another example, the semiconductor layer 13 is based on a SiGe alloy with an atomic fraction of Ge of between 10% and 60%. In this case, the semiconductor layer 13 preferably has a thickness less than the critical thickness, typically between 5 nm and 20 nm. When such a semiconductor layer 13 is used, the fusible layer 11 typically has a higher Ge content and possibly contains Sn.

[0093] According to another example, the semiconductor layer 13 comprises a plurality of alternating monocrystalline layers of silicon and silicon-germanium. The silicon-germanium layers may typically comprise between 20 and 60% of Ge. Each of the monocrystalline layers typically has a thickness of between 5 nm and 10 nm. Such a semiconductor layer 13 notably allows the formation of “nanosheet” type transistors.

[0094] The stress donor layer or stressor 14 is preferably based on silicon nitride SiN. This material has the advantage of being transparent in the UV, in a range of wavelengths suitable for the melting of the fusible layer 11. This material is also widely used for other process steps in the field of microelectronics. It is well known and perfectly compatible with many applications. Furthermore, the melting temperature of silicon nitride is of the order of 1900°C, which is strictly higher than that of silicon and most semiconductors used as the semiconductor layer 13 and / or fusible layer 11. The stressor 14 thus remains in the solid state during the stress transfer step involving the melting of the fusible layer 11. The stressor 14 typically has a thickness eu of between 30 nm and 200 nm.

[0095] The stressor 14 may be deposited by CVD on the semiconductor layer 13. This deposition may be plasma-assisted. According to one possibility, a thin oxide, of the order of 1 nm to 5 nm, is formed on the semiconductor layer 13 before the deposition of the silicon nitride-based stressor 14 (not shown). This makes it easier to subsequently remove the stressor 14.

[0096] According to one possibility, the SiN-based stressor 14 is deposited without internal stress. Alternatively, different stress states can be obtained during the deposition of the SiN. According to one possibility, a SiN-based stressor 14 in tensile stress, ty pitting up to 1.5 GPa, can be formed by CVD deposition. Alternatively, a SiN-based stressor 14 under compressive stress, typically up to -2 GPa or even -3 GPa, can be formed by CVD deposition. Further details on the type of stress as a function of the type of deposition or deposition conditions can be found in the document "A comparison of the mechanical stability of Silicon nitride films deposited with varying techniques" by Pierre Morin et al. published in Applied Surface Science 260 (2012) 69-72, in the case of a silicon nitride-based stressor 14.

[0097] Other materials can be used for the stressor 14, for example A12O3 or Ga2O3. The parameters to be taken into account for the choice of the stressor material 14 are mainly the transparency in the UV (when the melting is done by laser), the ability to be deposited with a high internal stress and a relatively low Young's modulus. [Fig. 17] illustrates the dependence of the strain obtained in a 10 nm thick Si layer on a 20 nm thick buried oxide layer, as a function of the Young's modulus E and the initial stress sO of a 100 nm thick stressor. A stressor based on silicon nitride deposited by plasma-enhanced CVD (PECVD) typically having an initial compressive stress of -2 GPa makes it possible to obtain a strain of the Si layer between 1 and 1.5%.

[0098] As illustrated in [Fig.2], a region of the semiconductor layer to be deformed may be previously defined by means of a pattern 100. This may be a sequence common to the FDSOI manufacturing process aimed at forming active areas of transistors. The pattern 100 typically comprises a mask protecting the stack in the region to be preserved.

[0099] As illustrated in Figures 3, 4, a structuring of the stack can be carried out by etching the exposed areas, around the pattern 100. This etching can be carried out by dry etching RIE (acronym for “Reactive Ion Etching”). The etching is typically carried out along the entire thickness of the stack, at least up to the base of the fusible layer 11, typically to a depth of approximately 200 nm from the upper face of the semiconductor layer 13. Trenches 110 surrounding a region RI of the semiconductor layer 13 are thus formed. One or more steps of defining patterns and etching can be chained together, for example in the context of a structuring called “double patterning”, depending on the dimensions targeted for the region RI and the lithography equipment used.Different trench depths 110 can also be achieved, for example in the context of so-called “double STI” technology.

[0100] It is advantageous to define RI regions of the largest possible dimension in the y direction to optimize the uniaxial stress transfer along y in the layer semiconductor 13. One possibility is to provide consecutive active zones of the same conductivity type (N or P) abutted along the y direction (direction of current flow) by replacing the separation trenches 110 with inactive gates. Such an organization is called "continuous active zone" or "continuous RX". According to one possibility, the dimension along y of the RI region is greater than or equal to six times the stressor thickness. This makes it possible to reach the maximum stress value theoretically transferable by the stressor, by moving away from the free edge of the RI region. The continuous active zone topology ultimately makes it possible to obtain more highly constrained transistor channels, produced from a stressor of given constraint and thickness.

[0101] After structuring, the stressor 14 overlying the semiconductor layer 13 in the RI region has a biaxial stress state Cl in the xy plane. In [Fig.4], the biaxial stress state Cl illustrated for the stressor 14 is in compression. As mentioned above, this stress state Cl can be alternatively in tension or zero.

[0102] As illustrated in Figures 5, 6, according to one embodiment, the stressor 14 is altered by the formation of bands 40 directed along y. This alteration modifies the biaxial stress state C1 to produce a uniaxial stress state C2.

[0103] A first way to alter the stressor 14 is to implant the strips 40 of the stressor 14 with argon ions. The implantation energy is preferably chosen so that the argon ions remain confined within the thickness eM of the stressor 14 while being distributed homogeneously along the thickness eu of the stressor 14. This implantation typically changes the stress of the strips 40 of stressor 14 by shifting the initial stress in the compression direction. The implanted dose, the implantation energy and the thickness eM of the stressor 14 determine the intensity of the resulting stress shift. For example, implanting 3xl0el5 at / cm2 of argon at 30 keV into a 100 nm layer of silicon nitride causes a stress shift of approximately -4 GPa, in the compression direction. By reducing the argon dose to lxl0el4 at / cm2 at an energy of 30 keV, the shift approaches -1.5 GPa, which is sufficient to relax an initially tensile stressor 14 to 1.5 GPa.

[0104] The implantation is preferably performed after a lithographic masking configured to define and expose strips 40 of stressor 14, and mask strips 41 of stressor 14.

[0105] According to one possibility, the initial biaxial stress state C1 of the stressor 14 is in tension at 1.5 GPa. The implantation then forms substantially relaxed nitride bands 40. The stress state C2 of the stressor 14 obtained at the end of the implantation is generally in uniaxial tension at 1.5 GPa. This is due to the non-implanted bands 41 of stressor 14 which have not relaxed in the y direction. The lithography is preferably configured so that the bands 41 have a width Lu along x approximately equal to half the thickness eM of the stressor 14. The strips 40 preferably have a width l40 along x as small as permitted by the lithography.

[0106] According to another possibility, the initial biaxial stress state Cl of the stressor 14 is relaxed. The implantation then forms bands 40 of nitride in compression, for example at -1.5 GPa for an implanted dose of lxl0el4 at / cm2 at 30 keV. In this case, the stress state C2 of the stressor 14 obtained at the end of the implantation is generally in uniaxial compression at -1.5 GPa. In this case, the bands 40 preferably have a width l40 along x approximately equal to half the thickness eM of the stressor 14, and the bands 41 preferably have a width Lu along x as small as permitted by the lithography.

[0107] This embodiment of alteration by implantation has the advantage of keeping the RI region(s) entirely covered by the stressor 14. The stress state of the stressor is thus modified without exposing the underlying semiconductor layer 13. The semiconductor layer 13 therefore remains protected from other process steps, typically during the formation, filling and planarization of the isolation trenches.

[0108] Apart from the RI regions intended to be placed under uniaxial stress, the same masking and implantation steps advantageously make it possible to obtain regions that are totally implanted or totally non-implanted, i.e. totally relaxed or under biaxial stress. Furthermore, if the lithography allows the definition of bands in several directions of the xy plane, uniaxial stresses in different directions of the xy plane can be obtained. The method therefore advantageously makes it possible to produce different uniaxial stress states on certain regions, while allowing the joint production of biaxial or relaxed stress states in other regions.

[0109] As illustrated in Figures 7, 8, after alteration of the stressor 14, a heat treatment is applied to the stack. This heat treatment is configured to at least partially melt the fusible layer 11, which becomes a melted layer 1 If. This makes it possible to release the stresses imposed on the upper layers 12, 13, 14 by the support 10 and / or the fusible layer 11. All of the layers 12, 13, 14 can thus relax into a configuration of lower elastic energy. In particular, the stressor 14 will at least partially relax by transferring all or part of its stress state C2 to the underlying semiconductor layer 13, and possibly to the insulating layer 12. The stressor 14 has, after relaxation, a residual stress state C2' lower than the stress state C2, or even substantially zero.A good transfer of the stress state C2 in the semiconductor layer 13 is favored by relatively low Young's moduli for the stressor 14 and / or the insulating layer 12 with respect to the semiconductor layer 13. The residual stress state C2' is then minimized.

[0110] In practice, according to a preferred possibility, the heat treatment can be carried out by rapid thermal annealing of the RTA type (acronym for “Rapid Thermal Annealing”). This type of RTA annealing advantageously allows a relatively homogeneous heat transfer over the entire extent of the fusible layer, at the wafer level, without significant influence of the size of the RI regions. According to another possibility, the heat treatment is carried out using a laser, in particular by subjecting the stack to one or more laser pulses. The heat treatment conditions disclosed by document FR3120738 A1 are directly applicable to the method according to the invention. At the end of the laser treatment step, the return to a solid state of the fusible layer 11 makes it possible to freeze the stress in the semiconductor layer 13.The heat treatment step leading to the temporary melting of the fusible layer 11 thus allows a modification of the stress state within the semiconductor layer 13. The use of a laser allows a rapid thermal rise of the stack of layers to a predetermined temperature allowing the melting of the fusible layer 11 and the modification of stress in the semiconductor layer 13, while limiting the thermal budget used. This makes it possible to avoid an untimely diffusion of atoms in the stack. The use of the laser also allows rapid cooling of the stack, once the exposure to the laser has stopped. Another advantage of this type of heat treatment by laser beam is that the modification of the stress state can be done locally, in a spatially targeted manner.

[0111] According to one example, the heat treatment step is carried out using a laser by emitting one or more successive laser pulses, the duration of each pulse being less than one microsecond and preferably between 10 ns and 1000 ns, advantageously between 20 ns and 500 ns. The laser has a wavelength typically between 100 nm and 550 nm and preferably between 250 nm and 400 nm. Long wavelengths may be favored to avoid or limit the influence of the size of the RI regions, in the xy plane, on the energy absorbed by the stack and in particular by the fusible layer 11. This makes it possible to ensure homogeneous stress transfer conditions over a wider range of RL region sizes.

[0112] The wavelength of the laser, the pulse duration of the laser beam and preferably the energy density of the laser beam are chosen as a function of the stack of layers 11, 12, 13, 14, so as to allow the melting, at least locally, of the material of the fusible layer 11 while retaining at least one continuous film of the semiconductor layer 13 in the solid state.

[0113] According to a particular embodiment, an energy density of between 0.01 and 2J / cm2 can be provided. The person skilled in the art can rely on a combination of simulation tools, for example as mentioned in the document “LIAB: a FEniCS based computational tool for laser annealing simulation”, by Lamagna et al., 2017, to determine the conditions for rapid laser thermal annealing.

[0114] According to one possibility, after a first stress transfer, the stressor 14 can be replaced or modified again, and a second stress transfer involving a second melting of the fusible layer 11 can be carried out. This makes it possible to increase the final stress state of the semiconductor layer 13.

[0115] As illustrated in Figures 9, 10, after transfer, the stressor 14 can be removed. The semiconductor layer 13 then retains a state of uniaxial stress C3. If the stressor 14 was in uniaxial tension, the semiconductor layer 13 is typically in uniaxial compression. If the stressor 14 was in uniaxial compression, the semiconductor layer 13 is typically in uniaxial tension, as illustrated in [Fig. 10]. In the case of a technology based on mesa isolation, there is no filling of the trenches 110 between RI regions, nor planarization step.

[0116] According to one possibility, after the stress transfer, a long annealing at a temperature lower than the liquidus of the fusible layer 11 SiGe is carried out. This makes it possible to diffuse the germanium into the support 10. The liquidus temperature of the fusible layer 11 is increased. This makes it possible to avoid the melting of the fusible layer 11 later.

[0117] Figures 11, 12 illustrate another embodiment of the step of altering the stressor 14. According to this embodiment, the alteration of the stressor 14 is obtained by forming by etching relaxation trenches 42 in the thickness eM of the stressor 14. These relaxation trenches 42 preferably have a depth equal to the thickness eM of the stressor 14. They are mainly directed along y and regularly spaced apart along x. This makes it possible to obtain strips 41 of stressor 14 in uniaxial stress along y. The strips 41 have a width Lu along x approximately equal to half the thickness eM of the stressor 14. The relaxation trenches 42 preferably have a width 142 along x as small as permitted by the lithography and the etching. These relaxation trenches 42 make it possible to transform the biaxial stress state Cl of the stressor 14 into the uniaxial stress state C2.This embodiment is notably directly applicable to all types and values of the non-zero biaxial stress state Cl.

[0118] If the lithography allows the definition of trenches 42 in several directions of the xy plane, uniaxial stresses in different directions of the xy plane can be obtained. Furthermore, outside the RI regions intended to be placed under uniaxial stress, the superposition of trenches 42 along x and along y advantageously makes it possible to obtain totally relaxed regions. Typically such a grid of trenches 42 is configured to form approximately square stressor blocks 14, with a side length of the order of half the thickness ei4 of the stressor. The method therefore advantageously allows different uniaxial stress states to be achieved in certain regions, while allowing the joint achievement of relaxed stress states in other regions.

[0119] Figures 13, 14 illustrate another embodiment in which the trenches 110 are filled to form isolation trenches 20, after transfer of the stress state by temporary fusion of the fusible layer 11, and before removal of the stressor 14. The RI regions are thus confined laterally between the isolation trenches 20 before removal of the stressor 14. This makes it possible to avoid relaxation by the free edges of the stack.

[0120] As illustrated in Figures 15, 16, after removal of the stressor 14, the uniaxial stress state C3' in the semiconductor layer 13 is thus increased. According to one possibility, the isolation trenches 20 extend only along yz planes, parallel to the direction of the uniaxial stress. This further promotes the increase in uniaxial stress in the semiconductor layer 13.

[0121] Through the examples described above, it appears clearly that the method for producing a uniaxial stress state in a semiconductor layer according to the invention is particularly advantageous for applications in the field of microelectronics and / or optoelectronics. The production of transistors on such a uniaxially stressed semiconductor layer benefits in particular from a significant increase in the mobility of the charge carriers, in particular for FDSOI MOSFET, FinFET and stacked channel MOSFET (“nanosheet”) architectures.

[0122] The invention is not limited to the embodiments previously described. Different combinations of alteration of the stressor and structuring of the stack can be envisaged. These steps can be reversed or alternated.

Claims

Claims

1. Method for producing a uniaxial stress state (C3, C3') in a semiconductor layer (13), said method comprising at least: - A provision of a stack comprising a support (10), the semiconductor layer (13) and a fusible layer (11) interposed between the support (10) and the semiconductor layer (13), - A formation of a stress-donor layer (14) on the semiconductor layer (13), - A definition of patterns (100) after formation of the stress-donor layer (14), - A formation, from said patterns (100), of regions (RI) surrounded by trenches (110) extending into the semiconductor layer (13), - A partial alteration of the stress-donor layer (14) at the level of said regions (RI),configured to modify a first stress state (Cl) of said stress-donating layer (14) so as to obtain a second stress state (C2) mainly in a determined direction (y), - An at least partial melting of the fusible layer (1 If), so that the stress-donating layer (14) transfers at least in part, by relaxation, the second stress state (C2, C2') into the semiconductor layer (13), so that the semiconductor layer (13) has a uniaxial stress state (C3) in said determined direction (y).,

2. A method according to the preceding claim further comprising filling the trenches (110) to form isolation trenches (20), after melting the fusible layer (11) and before removing the stress-giving layer (14).

3. A method according to any one of the preceding claims wherein the partial alteration comprises implantation of ions into a portion of the stress donor layer (14) forming im- planted (40) oriented in the determined direction (y), said implanted strips (40) extending over an entire dimension of the stress-giving layer (14) in the determined direction (y).

4. Method according to the preceding claim in which the first stress state (Cl) is substantially zero and the second stress state (C2) corresponds to uniaxial compression.

5. A method according to claim 3 wherein the first stress state (Cl) corresponds to a biaxial tension and the second stress state (C2) corresponds to a uniaxial tension.

6. Method according to any one of claims 1 to 2 in which the partial alteration comprises a formation of relaxation trenches (42) in the stress-giving layer (14), oriented in the determined direction (y).

7. Method according to the preceding claim in which the relaxation trenches (42) are separated by strips (41) of stress-donating layer (14) having a width Lu approximately equal to half the thickness eM of the stress-donating layer (14).

8. A method according to any preceding claim wherein the stack comprises an insulating layer (12) between the semiconductor layer (13) and the fusible layer (11).

9. A method according to any preceding claim wherein the stress-giving layer (14) is based on silicon nitride.

10. A method according to any preceding claim wherein the melting is carried out by thermal annealing of the rapid thermal annealing type or using a nanosecond laser.

11. A method according to any preceding claim wherein the fusible layer (11) is amorphous.

12. Method according to the preceding claim in which the amorphous fusible layer (11) is formed by epitaxy before being amorphized by implantation.

13. A method according to any preceding claim wherein the semiconductor layer (13) is based on silicon or silicon-germanium and the fusible layer (11) is based on silicon-germanium or germanium and has a higher germanium content than the semiconductor layer (13).

14. A method of manufacturing a transistor comprising implementing a method of producing a uniaxial stress state (C3, C3') according to any one of the preceding claims, the transistor comprising a channel region made in said semiconductor layer (13).

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