Functional integrated circuit tolerant of a maximum voltage exceeding its nominal voltage, and corresponding method

Abstract

The integrated circuit includes: - a terminal (IO_CC_PIN) configured to receive a signal (V_CC) at a nominal voltage level (Vnml) which can rise up to a maximum voltage level (Vmax); - an output circuit comprising a first transistor (TPcd) and a second transistor (TPcs) coupled in series between the terminal (IO_CC_PIN) and an output stage (Ra, Rb, Nout);- a protection circuit configured to generate a first voltage (V_CASCd) controlling the first transistor, and a second voltage (V_CASCs) controlling the second transistor, such that: -- in an activated (ON) state, the first voltage (V_CASCd) and the second voltage (V_CASCs) are obtained by dividing the voltage level of said terminal (V_CC), -- in an deactivated (OFF) state, the first voltage (V_CASCd) is obtained by the voltage level of said terminal (V_CC), and the second voltage (V_CASCs) is obtained by subtracting the threshold voltage of a protection transistor (TNc) from the level of a control voltage (V_CASC). Figure for the abbreviation: Fig 1;

Description

Title of the invention: Functional integrated circuit tolerant to a maximum voltage exceeding its nominal voltage, and corresponding method

[0001] Embodiments and implementations relate to integrated circuits, in particular circuit design with respect to operating constraints and tolerance to a maximum voltage greater than a nominal voltage, such as in USB type-C port input-output device circuits.

[0002] Indeed, USB Type-C specifically includes a "power delivery" mode, commonly referred to as "PD," which uses a DC channel to negotiate power between connected devices. Within this framework, there is a voltage level detection solution that requires a voltage divider by three for the DC channel pin. A small divider circuit must be able to guarantee functional and tolerant operation up to a maximum voltage of 5 V.

[0003] Functional at 5 V means that, when the USB type-C port input-output circuit is activated, the circuit connected to the external DC terminal can function properly when the voltage increases up to 5 V.

[0004] Tolerant to 5 V means that, when the USB type-C port input-output circuit is disabled, the circuit connected to the external DC terminal can withstand a voltage increasing up to 5 V.

[0005] In simple circuits of the classic voltage divider type, there is at least one transistor which must have a voltage withstand of 5 V to ensure the functionality and 5 V tolerance of the circuit.

[0006] However, there are technological sectors which do not provide for the manufacture of transistors with a voltage withstand of 5 V, in which it is nevertheless desirable to be able to ensure the operating and tolerance constraints at 5 V in order to benefit from a USB type-C port input-output circuit.

[0007] Some embodiments and implementation methods propose to create a functional circuit tolerant to a maximum voltage, for example of 5 V, greater than a nominal voltage, for example of 3.3 V, using only transistors having a voltage withstand (usually "maximum absolute rating" in English) less than the maximum voltage, for example substantially equal to the nominal voltage.

[0008] According to one aspect, a method is proposed in this regard for protecting, in an integrated circuit, an output circuit comprising a first transistor and a second transistor coupled in series between a terminal and an output stage, the terminal receiving a signal at a nominal voltage level that can rise up to a maximum voltage level, the method comprising generating, by a protection circuit, a first voltage controlling the first transistor, and generating a second voltage controlling the second transistor, wherein: - in an activated state, the first voltage and the second voltage are obtained by dividing the voltage level of said terminal; - in a deactivated state, the first voltage is obtained by the voltage level of said terminal, and the second voltage is obtained by the level of a control voltage subtracted from a threshold voltage of a protection transistor.

[0009] In other words, the second voltage is capped at a level equal to the control voltage less the threshold voltage, for example obtained by means of a "cascode" type arrangement of transistors which may have a voltage withstand lower than the maximum voltage, but arranged so as to be functional and tolerant to the maximum voltage.

[0010] Thus, a circuit, such as a voltage divider, can be built that is functional and tolerant to 5 V using only transistors with a voltage withstand of 3.3 V, i.e. without using "high voltage" transistors with a voltage withstand of 5 V or more.

[0011] According to one embodiment: - in the activated state the protection circuit and the output circuit are able to flow a current between the terminal and a ground terminal; - in the deactivated state the protection circuit and the output circuit are unable to flow a current between the terminal and the ground terminal.

[0012] According to one embodiment, the first voltage is obtained from the drain voltage of a protection transistor and the second voltage is obtained from the source voltage of the protection transistor, the protection transistor being coupled between a first resistive element and a second resistive element of a voltage divider bridge.

[0013] According to another aspect, an integrated circuit is proposed comprising a terminal configured to receive a signal at a nominal voltage level that can rise up to a maximum voltage level; - an output circuit comprising a first transistor and a second transistor coupled in series between the terminal and an output stage; - a protection circuit configured to generate a first voltage controlling the first transistor, and a second voltage controlling the second transistor, such that: — in an activated state, the first voltage and the second voltage are obtained by dividing the voltage level of said terminal, — in a deactivated state, the first voltage is obtained by the voltage level said terminal, and the second voltage is obtained by the level of a control voltage subtracted from a threshold voltage of a protection transistor.

[0014] According to one embodiment: - in the activated state the protection circuit and the output circuit are able to flow a current between the terminal and a ground terminal; - in the deactivated state the protection circuit and the output circuit are unable to flow a current between the terminal and a ground terminal.

[0015] According to one embodiment, the protection circuit comprises a resistive voltage divider bridge having a protection transistor coupled in series between a first resistive element and a second resistive element and configured to be controlled by the control voltage on its gate, the gate of the first transistor being coupled to the drain of the protection transistor, the gate of the second transistor being coupled to the source of the protection transistor.

[0016] According to one embodiment, the first resistive element is coupled between the terminal and the drain of the protection transistor, and the second resistive element is coupled between the source of the protection transistor and the ground terminal.

[0017] According to one embodiment, the protection transistor, the first transistor of the output circuit and the second transistor of the output circuit have a voltage withstand voltage lower than the maximum voltage level.

[0018] According to one embodiment, the nominal voltage is between 3.0 V and 3.6 V and the maximum voltage is between 4.7 V and 5.0 V.

[0019] According to another aspect, a system on a chip incorporating an integrated circuit as defined above, in an input-output device of a USB type-C port, is also proposed.

[0020] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is in no way limiting, and the accompanying drawings, in which the figures:

[0021] [Fig.l] ;

[0022] [Fig.2] ;

[0023] [Fig.3] ;

[0024] [Fig.4] ;

[0025] [Fig.5] ;

[0026] [Fig.6] illustrate embodiments and implementations of the invention.

[0027] Fig. 1 illustrates an example of a DIV circuit, such as a divider, functional and tolerant to a maximum voltage, for example 5 V, comprising transistors all having a voltage withstand of less than 5 V, for example approximately 3.3 V.

[0028] The voltage rating, or "maximum absolute rating" in English, is the voltage value beyond which the transistor risks breakdown (usually "breakdown") (in English) when it is applied between two of its bounds.

[0029] For the transistors in the DIV circuit, it is considered that the gate breakdown voltage, i.e. the voltage withstand between the gate terminal and the source / drain terminals, is the same as the junction breakdown voltage, i.e. the voltage withstand between the source and drain terminals.

[0030] A CRC_out output circuit of the DIV divider includes a Ra-Nout-Rb output stage, capable of dividing the V_CC voltage present at an input terminal. The Ra-Nout-Rb output stage will be referred to in this context as a "voltage divider".

[0031] The terminal is configured to receive a V_CC signal at a nominal voltage level Vnml (figures 2 and 4) which can rise up to a maximum voltage level Vmax (figures 3 and 5).

[0032] Voltage division is for example obtained by means of a series of resistive elements Ra, Rb, so as to provide the divided voltage V_CC_div on an output node Nout at a level equal to the ratio B / (A+B) of the level of the input signal voltage V_CC (with A the value of the resistance Ra and B the value of the resistance Rb).

[0033] For example, the values ​​A and B can be chosen so that the ratio B / (A+B) is equal to 1 / 3, particularly in a detector application on the CC1 / 2 channel of USB Type-C in power transmission mode, usually "USB PD CC". That being said, the ratio of the resistances Ra, Rb implementing the voltage division on the Nout output can be chosen to any value without affecting the functionality and tolerance of the DIV circuit to the maximum voltage.

[0034] The input signal voltage V_CC is transmitted to the divider bridge Ra, Rb via a first transistor TPcd and a second transistor TPcs coupled in series between the V_CC terminal and the Ra resistance of the output stage.

[0035] The first transistor TPcd and the second transistor TPcs are PMOS type transistors (acronym commonly known in itself for "P-type Metal Oxide Semiconductor" in English).

[0036] The first transistor TPcd is controlled on its gate by a first voltage, called "cascode", V_CASCd, while the second transistor TPcs is controlled on its gate by a second voltage, also called "cascode", V_CASCs.

[0037] The first cascode voltage V_CASCd and the second cascode voltage V_CASCd are generated by a protection circuit CRC_prot, in particular from the voltage V_CC of the input signal on the terminal.

[0038] The CRC_prot protection circuit includes a resistive voltage divider bridge Rl-TNc-R2 comprising a protection transistor TNc coupled in series between a first resistive element RI and a second resistive element R2.

[0039] For example, the first resistive element RI is coupled between the terminal and the drain of the protection transistor TNc, and the second resistive element R2 is coupled between the TNc protection transistor source and GND ground terminal.

[0040] In an example adapted for a nominal voltage of approximately 3.3 V (for example between 3.0 V and 3.6 V), and a maximum voltage of approximately 5 V (for example between 4.7 V and 5.3 V), a ratio approximately equal to 1 / 3 will be chosen in the voltage divider of the protection circuit CRC_prot.

[0041] The TNc protection transistor is for example of the NMOS type (acronym commonly known in itself for "N-type Metal Oxide Semiconductor" in English).

[0042] The TNc protection transistor is configured to be controlled by a V_CASC control voltage on its gate, again referred to as "cascode voltage".

[0043] Indeed, the term "cascode voltage" means a control voltage, for example static, which allows the transistor to be placed in a substantially invariable state with respect to the implementation of the functionality of the circuit to which it belongs.

[0044] In particular here, with the cascode control voltage V_CASC on the gate of the protection transistor TNc, the level of the source voltage "Vs" can be capped with respect to the drain voltage "Vd", the functionality of the circuit including the transistor being to divide the terminal voltage V_CC.

[0045] Indeed, the source voltage Vs of the protection transistor TNc is capped at the level of the gate voltage “Vg” (Vg=V_CASC) subtracted from the threshold value “Vt” of the protection transistor TNc.

[0046] That is: Vs <Vg-Vt=V_CASC-Vt.

[0047] The threshold voltage Vt of the protection transistor TNc is for example between 0.6 V and 0.8 V.

[0048] The cascode control voltage V_CASC is for example generated by an "external" power supply circuit PWR_I0, for example the power supply circuit of the integrated circuit incorporating the divider DIV.

[0049] The cascode control voltage V_CASC is for example generated at the nominal voltage level, independently of the actual voltage level V_CC on the terminal.

[0050] The first cascode voltage V_CASCd controlling the first transistor TPcd of the output circuit CRC_out, is taken from the drain of the protection transistor TNc.

[0051] Respectively, the second cascode voltage V_CASCd controlling the second transistor TPcs of the output circuit CRC_out, is taken from the source of the protection transistor TNc.

[0052] For example in this respect, the gate (V_CASCd) of the first transistor TPcd is coupled to the drain of the protection transistor TNc; while the gate (V_CASCs) of the second transistor TPcs is coupled to the source of the protection transistor TNc.

[0053] Finally, NMOS transistors of the type TNswl, TNsw2, TNsw3, having functions as on / off switches for the DIV divider circuit, are provided between a ground reference terminal GND and the CRC_prot protection circuit, the circuit of CRC_out output and the Nout output node.

[0054] A first TNswl switch controlled by an activation signal V_EN can for example be coupled between ground GND and the second resistive element R2 of the protection circuit CRC_prot.

[0055] A second switch TNsw2 controlled by the activation signal V_EN can for example be coupled between ground GND and the resistive element Rb of the output circuit CRC_out.

[0056] A third switch TNsw3 controlled by the inverse of the activation signal V_nEN can for example be coupled between ground GND and the output node Nout of the output circuit CRC_out.

[0057] Thus, the activation signal V_EN and its inverse V_nEN allow the DIV circuit to be placed either in the activated state ON (figures 2 and 3), or in the deactivated state OFF (figures 4 and 5).

[0058] In the activated ON state, the TNswl, TNsw2 switches are controlled to conduct by the activation signal V_EN, and the third switch TNsw3 is controlled to block by the inverse of the activation signal V_nEN.

[0059] Thus, in the activated ON state, the CRC_prot protection circuit and the CRC_out output circuit are able to flow a current between the terminal and the ground terminal GND.

[0060] In the OFF disabled state, the TNswl, TNsw2 switches are controlled blocked by the activation signal V_EN, and the third TNsw3 switch is controlled passing through the inverse of the activation signal V_nEN.

[0061] Thus, in the OFF state, the CRC_prot protection circuit and the CRC_out output circuit are unable to conduct current between the terminal and the ground terminal GND. Furthermore, the Nout output node is "short-circuited" to ground GND.

[0062] Therefore, this example of a CRC_prot protection circuit allows this dual functional condition to be implemented:

[0063] — In the ON state, the first cascode voltage V_CASCd and the second The cascode voltage V_CASCs controlling the CRC_out output circuit are obtained by dividing (by a factor of N / (N+2N)=1 / 3) the voltage level of the terminal V_CC. See Figures 2 and 3 below for further details.

[0064] — In the OFF state, the first cascode voltage V_CASCd commanding the The CRC_out output circuit is obtained by the voltage level of the terminal V_CC; and the second cascode voltage V_CASCs controlling the CRC_out output circuit is capped by the level of the cascode control voltage V_CASC subtracted from the threshold voltage Vt of the protection transistor TNc. See Figures 4 and 5 below for further details.

[0065] Fig.2 illustrates the DIV circuit described above in relation to Fig.1, in the ON activated state, for a voltage on the V_CC terminal at the nominal value Vnml.

[0066] The nominal voltage Vnml can be between 3.0 V and 3.6 V, for example 3.3 V. The activation signal V_EN is brought to 3.3 V and its inverse V_nEN to 0 V.

[0067] In this case, the control voltage V_CASC at 3.3V controls the protection transistor TNc (of type NMOS), with respect to its source voltage, in the conducting state.

[0068] The drain voltage V_CASCd of the TNc transistor is equal to the division (by 3) of the V_CC level on the terminal, i.e. to 1.1 V, since the CRC_prot protection circuit is capable of discharging a current.

[0069] The source voltage V_CASCs of the TNc transistor is equal to the drain voltage V_CASCd, at 1.1V.

[0070] The first voltage V_CASCd at 1.1 V controls the first TPcd transistor (of PMOS type) of the CRC_out output circuit in the conducting state; and similarly, the second voltage V_CASCd at 1.1 V controls the second TPcd transistor (of PMOS type) of the CRC_out output circuit in the conducting state.

[0071] Thus, the voltage V_CC at 3.3 V is transmitted to the output stage Ra-Nout-Rb and the division function of V_CC is implemented on the voltage V_CC_div on the output node Nout, there too since the output circuit CRC_out is capable of flowing a current.

[0072] Figure [3] illustrates the DIV circuit described above in relation to Figure [1], in the state activated ON, for a voltage on the terminal V_CC at the maximum value Vmax.

[0073] The maximum voltage Vmax can be between 4.7 V and 5.3 V, for example 5.0 V.

[0074] In this case, the control voltage V_CASC at 3.3V controls the protection transistor TNc (of type NMOS), with respect to its source voltage, in the conducting state.

[0075] The drain voltage V_CASCd of the TNc transistor is equal to the division (by 3) of the V_CC level on the terminal, i.e. approximately 1.7 V, since the CRC_prot protection circuit is capable of discharging a current.

[0076] The source voltage V_CASCs of the TNc transistor is equal to the drain voltage V_CASCd, at 1.7V.

[0077] The first voltage V_CASCd at 1.7 V controls the first TPcd transistor (of PMOS type) of the output circuit CRC_out, with respect to its source voltage, in the conducting state; and similarly, the second voltage V_CASCd at 1.7 V controls the second TPcd transistor (of PMOS type) of the output circuit CRC_out, with respect to its source voltage, in the conducting state.

[0078] Thus, the voltage V_CC at 5 V is transmitted to the output stage Ra-Nout-Rb and the division function of V_CC is implemented on the voltage V_CC_div on the output node Nout, there too since the protection circuit CRC_prot is capable of discharging a current.

[0079] Therefore, the DIV circuit is functional at the maximum voltage value v_cc.

[0080] Fig.4 illustrates the DIV circuit described above in relation to Fig.1, in the OFF deactivated state, for a voltage on the V_CC terminal at the nominal value Vnml, for example 3.3 V.

[0081] In this case, since the CRC_prot protection circuit is unable to discharge a current, the 3.3 V V voltage V_CC from the terminal is transmitted by resistive coupling to the conduction terminals (drain / source) of the TNc protection transistor.

[0082] Thus, the control voltage V_CASC at 3.3V controls the protection transistor TNc (of type NMOS), with respect to its source voltage, in the linear (or "ohmic") state, that is to say in a self-regulated manner at a source-gate voltage Vs-Vg equal to the threshold voltage Vt of the TNc transistor.

[0083] The drain voltage V_CASCd of the TNc transistor is equal to the V_CC level on the terminal, i.e. 3.3 V.

[0084] The source voltage V_CASCs of the transistor TNc is capped by the level of the cascode control voltage V_CASC removed from the threshold voltage Vt of the protection transistor TNc, that is to say at substantially 2.5 V.

[0085] The first voltage V_CASCd at 3.3 V controls the first transistor TPcd (of type PMOS) of the output circuit CRC_out in the conducting state.

[0086] The second voltage V_CASCd at 2.5 V controls the second transistor TPcd (of PMOS type) of the CRC_out output circuit in the linear state, i.e., in a self-regulated manner at a source-to-gate voltage Vs-Vg equal to the threshold voltage Vtp of the second transistor TPcs. The threshold voltage Vtp of the P-type transistor is negative, for example Vtp = -0.7 V.

[0087] This makes it possible to cap the source voltage V_INT1 of the second transistor TPcs of the output circuit CRC_out, at the second voltage V_CASCd subtracted from the threshold voltage Vtp of the P-type transistor, TPcs, that is to say at approximately 3.3V = 2.5V -(-0.7V) (or between 3.0 V and 3.3 V, in practice).

[0088] The output node Nout is connected to ground, and the voltage V_CC_div = 0V is transmitted to the drain of the second PMOS transistor TPcs, by resistive coupling via the resistor Ra.

[0089] Fig. 5 illustrates the DIV circuit described above in relation to Fig. 1, in the OFF deactivated state, for a voltage on the V_CC terminal at the maximum value Vmax, for example 5 V.

[0090] In this case, since the CRC_prot protection circuit is unable to discharge a current, the 5 V V_CC voltage of the terminal is transmitted by resistive coupling to the conduction terminals (drain / source) of the TNc protection transistor.

[0091] Thus, the control voltage V_CASC at 3.3V controls the protection transistor TNc (of NMOS type), with respect to its source voltage, in the linear state (or "ohmic"), that is, in a self-regulated manner at a source-gate voltage Vs-Vg equal to the threshold voltage Vt of the TNc transistor.

[0092] The drain voltage V_CASCd of the TNc transistor is equal to the V_CC level on the terminal, i.e. 5 V.

[0093] The source voltage V_CASCs of the transistor TNc is capped by the level of the cascode control voltage V_CASC removed from the threshold voltage Vt of the protection transistor TNc, that is to say at substantially 2.5 V = 3.3 V - 0.7 V.

[0094] The first voltage V_CASCd at 5 V controls the first transistor TPcd (of type PMOS) of the output circuit CRC_out in the conducting state.

[0095] The second voltage V_CASCd at 2.5 V controls the second transistor TPcd (of PMOS type) of the CRC_out output circuit in the linear state, i.e., in a self-regulated manner at a source-to-gate voltage Vs-Vg equal to the threshold voltage Vtp of the second transistor TPcs. The threshold voltage Vtp of the P-type transistor is negative, for example Vtp = -0.7 V.

[0096] This makes it possible to cap the source voltage V_INT1 of the second transistor TPcs of the output circuit CRC_out, at the second voltage V_CASCd subtracted from the threshold voltage Vtp of the P-type transistor, TPcs, that is to say at approximately 3.3V = 2.5V -(-0.7V) (or between 3.3 V and 3.5 V, in practice).

[0097] The output node Nout is connected to ground, and the voltage V_CC_div = 0V is transmitted to the drain of the second PMOS transistor TPcs, by resistive coupling via the resistor Ra.

[0098] Thus, in this case, none of the transistors in the DIV circuit are biased with a voltage greater than the breakdown voltage between each of their terminals.

[0099] In particular, neither the protection transistor, nor the first switch TNswl, nor the two transistors TPcd, TPcs of the output circuit CRC_out are biased with a voltage higher than the breakdown voltage, for example 3.3 V (or even 3.5 V), between their conduction terminals, nor between their gate terminal and the conduction terminals.

[0100] Therefore, the DIV circuit is tolerant to the maximum value of the voltage V_CC.

[0101] Figure 6 schematically illustrates a system-on-chip (SOC), which may include an IO_RNG input-output terminal network and various functional blocks.

[0102] The functional blocks may include a digital circuit DIG, for example a core or a processor; a memory circuit MEM, for example volatile memory of the type "SRAM" and possibly non-volatile memory of the type "EEPROM" or "Flash"; an analog circuit ANL, for example wireless communication or having an analog detection functionality of a physical quantity; a power supply circuit SUP, for example capable of providing a regulated voltage, and which may include the PWR_I0 power supply mentioned previously in relation to [Fig.1].

[0103] The input / output terminal network I0_RNG includes in particular an input / output device IO_CC_CIRC capable of driving an IO_CC_PIN terminal of a CC1 / CC2 port of a USB type-C connection.

[0104] The input-output device IO_CC_CIRC includes in particular a DET detection means on voltage levels which require a divide-by-3 solution of the voltage level V_CC on the IO_CC_PIN terminal.

[0105] The DET detection means incorporates in particular the DIV divider circuit, as described above in relation to figures 1 to 5, which makes it possible to guarantee functional and tolerant operation at the maximum voltage of 5 V (for a nominal voltage of 3.3 V).

[0106] The input-output device IO_CC_CIRC also includes internal terminals, INTRN_PIN, enabling communication with the DIG-SUP functional blocks of the system-on-chip SOC, for example according to conventional I2C, AHB or AXI protocols.

[0107] Thus, the 5V tolerance and functionality constraint imposed by the USB PD CC standard on the IO_CC_CIRC input / output device does not prevent the system-on-chip (SoC) from being manufactured using a technology that does not involve the production of transistors with a voltage rating greater than or equal to 5V. This can be particularly advantageous in terms of production costs and optimization of manufacturing processes.

Claims

Claims

1. A method of protecting, in an integrated circuit, an output circuit comprising a first transistor and a second transistor coupled in series between a terminal (IO_CC_PIN) and an output stage (Ra, Rb, Nout), the terminal (IO_CC_PIN) receiving a signal (V_CC) at a nominal voltage level (Vnml) which can rise to a maximum voltage level (Vmax), the method comprising a generation, by a protection circuit, of a first voltage (V_CASCd) controlling the first transistor, and a generation of a second voltage (V_CASCs) controlling the second transistor, in which: - in an activated state (ON), the first voltage (V_CASCd) and the second voltage (V_CASCs) are obtained by a division of the voltage level of said terminal (V_CC);- in a deactivated state (OFF), the first voltage (V_CASCd) is obtained by the voltage level of said terminal (V_CC), and the second voltage (V_CASCs) is obtained by the level of a control voltage (V_CASC) removed from a threshold voltage of a protection transistor (TNc).;

2. Method according to claim 1, in which: - in the activated state (ON) the protection circuit and the output circuit are capable of flowing a current between the terminal and a ground terminal; - in the deactivated state (OFF) the protection circuit and the output circuit are incapable of flowing a current between the terminal and the ground terminal.

3. Method according to one of claims 1 or 2, in which the first voltage (V_CASCd) is obtained by the drain voltage of a protection transistor (TNc) and the second voltage (V_CASCs) is obtained by the source voltage of the protection transistor (TNc), the protection transistor (TNc) being coupled between a first resistive element (RI) and a second resistive element (R2) of a voltage divider bridge (RDIV).

4. Integrated circuit comprising: - a terminal (IO_CC_PIN) configured to receive a signal (V_CC) at a nominal voltage level (Vnml) which can rise to a maximum voltage level (Vmax); - an output circuit comprising a first transistor (TPcd) and a second transistor (TPcs) coupled in series between the terminal (IO_CC_PIN) and an output stage (Ra, Rb, Nout); - a protection circuit configured to generate a first voltage (V_CASCd) controlling the first transistor, and a second voltage (V_CASCs) controlling the second transistor, such that: — in an activated state (ON), the first voltage (V_CASCd) and the second voltage (V_CASCs) are obtained by dividing the voltage level of said terminal (V_CC), — in a deactivated state (OFF), the first voltage (V_CASCd) is obtained by the voltage level of said terminal (V_CC), and the second voltage (V_CASCs) is obtained by the level of a control voltage (V_CASC) removed from a threshold voltage of a protection transistor (TNc).

5. Integrated circuit according to claim 4, in which: - in the activated state (ON) the protection circuit and the output circuit are capable of flowing a current between the terminal and a ground terminal; - in the deactivated state (OFF) the protection circuit and the output circuit are incapable of flowing a current between the terminal and the ground terminal.

6. Integrated circuit according to one of claims 4 or 5, in which the protection circuit comprises a resistive voltage divider bridge (RDIV) comprising a protection transistor (TNc) coupled in series between a first resistive element (RI) and a second resistive element (R2) and configured to be controlled by the control voltage (V_CASC) on its gate, the gate of the first transistor (V_CASCd) being coupled to the drain of the protection transistor, the gate of the second transistor (V_CASCs) being coupled to the source of the protection transistor.

7. Integrated circuit according to one of claims 4 or 5, in which the first resistive element (RI) is coupled between the terminal (IO_CC_PIN) and the drain of the protection transistor (TNc), and the second resistive element (R2) is coupled between the source of the protection transistor (TNc) and the ground terminal (GND).

8. Integrated circuit according to one of claims 4 to 6, in which the protection transistor (TNc), the first transistor (TPcd) of the output circuit and the second transistor (TPcs) of the output circuit have a voltage withstand lower than the maximum voltage level.

9. An integrated circuit according to one of claims 4 to 7, wherein the nominal voltage is between 3.0 V and 3.6 V and the maximum voltage is between 4.7 V and 5.3 V.

10. System on chip (SOC) incorporating an integrated circuit according to one of the claims 4 to 9, in an input-output device (IO_CC_CIRC) of a terminal (IO_CC_PIN) of a USB type-C port.

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