Method for manufacturing a microelectronic device based on a semi-metallic material

Abstract

Title: Method for Implementing a Microelectronic Device Based on a Semi-Metallic Material. The invention relates to a device comprising a transistor (T1, T2) including: • a source (42) and a drain (43), • a plurality of channels (41a, 41b, 41c) based on a semi-metallic material, • a surrounding gate (50) enclosing the channels (41a, 41b, 41c), • a dielectric gate layer (30) separating each channel (41a, 41b, 41c) and the surrounding gate (50), • source and drain contacts (40S, 40D) based on the semi-metallic material. Advantageously, the surrounding gate (50) completely encloses one or more channels (41a, 41b, 41c), according to a GAA architecture. The invention also relates to a method for implementing such a device. Figure for the abstract: Fig. 15A

Description

Title of the invention: Method for producing a microelectronic device based on a semi-metallic material Technical field

[0001] The present invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices whose conduction channels are based on a semi-metallic material. STATE OF THE ART

[0002] To meet the increasing demands on the performance of microelectronic devices and their miniaturization, the use of materials other than silicon is now being considered for the manufacture of transistors. An example of materials recently integrated into transistors is bismuth, a semi-metallic material. In the bulk state, a semi-metallic material has electrical properties similar to those of a metallic material. On the other hand, when the semi-metallic material is structured so as to have nanometric dimensions, this material adopts an electrical behavior similar to that of a semiconductor. This is notably due to a quantum confinement effect.

[0003] The paper "Semimetal to semiconductor transition and polymer electrolyte gate modulation in single-crystalline bismuth nanowires, Jeongmin Kim and Wooyoung Lee, Nanoscale, 2 (2017)" discloses a device based on bismuth nanowires. In this method, bismuth nanowires are initially synthesized on a bismuth substrate, then detached from their support and individually manipulated for the design of channels of a field-effect transistor. Although this device demonstrates promising performance, its manufacturing process does not allow its industrialization or large-scale production.

[0004] Document US2018 / 0190799 A1 discloses another manufacturing method incorporating a semi-metallic material in a conformal gate transistor. A vertical channel arrangement is disclosed in this document. A bismuth-based semi-metallic layer is deposited in holes having nanometric dimensions to form the semiconductor channels in the form of vertical nanowires. The semi-metallic layer opens out of the holes to form source or drain regions. These source / drain regions have dimensions larger than those of the channels, and have a metallic character. Such a method exploiting the semi-metal / semiconductor transition by geometric constriction is suitable for exploitation in industrial. The formation of holes with nanometric dimensions is difficult to control. The integration densities accessible by this process remain limited.

[0005] Document FR3095549 discloses another method for producing a transistor based on a semi-metallic material in a planar arrangement. The production of such an architecture is simpler and more reliable. A "mold" defining the patterns intended to form the channels and the source and drain regions and their contacts is here previously produced. The semi-metallic material is then deposited in this mold, then thinned by polishing. This makes it easier to obtain dimensions giving the channels a semiconducting character. Here again, the integration density remains limited. The electrostatic control of the transistors is also limited.

[0006] The present invention proposes to overcome at least in part the drawbacks of known methods and architectures. In particular, one objective of the present invention is to propose a device making it possible to increase the integration density of transistors based on a semi-metallic material. Another objective of the present invention is to propose a method for manufacturing such a device. SUMMARY

[0007] To achieve this objective, according to one embodiment, a microelectronic device is provided comprising at least one transistor comprising: - a source and a drain, - a plurality of channels based on a semi-metallic material, said channels extending in a longitudinal direction x between the source and the drain, each channel having at least one transverse dimension, taken perpendicular to the longitudinal direction x, such that the semi-metallic material has an electrical conduction property of a semiconductor material, - a so-called wrapping grid, surrounding at least one of the channels, and preferably several channels of the plurality of channels, - a gate dielectric layer separating each channel and the surrounding gate, - source and drain contacts connected respectively to the source and to the drain, at least one of the source and drain contacts being based on the semi-metallic material and having dimensions such that the semi-metallic material has an electrical conduction property of a metallic material, - spacers on either side of the grid, configured to electrically isolate the grid from the source and drain contacts.

[0008] Advantageously, the surrounding grid completely surrounds at least one of the channels, and preferably several channels of the plurality of channels, in a transverse plane yz perpendicular to the longitudinal direction x.

[0009] Such a gate-around architecture is called GAA (acronym for Gate Ail Around), and comprises channels stacked on top of each other in a so-called vertical direction z, surrounded by a common gate. This advantageously makes it possible to improve the electrostatic control of the transistors and to obtain a higher current density per unit area. Furthermore, such an architecture allows a high integration density of the transistors. In particular, the device may comprise at least two adjacent transistors in a horizontal direction, each transistor comprising channels stacked in the vertical direction z.

[0010] Such a device architecture advantageously exceeds the performance of known transistor architectures based on a semi-metallic material.

[0011] Another aspect of the invention relates to a method of manufacturing such a microelectronic device, comprising the following steps: - Providing on a substrate a stack comprising, in the z direction, a plurality of first layers made of a first material, alternating with a plurality of second layers made of a second material, the first material and the second material being different from each other and different from the semi-metallic material forming the channels, - Form in this stack the first openings defining the first patterns, - Form a sacrificial grid straddling the first patterns and partly in the first openings, - Forming in the first patterns second openings defining second patterns, such that the second patterns are transverse to the first patterns, - Form the grid dielectric layer, - Form the spacers, - Forming a retaining layer in said second openings on exposed sides of the second patterns, - Remove the sacrificial grid so as to form third openings, - Completely remove, from the third openings, the first material of the first layers selectively to the second material of the second layers, so as to form cavities, - Fill the cavities with a grid material, so as to form the surrounding grid, - Removing at least part of the retaining layer so as to reform at least part of the second openings exposing sides of the second layers, - Completely remove, from the second openings, the second material second layers so as to form second spaces, - Depositing a layer based on a semi-metallic material in the second spaces and at least partly in the second openings, so as to simultaneously form: • channels based on semi-metallic material directly above the surrounding grid, • at least one of the source and drain contacts based on the semi-metallic material.

[0012] One principle of the method according to the invention consists in selectively replacing certain layers of the initial stack with the semi-metallic material in order to form the channels of the transistor. The deposition of the semi-metallic material advantageously forms the channels and at least one of the drain or source contacts in a single step. The initial stack does not include the semi-metallic material. The subsequent deposition of the semi-metallic material aims to better preserve the semi-metallic material.

[0013] Thus, the layers of semi-metallic material are introduced at the end of the process, after structuring the stack and typically after the formation of the spacers and the surrounding grid. This advantageously limits the risk of degradation of the semi-metallic material during the process. The semi-metallic material is not exposed at all stages of the manufacturing process. The semi-metallic material is thus preserved.

[0014] Furthermore, the late introduction of the semi-metallic material during the manufacturing process makes it possible to use standard microelectronics technologies for the formation and structuring of the stack. There is no need to modify or adapt the standard technological structuring steps to the constraints of using the semi-metallic material. The costs of the process are thus advantageously limited. The process can also be more easily implemented in existing production lines.

[0015] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0016] [Fig. 1 A] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.ôA] [Fig.7A] [Fig.8A] [Fig.9A] [Fig. 10 A][Fig.llA][Fig.l2A][Fig.l3A][Fig.l4A][Fig.l5A] Figures nA (n=l... 15) schematically illustrate, along xz cross sections, steps in manufacturing a GAA transistor device, according to a first embodiment of the present invention.

[0017] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig. 1 IB] [Fig. 12B] [Fig. 13B][Fig. 14B] [Fig. 15B] Figures nB (n=l... 15) schematically illustrate, along transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device as those represented in figures nA (n=l... 15) respectively.

[0018] [Fig. 14C] [Fig. 14C] illustrates an alternative embodiment with regard to the shape of the channels of the transistors of the device according to the invention.

[0019] [Fig.l6A][Fig.l7A][Fig.l8A][Fig.l9A][Fig.20A] Figures nA (n=16...2O) schematically illustrate, along xz cross sections, steps in manufacturing a GAA transistor device, according to a second embodiment of the present invention.

[0020] [Fig.l6B][Fig.l7B][Fig.l8B][Fig.l9B][Fig.20B] Figures nB (n=16...2O) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device as those represented in figures nA (n=16...2O) respectively.

[0021] In the cross-sectional figures, section planes are indicated (A-A', B-B', ..., TT) with cross-references to the section planes of the corresponding figures. The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, in the principle diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all of the alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when they are reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned.A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0022] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0023] According to one example, the device comprises at least two transistors arranged in a first direction x or y called horizontal, and the channels of each transistor are stacked in a second direction z called vertical, perpendicular to the first direction x or y.

[0024] According to one example, one of the source and drain contacts is based on the semi-metallic material and the other among the source and drain contacts is based on a metal.

[0025] According to one example, the semi-metallic material is based on at least one element among bismuth (Bi), tin (Sn), antimony (Sb), arsenic (As).

[0026] According to one example, the formation of the spacers comprises the following steps: - Form the first spacers bordering the sacrificial grid and resting on the first patterns, - Before forming the retaining layer, partially removing, from the second openings, the first material of the first layers selectively to the second material of the second layers, so as to form first spaces directly above the first spacers, - Fill the first spaces with a first dielectric material to form internal spacers.

[0027] According to one example, the first patterns extend mainly in the longitudinal direction x, and the second patterns extend mainly in a transverse direction y.

[0028] According to one example, the encapsulating gate is formed before the deposition of the layer based on the semi-metallic material. This corresponds to a “gate first” type process (the replacement of the sacrificial gate by a functional gate is done before the formation of the transistor channels).

[0029] According to one example, the formation of the gate dielectric layer is formed after complete removal of the first material from the first layers and before formation of the encapsulating gate, by depositing a dielectric layer in the cavities and in the third openings, on the exposed portions of the second layers.

[0030] According to one example, the formation of the spacers and the formation of the gate dielectric layer are carried out at least in part by the same deposition of a dielectric layer in the cavities. This makes it possible to reduce the number of steps of the method and / or to thicken the spacers.

[0031] According to one example, the deposition of the layer based on the semi-metallic material is carried out in the second spaces and in all the second openings so as to form the channels and all the source and drain contacts. The number of steps of the method is advantageously reduced.

[0032] According to one example, the method further comprises, after deposition of the layer based on the semi-metallic material, crystallization annealing.

[0033] According to one example, the layer based on the semi-metallic material is covered prior to the crystallization annealing, and the crystallization annealing is carried out at a temperature higher than the melting temperature of the semi-metallic material.

[0034] According to one example, the second openings are reformed by exposing success- sively only one flank of the second layers, and the deposition of the layer based on the semi-metallic material forms a single contact among the source and drain contacts.

[0035] According to one example, the other contact of the source and drain contacts is a metal contact formed by depositing a metal layer in a portion of the second openings.

[0036] According to one example, the deposition of the layer based on the semi-metallic material is carried out by growth, preferably by epitaxy, from exposed areas of said metal contact through the second spaces.

[0037] The invention relates generally to a method for manufacturing a microelectronic device with GAA transistors, based on a semi-metallic material. Such a microelectronic device may have a “GAA stacked nanosheet” type architecture, i.e. with stacked nanosheets and a fully encapsulating gate. An architecture with stacked nanowires and a fully encapsulating gate is also possible.

[0038] The nanowires or nanosheets typically each comprise a conduction channel of a transistor. These channels are stacked in a z direction. This means that they each occupy a level of given altitude in the z direction. A level can be defined between two planes perpendicular to the z direction.

[0039] Advantageously, the method according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technological nodes.

[0040] A microelectronic device comprising GAA transistors can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems.

[0041] A particular aspect of the invention relates to the use of semi-metallic materials to produce the nanowires or nanosheets of the device. These semi-metallic materials may have properties of a metal or a semiconductor, typically depending on the temperature or dimensional confinement. The band structure of semi-metallic or semi-metallic materials brings them closer to metals, insofar as these materials do not have a band gap, but the low density of electronic states at the Fermi level splits the carriers into two populations, electrons and holes, as for semiconductors. Thus, it is possible to act on the type of electrical conduction of semi-metallic materials, by modifying their dimensions. When the dimensions of a semi-metal are reduced, the concentration of carriers is initially almost constant, as in metals, then increases substantially by quantum confinement, as in semiconductors.We thus observe a semimetal-semiconductor transition. Bismuth can be . behave like a semiconductor when deposited in thin layers with a thickness less than a critical value of 30 nm.

[0042] In the context of the present invention, the semi-metallic materials are preferably based on bismuth (Bi), tin (Sn), antimony (Sb), arsenic (As), tellurium (Te). Other materials having semi-metallic properties, at least under certain conditions, are also conceivable. Certain alloys may be semi-metallic, such as mercury telluride HgTe. Certain conductive polymers may have semi-metallic phases; certain thin-film graphene structures, for example, may be semi-metallic depending on their magnetic environment.

[0043] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0044] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0045] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20.

[0046] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0047] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0048] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a step different, and other actions of the first stage can be repeated later. Thus, the term stage does not necessarily mean unitary and inseparable actions in time and in the sequence of phases of the process.

[0049] The term “selective etching with respect to” or “etching having selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0050] The various patterns formed during the manufacturing steps typically have a structure intended to evolve during the process steps. Thus, the patterns may comprise the sacrificial layers of the initial stack, the layers based on semi-metallic material, the dielectric layers, continuous or discontinuous. The various patterns aim to form, at the end of the process, “transistor patterns” each comprising at least one conduction channel and a gate surrounding said channel, a dielectric barrier separating the gate and the channel, a source and a drain on either side of the channel. The assignment of the first and second layers in the initial stack may be reversed.

[0051] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0052] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken along a direction normal to the main extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along z. A gate pattern formed on such a surface layer has a height along z. The relative terms “on”, “overcomes”, “under”, “underlying” refer to positions taken along the z direction. A “lateral” dimension corresponds to a dimension along a direction of the xy plane. A “lateral” or “laterally” extension is understood to mean an extension along one or more directions of the xy plane.

[0053] In the present patent application, the longitudinal direction corresponds to the direction in which the channel of a transistor extends, between the source and the drain. The longitudinal direction is directed along x in the illustrative figures. A transverse direction is directed along y or z. A transverse dimension is typically taken along y or z. The thickness of the layer forming the channel is a transverse dimension of the channel.

[0054] An element located “perpendicular to” or “in line with” another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0055] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0056] The following description presents an example of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0057] Figures 1A, 1B to 15A, 15B schematically illustrate steps of manufacturing a device comprising GAA transistors based on a semi-metallic material, according to a first embodiment. Figures nA (n=1... 15) correspond to first transverse sections along an xz plane, each illustrating a different step of the manufacturing process. Figures nB (n=1... 15) correspond to second transverse sections along a yz plane, each illustrating the same step as the corresponding figure nA.

[0058] As illustrated in Figures 1A, 1B, a first step consists of producing a stack E of semiconductor layers 10, 20 on a substrate S. The substrate S may be a substrate of the SOI (Silicon On Insulator), GeOI (Germanium On Insulator) or SGOI (Silicon-Germanium On Insulator) type. These known substrates comprise, according to the terminology common to those skilled in the art, a thick silicon SI layer called “Si bulk”, a silicon oxide S2 layer called “BOX” (Burried Oxide) and a thin surface layer, respectively based on silicon, germanium or silicon-germanium. This thin surface layer may advantageously correspond to the first layer 10 of the stack E.

[0059] Alternatively, the substrate S can be a bulk Si substrate.

[0060] According to one example, the stack E comprises an alternation of first layers 10 made of silicon-germanium (SiGe) and second layers 20 made of silicon (Si).

[0061] The concentration of Ge in the SiGe alloy can be 20%, 30% or 45% for example. This concentration of germanium is chosen so as to allow good selectivity of the etching of the SiGe compared to the Si, during the selective etching steps. The higher the concentration of Ge, the greater the selectivity to Si will be during the subsequent removal of the SiGe. This stack E is advantageously formed by epitaxy of the layers of SiGe 10 and Si 20. This step of forming the stack E is inexpensive and well known to those skilled in the art. The thicknesses of the Si and SiGe layers can be between 5 nm and 20 nm, and preferably between 4 nm and 10 nm. In a known manner, in order to avoid the formation of structural defects, the thicknesses maximum permitted for SiGe layers 10 depend in particular on the chosen Ge concentration.

[0062] In the example illustrated in figures 1A, 1B three layers 10 of SiGe are alternated with three layers 20 of epitaxially grown Si. A Si / SiGe superlattice is thus obtained. The number of layers of Si and SiGe can naturally be increased. This ultimately makes it possible to increase the number of stacked channels per transistor in the final device.

[0063] Generally speaking, the first material of the first layers 10 and the second material of the second layers 20 are chosen so that one can be etched selectively relative to the other. Thus, other pairs of first and second materials are possible. By respecting this condition of selectivity during etching, the first and second materials can be chosen from dielectric materials (oxides and nitrides for example), semiconductor materials, metallic materials.

[0064] As illustrated in Figures 2A, 2B, a conventional lithography / etching step is carried out in order to define first patterns 101M, and first openings 100. The etching is anisotropic and directed along z. It is configured to etch the stack E, here the Si / SiGe superlattice, over its entire height, stopping on the substrate S, here the BOX S2. It can be carried out by plasma using an HBr / 02 etching chemistry. The first patterns 10IM can have a length Li along x of between 10 nm and 500 nm. They preferably have a width h along y of between 5 nm and 20 nm. This first structuring of the stack E in the form of fins or “fins” according to current English terminology, makes it possible to define a plurality of superimposed nanowires or nanosheets.

[0065] For the sake of clarity, the following figures iB (i=3... 15) illustrate only one “end” pattern 101M.

[0066] As illustrated in Figures 3A, 3B, sacrificial gates 150 are then formed on the “end” patterns 101M. The formation of these sacrificial gates 150 is typically done by deposition then lithography / etching. The formation of the sacrificial gates 150 is configured so that the sacrificial gates 150 are straddled on the “end” patterns 101M, as illustrated in [Fig. 3B]. The sacrificial gates 150 typically comprise an upper portion located on the “end” pattern 101M, and lateral portions located on the lateral flanks of the “end” pattern 101M. The sacrificial grids 150 typically rest on the substrate S. At this stage, the sacrificial grids 150 are typically surmounted by an etching mask 160, called a hard mask, implemented in the structuring of the sacrificial grids 150. The sacrificial grids 150 are for example based on polycrystalline silicon.A thin layer of SiO2 oxide, 7 nm thick for example, is preferably deposited prior to the formation of the sacrificial gates 150. This thin layer of SiO2 oxide (not . illustrated in the figures) is thus interposed between the sacrificial gates 150 and the “end” patterns 101M. This thin layer of SiO2 oxide can form a stop layer for the subsequent etching of the sacrificial gates 150.

[0067] As illustrated in FIGS. 4A, 4B, first spacers 170 are then formed on the yz-oriented flanks of the sacrificial gates 150. In general, in projection along z, these spacers form a continuous ring around each sacrificial gate 150, with a closed contour. In cross-section, however, along the xz plane illustrated in [Fig. 4A], the first spacer 170 has two facing portions on each of the flanks of the sacrificial gate 150. These two portions are generally designated as being the first spacers 170, even if they can be considered as belonging to a single spacer. The first spacers 170 typically extend to an upper face of the hard masks 160. The first spacers 170 are typically based on silicon nitride SiN or a dielectric material with a low dielectric constant, for example based on SiCO.

[0068] As illustrated in Figures 5A, 5B, after formation of the first spacers 170 by deposition / etching, the anisotropic etching along z is extended in order to define second patterns 102M, and second openings 200. The etching is configured to etch the stack E over its entire height, stopping on the substrate S. It can be carried out by plasma using an HBr / O2 etching chemistry.

[0069] As illustrated in Figures 6A, 6B, after formation of the second openings 200, the first layers 10 are partially etched selectively to the second layers 20, to the substrate S and to the first spacers 170. The etching of the first material of the first layers 10 typically has a SiO:2O selectivity relative to the second material of the second layers 20, of at least 5:1, preferably at least 10:1. This partial etching aims to form first spaces 11 directly above the first spacers 170. This partial etching is typically stopped in time. It has an isotropic character and can be carried out by a wet or dry method, from the second openings 200. At the end of this partial etching, central parts of the first layers 10 are preserved under the sacrificial gates 150.

[0070] As illustrated in Figures 7A, 7B, the first spaces 11 are then filled with a dielectric material, for example with silicon nitride or with a low permittivity dielectric, to form internal spacers 171. These “internal” spacers 171 are integrated into the stack E, preferably directly above the first spacers 170. They are in contact with the central parts of the first layers 10. The formation of the internal spacers 171 is typically done from the second openings 200.

[0071] As illustrated in FIGS. 8A, 8B, a retaining layer 25, for example based of SiO2, is deposited on and between the second patterns 102M so as to fill the openings 200. This retaining layer 25 is then planarized, typically by chemical-mechanical polishing CMP with stopping on the hard masks 160.

[0072] As illustrated in Figures 9A, 9B, the hard masks 160 are first removed, then the sacrificial gates 150 are also removed. This removal can be carried out by wet etching with stopping on the thin stop layer based on SiO2 or another dielectric. This wet etching typically has a high selectivity with respect to the stop layer and the first spacers 170. This wet etching can be based on a solution of ammonia salts TMAH (Tetramethylammonium hydroxide) or TEAH (Tetraethylammonium Hydroxide). The SiO2-based barrier layer is then typically wet-etched to expose the upper face of the last layer of the stack E, here a second layer 20. This removal of the sacrificial gates 150 makes it possible to form third openings 300 opening onto the central parts of the first layers 10 ([Fig.9B]).

[0073] As illustrated in Figures 10A, 10B, the central parts of the first layers 10 are then completely etched selectively to the second layers 20, to the internal spacers 171, and to the substrate S from the third openings 300. This etching aims to form cavities 21 in place of the central parts of the first layers 10. This total etching can be stopped in time, possibly after an over-etching time aimed at guaranteeing the total removal of the first material from the first layers 10. This total etching has an isotropic character and can be carried out by a wet or dry method, from the third openings 300. The second layers 20 are held by the spacers 170, 171 and by a holding layer 25, as illustrated in [Fig. 10A].

[0074] An advantageous step not illustrated in the figures consists of oxidizing the exposed parts of the second layers 20 from the third openings 300 and the cavities 21. This makes it possible to reduce the thickness along z and the lateral dimensions along y of the second material of the second layers 20. After replacing the second material of the second layers 20 to form the channels of the transistors, this ultimately makes it possible to obtain channels having reduced dimensions along z and along y. The channels of the transistors can thus have dimensions along z and along y of the order of a few nanometers.

[0075] As illustrated in Figures 1 1A, 1 1B, a dielectric layer 30 is then deposited in the cavities 21 from the openings 300. This dielectric layer 30 is typically based on a high permittivity material, for example based on HfO2. The dielectric layer 30 is typically intended to form the gate dielectric layer between the channels of the GAA transistors and their surrounding gates. It can be formed by chemical vapor deposition (CVD) position”), by chemical vapor deposition with organometallic precursors MOCVD (acronym for “Metal Organic Chemical Vapor Deposition”) or by atomic layer deposition ALD (acronym for “Atomic Layer Deposition”). It thus covers at least the exposed parts of the second layers 20, and preferably of the first spacers 170 and of the internal spacers 171, and the exposed upper face of the substrate S. The dielectric layer 30 typically has a thickness of between 1 nm and 5 nm.

[0076] As illustrated in Figures 12A, 12B, the third openings 300 and the cavities 21 are then filled with one or more metal layers 50, for example based on TiN, W, in order to form the encapsulating gates of the GAA transistors. According to one possibility, before deposition of the metal layers 50, a dielectric layer based on a high permittivity material, for example based on HfO2, is previously deposited in the third openings 300 and the cavities 21. This makes it possible to increase the thickness of the gate dielectric layer between the channels of the GAA transistors and their encapsulating gates 50. A chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the 102M patterns.

[0077] The method steps described above are common to the first and second embodiments of the present invention. The following method steps are described below for each of the two embodiments.

[0078] Figures 13A, 13B, 14A, 14B, 14C, 15A and 15B schematically illustrate, according to the first embodiment, the sequence of manufacturing steps of the method allowing the production of the device comprising stacked channel GAA transistors based on a semi-metallic material.

[0079] According to this first embodiment, as illustrated in FIGS. 13A, 13B, the holding layer 25 is opened by etching so as to partially reform the second openings 200b. These second openings 200b define the regions of the source and drain contacts. The two flanks along yz of each pattern 102M are exposed through these second openings 200b.

[0080] As illustrated in Figures 14A, 14B, 14C, the second layers 20 are then completely removed by selective etching with respect to the gate 50, the dielectric layer 30 and the spacers 170, 171. This etching can be stopped in time, possibly after an over-etching time intended to guarantee the total removal of the second material from the second layers 20. This total etching has an isotropic character and can be carried out by a wet or dry method, from the second openings 200b. At the end of this etching, second spaces 31 are formed in place of the second layers 20. The second openings 200b define the locations of the source and drain contacts. The second spaces 31 define the locations of the channels, drains and sources.

[0081] [Fig.l4C] illustrates a variant in which the section of the second spaces 31, and consequently of the channels of the transistors, is round or ovoid. Such a rounded shape can be obtained by oxidation of the second layers 20 after formation of the third openings 300 (removal of the sacrificial gate) and of the cavities 21 illustrated in [Fig.l0A]. More generally, it is understood that this section can adopt one of the following geometric shapes: rectangular as illustrated in [Fig.l4B], elliptical or ovoid as illustrated in [Fig.l4C], circular, square, rectangular with rounded corners or square with rounded corners. Whatever the geometric shape of this transverse section along yz, its dimension along z is preferably between 2 nm and 15 nm.

[0082] As illustrated in Figures 15A, 15B, a layer 40 based on a semi-metallic material is then deposited in the second openings 200b in the second spaces 31. The semi-metallic material may advantageously comprise bismuth. Thus, this semi-metallic material may correspond to bismuth or an alloy comprising bismuth and at least one of the following materials: tin, antimony, arsenic.

[0083] The deposition of such a semi-metallic material can be carried out by MOCVD, ALD or by a combination of these methods, using for example one or more of the following precursor gases: Bis(acetate-O) triphenylbismuth(V) (CH3CO2)2Bi(C6H5)3), tri-phenylbismuth (Bi(C6H5)3), and Tris(2-methoxyphenyl)bismuthine ((CH3OC6H4)3Bi). The semi-metallic material can be doped in situ during deposition. In the case of the bismuth-based semi-metallic material, an example of an N-type dopant is the element tellurium (Te). The in situ doping with the element Te can be carried out using one or more of the following precursor gases: anhydrous tellurium tetrabromide (TeBr4), tellurium tetrachloride (TeCl4). The concentration of Te in the N-doped bismuth-based semi-metallic material is typically between 1017 cm3 and 5xl020 cm3.

[0084] The deposition of the semi-metallic material is here configured so that the layer 40 completely fills the second spaces 31 and the second openings 200b. A crystallization annealing is carried out after deposition, in order to obtain a crystalline structure for the layer 40. This crystallization annealing may comprise the implementation of the following steps: - A deposit of at least one dielectric covering material, covering the exposed parts of the semi-metallic material, then - Annealing at a temperature higher than the melting temperature of the semi-metallic material.

[0085] After crystallization of the semi-metallic material, the layer 40 forms both the channels 41a, 41b, 41c of the GAA transistors T1, T2, the sources 42 and the drains 43 of the GAA transistors T1, T2, and the source and drain contacts 40S, 40D. The channels 41a, 41b, 41c and the sources 42 and the drains 43 advantageously have electrical conduction properties of a semiconductor, by constriction of the semi-metallic material of the layer 40. The source and drain contacts 40S, 40D advantageously have electrical conduction properties of a metal. Thus, the deposition and the crystallization annealing of the layer 40 form a plurality of functional elements of the transistors T1, T2, in a minimum of steps.

[0086] In this method, the portion of semi-metallic material forming the channel is not produced beforehand by growth on a metal substrate, but by deposition of the semi-metallic material in the channel location.

[0087] This method is typically based on the production of a "mold" formed by the channel locations and source and drain contacts, in which the semi-metallic material is then deposited. The deposition of the semi-metallic material in this mold makes it possible to constrain the shape that the semi-metallic material will take after its crystallization. This also makes it possible to prevent the semi-metallic material from having rough surfaces.

[0088] The semiconductor behavior of the channels 41a, 41b, 41c is obtained by quantum confinement effect of the charge carriers (electrons). When the semi-metallic material is for example bismuth, this quantum confinement effect can be obtained for dimensions of the order of 15 nm, at room temperature. When the semi-metallic material is for example tin, this effect can be obtained for dimensions of the order of approximately 2 nm at room temperature.

[0089] The crystallization annealing is preferably carried out at a temperature higher than the melting temperature of the semi-metallic material. When this semi-metallic material corresponds to bismuth, this annealing is carried out at a temperature higher than 271°C.

[0090] Figures 16A, 16B to 20A, 20B schematically illustrate a second embodiment of the method for manufacturing the device comprising stacked channel GAA transistors based on a semi-metallic material.

[0091] According to this second embodiment, as illustrated in FIGS. 16A, 16B, a portion of the holding layer 25 and the patterns 102M are masked by deposition of a second dielectric layer 26, in order to open only the drain region located between the two patterns 102M. The second opening(s) 200c correspond here to the definition of a single type of contact, for example the drain contacts. A single flank along yz of each pattern 102M is thus exposed through the second openings 200c.

[0092] As illustrated in Figures 17A, 17B, a layer based on a metallic material is then deposited in the second opening 200c to form the drain contact 45D. The metallic material of the drain contact 45D may conventionally be based on one of the following metals: copper (Cu), cobalt (Co), gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), tungsten (W), titanium nitride (TiN), or other metals. A dielectric cap 27 is then formed over the drain contact 45D, in order to protect the exposed portion of this drain contact 45D.

[0093] As illustrated in Figures 18A, 18B, second openings 200d are then formed in the holding layer 25. The second openings 200d correspond here to the definition of the other type of contact, for example the source contacts. The other flank along yz of each pattern 102M is thus exposed through the second openings 200d.

[0094] As illustrated in Figures 19A, 19B, the second layers 20 are then completely removed by selective etching with respect to the dielectric layer 30, the spacers 170, 171, and the contact 45D. This total etching can be done as previously, from the second openings 200d. At the end of this etching, the second spaces 31 are formed in place of the second layers 20.

[0095] As illustrated in Figures 20A, 20B, the layer 40 based on the semi-metallic material is here formed in the second spaces 31 by growth from the contact 45D. The metal of the contact 45D typically forms a substrate for the epitaxy of the semi-metallic material of the layer 40. As previously, a step of crystallization of the semi-metallic material is preferably carried out.

[0096] The layer 40 forms as previously the channels 41a, 41b, 41c, the sources 42 and the drains 43 of the GAA transistors T1, T2. The layer 40 here forms only the source contacts 40S of the GAA transistors T1, T2.

[0097] A microelectronic device comprising at least two transistors T1, T2, with channels 41a, 41b, 41c stacked along z and with a covering gate 50, is thus advantageously obtained. The channels 41a, 41b, 41c, the sources 42 and the drains 43 are advantageously based on a semi-metallic material. At least one of the source 40S and drain 40D contacts is also based on this semi-metallic material.

[0098] The nanometric dimensions along y and / or along z of the channels 41a, 41b, 41c allow the semi-metallic material to adopt the properties of a semiconductor. In addition, the larger dimensions of the source and drain contacts 40S, 40D allow the semi-metallic material to adopt the properties of a metallic material.

[0099] In view of the above description, it appears clearly that the proposed method offers a particularly effective solution for forming GAA transistors based on semi-metallic material. This solution is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

Claims

Claims

1. Microelectronic device comprising at least one transistor (T1, T2) comprising: • a source (42) and a drain (43), • a plurality of channels (41a, 41b, 41c) based on a semi-metallic material, said channels extending in a longitudinal direction (x) between the source (42) and the drain (43), each channel having at least one transverse dimension, taken perpendicular to the longitudinal direction (x), such that the semi-metallic material has an electrical conduction property of a semiconductor material, • a so-called wrapping gate (50), surrounding at least one of the channels (41a, 41b, 41c), and preferably several channels (41a, 41b, 41c) of the plurality of channels (41a, 41b, 41c), • a gate dielectric layer (30) separating each channel (41a, 41b, 41c) of the surrounding grid (50), • source and drain contacts (40S, 40D) electrically connected respectively to the source (42) and to the drain (43),at least one of the source and drain contacts (40S, 40D) being based on the semi-metallic material and having dimensions such that the semi-metallic material has an electrical conduction property of a metallic material, • spacers (170, 171) on either side of the gate (50), configured to electrically insulate the gate (50) from the source and drain contacts (40S, 40D), the device being characterized in that the surrounding gate (50) completely surrounds several channels (41a, 41b, 41c) of the plurality of channels (41a, 41b, 41c), in a transverse plane (yz) perpendicular to the longitudinal direction (x).,

2. Device according to the preceding claim comprising at least two transistors (Tl, T2) arranged in a first direction (x, y) called horizontal, in which the channels (41a, 41b, 41c) of each transistor (Tl, T2) are stacked in a second direction (z) called vertical, perpendicular to the first direction (x, y).

3. Device according to any one of the preceding claims in which the other of the source and drain contacts (40S, 40D) is made of a metal.

4. A device according to any preceding claim wherein the semi-metallic material is based on at least one element from bismuth (Bi), tin (Sn), antimony (Sb) or arsenic (As).

5. A method of manufacturing a microelectronic device according to any one of the preceding claims, said method comprising the following steps: • Providing on a substrate (S) a stack (E) comprising, in the direction (z), a plurality of first layers (10) made of a first material, alternating with a plurality of second layers (20) made of a second material, the first material and the second material being different from each other and different from the semi-metallic material forming the channels (41a, 41b, 41c), • Forming in this stack (E) first openings (100) defining first patterns (101M), • Forming a sacrificial gate (150) straddling the first patterns (101M) and partly in the first openings (100), • Forming in the first patterns (101M) second openings (200) defining second patterns (102M),such that the second patterns (102M) are transverse to the first patterns (101M), • Forming the gate dielectric layer (30), • Forming the gate spacers (170, 171), • Forming a holding layer (25) in said second openings (200), on exposed flanks of the second patterns (102M), • Removing the sacrificial gate (150) so as to form third openings (300), • Completely removing, from the third openings (300), the first material of the first layers (10) selectively to the second material of the second layers (20), so as to form cavities (21), • Filling the cavities (21) with a gate material, so as to form the encapsulating gate (50), • At least partially removing the holding layer (25) so as to at least partially reform the second openings (200b) exposing sides of the second layers (20), • Completely removing, from the second openings (200b), the second material of the second layers (20) so as to form second spaces (31), • Depositing a layer (40) based on a semi-metallic material in the second spaces (31) and at least partially in the second openings (200b), so as to simultaneously form: • channels (41a, 41b, 41c) based on the semi-metallic material directly above the surrounding gate (50), • at least one of the source and drain contacts (40S, 40D) based on the semi-metallic material.

6. Manufacturing method according to the preceding claim, wherein the formation of the spacers (170, 171) comprises the following steps: • Forming first spacers (170) bordering the sacrificial grid (150) and resting on the first patterns (101M), • Before forming the holding layer (25), partially removing, from the second openings (200), the first material of the first layers (10) selectively to the second material of the second layers (20), so as to form first spaces (11) directly above the first spacers (170), • Filling the first spaces (11) with a first dielectric material to form internal spacers (171).

7. Manufacturing method according to any one of claims 5 to 6, in which the encapsulating grid (50) is formed before the deposition of the layer (40) based on the semi-metallic material.

8. A manufacturing method according to any one of claims 5 to 7, wherein the formation of the gate dielectric layer (30) is formed after complete removal of the first material from the first layers (11) and before formation of the surrounding gate (50), by deposition of a dielectric layer in the cavities (21) and in the third openings (300), on the exposed parts of the second layers (20).

9. A manufacturing method according to any one of claims 5 to 8, wherein the formation of the spacers (170, 171) and the formation of the gate dielectric layer (30) are carried out at least in part by the same deposition of a dielectric layer in the cavities (21).

10. Manufacturing method according to any one of claims 5 to 9, in which the deposition of the layer (40) based on the semi-metallic material is carried out in the second spaces (31) and in all the second openings (200b) so as to form the channels (41a, 41b, 41c) and all the source and drain contacts (40S, 40D).

11. A manufacturing method according to any one of claims 5 to 9, wherein the second openings (200c, 200d) are reformed by successively exposing a single flank of the second layers (20), and wherein the deposition of the layer (40) based on the semi-metallic material forms a single contact (40S, 40D) among the source and drain contacts (40S, 40D).

12. A manufacturing method according to the preceding claim, wherein the other contact among the source and drain contacts is a metal contact (45D) formed by depositing a metal layer in a portion of the second openings (200c).

13. Manufacturing method according to the preceding claim, in which the deposition of the layer (40) based on the semi-metallic material is carried out by growth from exposed areas of said metal contact (45D) through the second spaces (31).

14. Manufacturing method according to any one of claims 5 to 13, further comprising, after deposition of the layer (40) based on the semi-metallic material, crystallization annealing.

15. Manufacturing method according to the preceding claim, in which the layer (40) based on the semi-metallic material is covered prior to the crystallization annealing, and in which the crystallization annealing is carried out at a temperature higher than the melting temperature of the semi-metallic material.

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