Clock signal supply circuit

Abstract

Clock Signal Supply Circuit This description relates to a clock signal supply circuit (180) comprising a selector (320) for one of several clock signals (CK50, CK100, CK150, CK200); a switch (225) between the selector and a supply node (NOUT) for the selected clock signal, the circuit (180) being configured so that applying a command to select one of the clock signals causes, in order, the opening of the switch (225), the selection of the signal via the selector (320), and the closing of the switch (225). Figure for the abstract: Fig. 3

Description

Title of the invention: Clock signal supply circuit technical field

[0001] This description relates generally to the circuits for supplying a clock signal, and the associated methods. Previous technique

[0002] Most digital circuits use multiple clock signals to control the synchronicity of their operations. In the use of these circuits, selecting and switching from one clock signal to another requires careful attention to the risk of generating unwanted pulses (a "glitch"). Current solutions for clock signal selection are energy-intensive and require significant chip area. Summary of the invention

[0003] There is a need to limit the creation of unwanted pulses (glitches) when selecting a clock signal while limiting energy consumption and the chip area required.

[0004] An embodiment overcomes all or part of the drawbacks of known electronic circuits.

[0005] One embodiment provides a clock signal supply circuit comprising: a selector of one signal among several clock signals; a switch between the selector and a node supplying the selected clock signal, the circuit being configured so that the application of a command to select one of the clock signals causes, in order, the opening of the switch, the selection of the signal via the selector, and the closing of the switch.

[0006] One embodiment provides a method for operating a clock signal supply circuit, the method comprising, following the application of a signal selection command, the following successive steps: - the opening of a switch connecting a selector of one clock signal among several and a supply node; - signal selection via the selector and; - the switch closing.

[0007] In one embodiment, the circuit is configured to open the switch when a change in the selection command is detected.

[0008] In one embodiment, the circuit is configured to select said signal after a first delay of at least two rising edges of an offset signal, following the detection of the change.

[0009] In one embodiment, the circuit is configured to close the switch after a second delay, of at least two rising edges of the offset signal, following said selection.

[0010] In one embodiment, the electronic circuit is configured to generate, with a first circuit, a first signal when the change is detected.

[0011] In one embodiment, the circuit is configured to generate, with a second circuit, a second signal, derived from the first signal, and shifted in time by the first delay.

[0012] In one embodiment, the second circuit includes an RS type flip-flop whose output is connected to an inverter which is in series with an input of a shift register of at least two stages and / or a delay cell; the second signal being generated on an output of the shift register; a first input of the RS type flip-flop being configured to receive the first signal and a second input of the RS type flip-flop being configured to receive the second signal.

[0013] In one embodiment, the circuit includes a third circuit configured to allow propagation of the selection command to the signal selector as a function of an output of a first logic block capable of performing a NOT-OR function from a signal present at the output of the inverter and the second signal.

[0014] In one embodiment, the third circuit comprises a control signal-locking flip-flop composing the selection control, each locking flip-flop having: - a gate input connected to the output of the first logic block, - a data input configured to receive the corresponding control signal, and - an output connected to the signal selector.

[0015] In one embodiment, said offset signal is a clock signal having a frequency less than or equal to that of the signal, among said several clock signals, having the lowest frequency.

[0016] In one embodiment, the switch includes a first block of which: a clock input is connected to the selector, a first activation input is connected to the output of the first logic block, and an output is connected to a second activation input of a second block of the switch; one output of the second block of the switch being connected to the supply node and a clock input of the second block being connected to an output of the selector.

[0017] In one embodiment, the switch is configured to be open when the output of the first logic block is at a low level.

[0018] In one embodiment, the switch is configured to be closed when the output of the first logic block is at a high level, the selected clock signal then being found on the supply node.

[0019] In one embodiment, the first block of the switch comprises a first and a second flip-flop in series, the clock input of the first block being a clock input of the first flip-flop and the output of the second flip-flop being connected to the second enable input of the second block.

[0020] One embodiment provides a microcontroller including a clock signal supply circuit as described above. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] Fig. 1 represents a schematic view of an example of an electronic circuit;

[0023] Figure 2 represents, in a very schematic way, an example of the implementation of a electronic circuit block of [Fig.1];

[0024] [Fig.3] represents in a very schematic way a block of the electronic circuit of [Fig.1] according to one embodiment;

[0025] [Fig.4] represents a circuit of the block of [Fig.3] according to one embodiment;

[0026] [Fig.5] represents a circuit of the block of [Fig.3] according to one embodiment;

[0027] [Fig.6] represents a circuit of the block of [Fig.3] according to one embodiment;

[0028] [Fig. 7] represents a circuit of the block of [Fig. 3] according to one embodiment; and

[0029] [Fig.8] is a timing diagram of the operation of the block in [Fig.3]. Description of the implementation methods

[0030] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0033] In the following description, when referring to positional qualifiers absolute, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "inferior", etc., or to orienting qualifiers, such as the terms "horizontal", "vertical", etc., refers, unless otherwise specified, to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0035] Fig. 1 represents a schematic view of an example of an electronic circuit 100.

[0036] The circuit 100 includes a memory 120 (FLASH MEMORY) for example not volatile, or of the FLASH memory type, capable of communicating, via a communication bus 110, with for example a memory interface 130 (FLASH INTERFACE) configured to write or read data into and from non-volatile memory 120.

[0037] The circuit 100 further includes, for example, a processing unit 150 (CPU) comprising one or more processors under the control of instructions stored in an instruction memory 170 (INSTR MEM). The instruction memory 170 is, for example, a volatile random access memory (RAM). The processing unit 150 and the memory 170 communicate, for example, via a system bus 160 (data, address, and control bus). The memory 120 is connected to the system bus 160 via the non-volatile memory interface 130 and via the bus 110. The device 100 further includes, for example, an input / output interface 140 (FO interface) connected to the system bus 160 for external communication.

[0038] The circuit 100 can integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, other processing units), not illustrated in [Fig. 1]. Among these other circuits, the circuit 100 includes, for example, a read-only or static memory.

[0039] Some or all of the different elements 110, 120, 130, 140, 150, 160, 170 may have a digital operation. In this case, the timing of their operations is obtained, for example, by using one or more clock signals representing a sequence of pulses, for example in the form of square waves, alternating between a high state (1) and a low state (0).

[0040] The circuit 100 includes a supply block 180 (CLKS PROVIDER) of one or more clock signals. This supply block is, for example, connected, preferably linked, to one or all of the elements 110, 120, 130, 140, 150, 160, 170.

[0041] The supply block 180 may need to change the clock signal, for example with a higher or lower frequency signal, that it supplies to the elements to which it is connected. This change is made, for example, by selecting one from several clock signals made available by clock signal generation circuits not shown.

[0042] Selecting one clock signal from several requires special attention because if the clock signal to be changed is interrupted at the wrong time, for example in the high state, or during the transition from one clock signal to another, this can generate spurious pulses.

[0043] Figure 2 schematically represents an example of the implementation of a block of the electronic circuit of Figure 1. More specifically, Figure 2 illustrates an example of the implementation of supply block 180.

[0044] The example in [Fig.2] includes a first, a second, a third and a fourth switching circuits 225, for example similar to each other.

[0045] Each of the switches 225 includes, for example, a first block 202 forming a resynchronization cell. The first block 202 includes, for example, a first and a second flip-flop 210, 220, for example D flip-flops, in series. In one example, these flip-flops form a shift register. In another example, the two flip-flops 210 and 220 are of the rising edge-detection type. The first flip-flop 210 includes a clock input CP, a reset input R, and an enable input D. An output of the first flip-flop 210 is connected to the input of the second flip-flop 220. The clock inputs CP and reset input R of the first flip-flop 210 of the switches 225 correspond respectively to a clock input CP and a reset input R of the respective switches 225.

[0046] The CP clock input of each switch 225 is configured to be connected to a rail receiving a C25, CK50, CK100, or CK200 clock signal, with a frequency or duty cycle that differs from one switch 225 to another. For example, a CK25 signal has a frequency of 25 MHz, a CK50 signal has a frequency twice that of a CK25 signal, a CK100 signal has a frequency twice that of a CK50 signal, and a CK200 signal has a frequency twice that of a CK100 signal. The D input of each of the first flip-flops 210 of each switch 225 is configured to receive a respective A EN 25, A EN 50, A EN 100, or A EN 200 turn-on signal. The D input of each first flip-flop 210 corresponds to a D turn-on input of the respective switch 225.

[0047] In the example shown, each switch 225 further comprises a second block 230. An output Q of the second flip-flop 220 of each switch 225 is connected to an enable input E of the second block 230 of the respective switch 225. The respective enable input E of each second block 230 is configured to receive an enable signal S_EN_25, S_EN_50, S_EN_100, S_EN_200, which corresponds to the output signal on the Q output of the second flip-flop 220 of the corresponding first block 225. Generally, the respective enable signal corresponding to the output signal on the Q output of the The second flip-flop 220 of the first block 202 corresponds to a clock signal CK. In one example, the second blocks 230 are formed with a D flip-flop.

[0048] The second 230 blocks further include a CP clock input connected to the corresponding first rail receiving one of the CK25, CK50, CK100, CK200 clock signals. An output Q of the second 230 block is connected to a supply node NOUT, NOUT2, NOUT3 and NOUT4 of the corresponding 225 switch.

[0049] The switches 225, via the second block 230, act as clock signal switching cells ("Clock Gating") by stopping the propagation of the clock signal to the respective supply nodes NOUT, NOUT2, NOUT3, NOUT4 only when the clock signal is low to avoid spurious pulses and provided that the activation signal of the second block 230 is synchronous with the clock signal to be stopped or propagated. The first block 202 ensures that the activation signal of the second block 230 is synchronous with the clock signal to be stopped or propagated.

[0050] During operation, the 225 switches can be in an open or closed state. In a closed state, the 225 switches allow the propagation of the clock signal received at their clock input CP, that is, the clock input common to the first flip-flop 210 and the second block, to their respective supply nodes NOUT, NOUT2, NOUT3, NOUT4. In an open state, the 225 switches no longer allow the propagation of the clock signal to the respective supply nodes NOUT, NOUT2, NOUT3, NOUT4.

[0051] In the following operating examples, both flip-flops 210 and 220 are of the rising edge detection type.

[0052] With regard to the 225 switches, to switch from open mode to closed mode, the respective activation signals A EN 25, A EN 50, A EN 100, and A EN 200 of the first block are low, as are the activation signals S_EN_25, S_EN_50, S_EN_100, and S_EN_200 of the second block 230 and the signal on the respective supply node NOUT, NOUT2, NOUT3, and NOUT4. Then, the respective activation signals A EN 25, A EN 50, A EN 100, and A EN 200 of the first block rise to a high state. Then the activation signal S_EN_25, S_EN_50, S_EN_100, S_EN_200 of the second block 230 also goes high after two rising edges (corresponding to the number of flip-flops 210, 220 present) are received on the clock input. The clock signal propagates to the corresponding supply node after a third rising edge is received on the clock input.

[0053] To switch from closed mode to open mode, the respective activation signals A EN 25, A EN 50, A EN 100, and A EN 200 of the first block are high, as are the activation signals S EN 25, S EN 50, S EN 100, and S EN 200 of the second block. In closed mode, the signal propagating on the supply node NOUT, NOUT2, NOUT3, and NOUT4 are the respective clock signals received at the clock input. Next, the respective activation signals A_EN_25, A_EN_50, A_EN_100, and A_EN_200 of the first block go low. Then, the activation signals S_EN_25, S_EN_50, S_EN_100, and S_EN_200 of the second block go low after two rising edges (corresponding to the number of flip-flops 210 and 220 present) are received at the clock input. The clock signal then stops propagating to the corresponding supply node after a third rising edge is received at the clock input.

[0054] In the example shown, the supply block 180 includes two logic blocks 240, 280 configured to perform a NOT-OR (NOR) type function from the signals present on the nodes NOUT,NOUT2 and NOUT3,NOUT4 respectively.

[0055] In the example shown, the supply block 180 further includes a logic block 290 configured to perform a NOT-AND (NAND) type function from the signals present respectively at the output of the logic blocks 240 and 280.

[0056] Depending on the state of the respective activation signals A_EN_25, A_EN_50, A_EN_100, A_EN_200 of each of the switches 225, the supply block 180 allows the selection, at the output of the logic block 290, of a clock signal from among the possible signals CK25, CK50, CK100 and CK200.

[0057] The fact that the circuit in [Fig. 2] requires as many 225 switches as there are clock signals to select implies a large chip area and high power consumption. In the case of microcontrollers, for example, these two factors are critical, and it is important to be able to limit them while maintaining the ability to filter out spurious pulses (glitch).

[0058] To this end, the described embodiments provide a clock signal supply circuit comprising: a selector of one signal among several clock signals; a switch between the selector and a node supplying the selected clock signal, the electronic circuit being configured so that the application of a command to select one of the clock signals causes, in order, the opening of the switch, the selection of the signal via the selector, and the closing of the switch.

[0059] Having only one switch for all available clock signals allows for chip area savings and also reduces power consumption. The fact that the switch is initially open before the selection of the clock signal to be supplied prevents the propagation of spurious pulses that might be generated during the clock signal selection process. Once the new clock signal is selected, and thus stabilized, it is then possible to close the switch to propagate the selected clock signal.

[0060] [Fig.3] represents, in a very schematic way, a block of the electronic circuit 100 of [Fig.1] according to one embodiment.

[0061] More specifically, [Fig.3] illustrates one embodiment of the supply block 180.

[0062] In the example of [Fig.3], the supply block 180 includes a selector 320 (MUX) whose output is connected to a switch, for example similar to the switch 225 of [Fig.2], so that a signal (CK_DIG_RAW) present at the output of the selector 320 is found at the clock input CP of the switch 225.

[0063] In the example shown, selector 320 is configured to select one of the clock signals CK50, CK100, CK200, and six other signals not shown, from control signals (MUX_CTRL_FILT<8:0>). The notation <8:0> is a concatenated notation for nine different signals, referenced from 0 to 8. The MUX_CTRL_FILT<8:0> control signals originate from a control unit 330 (CTRL) which generates raw selection control signals (MUX_CTRL<8:0>). The propagation of these raw MUX_CTRL<8:0> selection control signals to selector 320 is controlled by a latching circuit 360 (LATCH STD) based on the state of a signal (CHANGE_DELAYED).

[0064] In the example shown, the supply block 180 includes a circuit 340 (CHANGE DETECT) configured to detect a change in the raw MUX_CTRL<8:0> selection control signals. When a change is detected, a signal (CHANGE_PULSE) takes, for example, the form of a pulse.

[0065] The circuit 340 is connected, preferably linked, to a circuit 310 (DELAY) configured to generate a signal (CHANGE_DELAYED), according to the signal CHANGE_PULSE, and offset in time by a first time offset.

[0066] Circuit 310 receives as input a clock signal CK25 which, for example, has a frequency half that of the slowest available clock signal (here CK50) or a clock signal whose frequency is, for example, half that of the slowest clock signal. Circuit 310 is further configured to receive as input a reset signal RESET sent by control unit 330.

[0067] Circuit 310 is configured to provide an output signal (CHANGE) and a signal (CHANGE_DELAYED). The CHANGE and CHANGE_DELAYED signals are fed back into circuit 310 so that the CHANGE signal rises when a positive pulse is present on the CHANGE_PULSE signal, and it falls when the CHANGE_DELAYED signal rises. The CHANGE_DELAYED signal corresponds to the image of the CHANGE signal with a time offset of at least two, preferably at least three, rising edges of the CK25 clock signal which is at the input. of circuit 310.

[0068] In the example shown, input D of switch 225 is connected, preferably via a logic block 325 configured to perform a NOR function from the CHANGE and CHANGE_DELAYED signals. The output of logic block 325 is an A_EN activation signal from the first block 202 of switch 225.

[0069] A method for operating the supply circuit 180 of [Fig.3] comprises, following the application of a signal selection command, the following successive steps: - the opening of switch 225 connecting selector 320 of one clock signal among several and the NOUT supply node; - signal selection via selector 320 and; - the closing of switch 225.

[0070] In operation, circuit 340 is configured to open switch 225 when one or more changes occur in the MUX_CTRL<8:0> signals, which generates a pulse on the CHANGE_PULSE signal. Circuit 310 receives the CHANGE_PULSE pulse, which lowers the CHANGE signal at its output, which in turn lowers the A_EN signal, ultimately opening switch 225.

[0071] The CHANGE signal is looped back into circuit 310 and becomes the CHANGE_DELAYED signal after at least two clock cycles of the CK25 clock signal, whose frequency is half that of the slowest selectable signal, here CK50. The CHANGE_DELAYED signal is then high, which triggers the unlocking of the MUX_CTRL<8:0> signals by circuit 360 so that they propagate to the selector. The selected clock signal is then supplied to the CP clock input of switch 225, which is still open at this stage.

[0072] The CHANGE_DELAYED signal is also looped back into circuit 310 and the rising edge of the CHANGE_DELAYED signal resets the CHANGE signal to the low state.

[0073] The low state of the CHANGE signal then propagates to become the CHANGE_DELAYED signal after at least two rising edges of the CK25 clock signal. With the CHANGE and CHANGE_DELAYED signals in the low state, the A_EN signal goes high, which closes the 225 switch and allows the propagation, on the NOUT supply node of the 225 switch, of a CK_DIG signal, which is the new clock signal that has been selected.

[0074] Fig. 4 represents a circuit of the block of Fig. 3 according to one embodiment. In particular, [Fig.4] represents an example of the 340 circuit.

[0075] In the example shown, the circuit 340 comprises nine similar branches, each configured to receive, on a different input node, one of the signals from selection command MUX_CTRL<8:0>.

[0076] Each branch comprises one or more time-shifting circuits 402, 404 in series between the respective input node N0, N1, N2, N3, N4, N5, N6, N7, N8 of the branch, which respectively receives one of the MUX_CTRL<8:0> signals and an input from a logic block 410 of the same branch. Another input of the logic block 410 is fed back to the input node of its respective branch.

[0077] Each logic block 410 is configured to perform an exclusive OR (XOR) operation on the signal present at the input node of its respective branch and on the signal that has passed through the time-shifting circuits 402 and 404. The selection control signal MUX_CTRL<8:0> present at the input node of a branch will therefore be processed by the corresponding logic block 410 with its time-shifted version. This makes it possible to detect a change that occurred in the selection control signals MUX_CTRL<8:0> during the time shift, in other words, during the delay, introduced by circuits 402 and 404. The number of time-shifting circuits 402 and 404 in series in each branch can be greater than two or equal to one. The number of time-shifting circuits affects the pulse length of the CHANGE_PULSE signal.A person skilled in the art can adapt this number to ensure proper operation of the 310 circuit under all operating conditions of the integrated circuit. The output of each of the logic blocks 410, respectively labeled CHG_PULSE<8:0>, is connected, preferably directly connected, to a logic block configured to perform a NOR function. In the example shown, a logic block 450 is configured to perform a NOR function from the signals CHG_PULSE1, CHG_PULSE2 and CHG_PULSE3, a logic block 460 is configured to perform a NOR function from the signals CHG_PULSE4, CHG_PULSE5 and CHG_PULSE6, and a logic block 480 is configured to perform a NOR function from the signals CHG_PULSE0, CHG_PULSE7 and CHG_PULSE8.

[0078] The circuit 340 further includes a logic block 470 configured to perform a NAND function from the outputs of logic blocks 450, 460, and 480. The CHANGE_PULSE signal, which indicates whether a change has occurred on one or more MUX_CTRL<8:0> selection control signals, is generated on the output of logic block 470. In other words, logic blocks 450, 460, 470, and 480 together form an OR logic block that combines the CHG_PULSE<8:0> signals to generate a pull on the CHANGE_PULSE signal when a change is detected.

[0079] Figure 5 represents a circuit of the block in Figure 3 according to one embodiment. More particularly, Figure 5 represents an embodiment of circuit 310.

[0080] In the example shown, the circuit 310 includes a connected logic block 585, preferred The 585 logic block is configured to perform an AND operation using an ENABLE signal and a CHANGE_PULSE signal. The output of the 585 logic block is connected, preferably directly, to an input, for example S, of a 502 RS (SR) latch. In other words, when the ENABLE signal is activated, the CHANGE_PULSE signal is fed to the S input. Another input, for example the R input, of the 502 latch is connected to an output of a 512 shift register. An output of the 502 latch is connected to an input of the 512 shift register via a 535 inverter in series with an optional 575 time-shift block. The output signal of the 535 inverter is the CHANGE signal.

[0081] In the example shown, the shift register 512 is formed by two 565 and 555 flip-flops, for example D flip-flops, in series. Those skilled in the art may choose a shift register with more than two flip-flops in series. The D input of the 565 flip-flop is connected, preferably directly, to the output of the 535 inverter, optionally via the 575 time-shift block. The reset input R of the 565 flip-flop is configured to receive the ENABLE_N signal, and its clock input CP is configured to receive the slowest clock signal, here CK25. The Q output of the 555 flip-flop is connected to the R input of the 502 flip-flop.

[0082] In one example, the 502 flip-flop is formed of two logic gates 525, 545, for example of the N / OR type or possibly N / AND, inter-coupled (cross-coupled in English).

[0083] In the example shown, the 525 gate includes three inputs, the R input receiving the CHANGE_DELAYED signal from the 512 shift register, an input configured to receive an ENABLE_N enable signal and an input connected to the output of the 545 logic gate. One input of the 545 logic gate includes the S input and another input of the 545 logic gate is connected to the output of the 525 logic gate.

[0084] In operation, when the signals at inputs R and S are low, the output of the 502 flip-flop remains stable. If the signal at input S is a high pulse while the signal at input R remains low, the output signal changes and then remains stable, even when the signal at input S returns to a low state. Similarly, if the CHANGE_DELAYED signal is a rising pulse and the signal at input S is held low, then the output signal of the 502 flip-flop changes and remains stable, even when the CHANGE_DELAYED signal returns to a low state. Thus, the CHANGE signal goes high when a positive pulse is present on the CHANGE_PULSE signal and it goes low when the CHANGE_DELAYED signal goes high. On the other hand, the CHANGE_DELAYED signal is the image of the CHANGE signal with a time shift of three rising edges of the slowest clock signal, here CK25. The time shift The interplay between the CHANGE and CHANGE_DELAYED signals will allow switch 225 to close after the clock signal has been selected and supplied at the output of selector 320, thus ensuring that it is free from parasitic transient pulses that occurred during the selection.

[0085] The time shift block 575 prevents the output of the 502 flip-flop from being compromised when the CHANGE_DELAYED signal goes high, which could cause a falling edge on the CHANGE signal.

[0086] Fig. 6 represents a circuit of the block of Fig. 3 according to one embodiment. In particular, [Fig.6] represents one embodiment of the 360 ​​circuit.

[0087] In the example shown, the 360 ​​circuit comprises a single illustrated branch. Other branches, corresponding to the processing of all MUX_CTRL<8:0> signals, are not illustrated but are similar. The 360 ​​circuit includes a 610 logic block configured to perform an OR-type function using the CHANGE_DELAYED signal and the ENABLE_N enable signal. Each branch includes a 620 LATCH flip-flop. The LATCH output of the 610 logic block is connected to a control input G of each of the 620 LATCH flip-flops. Thus, the LATCH signal arrives at the G input of the 620 LATCH flip-flop in each branch. A D input of the 620 flip-flops is configured to receive one of the respective MUX_CTRL<8:0> select control signals. This MUX_CTRL<8:0> signal becomes the MUX_CTRL_FILT<8:0> signal once propagated to the Q output of the 620 latching flip-flop.Thus, the LATCH signal, which corresponds to the propagated CHANGE_DELAYED signal, controls the propagation of the raw selection control signals MUX_CTRL<8:0> before they are propagated to selector 320. The LATCH signal is preferably high only when the CK_DIG_RAW clock signal at the output of selector 320 is low; otherwise, a spurious pulse may be present.

[0088] In one example, the 620 locking flip-flop is replaced by a D flip-flop (which basically consists of two locking flip-flops in series) which is safer but occupies twice as much space as a simple locking flip-flop.

[0089] Fig. 7 represents a circuit of the block of Fig. 3 according to one embodiment. In particular, [Fig.7] illustrates one embodiment of selector 320.

[0090] In the example shown, the circuit 320 comprises four logic blocks 710, 712, 714, 716 configured to perform an AND type function from the signals MUX_CTRL_FILT4, CK200; MUX_CTRL_FILT3, CK100; MUX_CTRL_FILT2, CK50; MUX_CTRL_FILT1, CK150 respectively; the CK150 signal being for example a clock signal with a frequency intermediate between those of the CK100 and CK200 signals.

[0091] In the example shown, the circuit 320 also includes two logic blocks 718, 720 configured to perform a NOT-OR function from the outputs of logic blocks 714, 716 and 710, 712 respectively.

[0092] Circuit 320 further includes a logic block 730 configured to perform a NAND function from the outputs of logic blocks 718 and 720. The combination of logic blocks 718, 720, and 730 enables the implementation of an OR logic function from the outputs of logic blocks 710, 712, 714, and 716. The output signal of block 730 is the selected clock signal CK_DIG_RAW before it passes through switch 225.

[0093] In the example shown, only four logic blocks 710, 712, 714, 716 are shown, however the architecture shown in [Fig.7] can be duplicated so that the clock signal selection is made from a higher number of available clock signals.

[0094] In order for only one clock signal to be selectable at a time, the MUX_CTRL_FILT<8:0> signals are preferentially exclusive. When one of the MUX_CTRL_FILT<8:0> signals is high, then the clock signal present on the other input of the logic block 710,712,714,716 is propagated to the output of selector 320 and becomes the CK_DIG_RAW signal.

[0095] Figure 8 is a timing diagram of the operation of block 180 of Figure 3. More specifically, Figure 8 represents the time evolution of the signals CK100, CK50, CK_DIG_RAW, CK_DIG, MUX_CTRL, MUX_CTRL_FILT, CHANGE_PULSE, A_EN, S_EN_CK, EN_CK50, EN_CK100, RESET, CHANGE, CHANGE_DELAYED, LATCH, and CK25. In the example shown, the MUX_CTRL signal is the selection control signal among the MUX_CTRL<8:0> signals, which controls the selection of the CK100 signal.

[0096] The example shown illustrates the selection and switching of the CK50 signal to the CK100 signal on the NOUT node of [Fig.3].

[0097] Between a time t1 and a time t7, the signals CK25, CK50 and CK100 alternate high and low states with a duty cycle close to or equal to 50%. The frequency of CK100 is double that of CK50 and quadruple that of CK25.

[0098] Between time tl and a time t3 less than time t7, the CK_DIG_RAW signal selected and propagated by selector 320 is the CK50 signal.

[0099] At time t1, circuit 340 detects a change in the selection control signals MUX_CTRL<8:0> and the MUX_CTRL signal transitions from a low level to a high level and then remains stable at the high level. A pulse is then generated on the CHANGE_PULSE signal, which causes the A_EN signal to transition from a high to a low state and, one rising edge of the CK25 clock signal later, at a time t2 preceding time t3, the second block 230 of switch 225 transitions from the high state to the low state and interrupts the propagation of the CK50 signal. The CK_DIG output signal then becomes zero or stable in the low state.

[0100] At time t1, a positive pulse is sent to the RESET signal, which resets the 502 flip-flop of circuit 310, and the CHANGE signal goes from low to high and then remains stable. At the end of the third rising edge of the CK25 clock signal following this reset and the pulse of the CHANGE_PULSE signal, that is, at time t3, the CHANGE_DELAYED signal goes from low to high.

[0101] Circuit 360 blocks the modification of the MUX_CTRL signal between time t1 and time t3. At time t3, the LATCH signal and the EN_CK100 signal go from low to high, allowing the MUX_CTRL selection control signal to propagate through the corresponding latching flip-flop. At time t3, the EN_CK50 signal goes from high to low to stop the selection of the CK50 signal. The CK100 clock signal is then selected by selector 320 and forms the CK_DIG_RAW signal. However, this change in the clock signal has caused a spurious pulse (referenced as GLITCH on the timing diagram). However, since switch 225 is open at this point, the spurious pulse is not propagated.

[0102] At time t3, the RS 502 flip-flop is reset by the rising of the CHANGE_DELAYED signal, and the CHANGE signal transitions from high to low. The state of the CHANGE signal propagates to the state of the CHANGE_DELAYED signal on the third rising edge of the CK25 clock signal following t3 at time t4.

[0103] At time t4, the CHANGE_DELAYED signal transitions from high to low, and consequently, the LATCH signal does the same. The A_EN signal transitions from low to high, and after two subsequent rising edges of the CK100 clock signal, at time t5, the S_EN_CK signal transitions from low to high. The second block 230 of switch 225 then implements the propagation of the CK100 signal to the NOUT supply node of switch 225 after the next rising edge of the CK100 signal, and the CK_DIG signal then becomes the CK100 signal.

[0104] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, the number of flip-flops in series in block 202 of the switches may be greater than two, and the type of flip-flops in this block may be different from D flip-flops.

[0105] In another example, the shift register 512 can be replaced by a resynchronization cell of the same type as block 202. This allows the reduction of the risk of instabilities related to the potential desynchronization of the selection control signals and the clock signal used in the clock input of the shift register.

[0106] In general, the example of circuit 310 shows an example for generating a time lag between the opening of switch 225 and the selection of the new clock signal and also between the selection of the clock signal and the closing of switch 225. A person skilled in the art will be able to apply their knowledge to achieve such a time lag with other circuit architectures as long as the time lag is at least three, preferably four, rising edges of a clock signal (CK25) whose frequency is twice as low as the slowest clock signal to be selected (CK50).

[0107] An example of a 320 selector is shown in [Fig.7], however, the person of art will be able to apply their knowledge to implement a circuit for selecting a signal from among several signals based on selection control signals. Such a circuit is, for example, a multiplexer (MUX).

[0108] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional indications given above. In particular, with regard to the 225 switches, they may, for example, comprise only the second 230 block, without the first 202 block, provided that the clock signal is no longer propagated on the NOUT supply node only when the clock signal is low to avoid spurious pulses, and provided that the S_EN_CK activation signal of the second 230 block is synchronous with the clock signal to be stopped or propagated.

[0109] The supply circuit 180 as described above can be integrated into a low power microcontroller for example.

Claims

Claims

1. A circuit (180) for supplying a clock signal comprising: a selector (320) for selecting one of several clock signals (CK50, CK100, CK150, CK200); a switch (225) between the selector and a supply node (NOUT) of the selected clock signal, the circuit (180) being configured so that applying a command for selecting one of the clock signals causes, in order, the opening of the switch (225), the selection of the signal via the selector (320), and the closing of the switch (225).

2. The circuit (180) of claim 1, wherein the circuit (180) is configured to open the switch (225) when a change in the selection command is detected.

3. A circuit according to claim 2, wherein the circuit is configured to select said signal after a first delay of at least two rising edges of an offset signal (CK25), following detection of the change.

4. A circuit according to claim 3, wherein the circuit (180) is configured to close the switch (225) after a second delay, of at least two rising edges of the shift signal (CK25), following said selection.

5. A circuit according to any one of claims 2 to 4, wherein the electronic circuit is configured to generate, with a first circuit (340), a first signal (CHANGE_PULSE) when the change is detected.

6. Circuit according to claim 5, the circuit (180) being configured to generate, with a second circuit (310), a second signal (CHANGE_DELAYED), originating from the first signal (CHANGE_PULSE), and shifted in time by the first delay.

7. Circuit according to claim 6, the second circuit (310) comprising an RS type flip-flop (502) one output of which is connected to an inverter (535) which is in series with an input (D) of a shift register (512) of at least two stages and / or a delay cell (575); the second signal (CHANGE_DELAYED) being generated on an output (Q) of the shift register (512); a first input (S) of the RS type flip-flop (502) being configured to receive the first signal (CHANGE_PULSE) and a second input (R) of the RS type flip-flop (502) being configured to receive the second signal (CHANGE_DELAYED).

8. Circuit according to the preceding claim, the circuit (180) comprising a third circuit (360) configured to authorize the propagation of the selection command (MUX_CTRL<8:0>) to the signal selector (320) as a function of an output of a first logic block (325) capable of performing a NOR function (NOR) from a signal (CHANGE) present at the output of the inverter (535) and the second signal (CHANGE_DELAYED).

9. Circuit according to the preceding claim, the third circuit (360) comprising a latching flip-flop (620) per control signal (MUX_CTRL <8:0>) composing the selection command, each latching flip-flop (620) having: - a gate input (G) connected to the output of the first logic block (325), - a data input (D) configured to receive the corresponding control signal (MUX_CTRL <8:0>), and - an output (MUX_CTRL_FILT <8:0>) connected to the signal selector (320).

10. A circuit according to any one of claims 3, or 4 to 9 as dependent on claim 3, wherein said offset signal (CK25) is a clock signal having a frequency less than or equal to that of the signal (CK25), among said several clock signals, having the lowest frequency.

11. Circuit according to any one of claims 8, or 9 to 10 in their dependence on claim 8, in which the switch (225) comprises a first block (202) of which: a clock input (CP) is connected to the selector (320), a first activation input (D) is connected to the output of the first logic block (325), and an output (Q) is connected to a second activation input (E) of a second block (230) of the switch (225); an output (CK_DIG) of the second block (230) of the switch (225) being connected to the supply node (NOUT) and a clock input (CP) of the second block (230) being connected to an output of the selector (320).

12. A circuit according to any one of claims 8, or 9 to 111 as dependent on claim 8, wherein the switch (225) is configured to be open when the output of the first logic block (320) is at a low level.

13. Circuit according to the preceding claim, in which the switch (225) is configured to be closed when the output of the first logic block (325) is at a high level, the selected clock signal (CK_DIG) then being found on the supply node (NOUT).

14. A circuit according to any one of claims 11, or 12 or 13 in their dependence on claim 11, wherein the first block (202) of the switch (225) comprises a first and a second series flip-flop (210,220), the clock input (CP) of the first block (202) being a clock input of the first flip-flop (210) and the output of the second flip-flop (220) being connected to the second activation input (S_EN_CK) of the second block (230).

15. Method of operating a circuit for supplying a clock signal according to any one of the preceding claims, the method comprising, following the application of a signal selection command, the following successive steps: - opening a switch (225) connecting a selector (320) of a clock signal from among several and a supply node (NOUT); - selecting the signal via the selector (320) and; - closing the switch (225).

16. A microcontroller comprising a clock signal supply circuit according to any one of claims 1 to 14.

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