Optoelectronic device

Abstract

Optoelectronic Device This description relates to a device comprising at least one set (10) of pixels, the set comprising at least one first pixel (14) generating event data and at least one second pixel (12) generating light intensity data, each first and second pixel comprising a portion of a layer, said portion forming a photodiode, the device further comprising a first chip (16) comprising a first substrate (20) and a first interconnection network (22), and a second chip (18) comprising a second substrate (28) and a second interconnection network (30), the first and second chips being attached to each other by the interconnection networks, the layer (40) being located on a first face of the second substrate opposite a second face of the second substrate on which the interconnection network is located. Figure for the abstract: Fig. 1

Description

Title of the invention: Optoelectronic device technical field

[0001] This description relates generally to electronic devices, and more specifically to optoelectronic devices. Previous technique

[0002] Event cameras, like standard cameras, comprise a plurality of pixels, each pixel configured to provide a value corresponding to a location in an observed scene. However, unlike a standard camera, where each pixel is configured to periodically provide a light intensity value corresponding to the location, an event camera is configured to provide information indicating a change in light intensity. Event cameras are therefore configured to provide an event image of a scene. Standard cameras are therefore configured to provide a light intensity image of a scene. Thus, a standard camera is a synchronous camera that, at a given frame rate, produces a succession of images comprising as many intensity values ​​as there are pixels.An event camera is a synchronous or asynchronous camera that provides, for each pixel, information indicating the change in brightness of the corresponding location in the scene. When the scene is stationary, a standard camera continues to periodically provide all intensity values, whereas an event camera does not provide any value, indicating the absence of change. Summary of the invention

[0003] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices.

[0004] One embodiment provides for a device comprising at least one set of pixels, the set comprising at least a first pixel generating event data and at least a second pixel generating light intensity data, each first and second pixel comprising a portion of a layer, said portion forming a photodiode, the device further comprising a first chip comprising a first substrate and a first interconnection network, and a second chip comprising a second substrate and a second interconnection network, the first and second chips being fixed to each other by the interconnection networks, the layer being located on a first face of the second substrate opposite a second face of the second substrate on which the interconnection network is located.

[0005] According to one embodiment, the device is an event camera.

[0006] According to one embodiment, the first chip comprises at least a part of a the control circuit of the first pixel and the second chip includes the control circuit of at least a second pixel.

[0007] According to one embodiment, part of the control circuit of the first pixel is in the second chip.

[0008] According to one embodiment, the first and second chips are fixed by molecular bonding.

[0009] According to one embodiment, the device comprises a plurality of sets of pixels arranged in a matrix.

[0010] According to one embodiment, each set comprises four second pixels surrounding a first pixel.

[0011] According to one embodiment, each set comprises eight second pixels surrounding a first pixel.

[0012] According to one embodiment, each set comprises three second pixels and one first pixel arranged in matrices.

[0013] According to one embodiment, the layer is continuous.

[0014] According to one embodiment, the layer completely covers the first face of the second substrate.

[0015] According to one embodiment, the layer material is homogeneous.

[0016] According to one embodiment, the layer is in contact with the second substrate.

[0017] According to one embodiment, the layer is a layer of quantum dots or colloidal quantum dots.

[0018] According to one embodiment, the layer is made of a photosensitive perovskite material based on lead or tin or a volumetric heterojunction composed of photosensitive organic semiconductors. Brief description of the drawings

[0019] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0020] [Fig.1] represents a cross-sectional view of an embodiment of an optoelectronic device;

[0021] [Fig.2] represents a perspective view of the embodiment of [Fig.1];

[0022] [Fig.3] represents an example of a pixel control circuit;

[0023] Figure 4A represents a variant arrangement of a set of pixels; and

[0024] [Fig.4B] represents another variant of the arrangement of a set of pixels. Description of the implementation methods

[0025] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0027] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0030] Fig. 1 shows a cross-sectional view of an embodiment of an optoelectronic device. Fig. 2 shows a perspective view of the embodiment of Fig. 1. More precisely, Fig. 1 shows a cross-sectional view along plane AA of the device of Fig. 2.

[0031] Figures 1 and 2 represent a set 10 of pixels of the optoelectronic device. Set 10 corresponds, for example, to a portion of an image capture device, such as a camera. Set 10 comprises at least one pixel 12 and at least one pixel 14. More precisely, set 10 comprises at least one pixel 12 of an event camera and at least one pixel 14 of a standard camera. Pixel 14 is, for example, a "global shutter" pixel or a "rolling shutter" pixel. Set 10 thus allows for the acquisition of event data and standard brightness data. The camera is therefore an event camera, or neuromorphic camera (or "event-based camera").

[0032] In the example of figures 1 and 2, the set 10 comprises only one pixel 12 and four pixels 14. The pixel 12 is surrounded by the pixels 14. The device, i.e. for example the camera, comprises a plurality of sets 10, preferably arranged in a matrix.

[0033] The device comprises a first chip 16 and a second chip 18. The first chip 16 comprises a semiconductor substrate 20 and an interconnection network 22. The substrate 20 comprises an upper face 20a and a lower face 20b. Clearly, the interconnection network comprises an upper face 22a and a lower face 22b. The interconnection network 22 is fixed to the substrate 20. More precisely, the lower face 22b of the interconnection network 22 is fixed to the upper face 20a of the substrate 20.

[0034] The substrate 20 is, for example, made of silicon. Electronic components, not shown in Figures 1 and 2, are formed in and on the substrate 20. For example, electronic components are formed on the upper surface of the substrate 20.

[0035] The substrate 20 includes at least part of the control circuit of pixel 12. In other words, at least part of the electronic components forming the control circuit of pixel 12 are located in and on the substrate 20. For example, the substrate includes an amplifier, logic circuits, memory cells and a read circuit, synchronous or asynchronous, of pixel 12. Some components may be common to several pixels.

[0036] The interconnection network 22 comprises a stack of insulating layers, metallic tracks 24 located within the insulating layers, and conductive vias 26 located within the insulating layers and connecting the conductive tracks together. The bottom layer of the stack of insulating layers is in contact with the substrate 20, and in particular with the upper face of the substrate 20. The top layer of the stack, i.e., the insulating layer of the interconnection network furthest from the substrate 20, comprises, for example, metallic tracks 28. The tracks 28 are flush with the upper face 22a of the interconnection network.

[0037] Similarly, the second chip 18 comprises a semiconductor substrate 28 and an interconnect network 30. The substrate 28 comprises an upper face 28a and a lower face 28b. Similarly, the interconnect network comprises an upper face 30a and a lower face 30b. The interconnect network 30 is fixed to the substrate 28. More precisely, the lower face 30b of the interconnect network 30 is fixed to the upper face 28a of the substrate 28.

[0038] The substrate 28 is, for example, made of silicon. Electronic components, not shown in Figures 1 and 2, are formed in and on the substrate 28. For example, electronic components are formed on the upper surface of the substrate 28.

[0039] The substrate 28 preferably includes in its entirety the control circuits for pixels 14. In particular, the substrate 28 preferably includes the read circuits for pixels 14. The substrate 28 includes, for example, a part of the control circuit for pixel 12.

[0040] The interconnection network 30 comprises a stack of insulating layers, metallic tracks 32 located within the insulating layers, and conductive vias 34 located within the insulating layers and connecting the conductive tracks together. The bottom layer of the stack of insulating layers is in contact with the substrate 28, and in particular with the upper face of the substrate 28. The upper layer of the stack, i.e. the insulating layer of the interconnection network furthest from the substrate 28, includes for example metallic tracks 36. The tracks 36 are flush with the upper face 30a of the interconnection network.

[0041] Chips 16 and 18 are fixed to each other. More precisely, arrays 22 and 30 are fixed to each other. More precisely, the upper face 22a of array 22 and the upper face 30a of array 30 are fixed to each other. In the example shown in Figures 1 and 2, chips 16 and 18 are fixed by molecular bonding. Thus, tracks 28 and 36 are positioned so as to be in contact with each other. Alternatively, chips 16 and 18, more precisely the upper faces 22a and 30a, can be fixed in another way, for example by solder balls, for example solder balls between tracks 28 and 36.

[0042] Chips 16 and 18 are thus electrically connected. In other words, substrates 20 and 28 are electrically connected via vias 26, tracks 24, tracks 28, tracks 36, tracks 32 and vias 34.

[0043] The assembly 10 further comprises a layer 40. The layer 40 comprises, for example, quantum dots (QDs). The layer 40 comprises, for example, colloidal quantum dots (CQDs). The layer 40 may, alternatively, be made of photosensitive perovskite materials based on lead or tin. In other words, the layer 40 is, for example, made of a material having a formula of the type ABX3, in which element A is among the following: methylammonium, formamidinium, or cesium; in which element B is among the following: lead or tin; and in which element X is a halide, that is to say, an element among the following: iodine, chlorine, or bromine.The quantum dots of layer 40 can be made of perovskites, for example, lead- or tin-based photosensitive perovskites as described previously, or passivated with lead- or tin-based photosensitive perovskites. Layer 40 can also be a volumetric heterojunction composed of photosensitive organic semiconductors such as PDPP3T and fullerenes. Layer 40 is located on chip 18, more precisely on substrate 28, more precisely on the lower face 28b of substrate 28. Layer 40 is, for example, in contact with at least part of substrate 28. In other words, layer 40 and substrate 28 are not separated by an interconnection network.

[0044] Layer 40 is a continuous layer. Layer 40 preferably completely covers face 28b. In other words, layer 40 preferably does not include any openings exposing face 28b. Layer 40 is common to all pixels 10. Preferably, layer 40 is common to all pixels of the device.

[0045] Layer 40 comprises quantum dots. The quantum dots of layer 40 are for example located in a layer of a material other than a semiconductor material, for example in an electrically insulating material, for example in a resin.

[0046] By quantum dot, we mean that each quantum dot forms a confinement zone by quantum effect in all dimensions, that is to say in the three dimensions of space. Each quantum dot therefore preferably has dimensions, in all directions, on the order of a few tens of nanometers, in other words less than 100 nm, preferably between 2 nm and 15 nm.

[0047] Each quantum dot comprises a core made of a semiconductor material, for example lead sulfide. This core preferably has dimensions in all directions on the order of a few tens of nanometers, i.e., less than 100 nm. Each quantum dot further comprises ligands extending from the core. The ligands are preferably aliphatic organic molecules or organometallic and inorganic molecules.

[0048] Due to their net charge and dipole moment, ligands modify the effective doping of quantum dot layers as well as their electron affinity. For example, the ligands of quantum dots in layer 40 can be molecules acting as N-type dopants, for example, organic molecules such as thiolates.

[0049] Layer 40 constitutes photodiodes. In other words, layer 40 generates charges in the layer when light rays at an operating wavelength of layer 40, dependent on the quantum dots, are absorbed by layer 40.

[0050] The materials composing the quantum dots and the dimensions of each quantum dot, in particular the dimensions of the semiconductor core, determine the absorption wavelengths of the quantum dots, i.e., the operating wavelengths of the photodiode. The operating wavelengths correspond, for example, to the near-infrared, i.e., wavelengths between 700 nm and 1.6 mm. The operating wavelengths can also correspond to the mid-infrared, i.e., wavelengths between 1.6 pm and 4 pm, or to the visible, i.e., wavelengths between 300 nm and 700 nm.

[0051] It is possible to choose an operating wavelength from a wider range of wavelengths than the range of wavelengths possible with a standard photodiode, that is, a photodiode not comprising a quantum dot layer. Indeed, quantum dot layers correspond to an absorption curve having a peak significantly localized at a wavelength, said wavelength depending on the materials of the quantum dot and can be any wavelength from a range of wavelengths including at least the wavelengths from 300 nm to 4 pm.

[0052] For example, layer 40 comprises a single type of quantum dot. In other words, all the quantum dots in layer 40 have, for example, a core made of the same material and ligands made of the same material. Preferably, layer 40 is homogeneous. In other words, the composition of layer 40 is preferably identical throughout the entire layer 40.

[0053] Layer 40 comprises different regions 42, 44. Each pixel 14 comprises a region 44. Each pixel 12 comprises a region 42. Each region 42 is the portion of layer 40 that generates charges for the corresponding pixel 12. Similarly, each region 14 is the portion of layer 40 that generates charges for the corresponding pixel 14.

[0054] Each pixel includes, for example, means for attracting the charges generated throughout the region. For example, each pixel includes a first electron-extracting layer, or hole electrode, respectively, not shown, in contact with the lower face of layer 40. Each pixel includes, for example, a second hole-extracting layer, or electron electrode, respectively, in contact with the upper face of layer 40. The second extracting layer is transparent to the operating wavelengths of the pixel covered by said second layer. The first and second extracting layers are, for example, made of doped silicon, for example formed by doped regions of the substrate 28 in the case of the first layer, or of a metal oxide, for example TiOx, ZnO, AZO, IGZO, MoOx, CoO, CuOx, or NiOx.For example, each pixel includes a means of attracting charges to the circuits located in substrates 20 and 28 corresponding to said pixel.

[0055] Thus, during the operation of the device, charges are generated throughout the layer 40. The charges located in each region 42, 44 are attracted by said means to the circuits corresponding to the pixel associated with the region 42, 44.

[0056] The regions 42, for example, have a rectangular shape, preferably a square, with one beveled corner. The beveled corners of the four regions 42 are oriented towards the same point, that is, towards the center of the assembly, so that the parts of the layer 40 located at the center of the assembly, between the beveled corners, form the regions 44. Thus, the regions 42 comprise, in the same row of pixels, two parallel sides, one being shorter than the other, the shorter sides being in contact with each other. Similarly, the regions 42 comprise, in the same column of pixels, that is, in the direction opposite to the direction of the rows, two parallel sides, one being shorter than the other, the shorter sides being in contact with each other. Each region 42 further comprises a side connecting the shorter sides of said region 42, said side corresponding to a side of region 44. Region 44 is thus a quadrilateral in top view. Thus, region 44 is entirely surrounded by region 42.

[0057] The sets 10 are, for example, arranged in a matrix in the device. Preferably, each set 10 comprises pixels distinct from the pixels of the other sets. Thus, each pixel 14 is, for example, separated from pixel 14 of another set by pixels 12 from two sets 10.

[0058] In one operating mode of the device, the pixels can operate non-simultaneously, so as to generate the event and light intensity images at different times. When only the event image is generated, only the event sensors operate, with all charges being collected by a charge extraction layer located in the corresponding pixels. This is made possible, among other things, by the continuity of layer 40. This increases the sensitivity and speed of the event sensor without loss of spatial information or spectral aliasing.

[0059] In another operating mode, the event sensor is turned off and the photo charges generated in the event pixels are distributed among the adjacent pixels.

[0060] In another mode of operation, the two types of sensors can also be operated simultaneously, the electric field generated by each electrode allowing the collection of charges without electrical cross-talk between the pixels.

[0061] Figure 3 shows an example of a pixel control circuit. More specifically, Figure 3 schematically represents a pixel 12 and a pixel 14.

[0062] Pixel 12 includes a photodiode 50. Photodiode 50 corresponds to portion 42 of layer 40 associated with said pixel 12. Photodiode 50 includes a terminal, for example the cathode, connected, preferably connected, for example via doped boxes of the substrate 28 of the chip 18, to a node for applying a bias voltage Vbias.

[0063] Pixel 12 further includes a pixel 12 control circuit. The pixel 12 control circuit includes a photodiode 50 control circuit (RS / GS) 52. Each photodiode 50, i.e., each pixel 12, includes, for example, a circuit 52. The circuit 52 is located in the substrate 28, preferably entirely within the substrate 28. The pixel's photodiode 50 is connected, preferably via a link, to the circuit 52.

[0064] A circuit 54 is located in the substrate 28. The circuit 54 is an analog-to-digital converter. The circuit 54 is preferably entirely within the substrate 28. The circuit 54 is, for example, common to several pixels 12, for example common to all the pixels 12 of a set 10, for example only to the pixels 12 of a assembly 10. Circuit 54 is, for example, connected, preferably linked, to circuit 52.

[0065] A circuit 56 is located in the substrate 28. Circuit 56 is a pixel reading circuit, for example, the reading circuit of assembly 10. Circuit 56 is preferably entirely within substrate 28. Circuit 56 is, for example, common to several pixels 12, for example, common to all pixels 12 of an assembly 10, for example, only to the pixels 12 of an assembly 10. Circuit 56 is, for example, connected, preferably linked, to circuit 54. Circuit 56 provides, on an output 58, a value representative of the illumination of one or more pixels 12, for example, pixels 12 of assembly 10.

[0066] Pixel 14 includes a photodiode 60. Photodiode 60 corresponds to portion 44 of layer 40 associated with said pixel 14. Photodiode 60 includes a terminal, for example the cathode, connected, preferably connected, for example via doped boxes of the substrate 28 of the chip 18, to a node for applying a bias voltage Vbias.

[0067] Pixel 14 includes a pixel 14 control circuit. The pixel 14 control circuit includes, for example, a circuit 62 whose function is to apply a logarithm to the value obtained by the photodiode 60. The circuit 62 is, for example, connected, preferably connected, to the anode of the photodiode 60. The circuit 62 is, for example, preferably entirely located within the substrate 28.

[0068] Pixel 14 includes a circuit 64. Circuit 64 is an amplifier, for example of the common-drain type. Circuit 64 is, for example, connected, preferably linked, to circuit 62. Circuit 64 is, for example, located, preferably entirely, within the substrate 28.

[0069] The control circuit for pixel 14 further includes other components located in the substrate 20. The control circuit for pixel 14 includes, for example, an amplifier 66 connected, preferably connected, to the circuit 64. The control circuit for pixel 14 further includes a logic circuit 68, for example a high-pass filter, associated with a memory 70. The circuit 68 is connected, preferably connected, to the amplifier 66, so as to receive as input the signal amplified by the amplifier 66. The memory 70 is configured to contain a value obtained by the logic circuit 68.

[0070] Similarly, the control circuit of pixel 14 includes another logic circuit 72, for example a high-pass filter, associated with a memory 74. The circuit 72 is connected, preferably linked, to the amplifier 66, so as to receive as input the signal amplified by the amplifier 66. The memory 74 is configured to contain a value obtained by the logic circuit 72.

[0071] According to one embodiment, the amplifier 66 is, for example, configured to be resettable, the reset depending, for example, on the output values circuits 68 and 72. For example, pixel 17 may include a logic circuit not shown, for example an OR gate. Said logic circuit is, for example, in chip 16. Said logic circuit includes, for example, an input connected, preferably connected, to the output of circuit 68, another input connected, preferably connected, to the output of circuit 72, and an output connected, preferably connected, to an input of amplifier 66. For example, when the logic circuit not shown provides a first binary value, the amplifier is reset.

[0072] The pixel 14 further includes a data processing circuit 76 and a read circuit 78. The circuit 76 is for example connected, preferably connected, to the memories 70 and 74 and the circuit 78 is for example connected, preferably connected, to the circuit 76. The circuits 76 and 78 are for example common to several pixels 14.

[0073] Thus, substrate 28 includes the pixel control circuit 12, preferably the entire pixel control circuit 12. Substrate 20 preferably does not include any component of the pixel control circuit 12. Substrate 20 includes at least part of the pixel control circuit 14. Substrate 28 may, for example, include part of the pixel control circuit 14. The components of the control circuits located in the different substrates are interconnected by the interconnection networks 22 and 30. In particular, the components of the pixel control circuit 14 located on substrates 20 and 28 are interconnected by the interconnection networks 22 and 30.

[0074] Figure 4A represents a variant arrangement of a set of pixels. More precisely, Figure 4A represents a top view of a layer 40 of a set of pixels 12 and 14 such as the set of Figures 1 and 2.

[0075] In the example in [Fig. 4A], the pixel set comprises one pixel 14 and three pixels 12, the pixels being arranged in a matrix. The set thus comprises a column of two pixels 12 and a column comprising one pixel 14 and one pixel 12.

[0076] The set of pixels is, for example, arranged in a matrix with other identical sets. Each pixel 14 is thus surrounded by pixels 12 from the same set and neighboring sets.

[0077] Figure 4B represents another variant of the arrangement of a set of pixels. More precisely, Figure 4B represents a top view of a layer 40 of a set of pixels 12 and 14 such as the set in Figures 1 and 2.

[0078] In the example in [Fig. 4B], the pixel set comprises one pixel 14 and eight pixels 12, the pixels being arranged in a matrix. The set thus comprises two columns of three pixels 12 and one column comprising one pixel 14 and two pixels 12, such that the pixel 14 is surrounded by the pixels 12.

[0079] The set of pixels is, for example, arranged in a matrix with other identical sets. Each pixel 14 is thus separated from its neighboring pixels 14 by at least two pixels 12.

[0080] One advantage of the described embodiments is that the pixel size is not limited by the distance required by the via fabrication processes, as is the case in devices in which the photodiode is connected to the substrate by the interconnect network.

[0081] Another advantage of the described embodiments is that the control circuits, divided over several chips, allow the pixels to be brought closer together.

[0082] Another advantage of the embodiments described above is that the device can provide an event image and a light intensity image, for example non-simultaneously, with the event and standard pixels being able to be read independently.

[0083] Another advantage of the described embodiments is that it is possible to form a complete screen by using a layer of quantum dots. In other words, charges can be generated over the entire surface of the screen. There are no areas between pixels in which charges cannot be generated.

[0084] Another advantage of the described embodiments is that the range of possible wavelengths is greater, depending on the choice of quantum dots.

[0085] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0086] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Device comprising at least one set (10) of pixels, the set comprising at least one first pixel (14) generating event data and at least one second pixel (12) generating light intensity data, each first and second pixel comprising a portion of a layer, said portion forming a photodiode (50, 60), the device further comprising a first chip (16) comprising a first substrate (20) and a first interconnection network (22), and a second chip (18) comprising a second substrate (28) and a second interconnection network (30), the first and second chips being fixed to each other by the interconnection networks, the layer (40) being located on a first face of the second substrate opposite a second face of the second substrate on which the interconnection network is located.

2. The device of claim 1, wherein the device is an event camera.

3. Device according to claim 1 or 2, wherein the first chip (16) comprises at least part of a control circuit of the first pixel (14) and the second chip (18) comprises the control circuit of the at least one second pixel (12).

4. A device according to any one of claims 1 to 3, wherein part of the control circuit of the first pixel (14) is in the second chip (18).

5. A device according to any one of claims 1 to 4, wherein the first and second chips are attached by molecular bonding.

6. A device according to any one of claims 1 to 5, wherein the device comprises a plurality of sets of pixels arranged in a matrix.

7. Device according to claim 6, wherein each set comprises four second pixels (12) surrounding said at least one first pixel (14).

8. A device according to claim 6, wherein each set comprises eight second pixels (12) surrounding said at least one first pixel (14).

9. Device according to claim 6, wherein each set comprises three second pixels (12) and said at least one first pixel (14) arranged in matrices.

10. A device according to any one of claims 1 to 9, wherein the layer (40) is continuous.

11. Device according to any one of claims 1 to 10, in which the layer (40) entirely covers the first face of the second substrate.

12. Device according to any one of claims 1 to 11, in which the material of the layer (40) is homogeneous.

13. A device according to any one of claims 1 to 12, wherein the layer (40) is in contact with the second substrate.

14. A device according to any one of claims 1 to 13, wherein the layer is a layer of quantum dots or colloidal quantum dots.

15. A device according to any one of claims 1 to 13, wherein the layer is made of a photosensitive perovskite material based on lead or tin or a bulk heterojunction composed of photosensitive organic semiconductors.

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