SERVER NODE

Abstract

Server nodes are provided. The server node has a housing with a server node body designed to accommodate a motherboard (3000). The motherboard has a BIOS / BMC load module, a first security chip of type ASTXXXX (3021), and a second security chip of type CECXXX (3023). The first security chip (3021) and the second security chip (3023) are connected to the BIOS / BMC load module via a switch. The switch is configured to selectively enable the operation of the first security chip (3021) and the second security chip (3023). [FIG. 9]

Description

Title of the invention: SERVER NODE technical field

[0001] The present technology relates to a server node, and more particularly to a server node incorporating security microchips. CONTEXT

[0002] A server is a central computer that typically serves computers in a network environment and provides necessary functionalities to these network computers, such as information storage, processing, and exchange. Conventional servers can be implemented in the same way as conventional personal computers and generally comprise one or more central processing units (CPUs), one or more memory units, and one or more input / output devices, all of which are internally coupled for communication via a bus. These internal components of the server or server hardware operate according to inherent specifications and can be influenced by external factors such as temperature, humidity, pressure, and the like. A server rack can encompass a plurality of computer nodes.

[0003] A computer node uses firmware associated with node startup functions. The firmware first starts the hardware components, checks for driver errors, etc. In data center-based solutions, it is essential to validate the hardware components and their immutability when loading the computer node and / or server array. More specifically, when starting the computer node and / or server array, it is necessary to verify that no changes in the server firmware could lead to a security vulnerability, for example, for the purpose of stealing data or generating fake traffic. SUMMARY

[0004] The embodiments of this technology were developed based on the developers' assessment of the demand for security measures for firmware. To this end, security chips can be used to provide protection against a wide range of cyber threats. Security chips can incorporate advanced encryption, authentication, and intrusion detection mechanisms. Security chips can also include tamper-proof features to thwart physical attacks on the devices containing these chips.

[0005] However, developers have also become aware of the lack of versatility or interoperability of security chips when integrated in various devices and systems, ranging from personal computers and mobile devices to server racks and / or other critical infrastructure components. The embodiments of this technology were developed based on the developers' assessment of at least one technical problem associated with prior art solutions.

[0006] In one aspect of the present technology, a server node is provided comprising an enclosure having a server node body for housing a motherboard, the motherboard having: (i) a BIOS / BMC load module, (ii) a first security chip of type ASTXXXX, and (iii) a second security chip of type CECXXX. The first security chip and the second security chip are connected to the BIOS / BMC load module via a switch. The switch is configured to selectively enable the operation of the first and second security chips.

[0007] In some embodiments of the server node, the switch includes a first jumper associated with the first security chip and a second jumper associated with the second security chip.

[0008] In some embodiments of the server node, the switch includes a programmable element.

[0009] In some embodiments of the server node, the programmable element is a programmable pre-diffused integrated circuit (FPGA).

[0010] In some embodiments of the server node, the first jumper is a first hardware jumper and the second jumper is a second hardware jumper.

[0011] In certain embodiments of the server node, the first jumper is a first software jumper and the second jumper is a second software jumper. Brief description of the drawings

[0012] These features, aspects and advantages, as well as other features, aspects and advantages of the present technology, will be better understood with regard to the following description and the drawings and claims in the appendix where:

[0013] [Fig.1] is a front left perspective view of a server bay housing a chassis structure;

[0014] [Fig.2] is a front left perspective view of the chassis structure of [Fig.1] with first and second computer nodes in a receiving position, and housing a plurality of electronic components;

[0015] [Fig.3] is a front left perspective view of a chassis of the chassis structure of [Fig.1], with fans, and with the first and second computer nodes removed;

[0016] [Fig.4] is an exploded front left view of the chassis and second computer node of [Fig.2], with the electronic components of the second computer node removed, with the fans removed and with the first computer node removed;

[0017] [Fig.5] is a front left perspective view of the chassis structure of [Fig.2] with the first computer node in a first retracted position and with the second computer node removed;

[0018] [Fig.6] is a front left perspective view of the chassis structure of [Fig.5] with the first computing node in a second retracted position and with fourth electronic components in a storage position;

[0019] [Fig.7] is a top plan view of the chassis structure of [Fig.2], with different parts of fluid flow during operation;

[0020] [Fig.8] is a right rear perspective view of the chassis structure of [Fig.2];

[0021] [Fig. 9] is a wiring diagram of a motherboard of the second computing node of [Fig. 2]; and

[0022] the [Fig. 10] is a subsystem of the motherboard of the [Fig.9] implemented according to certain embodiments of the present technology. DETAILED DESCRIPTION

[0023] The examples and conditional formulations mentioned in this document are primarily intended to aid the reader in understanding the principles of this technology and are not intended to limit its scope to the examples and conditions expressly mentioned. It will be understood that a person skilled in the art can devise various arrangements which, although not explicitly described or depicted in this document, embody the principles of this technology and do not depart from its spirit or scope.

[0024] Furthermore, to facilitate understanding of the present technology, the following description may describe relatively simplified implementations thereof. Those skilled in the art will understand that various implementations of the present technology may be more complex.

[0025] In some cases, examples of modifications to the present technology that are considered useful may be given. These are simply intended to facilitate understanding and, again, do not define the scope or establish the limits of the present technology. These modifications are not an exhaustive list, and a person skilled in the art may make other modifications without departing from the scope of the present technology. Furthermore, the absence of examples of modifications should not be inferred from this that no modifications are possible and / or that what is described is the only way to implement this element of the present technology. chassis structure

[0026] With reference to [Fig. 1], a server rack 1200 is shown housing a chassis structure 100 among a plurality of chassis structures (unnumbered). It can therefore be said that the chassis structure 100 is configured to be housed within the server rack 1200. Generally, one or more chassis structures within the server rack 1200 are configured to process requests and / or processable tasks for an external client. For example, data indicating a given processable request can be acquired by one or more electronic components of the chassis structure 100 (and / or by electronic components of other chassis structures within the server rack 1200). This data can then be processed and / or stored by one or more electronic components of the chassis structure 100.

[0027] As shown in [Fig. 2], the chassis structure 100 comprises a chassis 200 and two computer nodes, namely a first computer node 301 and a second computer node 302. The chassis structure 100 also includes fans 400 at the rear. It is envisaged, in alternative embodiments of the present technology, that the fans 400 may be omitted. It is further envisaged that the fans 400 may, alternatively, be placed on a rear portion of the server bay 1200. It should be noted that, in some embodiments of the present technology, the first computer node 301 may be identical to the second computer node 302. Chassis

[0028] The manner in which the chassis 200 of the chassis structure 100 can be implemented in at least some embodiments of the present technology will now be described with reference to [Fig.3].

[0029] As shown in [Fig. 3], the frame 200 comprises a first lower panel 202, a first side wall 204, a second side wall 206, a partition wall 208, and a rear wall 210. The first side wall 204 and the second side wall extend longitudinally within the frame 200 and are located on respective sides of the first lower panel 202. The partition wall 208 also extends longitudinally within the frame 200 and is located between the first side wall 204 and the second side wall 206. The partition wall 208 is substantially parallel to the first side wall 204 and the second side wall 206. The rear wall 210 extends laterally between the first side wall 204 and the second side wall 206 at the rear of the frame 200 and is connected to them.

[0030] The first side wall 204, the second side wall 206, the partition wall 208, and the rear wall 210 are attached to the first lower panel 202 of the chassis 200 using any suitable fastening means, such as bolts and / or screws, for example. Alternatively, the first side wall 204, the second side wall 206, the partition wall 208, and the rear wall 210 can be formed as a single unit with the first lower panel 202 to provide the chassis 200.

[0031] The rear panel 210 is also configured to house, among other things, a power connector 214, motherboard connectors 216, and other (unnumbered) connectors that will be discussed in more detail later in this document. The rear panel 210 has openings 212 intended, generally, to allow fluid communication between the inside of the chassis 200 and the outside of the chassis 200 through the rear panel 210.

[0032] It should be noted that, in the non-limiting embodiment shown in [Fig. 3], the fans 400 are removably attached to the rear wall 210 on the outside of the chassis 200. As illustrated, when the fans 400 are removably attached to the rear wall 214, the fans 400 are aligned longitudinally with respective ports 212. As will be described in more detail below in this document, the position of the fans 400 relative to the ports 212 enables the fans 400 to produce one or more fluid flows in the direction 250, namely from the inside of the chassis 200, through the rear wall 210, to the outside of the chassis 200.

[0033] It should be noted that the first side wall 204, the second side wall 206, the partition wall 208 and the rear wall 210 and the first lower panel 202 define two storage spaces in the chassis 200, namely a first storage space 270 and a second storage space 260.

[0034] The first storage space 270 is defined by the first lower panel 202, the first left-hand side wall 204, the right-hand partition wall 208, and the rear wall 210. Similarly, the second storage space 260 is defined by the first lower panel 202, the second right-hand side wall 206, the left-hand partition wall 208, and the rear wall 210. The two storage spaces 120 are arranged on respective sides of the partition wall 208. In a specific, non-limiting embodiment of the present technology, the two storage spaces 270 and 260 may be substantially identical to each other.

[0035] The chassis handles 285 are arranged on the first lower panel 202 and extend forward away from the chassis 200.

[0036] The first storage space 270 of chassis 200 is configured to house the first computer node 301 (see [Fig. 1]) and the second storage space 260 of the Chassis 200 is configured to house the second computer node 302 (see [Fig. 1]) or vice versa. It can be said that a given storage space among the two storage spaces 270 and 260 houses a respective computer node among computer nodes 301 and 302. Computer node

[0037] The way in which the second computer node 302 is implemented will now be described with reference to [Fig. 4]. However, it should be noted that the first computer node 301 can be implemented in a similar way to the second computer node 302, without departing from the scope of the present technology.

[0038] Figure 4 illustrates an exploded view of the chassis 200 and the second computer node 302. It should be noted that the first computer node 301 and the internal components of the chassis structure 100 have been omitted from Figure 4 for the sake of simplicity. Furthermore, Figure 4 shows a simplified representation of the chassis 200 and the second computer node 302 for the sake of simplicity.

[0039] As can be seen, the second computer node 302 comprises a body 304, a tray frame 320 and a sliding assembly 325, which will now be described in turn.

[0040] The body 304 comprises a first lower panel 306, a third side wall 308, and a fourth side wall 310. The third side wall 308 and the fourth side wall 310 extend longitudinally within the chassis 304 and are located on respective sides of the second lower panel 306. The computer node handle 280 is disposed on the second lower panel 306 and extends forward away from the body 304. The third side wall 308 and the fourth side wall 310 are attached to the second lower panel 306, but alternatively, may be formed as a single unit with the second lower panel 306.

[0041] It should be noted that a given computer node is configured to be removed from its respective storage space, which may be desirable for various reasons. For example, the given computer node may be removed from its respective storage space by an operator for maintenance and / or replacement. Thus, it can be said that body 304 is configured to be stored removably in the second storage space 260. It can therefore be said that the second computer node 302 can be stored removably in the second storage space 260.

[0042] Furthermore, the body 304 has a front part 312 and a rear part 314. The front part 312 of the body 304 and the rear part 314 of the body 304 are arranged longitudinally in a sequential manner in the body 304 from the front end thereof to a rear end thereof.

[0043] The front portion 312 of the body 304 is configured to house the turntable frame 320. The turntable frame 320 has two sides (not numbered) and an opening at the top 322. The turntable handle 290 is located on one of the two sides of the turntable frame 320 and extends forward from the turntable frame 320. The turntable frame 320 can be slidably moved from a receiving position to at least one retracting position so that, when the turntable frame 320 is in the receiving position, the turntable frame 320 is located in the front portion 312 of the body 304.

[0044] It should be noted that the tray frame 320 is configured to slide between the receiving position and at least one retracting position by means of the sliding assembly 325 of the second computer node 302. The sliding assembly 325 is located in the front part of the body 304. The sliding assembly 325 comprises one side of the tray frame 320 and the corresponding fourth side wall 310 of the body 304. However, the sliding assembly 325 may comprise the other side of the tray frame 320 and the corresponding third side wall 308. In some embodiments, however, the second computer node 302 may have two sliding assemblies, one on each side of the tray frame 320, and implemented in the same manner as the sliding assembly 325.

[0045] In one embodiment, the given side of the tray frame 320 can be fitted into the corresponding side wall of the body 304 to provide the sliding assembly 325. In other words, the corresponding side wall of the body can be configured to receive the given side of the tray frame 320 by fitting it into place to provide a sliding assembly. In a further embodiment, the corresponding side wall of the body can be adapted to receive the given side of the tray frame 320 by fitting it into place to provide a sliding assembly. In another embodiment, the given side of the tray frame 320 and the corresponding side wall of the body 304 may have suitable railing structures to provide the sliding assembly 325.

[0046] It should be noted that the sliding assembly 325 can be implemented in various ways for a specific application of the present technology. However, the sliding assembly 325 is configured to move longitudinally and by sliding a respective tray frame of a given computer node between (i) a receive position (see [Fig. 2]), (ii) a first retraction position (see [Fig. 5]), and (iii) a second retraction position (see [Fig. 6]). As will become clearer from the description below in this document, the purpose of sliding the given tray frame is to provide access or additional access to at least some components electronics of the respective computer node, without it being necessary to remove the respective computer node from chassis 200.

[0047] It should also be noted that the second computer node 302 also includes a chain structure 3020 (see [Fig. 7]). The chain structure 3020 is attached (i) to the tray frame 320, to a rear of the tray frame 320, at one end thereof, and (ii) to the second lower panel 306 of the body 304 at the other end thereof. Generally, the chain structure 3020 is provided to prevent the tray frame 320 from detaching from the body 304 at a point where it is separated from it. It can be said that the chain structure 3020 can constrain the position of the tray frame 320 and cooperates with the sliding assembly 325 to prevent the tray frame 320 from falling or being inadvertently separated from the body 304.

[0048] It is envisaged, in at least some embodiments of the present technology, that the chain structure 3020 can be pivotally fixed to the tray frame 320 at the rear of the tray frame 320 at one end thereof and pivotally fixed to the second lower panel 306 of the body 304 at the other end thereof.

[0049] In addition to connecting the tray frame 320 to the body 304, the chain structure 3020 can define a hollow passage (not numbered) in order to house wiring to electrically couple at least some electronic components in the tray frame 320 to at least some electronic components in the body 304. Electronic components

[0050] As mentioned above, the second computer node 302 is configured to house electronic components for data processing and / or storage. It should be noted that at least some of the electronic components are housed in the tray frame 320, while other electronic components are housed in the body 304. With reference to Figures 7 and 8, we will now describe the electronic components of the second computer node 302 that are housed in the tray frame 302 (e.g., the one housed in the front portion 312 of the body 304) and the electronic components of the second computer node 302 that are housed in the body 304 (e.g., the rear portion 314 of the body 302).

[0051] The second computing node 302 houses, within the tray frame 320, the first electronic components 1000 and the fourth electronic components 2000. Generally, the first electronic components 1000 and the fourth electronic components 2000 can be distinct types of storage media. For example, the first electronic component 1000 can be a hard disk drive (HDD). The fourth electronic component 2000 can be a solid-state drive (SSD) or a non-volatile memory storage medium (NVME). The first electronic component 1000 can be arranged at the front of the tray frame. 320 and the fourth electronic components 2000 at the rear of the 320 tray frame (longitudinally behind the first 1000 electronic components).

[0052] The rear portion 314 of the second computer node 302 houses a motherboard 3000. The motherboard 3000 is electrically connected to the first electronic components 1000 and the fourth electronic components 2000 by wiring (not shown), as is known in the art. The motherboard 3000 is also electrically connected to the power connector 214 via the motherboard connector 216. For example, the power connector 214 can be electrically connected to a power bus of the server bay 1200 (see [Fig. 1]), then to a power supply, and can provide electrical power to the motherboard 3000 and other electronic components of the second computer node 302. Motherboard

[0053] With reference to [Fig. 9], the 3000 motherboard will now be described in more detail. The 3000 motherboard comprises two central processing units (CPUs), namely a first CPU 3014 and a second CPU 3016. The first CPU 3014 and the second CPU 3016 are connected to the 3000 motherboard. It is envisaged that the first CPU 3014 and the second CPU 3016 can be coupled in communication and / or electrically connected to one or more other electronic components via the 3000 motherboard. In some embodiments of the present technology, each of the first and second CPUs 3014 and 3016 can be inserted into a respective socket on the 3000 motherboard. In some embodiments, the sockets are identical so that the first and second CPUs 3014 and 3016 can be interchangeable.In alternative embodiments, a first socket is configured to receive the first 3014 CPU and a second socket is configured to receive the second 3016 CPU, so that the first socket is dedicated to the first 3014 CPU and the second socket is dedicated to the second 3016 CPU. Although two 3014 and 3016 CPUs are represented, it is envisaged that a number of CPUs could be connected to the 3000 motherboard without exceeding the scope of the present technology.

[0054] The 3000 motherboard includes a 3018 platform controller hub. The 3018 platform controller hub is connected to the 3000 motherboard. It is envisaged that the 3018 platform controller hub can be coupled in communication and / or electrically connected to one or more other electronic components via the 3000 motherboard. The 3018 platform controller hub is further connected to the first CPU 3014 and the second CPU 3016.

[0055] It should be noted that a platform controller hub (PCH) is a component in computer architectures that serves as a central hub for the management and control of various functions of a computer's motherboard, such as the card The PCH 3018 acts as a communication and management hub, facilitating data flow between one or more CPUs, memory chips, storage devices, and / or peripherals. It is envisioned that the PCH 3018 could also be used for tasks such as connecting USB ports, SATA ports, Ethernet ports, audio components, and other input / output interfaces to the 3000 motherboard. The PCH 3018 can also handle power management, system configuration, and various low-level operations that allow different hardware components to work together. By consolidating one or more of these functions onto a single chip, the PCH 3018 helps simplify communication and coordination between different hardware components, thereby optimizing overall system performance and efficiency. It is envisioned that the PCH 3018 will support various interfaces and connectivity options.

[0056] The 3000 motherboard further includes a motherboard management controller (BMC) chip 3021 for remote management, monitoring, and control of the hardware. The BMC chip 3021 may include a serial peripheral interface (SPI) flash device 3043. The BMC chip 3021 is integrated into the 3000 motherboard and is connected via an SPI bus 3044. In some embodiments of the present technology, the BMC chip 3021 may be connected via an inter-integrated circuit (I2C) 3040 and / or a system management bus (SMBus). The BMC 3021 chip has firmware storage that contains code for remote management and monitoring functions and is typically stored in a flash chip located on the 3000 motherboard. As shown in [Fig.9], the BMC 3021 chip is connected to the 3018 platform controller hub via a first multiplexer 3024.

[0057] It is envisaged that a BMC could be implemented as a specialized microcontroller embedded on a computer motherboard, such as the 3000 motherboard. As such, a BMC chip can be responsible for monitoring, managing, and controlling many aspects of a system, even when a CPU is powered off or unresponsive. The 3021 BMC chip can be used for remote management, system status monitoring, and maintenance of servers, network equipment, and other business hardware. For example, the 3021 BMC chip can be used for system security by enabling features such as BIOS updates, monitoring intrusion detection sensors, and providing a secure interface for managing encryption keys.

[0058] A 3022 SPI flash device for a basic input / output system (BIOS) is connected to the 3000 motherboard. The 3022 SPI flash device is connected to the 3000 motherboard via an SPI 3042 bus. In some embodiments of the present technology, the 3022 SPI flash device can be connected via an I3C or an SMBus. The SPI 3022 flash device stores instructions in memory for a hardware initialization and boot process, as well as to facilitate communication between the operating system and the hardware components during boot. As shown in [Fig. 9], the SPI 3022 flash device is connected to the PCH 3018 via a second multiplexer, the 3024.

[0059] Generally speaking, an SPI flash device is a type of non-volatile memory used in electronic devices, such as systems, microcontrollers, and other embedded hardware components. An SPI flash device can store data when the power is off and is accessed using the SPI protocol. SPI flash memory comes in various capacities and is used for storing firmware, boot sequences, configuration data, and other information that must be retained from one power cycle to the next. The SPI protocol is a synchronous communication protocol commonly used to connect microcontrollers, sensors, and other peripherals to a CPU or other microcontrollers. It involves a master-slave architecture where one device (master) controls communication with one or more peripherals (slaves).SPI uses a clock signal and multiple data lines to transmit data between devices. The clock signal synchronizes data transmission, and data can be exchanged in full-duplex mode, allowing simultaneous sending and receiving operations. The SPI protocol is often used for tasks involving reading and writing to memory devices (such as SPI flash memory), controlling peripherals such as sensors and displays, and establishing communication between microcontrollers in various embedded systems. This may require more pins compared to other communication protocols such as I2C, for example.

[0060] During server startup, validation of the software and / or hardware components must be completed to determine whether they have been tampered with by hackers or fraudulent users who could modify the firmware or the server(s) to steal data and / or generate fake traffic. It is possible to implement microchips incorporating security controls that can verify the server's operating system and hardware components. More specifically, the present technology implements a microchip from the ASTxxxx 3021 series of chips by AspeedTech™ for the BMC 3021 chip. It will be understood that, in this context, the identifier xxxx indicates a serial number associated with the ASTxxxx series of chips. In embodiments of the present technology, an AST2xxx 3021 chip, such as FAST2600, may be used. The present technology implements a microchip from the CECxxx 3023 series of chips by Microchip™ for the BIOS 3023 chip.It will be understood that, . In this context, the identifier xxx indicates a serial number associated with the CECxxx series of chips. In embodiments of this technology, a CEC173x 3023 chip is implemented.

[0061] The AST2xxx 3021 chip provides security features such as secure boot, encryption, and remote authentication to protect the server and its management functions. The AST2xxx 3021 chip uses a special memory section that writes instructions only once, eliminating any possibility of overwriting instructions.

[0062] The CEC173x 3023 chip serves as a root of trust, providing robust security features, such as hardware cryptographic acceleration capabilities, secure boot, secure key storage and encryption that make the CEC173x chip suitable for a high level of data protection.

[0063] The AST2xxx 3021 chip and the CEC173x 3023 chip are integrated into the 3000 motherboard. Having the AST2xxx 3021 and CEC173x 3023 chips on the same 3000 motherboard provides end users with the flexibility and adaptability needed to optimize chip selection to meet server / data center requirements. In other words, end users can choose whether to use the AST2xxx 3021 or CEC173x chip to best suit their needs.

[0064] Each of the AST2xxx chip 3021 and the CEC173x chip 3023 can be connected to the 3000 motherboard via jumpers 3028 and 3029, respectively. A host RST line 3045 is used in conjunction with jumper 3028, and a BMC RST line 3046 is used in conjunction with jumper 3029. Generally, the host RST line 3045 and the BMC RST line 3046 correspond to wired (circuit) communication lines for transmitting a reboot command to restart the host and the BMC, respectively.

[0065] Generally, a jumper connection, often simply called a "jumper," is an electrical component used in electronic components and computer hardware to configure and / or modify the behavior of a device and / or circuit. In some embodiments, a jumper has a pair of conductive metal pins or "terminals" that can be connected and / or disconnected using a plastic cap or a metal bridge. Jumper connections are used to define specific parameters and modes on printed circuit boards, such as motherboards. They allow operators to select options without necessarily requiring specialized programming or software. By placing or removing the jumper cap over the appropriate pins, specific functions or configurations can be selectively enabled or disabled.

[0066] In some cases, jumpers can be used to configure hardware settings such as disk master / slave settings, clock frequencies, voltage levels, and data transfer modes. For example, on hard drives, they can determine whether a disk is designated as the master or the slave in a two-disk configuration. In other cases, a given motherboard can be implemented with a jumper to clear BIOS or CMOS settings, effectively resetting the hardware to its default values. In still other cases, jumpers can enable or disable specific features or components on a printed circuit board, as will be discussed in this document.

[0067] In certain embodiments, one or more jumpers can be implemented as software jumpers, as opposed to physical / hardware jumpers. A software jumper can be said to enable the same functionality as a hardware jumper using software commands without necessarily requiring physical manipulation. It is envisaged that a software jumper could allow the alteration of configuration parameters, via software interfaces or commands, which can be modified easily and remotely, unlike with hardware jumpers. This virtual approach to jumper functionality allows for dynamic reconfiguration and customization. Jumpers offer the flexibility needed to adjust the system's behavior, parameters, and / or operating modes without requiring operators to access the physical hardware.This simplifies system maintenance, troubleshooting, and upgrades. In some embodiments, a software jumper can be implemented via one or more built-in BIOS commands.

[0068] It should be noted that the AST2xxx 3021 chip is associated with a first jumper 3028 and the CEC173x 3023 chip is associated with a second jumper 3029. In this embodiment, the first and second jumpers 3028 and 3029 are physical connectors with jumper caps that are used to close the electrical circuit on the motherboard 3000. The end user can select whether the AST2xxx 3021 chip or the CEC173x chip is connected by connecting the respective jumper 3028 and 3029. More specifically, when the first jumper 3028 is connected, the AST2xxx 3021 chip is connected. Similarly, when the second jumper 3029 is connected, the CEC173x chip is connected. It is envisaged, in other embodiments of the present technology, that the first and second jumpers 3028, 3029 could be other forms of connectors without departing from the scope of the present technology.

[0069] In some embodiments, a server node is provided. The server node may include a housing containing a motherboard. More specifically, the The motherboard includes (i) a loading module such as a BIOS / BMC module, for example, (ii) a first security chip such as the AST2xxx chip, for example, and (üi) a second security chip such as the CEC173x chip, for example. The first security chip is associated with a first connection and a first jumper on the motherboard, and the second security chip is associated with a second connection and a second jumper on the motherboard.

[0070] During operation, one or more motherboard components can be configured to use at least one of the first and second security chips by closing and / or opening at least one of the first or second jumpers. In some embodiments, one or more motherboard components can use the first and second jumpers to selectively and interchangeably use the first and second security chips during server node operation.

[0071] In certain embodiments, the functionality of one or more jumpers can be implemented by means of a switch comprising a programmable element. For example, the switch may include user-programmable pre-broadcast arrays (FPGAs), which are integrated circuits offering reconfigurable hardware functionality. Unlike traditional application-specific integrated circuits (ASICs), FPGAs can be programmed and reprogrammed after manufacturing, allowing rapid customization for various computing tasks. FPGAs consist of an array of programmable logic blocks interconnected by configurable routing paths, allowing users to create custom digital circuits or even entire processors.

[0072] In certain embodiments, the 3000 motherboard can be configured to implement one or more secure boot mechanisms. It should be noted that the first security chip and the second security chip may include respective Roots of Trust (RoTs) that can be used to verify firmware and / or generate reset signals for application processors. It is envisaged that a first RoT of the first security chip or a second RoT of the second security chip may be used selectively depending, among other things, on the needs or configuration of a client system.

[0073] With reference to [Fig. 10], a subsystem 1000 is shown, comprising a RoT device 1002, an application processor 1004, and a flash device 1006. Generally, the RoT device 1002 is a hardware component configured to store encryption keys used in a "chain of trust" (CoT) where the The code to be executed is initially verified. In computer security, a Certificate of Trust (CoT) is established by validating each hardware and software component of the end-user entity against the root certificate. It is designed to ensure that only trusted software and hardware can be used while maintaining a degree of flexibility.

[0074] During the verification operation, if the code execution is valid / legitimate at a given time and / or in a given server state, the cryptographic signature can be calculated and verified by the RoT 1002 device. The public and private key pair is used in this process—the private key is used to generate a signature, and the public key is used to verify that the signature is correct (i.e., that the signed file has not been modified). On the one hand, access to the private key is controlled or kept "secret" for an environment that generates signatures. On the other hand, the public key is written to the RoT 1002 device and is used by the hardware for firmware verification.

[0075] In addition, or alternatively, the RoT 1002 device can be configured to perform data encryption and / or decryption mechanisms (without exposing the keys), key generation mechanisms, key revocation mechanisms, the storage of at least certain startup parameters, and the like. Although the RoT 1002 device is considered "secure"—that is, the recovery of cryptographic data from the device is complex—the developers of the present technology have recognized that it can be beneficial for security reasons by avoiding the storage of private keys in RoT devices.

[0076] It is envisaged that a one-time programmable (OTP) memory device may further be used to store cryptographic data and hardware parameters. Depending on a specific implementation of a RoT device, hardware startup parameters and other parameters may also be stored in a corresponding OTP memory device. In some implementations, a write operation may be performed in configurable regions of the OTP memory device after the initial OTP provisioning in order to support key revocation mechanisms.

[0077] In certain embodiments, it is envisaged that the RoT 1002 device can be used to prevent the execution of unreliable / unverified code on one or more components of the motherboard 3000 and / or the subsystem 1000. To this end, during the power-up phase, the RoT 1002 device can generate a reset signal for the application processor 1004, such as a BMC or a host device, thereby preventing the execution of a CPU of the application processor 1004. In addition, the RoT 1002 device can read the firmware data of the application processor 1004, generate signatures, and perform a check against the keys in the OTP memory device. In cases where the check fails, the RoT 1002 device can, among other things, program a master image (an immutable firmware known to be secure) into the SPI image of the application processor 1004. In addition, or alternatively, the RoT 1002 device can also transmit signals to report a current check status to external subsystems such as a BMC, for example, via an I2C interface.

[0078] Modifications and improvements to the implementations of this technology described above may be obvious to those skilled in the art. The preceding description is given by way of example and is not limiting. The scope of this technology is therefore intended to be limited only by the scope of the claims in the appendix.

Claims

Demands

1. Server node comprising: an enclosure having a server node body for housing a motherboard (3000); the motherboard having (i) a BIOS / BMC load module, namely basic input / output system - management control chip, (ii) a first security chip of type ASTXXXX (3021), and (iii) a second security chip of type CECXXX (3023); the first security chip (3021) and the second security chip (3023) being connected to the BIOS / BMC load module via a switch; the switch being configured to selectively enable the operation of the first security chip (3021) and the second security chip (3023).

2. Server node according to claim 1, wherein the switch includes a first jumper (3028) associated with the first security chip (3021) and a second jumper (3029) associated with the second security chip (3023).

3. Server node according to claim 1, wherein the switch includes a programmable element.

4. Server node according to claim 3, wherein the programmable element is a programmable pre-diffused integrated circuit FPGA.

5. Server node according to claim 2, wherein the first jumper (3028) is a first hardware jumper and the second jumper (3029) is a second hardware jumper.

6. Server node according to claim 2, wherein the first jumper is a first software jumper and the second jumper is a second software jumper.

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