Semiconductor substrate on insulator optimized for low temperatures

Abstract

Semiconductor-on-insulator substrate optimized for low temperatures The present description relates to a substrate (100) of the semiconductor-on-insulator type, comprising at least: - a support layer (102) of a first semiconductor, - a surface layer (106) of a second semiconductor, - a buried dielectric layer (104) arranged between the support layer and the surface layer, and in which the support layer comprises at least one region (108) doped with a doping level greater than or equal to 1015 cm-3. Figure for the abstract: Fig. 1

Description

Title of the invention: Semiconductor substrate on insulator optimized for low temperatures Technical field

[0001] The present description relates generally to the field of substrates of the semiconductor-on-insulator type, for example SOI (“Silicon-On-Insulator” in English, or silicon on insulator). Prior art

[0002] Certain applications require the use of high-quality electronic components, such as for example for the production of RF (radiofrequency) integrated circuits intended to be used at very low temperatures, for example between 4 K and 150 K. Such integrated circuits are for example used in the aerospace field or for the production of quantum devices (in particular for reading qubits) which are required to operate at cryogenic temperatures (temperatures below 100 K). Such circuits are called cryo-CMOS or RF cryo-CMOS circuits.

[0003] To produce high-quality electronic components, and in particular to reduce microwave losses as much as possible, it is advantageous to produce these integrated circuits from an SOI substrate, in particular of the HR-SOI type (High-Resistivity Silicon-On-Insulator). Such a substrate has good performance at room temperature (300 K). However, this performance is limited in particular because of a parasitic surface conduction layer forming on the surface of the silicon of the support layer, or bulk, because of the fixed charges present in the buried dielectric layer. This limitation of performance occurs both at room temperature and at low temperature, in particular below 100 K.

[0004] To improve the performance of HR-SOI substrates at room temperature and low temperature, it is possible to use a TR-SOI (Trap-Rich Silicon-On-Insulator) type substrate, also called a TR HR-SOI substrate. Compared to an HR-SOI substrate, a TR-SOI substrate has an additional layer of undoped polysilicon (a so-called "Trap-Rich" layer) between the silicon support layer and the buried dielectric layer, or BOX (Buried Oxide) of the substrate. However, the disadvantage of such a TR-SOI substrate is its high cost. Summary of the invention

[0005] There is therefore a need to propose a new type of semiconductor-on-insulator substrate making it possible to improve the performance / cost ratio, particularly at low temperatures, compared to existing substrates.

[0006] One embodiment overcomes all or part of the drawbacks of the known solutions and proposes a semiconductor-on-insulator type substrate, comprising at least:

[0007] a support layer of a first semiconductor,

[0008] a surface layer of a second semiconductor,

[0009] a buried dielectric layer disposed between the support layer and the surface layer,

[0010] and in which the support layer comprises at least one region (108) doped with a doping level greater than or equal to 1015 cm 3.

[0011] According to a particular embodiment, the doping level of said at least one region is less than or equal to 1019 cm 3.

[0012] According to a particular embodiment, said at least one region is arranged at the interface between the buried dielectric layer and the support layer.

[0013] According to a particular embodiment, said at least one region is located at only part of the interface between the buried dielectric layer and the support layer.

[0014] According to a particular embodiment, said at least one region is arranged at the level of the entire interface between the buried dielectric layer and the support layer.

[0015] According to a particular embodiment, said at least one region has a thickness greater than or equal to 3 μm.

[0016] According to a particular embodiment, the buried dielectric layer is directly in contact with the support layer and / or said at least one region.

[0017] A method for producing a substrate of the semiconductor-on-insulator type is also proposed, comprising producing a support layer of a first semiconductor, a surface layer of a second semiconductor, and a buried dielectric layer arranged between the support layer and the surface layer, and comprising doping of at least one region of the support layer with a doping level greater than or equal to 1015 cm 3.

[0018] According to a particular embodiment, the doping of said at least one region of the support layer comprises the implementation of a localized ionic implantation of dopants in said at least one region of the support layer.

[0019] According to a particular embodiment, the ion implantation is implemented with an energy between 1 keV and 100 keV.

[0020] According to a particular embodiment, parameters for implementing the doping of said at least one region of the support layer are chosen such that, for a temperature T less than 150 K, the resistivity q of said at least one region of the support layer is greater than that of an HR-SOI substrate comprising a support layer of the first semiconductor whose doping is less than 1015 cm 3.

[0021] According to a particular embodiment, the resistivity q of said at least one region of the support layer is calculated according to the following equation:

[0022] [Math.l] 1

[0023] with q expressed in Ohm.cm;

[0024] q corresponding to the elementary charge;

[0025] N ion corresponding to the density of ionized dopants, at temperature T, in said at least one region of the support layer, expressed in cm 3;

[0026] corresponding to the mobility, at temperature T, of the carriers whose type corresponds to that of the ionized dopants, expressed in cm2.V '.s *.

[0027] An integrated circuit is also proposed comprising several electronic components produced directly above said at least one doped region of the support layer of a semiconductor-on-insulator type substrate according to a particular embodiment. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0029] [Fig.l] and [Fig.2] schematically represent examples of a semiconductor-on-insulator type substrate according to a particular embodiment;

[0030] [Fig.3] represents the variation of the Fermi level, as a function of the temperature, in a semiconductor-on-insulator type substrate according to a particular embodiment, for different doping levels of at least one doped region of the support layer of the substrate;

[0031] [Fig.4] schematically represents integrated circuits produced in a semiconductor-on-insulator type substrate according to a particular embodiment;

[0032] [Fig.5] represents the variation of the resistivity of at least one doped region of the support layer of a semiconductor-on-insulator type substrate according to a particular embodiment, as a function of the temperature and for different doping levels of said at least one doped region of the support layer of the substrate;

[0033] [Fig.6] represents the variation of the density of ionized dopants, as a function of temperature, in a semiconductor-on-insulator type substrate according to a mode of particular realization, and for different doping levels in the support layer of the substrate. Description of the embodiments

[0034] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed below.

[0036] In the various figures, the visible elements are not represented on the same scale relative to each other to facilitate understanding of these figures.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures, in a normal position of use of the device.

[0038] Unless otherwise specified, the expressions "approximately", "approximately", "substantially" and "in the order of" mean within 10%, preferably within 5%.

[0039] A first example of a semiconductor-on-insulator type substrate 100 according to a particular embodiment is described below in connection with [Fig.l].

[0040] The substrate 100 comprises a support layer 102 based on a first semiconductor, for example silicon. The thickness of the support layer 102 (dimension along the Z axis visible in [Fig.l]) is for example greater than or equal to 700 μm. In a particular configuration, the first semiconductor may be monocrystalline.

[0041] The substrate 100 also comprises a buried dielectric layer 104, or BOX, arranged on the support layer 102. The buried dielectric layer 104 comprises for example SiO2, and its thickness is for example between 10 nm and 1000 nm. In the example described, the buried dielectric layer 104 can be arranged directly in contact with the support layer 102, that is to say without the presence of an intermediate layer between the layers 102 and 104.

[0042] The substrate 100 also comprises a surface layer 106 based on a second semiconductor, for example silicon, germanium or any other semiconductor suitable for producing the surface layer of the substrate 100. The second semiconductor may or may not be similar to the first semiconductor. The thickness of the surface layer 106 is for example between 5 nm and 100 nm.

[0043] The support layer 102 comprises at least one region 108 doped with a doping level greater than or equal to 1015 cm' 3. In the example described, this doping level may be less than or equal to 1019 cm'3. The dopants present in the region 108 may be of n or p type, and may correspond for example to boron, phosphorus or arsenic atoms. In the examples below, in particular the curves shown in FIGS. 3, 5 and 6, the dopants of the region 108 correspond to boron atoms.

[0044] The region 108 can be made such that its thickness (dimension parallel to the Z axis in [Fig.l], and which corresponds to the dimension of the region 108 which is perpendicular to the interface between the buried dielectric layer 104 and the support layer 102) is greater than or equal to 3 μm. In the example of [Fig.l], the depth to which the region 108 extends is symbolically represented by a dotted line. Alternatively, it is possible for the region 108 to extend over the entire thickness of the support layer 102. Furthermore, in the example of [Fig.l], the region 108 is arranged at the interface between the buried dielectric layer 104 and the support layer 102.

[0045] In the first example described, the region 108 is arranged at the level of the entire interface between the buried dielectric layer 104 and the support layer 102. As a variant, it is possible for one or more doped regions 108 to be located at only a part of the interface between the buried dielectric layer 104 and the support layer 102. [Fig. 2] represents a second example embodiment of the substrate 100 corresponding to such a variant. In this [Fig. 2], three distinct regions 108 are represented. As for the variant previously described in connection with the first example, it is possible for one or more of the regions 108 to extend over the entire thickness of the support layer 102.

[0046] In the absence of the region(s) 108, when the temperature drops below the carrier freezing temperature, also called the freeze-out temperature, the effective doping in the semiconductor of the support layer decreases exponentially with temperature. In this case, for a lightly doped support layer, for example less than 1015 cm3, the formation of a parasitic surface conduction layer prevents the electrical resistivity from increasing exponentially.In the substrate 100, thanks to the doping carried out in the part or parts of the support layer 102 forming the region or regions 108, the gel temperature of the carriers of the semiconductor of the support layer 102 increases compared to that of a substrate comprising the same elements but in which the support layer would be less heavily doped and would not comprise the region or regions 108, because a gel of carriers occurs with the lowering of the temperature without the formation of a parasitic surface conduction layer in the substrate 100. Thus, when the . substrate 100 is used at low temperatures, for example below 150 K and possibly between 4 K and 150 K, or between 4 K and 100 K, its resistivity is greater than that of a substrate without a doped support layer.

[0047] By adjusting the doping value of the region(s) 108, for example between 1015 and 1018 cm3, it is possible to adjust the gel temperature of the carriers which increases with the doping level. For a given temperature, it is therefore possible to achieve higher resistivity values ​​of the substrate by choosing a higher doping of this or these regions 108. Furthermore, it is possible to play on the gel temperature of the carriers by using different dopants (boron, Al, Ga, In, ...).

[0048] Curves 12, 14, 16 and 18 visible in [Fig.3] represent the variation of the Fermi level, in eV, as a function of the temperature, in K, of the doped semiconductor of the 108 region for different doping levels of the 108 region:

[0049] curve 12: doping equal to 1015 cm3;

[0050] curve 14: doping equal to 1016 cm3;

[0051] curve 16: doping equal to 1017 cm3;

[0052] curve 18: doping equal to 1018 cm 3.

[0053] For comparison, curves 10 and 20 represent the variation of the Fermi level, as a function of temperature, in a semiconductor similar to that of region 108 but doped at a doping level respectively equal to 1014 and 1013 cm3.

[0054] A standard substrate has a carrier gel temperature of between 30K and 50K, due to the low doping level (about a few 1015 cm 3). Curves 10 to 20 show that the carrier gel temperature, given by the intersection of the Fermi level with the activation level of the dopants considered, and designated here by curve 22 for boron dopants in silicon, increases with the doping level in the semiconductor of this or these regions 108.

[0055] To produce the substrate 100, it is possible to produce the layers 102, 104 and 106 of the substrate 100 by implementing steps conventionally used to produce a SOL substrate.

[0056] Then, the doping of the support layer 102 can be carried out to form the region(s) 108. For this, it is possible to implement a localized ion implantation of dopants to form the region(s) 108 in the support layer 102. Such an ion implantation can be implemented with an energy of between 1 keV and 100 keV. For example, the dose used can be between 1012 and 1016 cm 2. The parameters for implementing this ion implantation (in particular the beam energy) are chosen according to the desired doping level in the region(s) 108.

[0057] Alternatively, doping techniques other than localized ion implantation may be implemented to produce the region(s) 108 in the support layer 102. For example, it is possible to implement, before the deposition of the buried dielectric layer 104, full-plate in situ doping.

[0058] The substrate 100 can be used to produce integrated circuits 200 comprising, for example, passive and / or active components such as MOS transistors. [Fig. 4] schematically represents several integrated circuits 200 produced in or on the active layer 106 of the substrate 100, after the production of the region(s) 108, these integrated circuits 200 corresponding, for example, to RF integrated circuits, for example RF cryo-CMOS type circuits. The electronic components of the integrated circuits 200 can be produced directly above the doped regions 108.

[0059] As indicated previously, the doping implemented to form the region(s) 108 in the support layer 102 makes it possible to increase the carrier gel temperature in the semiconductor of this or these regions 108. A user can choose to use a substrate 100 whose doping level in the region(s) 108 makes it possible to have the desired resistivity, depending on the expected operating temperature for the circuits which are produced from the substrate 100.

[0060] Curves 30, 32, 34 and 36 visible in [Fig.5] represent the variation of the resistivity q, in Ohm.cm, of the region 108 of the support layer 102 of the substrate 100, as a function of the temperature T, in K, and for different doping levels:

[0061] curve 30: doping equal to 1015 cm 3;

[0062] curve 32: doping equal to 1016 cm3;

[0063] curve 34: doping equal to 1017 cm3;

[0064] curve 36: doping equal to 1018 cm 3.

[0065] Curves 38 and 39 represent, by way of illustration, the resistivity obtained for a doping level respectively equal to 1013 and 1014 cm 3, representing the effective doping of a substrate with a so-called “Trap-Rich” layer.

[0066] Furthermore, curve 40 represents the resistivity obtained with a standard HR-SOI substrate having a doping level equal to 1013 cm3 but whose resistivity is impacted, at low temperature, by the presence of a parasitic surface conduction layer between the support layer and the buried dielectric layer.

[0067] In order for the performances of the components produced in the substrate 100 to be better than those obtained for components produced in an HR-SOI substrate, the parameters for implementing the doping of the region(s) 108 of the support layer 102 may be chosen such that, for a temperature T lower than 150 K, the resistivity q of the region(s) 108 of the support layer 102 is higher than that of a standard HR-SOI substrate, i.e. comprising a support layer of the first semiconductor (silicon in the example described) whose doping is less than 1015 cm 3. The value of the resistivity q can be expressed by the following equation:

[0068] [Math.2] 1 P ~ 9*^

[0069] with q expressed in Ohm.cm;

[0070] q corresponding to the elementary charge;

[0071] N ion corresponding to the density of ionized dopants, at temperature T, in the region(s) 108 of the support layer 102, expressed in cm3;

[0072] / 1 corresponding to the mobility, at temperature T, of the carriers whose type corresponds to that of the ionized dopants, expressed in cm2.V '.s

[0073] The value of the density of ionized dopants N ion depends in particular on the temperature as well as on the doping level of the region(s) 108. It can be determined by applying the incomplete ionization model as described in the document AK Jonscher, “Semiconductors at cryogenic temperatures”, Proceedings of the IEEE, vol. 52, n°10, pp.1092-1104 (1964). Curves 41, 42, 44 and 46 visible in [Fig. 6] represent the value of the density of ionized dopants, in cm3, as a function of the temperature T, in K, when the dopants correspond to boron atoms and for different doping levels:

[0074] curve 41: doping equal to 1015 cm3;

[0075] curve 42: doping equal to 1016 cm3;

[0076] curve 44: doping equal to 1017 cm3;

[0077] curve 46: doping equal to 1018 cm3.

[0078] Curve 48 represents, for illustrative purposes, the density of ionized dopants obtained with a doping level equal to 1013 cm3.

[0079] The value of the mobility p also depends on the temperature E as well as on the type of dopants and the doping level of the region(s) 108. The value of the mobility p can be determined from curves obtained experimentally or from charts.

[0080] Thanks to the doping carried out in the support layer 102 of the substrate 100 to form the region(s) 108, the semiconductor of this or these regions 108 is more resistive at low temperatures (less than 150 K, or less than 100 K) and the position of the Fermi level is modified via the implanted dopants, which causes an increase in the gel temperature of the carriers and therefore an increase in the performance of the components produced in this or these regions 108 of the substrate 100. The proposed substrate 100 makes it possible to have, at low temperatures (for example less than 150 K or 100 K), a significant resistivity, making it possible to obtain performances close to or equal to those obtained with a TR-SOI type substrate but with a lower cost. In addition, it is possible to locate the region(s) 108 in certain areas only of the substrate 100, for example in regions of the substrate 100 at which one or more RF integrated circuits are intended to be produced.

[0081] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0082] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. For example, the precise nature of the deposition and etching steps implemented can be chosen in particular as a function of the material(s) to be deposited or etched, as well as the thicknesses of material to be deposited or etched.

Claims

Claims

1. Substrate (100) of the semiconductor-on-insulator type, comprising at least: - a support layer (102) of a first semiconductor, - a surface layer (106) of a second semiconductor, - a buried dielectric layer (104) arranged between the support layer (102) and the surface layer (106), and in which the support layer (102) comprises at least one region (108) doped with a doping level greater than or equal to 1015 cm 3.

2. The semiconductor-on-insulator substrate (100) of claim 1, wherein the doping level of said at least one region (108) is less than or equal to 1019 cm 3.

3. A semiconductor-on-insulator substrate (100) according to one of the preceding claims, wherein said at least one region (108) is disposed at the interface between the buried dielectric layer (104) and the support layer (102).

4. A semiconductor-on-insulator substrate (100) according to one of the preceding claims, wherein said at least one region (108) is located at only a portion of the interface between the buried dielectric layer (104) and the support layer (102).

5. A semiconductor-on-insulator substrate (100) according to one of claims 1 to 3, wherein said at least one region (108) is disposed at the entire interface between the buried dielectric layer (104) and the support layer (102).

6. Substrate (100) of the semiconductor on insulator type according to one of the preceding claims, in which said at least one region (108) has a thickness greater than or equal to 3 pm.

7. Substrate (100) of the semiconductor on insulator type according to one of the preceding claims, in which the buried dielectric layer (104) is in direct contact with the support layer (102) and / or said at least one region (108).

8. Method for producing a substrate (100) of the semiconductor-on-insulator type, comprising producing a support layer (102) of a first semiconductor, a surface layer (106) of a second semiconductor, and a dielectric layer buried (104) disposed between the support layer (102) and the surface layer (106), and comprising doping of at least one region (108) of the support layer (102) with a doping level greater than or equal to 1015 cm 3.

9. Method for producing a substrate (100) of the semiconductor on insulator type according to claim 8, in which the doping of said at least one region (108) of the support layer (102) comprises the implementation of a localized ion implantation of dopants in said at least one region (108) of the support layer (102).

10. Method for producing a substrate (100) of the semiconductor on insulator type according to claim 9, in which the ion implantation is carried out with an energy of between 1 keV and 100 keV.

11. Method for producing a substrate (100) of the semiconductor-on-insulator type according to one of claims 8 to 10, in which parameters for implementing the doping of said at least one region (108) of the support layer (102) are chosen such that, for a temperature T less than 150 K, the pdc resistivity of said at least one region (108) of the support layer (102) is greater than that of an HR-SOI substrate comprising a support layer of the first semiconductor whose doping is less than 1015 cm 3.

12. Method for producing a substrate (100) of the semiconductor on insulator type according to claim 11, in which the resistivity q of said at least one region (108) of the support layer (102) is calculated according to the following equation: _ । with q expressed in Ohm.cm; q corresponding to the elementary charge; N ion corresponding to the density of ionized dopants, at temperature T, in said at least one region (108) of the support layer (102), expressed in cm 3; corresponding to the mobility, at temperature T, of the carriers whose type corresponds to that of the ionized dopants, expressed in cm2.V '.s

13. Integrated circuit (200) comprising several electronic components produced directly above said at least one doped region (108) of the support layer (102) of a substrate (100) of the semiconductor on insulator type according to one of claims 1 to 7.

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