LOW LEAKAGE CURRENT MOS TRANSISTOR

Abstract

One aspect of the invention relates to a field effect transistor (3) comprising: a channel region (11); a source region (12) and a drain region (13); a gate structure (14) comprising: a gate dielectric layer (14b); a gate electrode (14a) having a first work function (W1); and a lateral gate conductor (14c) arranged at least against the flank of the gate electrode (14a) located on the side of the drain region (13), the lateral gate conductor (14c) extending to the gate dielectric layer (14b) in direct contact with the gate electrode (14a) and having a second work function (W2); the second work function (W2) being: strictly greater than the first work function (W1) when the transistor is of the p-type; strictly less than the first work function (W1) when the transistor is of the n-type. Figure to be published with the abstract: Figure 3

Description

Title of the invention: LOW CURRENT MOS TRANSISTOR OF ESCAPE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of metal-oxide-semiconductor field effect transistors or MOSFETs (acronym for "metal oxide semiconductor field effect transistor"), and in particular those manufactured from a substrate comprising a buried insulating layer, typically a silicon-on-insulator (or SOI) type substrate. The present invention relates more particularly to a field effect transistor comprising a gate structure configured to reduce the gate-induced drain leakage current, or GIDL current (for "gate induced drain leakage" in English). TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] A silicon-on-insulator or SOI substrate successively comprises a silicon support layer, an electrically insulating layer known as buried, generally an oxide layer (or BOX layer, for buried oxide layer), and a thin film of monocrystalline silicon, also called an active layer. The active layer is so named because it is intended to receive active components, typically metal-oxide-semiconductor field effect transistors or MOSFETs (acronym for metal oxide semiconductor field effect transistor). The conduction channel of the MOSFETs is formed in the active layer. The SOI substrate notably offers the possibility of manufacturing fully depleted SOI transistors (or FDSOI, for Fully Depleted SOI) or partially depleted SOI transistors (or PDSOI, for Partially Depleted SOI).

[0003] [Fig.l] is a schematic sectional view of an SOI transistor 1. The SOI transistor 1 comprises a channel region 11, a source region 12 and a drain region 13, all three formed in the silicon thin film of the SOL substrate. The channel region 11 is disposed between the source region 12 and the drain region 13. The silicon thin film is topped with a gate electrode 14a, disposed opposite the channel region 11. The gate electrode 14a is separated from the channel region 11 by a gate dielectric layer 14b.

[0004] The SOI transistor 1 further comprises a doped silicon region 15 called a well, a part 15' of which called the ground plane or back gate is located under the electrically insulating layer 16 of the SOL substrate.

[0005] The rear grid 15' acts as a second grid. By varying the potential electrical of the back gate 15', separated from the channel region 11 by the electrically insulating layer 16, it is possible to modulate (dynamically) the threshold voltage of the SOI transistor 1 and consequently its on-state resistance (R0N)-

[0006] The SOI transistor 1 may be an n-channel transistor, also called an nFET transistor, or a p-channel transistor, also called a pFET transistor. In an nFET transistor, the source and drain regions 12-13 are n-type doped and the channel region 11 is p-type doped. Conversely, in a pFET transistor, the source and drain regions 12-13 are p-type doped and the channel region 11 is n-type doped.

[0007] Like most MOSFETs formed on a bulk silicon substrate, the SOI 1 transistor suffers in the off state from a leakage current called gate-induced drain leakage or GIDL current (for "gate induced drain leakage" in English).

[0008] The GIDL current results from the generation of electron-hole pairs in a depletion zone which forms on the surface of the drain region 13, where the gate electrode 14a overlaps the drain region 13. It manifests itself for negative gate-source voltage values ​​Vgs in the case of an nFET and positive in the case of a pFET.

[0009] [Fig.2] represents a field effect transistor 2 designed to have a low GIDL current and described in patent application US2004 / 137689A1. This field effect transistor 2, of nFET type, comprises: • a channel region 21, a source region 22, a drain region 23, all three formed in a bulk substrate; • a grid structure comprising: • a so-called “central” grid electrode 24a made of p-type doped polycrystalline silicon; • a gate dielectric layer 24b separating the gate electrode 24a from the channel region 21; • lateral gate extensions 25a made of n-type doped polycrystalline silicon, arranged against flanks of the gate electrode 24a; • an electrically insulating barrier layer 25b made of silicon oxide separating the lateral gate extensions 25a from the substrate and the gate electrode 24a; • metal spacers 26a made of tungsten or tungsten nitride arranged on the lateral grid extensions 25a; and • an electrically conductive barrier layer 26b separating the metal spacers 26a from the gate electrode 24a and the lateral gate extensions 25a; and • insulating spacers 27 arranged against sides of the gate structure.

[0010] The thickness of the electrically insulating barrier layer 25b (made of silicon oxide) is greater than the thickness of the gate dielectric layer 24b.

[0011] The field effect transistor 2, however, has significant parasitic capacitances and offers less control of short channel effects. In particular, the drain-induced barrier lowering effect or DIBL effect (for "drain-induced barrier lowering" in English) is accentuated. Furthermore, the manufacture of the transistor requires a very large number of technological steps. Summary of the invention

[0012] There is therefore a need to provide a field effect transistor which has better electrical performance and which can be manufactured more simply.

[0013] According to a first aspect of the invention, this need is tended to be satisfied by providing a field effect transistor comprising: • a source region and a drain region; • a channel region disposed between the source and drain regions; • a grid structure comprising: • a gate dielectric layer disposed over the channel region; • a gate electrode separated from the channel region by the di layer gate electrode and formed from a first conductive material having a first output work, the gate electrode comprising a first flank located on the source region side and a second flank located on the drain region side; and • a lateral gate conductor disposed at least against the second flank of the gate electrode and extending to the gate dielectric layer in direct contact with the gate electrode, the lateral gate conductor being formed from a second conductive material having a second output work, and wherein the second output work is: • strictly greater than the first output work when the transistor is p-type; • strictly less than the first output work when the transistor is n-type.

[0014] The lateral gate conductor reduces the vertical electric field at least near the drain region when the transistor is biased to negative gate-source voltage values ​​VGs in the case of an nFET and positive in the case of a pFET, and therefore the generation of electron-hole pairs by band-to-band tunneling at the origin of the GIDL current. The direct contact between the lateral gate conductor and the gate electrode avoids the appearance of new parasitic capacitances, ensures good control of short channel effects such as the DIBL effect and simplifies the fabrication of the transistor.

[0015] In a preferred embodiment, the transistor further comprises an electrically insulating layer, on which the channel region and the source and drain regions are arranged.

[0016] According to a development of this preferred embodiment, the transistor further comprises a rear gate separated from the channel region by the electrically insulating layer.

[0017] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the transistor according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • the second conductive material is a compound of semiconductor material and one or more metallic elements, preferably a silicide; • the gate structure overlaps the source and drain regions; • the side gate conductor is arranged all around the gate electrode; • the transistor further comprises a spacer arranged against at least one side of the gate structure and separated from the gate structure by a layer of dielectric material; • the grid dielectric layer is of constant thickness; • the side grid conductor extends over the entire height of the electrode of grid ; • the second output work is: • greater than or equal to 110% of the first output work when the transistor is p-type; and • less than or equal to 90% of the first output work when the transistor is n-type.

[0018] A second aspect of the invention relates to a method of manufacturing a field effect transistor comprising a source region, a drain region and a channel region disposed between the source and drain regions, this method comprising the following steps: • forming a gate stack on a semiconductor layer, the gate stack comprising a gate dielectric layer arranged on the semiconductor layer and a gate electrode separated from the semiconductor layer by the gate dielectric layer, the gate electrode being formed from a doped semiconductor material having a first output work, the gate electrode having a first flank intended to be on the source region side and a second flank intended to be on the drain region side; • form a sacrificial layer covering at least the second side of the gate electrode; • forming a spacer against at least the second flank of the gate electrode, the spacer being separated from the gate electrode by the sacrificial layer; • partially etch the sacrificial layer so as to expose part of the second side of the gate electrode; • depositing a layer of metal at least on the exposed part of the second side of the gate electrode; • performing annealing so as to react the metal with the doped semiconductor material of the gate electrode and transform a portion of the gate electrode into a lateral gate conductor extending to the gate dielectric layer in direct contact with a remaining portion of the gate electrode, the metal being chosen so that the lateral gate conductor is formed from a second conductive material having a second output work, the second output work being: • strictly greater than the first output work in the case of a p-type transistor; • strictly less than the first output work in the case of an n-type transistor.

[0019] In a preferred embodiment, the sacrificial layer is deposited on the semiconductor layer, the sides of the gate electrode and an upper face of the gate electrode, the spacer being further separated from the semiconductor layer by the sacrificial layer.

[0020] According to a development of this preferred embodiment, the step of partial etching of the sacrificial layer advantageously comprises the following operations: • etch an upper portion of the sacrificial layer arranged on the upper face of the gate electrode; • over-etching the sacrificial layer, so as to etch a portion of the sacrificial layer located between the gate electrode and the spacer.

[0021] Advantageously, the method further comprises, before the step of depositing the metal layer, a step of cleaning an exposed surface of the semiconductor layer, an upper face of the gate electrode and the exposed part of the second flank of the gate electrode, the cleaning step being carried out so as to continue the etching of the sacrificial layer between the gate electrode and the spacer.

[0022] Advantageously, the metal layer is further deposited on an upper face of the gate electrode and on exposed regions of the semiconductor layer located on either side of the grid stack and spacer. BRIEF DESCRIPTION OF THE FIGURES

[0023] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which: • [Fig.l] schematically represents an SOI transistor according to the prior art; • [Fig.2] schematically represents a field effect transistor on solid silicon substrate according to the prior art; • [Fig.3] schematically represents a preferred embodiment of a field effect transistor according to the first aspect of the invention, the transistor comprising lateral gate conductors; • [Fig.4] represents, as a function of the gate-source voltage VGs, the drain current ID of a pFET type transistor for several values ​​of the output work W2 of the lateral gate conductors; • [Fig.5] represents, as a function of the gate-source voltage VGs, the drain current ID of an nFET type transistor for several values ​​of the output work W2 of the lateral gate conductors; and • Figures 6A to 6G illustrate a preferred embodiment of the field effect transistor manufacturing method according to the second aspect of the invention.

[0024] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0025] In the following description, the terms "front", "rear", "upper", "lower", "above", "below", "horizontal", "vertical", "lateral", etc. used to qualify the position or orientation of certain elements refer to the orientation of Figures 3 and 6A to 6G. Furthermore, unless otherwise specified, the expressions "approximately", "substantially" and "of the order of" mean within 10%.

[0026] [Fig. 3] is a schematic sectional view of a field effect transistor (FET) 3 according to a preferred embodiment of the invention.

[0027] Like transistor 1 illustrated in [Fig.l], field effect transistor 3 (hereinafter referred to as transistor 3) comprises: • a channel 11 region; • a source region 12 and a drain region 13 arranged on either side from channel 11 region; • a grid structure 14 arranged on the channel region 11; • an electrically insulating layer 16 on which the channel region 11, the source region 12 and the drain region 13 are arranged.

[0028] In this preferred embodiment, the transistor 3 is manufactured from a multilayer structure successively comprising a support layer, a so-called buried insulating layer and an active layer.

[0029] The support layer is preferably made of a semiconductor material, for example silicon.

[0030] The buried insulating layer is preferably a buried oxide layer (or BOX layer, for “buried oxide layer” in English), for example made of silicon dioxide (SiO2). Its thickness is for example between 5 nm and 145 nm.

[0031] The active layer (also called thin layer, device layer or upper layer) is made of a semiconductor material, for example silicon, germanium or silicon-germanium alloy. Its thickness is for example between 3 nm and 100 nm.

[0032] The multilayer structure may in particular be a silicon-on-insulator (or SOI) type substrate. Transistor 3 is then referred to as a SOL transistor.

[0033] The channel region 11, the source region 12 and the drain region 13 are formed in the active layer of the multilayer structure. They lie on the insulating layer 16 (which corresponds to the buried insulating layer of the multilayer structure). These regions belong to the active area of ​​the transistor, which can be delimited laterally by electrical isolation trenches (not shown in [Fig. 3], but visible in [Fig. 1]). The electrical isolation trenches extend through the active layer, the buried insulating layer and a part of the support layer of the multilayer structure. The gate structure 14 is arranged on the active layer.

[0034] The channel region 11 may extend, in a direction perpendicular to a surface S of the multilayer structure, from the gate structure 14 to the insulating layer 16 and, in a plane parallel to this same surface S, from the source region 12 to the drain region 13. Thus, the channel region 11 may have a thickness equal to that of the active layer. The source and drain regions 12-13 may also occupy the active layer in its entire thickness, as illustrated in [Fig. 3]

[0035] The source and drain regions 12-13 are doped n-type in the case of an n-type field effect transistor (nFET) and p-type in the case of a p-type field effect transistor (pFET). Each of the source and drain regions 12-13 comprises a heavily doped region, i.e. a region whose concentration of doping impurities (donor type in an nFET and acceptor type in a pFET) is greater than or equal to 1018 cm3, for example equal to 1020 cm3.

[0036] Each of the source and drain regions 12-13 may further comprise a lightly doped region, commonly called an LDD extension (for “low doped drain” in English), located between the channel region 11 and the heavily doped region. The doping impurity concentration of the LDD extensions is strictly lower than the doping impurity concentration of the heavily doped regions. It is for example equal to 1019 cm3 when the doping impurity concentration of the heavily doped regions is equal to 1020 cm3.

[0037] The gate structure 14 comprises a gate electrode 14a and a gate dielectric layer 14b separating the gate electrode 14a from the channel region 11. The transistor 3 is therefore a MOSFET. The gate electrode 14a is formed from a first electrically conductive material having a first output work function Wp. This first conductive material may be a metallic material such as titanium nitride (TiN) or tungsten (W), or doped polycrystalline silicon (similar to a metal within the meaning of the term MOS). The gate dielectric layer 14b may be made of silicon dioxide (SiO2) or a dielectric material having a higher dielectric constant than that of silicon dioxide (a so-called “high-k” material). It may also comprise several sub-layers formed from different dielectric materials.

[0038] A particular feature of the transistor 3 is that the gate structure 14 further comprises a lateral gate conductor 14c arranged against at least one of the flanks (or lateral surfaces) of the gate electrode 14a. This lateral gate conductor 14c, also called lateral gate extension, preferably extends over the entire height of the gate electrode 14a. It is formed of a second electrically conductive material having a second output work W2 different from the first output work Wh. The flank against which the lateral gate conductor 14c rests is located on the side of the drain region 13.

[0039] The lateral gate conductor 14c is preferably annular in shape and arranged around the gate electrode 14a. It is then arranged against all the flanks of the gate electrode 14a. Alternatively, the gate structure 14 may comprise two separate lateral gate conductors 14c arranged against the two opposite flanks of the gate electrode 14a located on the side of the source region 12 and on the side of the drain region 13.

[0040] The second conductive material (and therefore the second output work W2) is chosen so as to decrease the vertical electric field in the vicinity of at least the drain region 13, and preferably in the vicinity of the source and drain regions 12-13, when the transistor 3 is biased at negative gate-source voltage values ​​VGs in the case of an nFET and positive in the case of a pFET. Thus, the generation of electron-hole pairs by band-to-band tunneling, which is at the origin of the current GIDL, is decreased.

[0041] The gate structure 14 comprising the lateral gate conductor (or lateral gate conductors) 14c may overlap the source and drain regions 12-13, i.e. partially cover them. The effect of reducing the GIDL current is then particularly strong.

[0042] The second conductive material is preferably a compound of semiconductor material and one or more metallic elements, such as a silicide (composed of silicon and one or more metallic elements). Alternatively, the second conductive material may be a metallic material (i.e., comprising one or more metals) or doped polycrystalline silicon.

[0043] Figures 4 and 5 show numerical simulation results of two examples of transistor 3 according to [Fig.3], respectively a pFET and an nFET. For each transistor, only the second work function W2 of the lateral gate conductor 14c varies between the different numerical simulations. The first work function Wi of the gate electrode 14a is invariable and, in these simulations, equal to 4.61 eV (typical value of a “midgap” gate metal such as TiN and W). The reference simulation denoted “Ref”, in which the second work function W2 is equal to the first work function Wi (W2 = Wi = 4.61 eV), corresponds to a transistor comprising a lateral gate conductor formed from the same material as the gate electrode 14a (i.e. the equivalent of a transistor according to [Fig.l] comprising only the gate electrode 14a).

[0044] [Fig.4] represents the evolution of the drain current ID of the pFET as a function of the gate-source voltage VGs for different values ​​of the second output work W2 (ranging from 3.8 eV to 5.4 eV).

[0045] This figure shows that the drain current ID at a positive voltage VGs (in other words the drain current of the pFET in the off state) decreases when the second output work W2 increases and that it becomes lower than that of the reference transistor (curve "Ref") when the second output work W2 exceeds the value of the first output work Wb

[0046] In other words, when the transistor 3 is of the pFET type, a second output work W2 strictly greater than the first output work Wi makes it possible to reduce the current GIDL.

[0047] For example, when the first conductive material (gate electrode 14a) is chosen from titanium nitride (TiN) (Wi ~ 4.6 eV), tungsten (W) (Wi ~ 4.7 eV) and n-doped polycrystalline silicon (Wi ~ 4.0 eV), the second conductive material is advantageously chosen from nickel silicides (4.6 eV < W2 < 4.8 eV) and platinum silicides (5.16 eV < W2 < 5.25 eV).

[0048] Similarly, [Fig.5] represents the evolution of the drain current ID of the nFET as a function of the gate-source voltage VGs for different values ​​of the second output work W2 (ranging from 3.8 eV to 5.4 eV).

[0049] This figure shows that the drain current ID at a negative voltage VGs (in other words the drain current of the nFET in the off state) decreases when the second output work W2 decreases and that it becomes lower than that of the reference transistor (curve "Ref") when the second output work W2 becomes strictly lower than the first output work Wb

[0050] Thus, when the transistor 3 is of the nFET type, a second output work W2 strictly lower than the first output work Wi makes it possible to reduce the current GIDL.

[0051] For example, when the first conductive material (gate electrode 14a) is chosen from titanium nitride (TiN) (Wi ~ 4.6 eV), tungsten (W) (Wi ~ 4.7 eV) and p-doped polycrystalline silicon (Wi « 5.2 eV), the second conductive material is advantageously chosen from titanium silicides (for example, W2 ~ 4.0 eV for TiSi2) and tantalum silicides (e.g., W2 ~ 4.2 eV for TaSi2).

[0052] In order to obtain a significant reduction in the GIDL current, the second output work W2 is advantageously: • greater than or equal to 110% of the first output work Wi when the transistor is of the pFET type; and • less than or equal to 90% of the first output work Wi when the transistor is of the nFET type.

[0053] As illustrated in [Fig. 3], the lateral gate conductor 14c extends to the gate dielectric layer 14b, in direct contact with the gate electrode 14a. In other words, there is therefore no intermediate layer (such as the electrically insulating barrier layer 25b in the transistor 2 of [Fig. 2]) between the lateral gate conductor 14c and the gate electrode 14a. The parasitic capacitances and other figures of merit of the transistor 3, such as the leakage current due to the DIBL effect, are therefore not affected.

[0054] The lateral gate conductor 14c has a section of width 1 which can be between 1 nm and 30 nm, for example equal to 10 nm or 20 nm. The width 1 of the lateral gate conductor 14c is measured parallel to the surface S of the multilayer structure in the section plane of [Fig.3] (in other words in the same direction as the distance between the source and drain regions 12-13). Other numerical simulations have shown that the width 1 of the lateral gate conductor 14c has a negligible impact on the current-voltage characteristic ID-VGS of the transistor 3, and therefore on the current GIDL.

[0055] Under the gate electrode 14a and the lateral gate conductor 14c, the gate dielectric layer 14b advantageously has a constant thickness, from one side to the other. the other of the gate structure 14 (or from the source region 12 to the drain region 13). The thickness of the gate dielectric layer 14b is for example between 2 nm and 20 nm.

[0056] The transistor 3 may also comprise a rear gate 15' separated from the channel region 11 by the insulating layer 16. The rear gate 15', also called the ground plane, is located under the insulating layer 16, opposite the channel region 11. It acts as a second gate. By varying the electrical potential of the rear gate 15', it is possible to modulate (dynamically) the threshold voltage of the transistor 3 and consequently its on-state resistance (R0N)-

[0057] The rear gate 15' is formed from a doped semiconductor material. It preferably belongs to a doped semiconductor region called a well, extending beyond the active zone of the transistor 3 (therefore beyond the electrical insulation trenches; see [Fig.l]).

[0058] This box may be formed by implanting doping impurities into the support layer of the multilayer structure. The box may be n-type or p-type doped. The rear gate 15' may have a higher concentration of doping impurities than the remaining portion of the box.

[0059] Finally, the transistor 3 may comprise a spacer 17 arranged against one or more sides of the gate structure 14, and preferably all around the gate structure 14. This spacer 17 may be in direct contact with the gate dielectric layer 14b and the lateral gate conductor 14c, and preferably, in direct contact with the source and drain regions 12-13. It is formed of a dielectric material such as silicon nitride (SiN). Alternatively, it may be separated from the lateral gate conductor 14c and the source and drain regions 12-13 by a layer of dielectric material.

[0060] In an alternative embodiment not shown in the figures, the transistor 3 is manufactured from a solid semiconductor substrate, for example made of silicon, germanium or silicon-germanium alloy. The transistor 3 then differs from that shown in [Fig. 3] essentially in that it is devoid of an insulating layer 16 and a rear gate 15'. The channel region 11, the source region 12 and the drain region 13 are formed in the solid semiconductor substrate.

[0061] The GIDL current of a MOSFET transistor on a solid substrate is also reduced by the use of the lateral gate conductor 14c having an output work (W2) different from that of the gate electrode 14a.

[0062] A preferred embodiment of a method for manufacturing the transistor 3 will now be described with reference to FIGS. 6A to 6G. These figures represent, in sectional view, different steps S1-S7 of the method for manufacturing the transistor 3.

[0063] The first step SI, represented by [Fig.6A], consists of forming a stack of gate 14' on a semiconductor layer 30, for example made of silicon. The semiconductor layer 30 can be either the active layer of a multilayer structure (typically an SOI substrate), or a bulk semiconductor substrate. The gate stack 14' comprises the gate electrode 14a and the gate dielectric layer 14b. The gate electrode 14a is here made of a doped semiconductor material, such as doped polycrystalline silicon. The gate dielectric layer 14b is for example made of silicon dioxide (SiO2) or silicon oxynitride (SiON).

[0064] The formation of the gate stack 14' may in particular comprise the deposition of a dielectric layer on the semiconductor layer 30, the deposition of a layer of doped semiconductor material on the dielectric layer, the etching of the layer of doped semiconductor material to delimit the gate electrode 14a and, preferably, the etching of the dielectric layer through the gate electrode 14a to delimit the gate dielectric layer 14b. These operations being conventional, they will not be described in more detail here.

[0065] Then, in step S2 of [Fig.6B], a sacrificial layer 31, preferably made of a dielectric material such as SiO2, is formed at least on the sides of the gate electrode 14a. This sacrificial layer 31 has a thickness e which is preferably between 5 nm and 15 nm.

[0066] As illustrated in [Fig.6B], the sacrificial layer 31 is preferentially deposited on the semiconductor layer 30 (outside the gate stack 14'), the flanks (or lateral surfaces) of the gate electrode 14a and an upper face of the gate electrode 14a. Thus, the sacrificial layer 31 completely covers the gate stack 14'. The deposition is advantageously conformal, that is to say that the thickness e of the sacrificial layer 31 (measured perpendicular to the surface on which it rests) is substantially constant.

[0067] In S3 (see [Fig.6C]), the spacer 17 of the transistor 3 is formed around the gate electrode 14a. The spacer 17 is not in direct contact with the gate electrode 14a, but separated from the gate electrode 14a by the sacrificial layer 31. The spacer 17 is preferably made of a dielectric material, for example silicon nitride (SiN). The dielectric material of the spacer 17 is different from that of the sacrificial layer 31. Its formation may comprise: • a sub-step of conformal deposition of a dielectric layer on the semiconductor layer 30 (outside the gate stack 14'), the sides of the gate electrode 14a and the upper face of the gate electrode 14a; and • a sub-step of anisotropic etching of the dielectric layer, according to a preferential etching direction perpendicular to the surface S of the semiconductor layer 30, in order to etch the horizontal parts of the dielectric layer (located on the semiconductor layer 30 and the upper face of the grid electrode 14a) and keep its vertical parts (leaning against the sides of the grid electrode 14a).

[0068] When the sacrificial layer 31 has been deposited on the semiconductor layer 30, the spacer 17 is further separated from the semiconductor layer 30 by the sacrificial layer 31 (see [Fig.6C]).

[0069] The anisotropic etching is advantageously selective with respect to the sacrificial layer 31 (the sacrificial layer 31 therefore serves as an etching stop layer).

[0070] During step S4 represented by [Fig.6D], the sacrificial layer 31 is partially etched so as to expose a portion of the sides of the gate electrode 14a.

[0071] This etching step S4 may comprise two successive operations: a first etching operation of the upper portion of the sacrificial layer 31, with a stop on the upper face of the gate electrode 14a, and a second over-etching operation of the sacrificial layer 31, to etch a portion located between the gate electrode 14a and the spacer 17. The portion of the sacrificial layer 31 arranged on the semiconductor layer 30 and not covered by the spacer 17 is etched at the same time as the upper portion, during the first operation.

[0072] For example, the sacrificial layer 31 is etched anisotropically using a fluorocarbon plasma, then by wet etching in a hydrofluoric acid (HF) bath, with an over-etching less than or equal to 30%. The sacrificial layer 31 can also be etched solely by plasma etching.

[0073] With reference to [Fig.6E], the manufacturing method may then comprise a step of cleaning the exposed surface of the semiconductor layer 30 (or so-called “free” surface, i.e. not covered by the gate stack 14', the sacrificial layer 31 and the spacer 17), the upper face of the gate electrode 14a and the exposed part of the sides of the gate electrode 14a. This optional cleaning step is advantageously carried out so as to continue the etching of the sacrificial layer 31 between the gate electrode 14a and the spacer 17.

[0074] Such cleaning is particularly useful when the gate electrode 14a is made of polycrystalline silicon. It allows the etching of the sacrificial layer 31 to continue while limiting the consumption of the gate electrode 14a (and of the semiconductor layer 30, if applicable). The cleaning then has an etching selectivity (of the sacrificial layer 31 with respect to the gate electrode 14a) greater than the etching of the step S4 which precedes it.

[0075] Cleaning further makes it possible to remove impurities or contaminants on the surface of the semiconductor layer 30 and the gate electrode 14a, in preparation for subsequent steps of the method.

[0076] Cleaning can be accomplished wet (for example using a hydrofluoric acid solution in the case of a sacrificial layer 31 made of SiO2) or by dry process (for example using the Siconi™ process in the case of a sacrificial layer 31 in SiO2).

[0077] The following steps S6 and S7 of FIGS. 6F and 6G relate to the formation of the lateral gate conductor 14c of the transistor 3. The lateral gate conductor 14c is, in this embodiment of the manufacturing method, formed from a compound of semiconductor material and one or more metallic elements, and more particularly from a silicide in the case of a polycrystalline silicon gate. Steps S6 and S7 can therefore be described as siliciding steps.

[0078] In S6 (cf. [Fig.6F]), a metal layer 32 is deposited at least on the exposed part of the sides of the gate electrode 14, and advantageously, on the upper face of the gate electrode 14a and the exposed surface of the semiconductor layer 30. The metal layer 32 is for example made of titanium, tantalum, platinum, nickel, cobalt or an alloy of several of these metals. Its thickness is for example between 5 nm and 15 nm.

[0079] Finally, in S7 (cf. [Fig.6G]), an annealing is performed so as to react the metal with (at least) the doped semiconductor material of the gate electrode 14a and transform (at least) a portion (here peripheral) of the gate electrode 14a into a lateral gate conductor 14c. The lateral gate conductor 14c extends to the gate dielectric layer 14b, in direct contact with a remaining portion (central) of the gate electrode 14a. The residual portion of the sacrificial layer 31 prevents the reaction of the metal with the semiconductor layer 30 between the spacer 17 and the gate electrode 14a.

[0080] The metal of the metal layer 32 is chosen so that the metal-semiconductor compound of the lateral gate conductor 14c has an output work W2 different from the output work Wi of the gate electrode 14a (strictly greater or strictly less than the output work Wi depending on the type of transistor, respectively pFET or nFET).

[0081] After step S4 of partial etching of the sacrificial layer 31, and the cleaning step S5 if applicable, the exposed part of the flanks of the gate electrode 14a extends over a height hi such that the lateral gate conductor 14c obtained at the end of step S7 extends to the gate dielectric layer 14b (see Figs. 6E-6G). According to an exemplary embodiment, it can be provided that the height hi of the exposed part of the flanks of the gate electrode 14a is greater than or equal to half the height h 2 of the gate electrode 14a and strictly less than the height h2 of the gate electrode 14a (h2 > hi > h2 / 2). This exemplary embodiment of course depends on the experimental conditions but also on the materials used (species, deposition, annealing, duration, temperatures, etc.). Any change in one of the experimental conditions or in one of the materials will necessarily imply changes on the heights to be provided to ensure that the side gate conductor 14c obtained at the end of step S7 extends to the gate dielectric layer 14b.

[0082] When the metal layer 32 has furthermore been deposited in direct contact with the upper face of the gate electrode 14a and the regions of the semiconductor layer 30, on either side of the gate stack 14' and the spacer 17, electrically conductive zones 33 are obtained at the same time as the lateral gate conductor 14c, respectively for making electrical contact with the gate electrode 14a and the source and drain regions 12-13.

[0083] A portion of the metal layer 32 may not have reacted during annealing (this is particularly the case for the portion of the metal layer 32 placed on the spacer 17, in the case of a “full plate” deposition). This remaining portion of the metal layer 32 is then removed after annealing.

[0084] The manufacturing method further comprises a step of forming the source and drain regions 12-13 in two distinct regions of the semiconductor layer 30, preferably by (ionic) implantation of doping impurities, the remaining (non-implanted) portion of the semiconductor layer 30 then forming the channel region 11 of the transistor 3 (this step therefore also makes it possible to delimit the channel region 11).

[0085] This step of forming the source and drain regions 12-13 is accomplished after step S3 of forming the spacer 17, preferably before step S4 of etching the sacrificial layer 31 (the implantation of the ions therefore being carried out through the sacrificial layer).

[0086] The manufacturing method may also comprise, in the case of a multilayer structure, a step of forming a rear gate 15' under the buried insulating layer 16, preferably by implanting doping impurities (ions) in the support layer of the multilayer structure. This step of forming the rear gate 15' is accomplished before the step SI of forming the gate stack 14'.

[0087] These other manufacturing steps being conventional, they will not be described in more detail.

[0088] The manufacturing method described above in relation to Figures 6A-6G is particularly simple to implement and comprises fewer technological steps than the manufacturing method of the transistor 2 of [Fig.2]. It further allows the simultaneous formation of the lateral gate conductor 14c and the contact areas 33, for the gate electrode 14a and the source and drain regions 12-13. The remaining portion of the sacrificial layer 31, when formed from a dielectric material such as SiO2, contributes to reducing the parasitic capacitances of the transistor 3.

[0089] Many variations and modifications of the manufacturing method will be apparent to those skilled in the art. In particular, the sacrificial layer 31 and the spacer 17 may be formed against only a portion of the sides of the gate electrode, and in particular against a single flank, the one intended to be on the drain region side (from which it follows that the lateral gate conductor 14c is arranged against this single flank).

Claims

Claims

1. Field effect transistor (3) comprising: - a source region (12) and a drain region (13); - a channel region (11) arranged between the source (12) and drain (13) regions; - a gate structure (14) comprising: • a gate dielectric layer (14b) arranged on the channel region (11); • a gate electrode (14a) separated from the channel region (11) by the gate dielectric layer (14b) and formed of a first conductive material having a first output work (WJ, the gate electrode (14a) comprising a first flank located on the side of the source region (12) and a second flank located on the side of the drain region (13);and • a lateral gate conductor (14c) arranged at least against the second flank of the gate electrode (14a) and extending to the gate dielectric layer (14b) in direct contact with the gate electrode (14a), the lateral gate conductor (14c) being formed from a second conductive material having a second output work (W2); transistor in which the second output work (W2) is: - strictly greater than the first output work (Wi) when the transistor is p-type; - strictly less than the first output work (Wi) when the transistor is n-type.;

2. Transistor (3) according to claim 1, wherein the second conductive material is a compound of semiconductor material and one or more metallic elements, preferably a silicide.

3. Transistor (3) according to one of claims 1 and 2, in which the gate structure (14) overlaps the source (12) and drain (13) regions.

4. Transistor (3) according to any one of claims 1 to 3, in which the side gate conductor is arranged all around the gate electrode (14a).

5. Transistor (3) according to any one of claims 1 to 4, further comprising a spacer (17) disposed against at least one flank of the gate structure (14) and separated from the lateral gate conductor (14c) by a layer of dielectric material (31).

6. Transistor (3) according to any one of claims 1 to 5, wherein the gate dielectric layer (14b) is of constant thickness.

7. A transistor (3) according to any one of claims 1 to 6, wherein the lateral gate conductor (14c) extends over the entire height of the gate electrode (14a).

8. Transistor (3) according to any one of claims 1 to 7, further comprising an electrically insulating layer (16), on which the channel region (11) and the source (12) and drain (13) regions are arranged.

9. Transistor (3) according to claim 8, further comprising a back gate (15') separated from the channel region (11) by the electrically insulating layer (16).

10. Transistor (3) according to any one of claims 1 to 9, in which the second output work (W2) is: - greater than or equal to 110% of the first output work (Wi) when the transistor is of p type; and - less than or equal to 90% of the first output work (Wi) when the transistor is of n type.

11. A method of manufacturing a field effect transistor (3) comprising a source region (12), a drain region (13) and a channel region (11) arranged between the source (12) and drain (13) regions, the method comprising the following steps: - forming a gate stack (14') on a semiconductor layer (30), the gate stack comprising a gate dielectric layer (14b) arranged on the semiconductor layer (30) and a gate electrode (14a) separated from the semiconductor layer (30) by the gate dielectric layer (14b), the gate electrode (14a) being formed of a doped semiconductor material having a first output work (Wi), the gate electrode (14a) having a first flank intended to be on the side of the source region (12) and a second flank intended to be on the side of the drain region (13); - forming a sacrificial layer (31) covering at least the second flank of the gate electrode (14a); - forming a spacer (17) against at least the second flank of the gate electrode (14a), the spacer (17) being separated from the gate electrode (14a) by the sacrificial layer (31); - partially etching the sacrificial layer (31) so as to expose a part of the second flank of the gate electrode (14a); - depositing a metal layer (32) at least on the exposed part of the second flank of the gate electrode (14a);- performing annealing so as to react the metal with the doped semiconductor material of the gate electrode (14a) and transform a portion of the gate electrode into a lateral gate conductor (14c) extending to the gate dielectric layer (14b) in direct contact with a remaining portion of the gate electrode (14a), the metal being chosen so that the lateral gate conductor (14c) is formed of a second conductive material having a second output work (W2), the second output work (W2) being: • strictly greater than the first output work (Wi) in the case of a p-type transistor; • strictly less than the first output work (Wi) in the case of an n-type transistor.;

12. The method of claim 11, wherein the sacrificial layer (31) is deposited on the semiconductor layer (30), the sides of the gate electrode (14a) and an upper face of the gate electrode, the spacer (17) being further separated from the semiconductor layer (30) by the sacrificial layer (31).

13. Method according to claim 12, in which the step of partially etching the sacrificial layer (31) comprises the following operations: - etching an upper portion of the sacrificial layer (31) arranged on the upper face of the gate electrode (14a); - performing an over-etching of the sacrificial layer (31), so as to etch a portion of the sacrificial layer located between the gate electrode (14a) and the spacer (17).

14. A method according to any one of claims 11 to 13, further comprising, before the step of depositing the metal layer (32), a step of cleaning an exposed surface of the semiconductor layer (30), an upper face of the gate electrode (14a) and the exposed portion of the second flank of the gate electrode, the cleaning step being performed so as to continue the etching of the sacrificial layer (31) between the gate electrode (14a) and the spacer (17).

15. A method according to any one of claims 11 to 14, wherein the metal layer (32) is further deposited on an upper face of the gate electrode (14a) and on exposed regions of the semiconductor layer (30) located on either side of the gate stack (14') and the spacer (17).

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