Method of manufacturing an integrated circuit and corresponding integrated circuit

Abstract

The method for manufacturing an integrated circuit comprises forming lateral isolation regions (STI) delimiting active regions (ACT) in a semiconductor substrate (SUB), and etching a trench (GRTR) extending vertically deep into the substrate (SUB) and intended to cross said lateral isolation regions (STI) and said active regions (ACT). Said formation of the lateral isolation regions (STI) comprises forming sacrificial lateral isolation regions (STI_SAC) positioned at the location of said etching of the trench (TR) crossing the active regions. Figure for abstract: Fig 5A

Claims

limiting active regions (ACT) in a semiconductor substrate (SUB), and a component arranged in a trench (TR) extending vertically deep into the substrate (SUB) and through said lateral isolation regions (STI) and said active regions (ACT), wherein the bottom of the trench is located at a constant and equal depth (plO) with respect to the locations of the trench which cross the lateral isolation regions (STI) and the locations which cross the active regions (ACT).

7. Integrated circuit according to claim 6, in which the component arranged in the trench has flanks directly in contact with the active regions (ACT), at the locations of the trench which cross the active regions.

8. Integrated circuit according to one of claims 6 or 7, in which the lateral insulation regions (STI) delimit the active regions in strips extending lengthwise in a first direction (X), while said trench (TR) extends lengthwise in a second direction (Y) perpendicular to the first direction (X), the bottom of the trench being located at a constant and equal depth (pl0) along the second direction (Y).

9. Integrated circuit according to one of claims 6 to 8, comprising a buried access transistor (TA) with vertical gate (GV), the vertical gate (TRG) being the component arranged in said trench (TR), and a state transistor (TE) comprising a stack of a floating gate (FG) and a control gate (CG) at least partly covering said active regions (ACT) in the vicinity of the trench (TR).

10. Semiconductor device, comprising lateral isolation regions (STI) delimiting active regions (ACT) in a semiconductor substrate (SUB), in which sacrificial lateral isolation regions (STI_SAC) are further positioned through the active regions; capable of being shaped by etching a trench (GRTR) at the location of the sacrificial lateral isolation regions (STI_SAC) as defined in one of claims 1 to 5. [Fig. IB] CEL1 CEL2 [Fig. 3A] [Fig. 3C]

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