ELECTRONIC CIRCUITS FOR ACQUIRING THE THRESHOLD VOLTAGE OF A POWER TRANSISTOR

Abstract

The invention relates to a device (10, 20) for monitoring the health status of a power transistor, comprising: - means (8) for applying an "ultra-slow" trigger voltage (VGS) to this transistor; - means (12-22) for measuring the trough of the gate voltage (VGS) that follows the Miller plateau. Figure for the abstract: Fig. 4

Description

Title of the invention: ELECTRONIC CIRCUITS FOR ACQUIRING THE THRESHOLD VOLTAGE OF A POWER TRANSISTOR TECHNICAL FIELD AND PREVIOUS ART

[0001] The invention relates to the field of power electronics, and in particular to that of electrification and electrical hybridization of power in general and particularly in aeronautics.

[0002] In this context, there is a need for high-performance, integrated, reliable, and secure power electronic systems. The power module for motor control is a key function on which significant efforts must be focused. The introduction of wide-bandgap power semiconductor components such as silicon carbide (SiC) MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) within the power module has made it possible to reduce the onboard mass and volume by 15 to 30% and to increase the electrical efficiency by 2 to 3 points.

[0003] SiC MOSFETs are power semiconductor devices that offer numerous advantages, such as high performance, increased energy efficiency, and better resistance to high temperatures compared to traditional silicon (Si) MOSFETs. However, their adoption in the aerospace industry still presents certain challenges that limit their maturity and widespread deployment.

[0004] In particular, there are no means available to monitor the reliability of these transistors during continuous operation in a non-intrusive manner. The same problem arises more generally for semiconductor transistors based on wide-bandgap semiconductors, such as GaN technology. By "wide bandgap," we mean an energy gap or a band gap height Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is greater than that of silicon. The same problem also arises for conventional silicon (Si) MOSFETs.

[0005] However, monitoring the health status of such a transistor, particularly a wide bandgap transistor, especially a SiC MOSFET, is a key issue for its adoption in high-reliability and long-life applications, such as aerospace. Indeed, during its operation within a power converter, performance degradations related to component aging can occur. These performance degradations result from variations in intrinsic physical parameters, particularly in the case of a SiC MOSFET, linked to phenomena of trapping electrical charges, for example, in the case of a SiC MOSFET, within the silicon dioxide (SiO2) gate oxide layer in the presence of defects at the interface with the SiC substrate.

[0006] These effects are all the more pronounced in SiC technology than in Si technology given the lower quality of realization of the gate oxide layer which is itself, in parallel, subjected to stronger electric field stress on SiC MOSFET.

[0007] Indeed, in a silicon MOSFET, the gate oxide (SiO2) is generally well-suited to the silicon crystal structure. Silicon and silicon dioxide have a natural chemical affinity, which facilitates the growth of a native, uniform, and low-deficiency gate oxide layer. In contrast, silicon carbide (SiC) has a different and more complex crystal structure compared to silicon. The growth of a high-quality gate oxide layer on SiC is more difficult due to the less natural nature of the interface between SiC and SiO2.

[0008] Crystalline defects in the gate oxide layer of Si MOSFETs are generally less frequent and more stable. SiO2-on-Si fabrication technologies are highly developed, enabling the production of high-quality oxide layers with few defects. In the case of SiC MOSFETs, gate oxide growth on SiC can be more prone to defect formation. These defects can include oxygen vacancies, structural imperfections, and recombination sites. They can be caused by differences in atomic mobility between SiC and SiO2, thermal stresses during the fabrication process, and other factors.

[0009] All of these defects can lead to charge trapping in the gate oxide. This tunneling trapping can occur either at the surface, at the SiC / SiO2 interface, or deeper within the oxide. Tunneling is a quantum process that allows electrons to "tunnel" through an energy barrier that, classically in silicon, would be too high for them to pass through. In the context of SiC MOSFETs, tunneling occurs when the channel electrons, under the influence of the gate voltage, acquire sufficient kinetic energy to pass through the thin gate oxide layer and become trapped within it.

[0010] These trapping phenomena on SiC MOSFETs are complex and depend on the voltage biasing conditions of the gate oxide (DC component and AC component related to the control switching). They are also exacerbated at high operating temperatures. Trapping leads, on the one hand, to a slow but continuous increase in the threshold voltage VTh, and on the other hand, to a decrease in the mobility p of electrons in the channel. The combination of these two effects results, on the one hand, in an increase in channel resistance, and therefore in losses due to conduction, and on the other hand an increase in the amplitude of the Miller plateau, thus reducing the switching speed (especially the dv / dt at startup, the loss component of which is dominant) and increasing switching losses.

[0011] Several secondary indicators of the health status of a SiC MOSFET exist: the on-state resistance RDson, and the duration and amplitude of the Miller plateau. While these quantities are certainly affected by transistor aging, they are composed of several other components, each contributing to mask the intrinsic variations due to the component's own aging. Their relevance for monitoring the transistor's health status can therefore be questioned.

[0012] There are other indirect indicators such as gate leakage currents IGSS and drain leakage currents IDSS, internal gate resistance Rgint(Vgs) and the characteristic C1Ss = f(VGS) (see in particular A.E1 Boubkari, Development of fast, precise and integrated CMOS features, for optimal switching and internal protection of SiC MOSFET module inverters (hal.science. 2023)): • The gate leakage current (IGSs) increases by several orders of magnitude between a healthy component (a few hundred femtoamperes) and a component with a cracked gate (approximately 10 mA). Measuring this parameter requires an extremely precise and stable differential measurement of the voltage across the external gate resistor, but IGSs does not act as a precursor, but rather as a final indicator of irreversible degradation. This leakage measurement as a precursor (before gate oxide cracking) is possible using a dedicated driver channel, as explained in PCT / FR2023 / 051145, with a sensitivity of 30 nA. However, its implementation remains complex. • Drain leakage monitoring relies on measuring a power-side observable (between drain and source) and must be accurate on the order of milliamperes, making it impractical within a converter. • It is shown that by sweeping VGS from negative to positive values ​​using a static characteristic plotter (such as the Keysight B1505A), a flatband voltage shift appears for the aged component. A similar property can be obtained by sweeping RGint(Vgs) and monitoring the variation of this value. However, this method remains difficult to apply to embedded measurements.

[0013] The main indicator whose variations faithfully reflect the evolution of the component's health status remains the threshold voltage VTH. However, in the current state of the art, this parameter is not directly measurable in real time when the transistor is integrated within an operating power converter and subject to a partitioning regime. Description of the invention

[0014] The present invention aims to solve all or part of the problems described above.

[0015] In particular, it proposes an electronic circuit for monitoring, for example within a power converter, the health status of a MOSFET power transistor, by measuring in real time the threshold voltage of the transistor VTh-

[0016] The invention relates in particular to a device for monitoring or tracking the health status of a MOSFET power transistor comprising:

[0017] - means for providing or applying to a MOSFET power transistor a ignition voltage (VGS) these means comprising at least one resistor (R3, R4), forming external grid resistance, of at least 1OkQ;

[0018] - means for measuring or estimating the gate voltage dip (VGS) that follows the Miller's plateau.

[0019] The first means can provide a MOSFET power transistor with an "ultra slow" trigger voltage (VGS).

[0020] The transistor is, for example, of the wide-bandgap semiconductor type, such as those using SiC or GaN technology. "Wide bandgap" refers to an energy gap or band gap height Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is greater than that of silicon. Alternatively, it could also be a silicon (Si) MOSFET transistor.

[0021] Thus the invention makes it possible to estimate the threshold voltage of the transistor by measuring the trough of the gate voltage (VGS) which follows the Miller plateau.

[0022] The invention therefore proposes a real-time monitoring device that can be embedded. The integration of this type of device makes it possible to detect early signs of degradation and aging of MOSFETs, particularly SiC MOSFETs, thus enabling rapid intervention to prevent more serious problems.

[0023] According to one embodiment, a monitoring device according to the invention may include means or a stage for detecting the cancellation of the derivative of the grid voltage (VGs).

[0024] Optionally, means or a comparison stage may or may be provided for comparing the value of the derivative of VGS to a comparison threshold value.

[0025] Preferably, the threshold value for comparison is negative.

[0026] According to a particular embodiment, the means or the comparison stage includes means forming hysteresis.

[0027] A device according to the invention may further include means for memorizing a value of said hollow.

[0028] It includes, for example, at least one sample-and-hold device to maintain said trough value.

[0029] The means for storing a minimum value of said hollow may include a capacitor. They may further be associated with means forming a switch.

[0030] A device according to the invention may further comprise second means for applying a voltage to a power MOSFET transistor, these second means comprising at least one resistance of low value compared to said resistance forming external gate resistance.

[0031] Such a device may further include control means for the first means and the second means with Pulse Width Modulation (PWM).

[0032] A device according to the invention may further include means for synchronizing with a current sensor.

[0033] The invention also relates to a method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN or MOSFET-Si type or, more generally, of a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds) or of a MOSFET-Si type power transistor, implementing a device as described above and in the remainder of this application.

[0034] The invention also relates to a power converter or module comprising several power transistors and at least one device as described above and in the remainder of this application.

[0035] The invention also relates to an aircraft comprising at least one converter or power module according to the invention. brief description of the figures

[0036] - Figures [Fig. 1A] and [Fig. 1C] illustrate the dependency relationship between Cgd and VDS> re showing the curve Cgd as a function of VDs([Fig.1A]), and the time evolution of respectively VDS (figure IB), and VGS ([Fig. IC]) of a MOSFET - SiC transistor;

[0037] - Figures [Fig. 2A] and [Fig. 2B] represent the influence of the driver voltage VDD on the shape of the hollow of VGS ([Fig.2A]) and on VDS ([Fig.2B]);

[0038] - Figure 3 represents a comparison of the VGs waveforms between components new with healthy oxide (curve I) and stressed component with aged oxide (curve II);

[0039] - [Fig. 4] schematically represents a measurement chain for monitoring analog of the trough with derivative of VGs and direct sampling;

[0040] - Figures [Fig. 5A] and [Fig. 5B] represent simulation results of the evolution temporal of VGs and (dVGs / dt);

[0041] - Figures [Fig. 6A] and [Fig. 6B] represent the same curves as in Figures 5A-5B with, in addition, the output of the sample-and-hold (EB);

[0042] - the [Fig.7A], [Fig.7A1], [Fig.7B][Fig.7B1], [Fig.7C], [Fig.7C1], represent a possible implementation of means to automatically memorize the hollow;

[0043] - [Fig.8] schematically represents another possible embodiment of means to memorize the hollow;

[0044] - Figure 9 schematically represents a measurement chain for monitoring analog with automatic memorization of the hollow;

[0045] - Fig. 1OA and Fig. 1OC represent simulation results of the evolution time of VGS ([Fig.1OA]) and (dVGS / dt) ([Fig.1OC]) with the waveforms of interest and the switch opening and sample-hold signal ([Fig.1OB]);

[0046] - Figures [Fig. 11] and [Fig. 12] respectively represent examples of realizations cut from the circuits of figures 4 and 9;

[0047] - Figures [Fig. 13A], [Fig. 13B], [Fig. 14A] and [Fig. 14B] represent an application of the invention has a Pulse Width Modulation (PWM) control frame;

[0048] - Figures [Fig. 15A] and [Fig. 15B] represent an application of the invention to an inverter three-phase involving common mode control on a line of low-side (A) and high-side (B) transistors;

[0049] - [Fig. 16] represents an application of the invention to a commutation according to the invention around the zero of a charging current;

[0050] - the [Fig. 17] represents an electronic gate control circuit.

[0051] - Fig. 18 represents an example of timing diagrams for controlling the device the [Fig. 17];

[0052] - [Fig. 19] represents an implementation of the synchronization of a measurement according to the invention with a current sensor.

[0053] DETAILED DESCRIPTION OF EMBODIMENT METHODS OF THE INVENTION

[0054] The invention relates to a method for monitoring the health status of a power transistor, particularly one based on a large-bandgap semiconductor, for example, SiC or GaN, i.e., one comprising a larger energy gap or bandgap height Eg separating the last occupied states of the valence band and the first free states of the conduction band than silicon. This could be, for example, a SiC MOSFET or a p-GaN HEMT (high electron mobility gallium nitride transistor), or a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds). However, the invention also applies to Si MOSFET power transistors. In the following, most of the explanations are given for a SiC MOSFET.

[0055] According to the invention, such a monitoring method implements monitoring of the threshold voltage VTH of the device. This quantity is, however, not directly accessible. An observable that relatively faithfully reproduces the variations of VTH is the Miller plateau during a start-up switching event. The amplitude of this plateau depends on several other parameters, as shown in equation (1) below.

[0056] [Math.l] -r -.......•- .........*.....----- -t- / (A * V

[0057] in which VP is the amplitude of the Miller plateau, ICH the charging current, GFS the transconductance of the transistor, COss the internal output capacitance of the MOSFET, VDS the drain-source voltage, X the parameter translating the "short-channel" effect on the SiC MOSFET and generating an oblique plane evolution of the plateau.

[0058] In order to keep only the influence of VTH on this Miller plateau, we seek to minimize the parasitic contributions on the plateau voltage, therefore to minimize ICH (to minimize ICH / GFs) and to have a very large "dt" (to minimize dVDS / dt), f(X, VDS) being a parameter specific to the transistor on which we cannot act.

[0059] For example, a very slow switching of the transistor is performed, the switching time being then greater than that of the nominal switching at a very high external gate resistance Rg (several kΩ, for example RG = 10 kΩ), whereas the nominal value Rgnom of the external gate resistance RG for "nominal" switching is, for example, approximately 10Ω: the switching slowdown factor is therefore 1000 compared to normal or nominal switching, under low external gate resistance, i.e., fast, with zero load current. The influence of parameters that are not of interest here on the plateau amplitude is then minimized, and the plateau duration is increased to facilitate its reading (for example on an oscilloscope) and / or its extraction.

[0060] To this end, it is sought, for example, that RG (external grid resistance) be at least 100 times greater than its nominal value RGNom-

[0061] In other words, we seek to control the switching of the transistor in a slow or very slow manner, by varying the value of the external gate resistance RG, that is to say the resistance applied to the gate of the transistor (whereas RGint designates the internal gate resistance, intrinsic to the transistor and its technology).

[0062] Thus, during the Miller plateau, the buffer does not supply more charge to the internal grid-source capacitance CGs than the internal grid-drain capacitance CGd draws from it.

[0063] According to one embodiment, the current delivered by the driver to the gate IG can, for example, be increased by the gate-drain current ICgd, which leads to the following condition (the numerical values ​​are specific to the SiC MOSFET component used during testing). (C2M0080120D)):

[0064] [Math.2] Rs » (VD0-VP) / C^dV^ / dt, Let Rg be (20-5) / 100pF . 200V / gs

[0065] We therefore obtain: RG » 750Q; we can therefore take for example RG equal to approximately WkQ.

[0066] The switching is then slowed down by a factor of about 1000 compared to normal switching under a grid resistance RG of 10Q.

[0067] An example of an electronic circuit 100 for gate control of a power transistor 32, for example a SiC MOSFET, is shown in [Fig. 17]. It comprises:

[0068] - on the one hand, the first means (a buffer) 15 of classical control, also named "Fast", which can be put into high impedance via a dedicated control input 17 ("Enable Fast"). These means 15 are associated with the gate resistors RrR2 (Ri for ignition, R2 for blocking), which are low value resistors (e.g. typically 10Q);

[0069] - on the other hand, second means (buffer) 12, also called "Ultra-Slow", connected in parallel with means 15 to the gate of the power transistor 32 to be driven. These means 15 are associated with gate resistors R3-R4, which are larger than Ri and R2 by a factor of, for example, 1000 (R3 and R4 have a value of 1000 in this example). The power supplies of these two means 12, 15 (VDdx and VSsx) can be adjusted independently of each other.

[0070] Figure 17 represents a multi-buffer architecture comprising the means or circuits 12, 15, connected in parallel, for close electronic control of the gate of a power transistor 32, for example a transistor in a power converter as illustrated in Figures 15A and 15B. This figure highlights the dedicated control channel (comprising the means 12 and the resistors R3 and R4) for measuring and monitoring VTH (VGSTh) to track the health status of the transistor.

[0071] A device according to the invention, for example that of [Fig.17], is applicable as well to a measurement on a "high side" component (for example transistor 42 of [Fig.15A]), as on a "low side" component (for example transistor 422 of [Fig.15A]).

[0072] Figure 18 shows an example of the timing diagrams for controlling the device in Figure 17, with the "ultra-slow" mode activated when the "fast" mode is inhibited, and vice versa. A measurement according to the invention can be performed when the "ultra-slow" mode is activated.

[0073] The inventors observed that VGS (represented in [Fig. IC]) corresponds to the hollow appearing after Miller's set.

[0074] This dip appears at low drain-source voltage VDS (represented in Figure IB): in the region of strong non-linearity of the internal drain-gate capacitance CGd (represented in [Fig. 1A]), from an instant tb. This strong capacitance variation then generates a charge pumping effect from the gate to the drain, thus creating a dip on VGS through the strong external gate resistance (here: lOkQ), a dip which is visible in [Fig. IC].

[0075] This dip appears at time tb, corresponding to the end of the switching dVDS / dt, when CGd becomes strongly non-linear. The electrical charges thus drawn from the gate to the drain discharge CGS and contribute to decreasing VGS. On the other hand, the transistor's gate driver injects charges towards the gate through the external gate resistor. These two opposing phenomena compete, and the contribution from the gate driver regains dominance when CGS stops varying, allowing the gate charging and thus the switching to resume and continue.

[0076] Tests were conducted at a reduced VDd voltage (control circuit supply voltage). These tests demonstrate the impact of a reduced contribution from the control circuit's charge input on the dip phenomenon mentioned above. It appears that the minimum value of the dip tends towards the intrinsic threshold value VTh. This is explained by the fact that at the end of the plateau, at the beginning of the dip, the current ICGd drawn by CGD from the gate to the drain passes through the transistor channel, the formation of which depends on the gate bias VGS. As ICGD discharges the gate, the channel narrows (pinches), and limits the current that can pass through the channel: this slows down the phenomenon and lengthens the duration of the dip.

[0077] This is valid, and visible at reduced VDD, because the driver injects little charge into the gate, which allows the trough voltage to approach, to touch the gate voltage VTH of the transistor at the channel conduction limit, as illustrated in Figures 2A and 2B; in these figures, the evolution of VGS ([Fig.2A]; in this figure, SMU means "source measurement unit") and VDS ([Fig.2B]) for various values ​​of VDD, between 10 V and 20 V as shown in these figures.

[0078] Consequently, the grid voltage dip appears as a reliable, novel, low-noise indicator corresponding to a VTH image. The value of this dip can be defined as the difference between the Miller plateau level and the absolute minimum value of the dip. Suitable conditions for measuring or estimating the grid voltage dip are preferred, ideally with:

[0079] - a slower boot switching, for example about 1000 times, compared to a conventional ignition; this can be achieved by using a grid resistor (RG) external 1000 times greater than the nominal case;

[0080] - a zero charging current during this initiation; Figures 15A to 16 illustrate Implementations for monitoring the health status of a transistor within a three-phase power converter, and for enabling measurement at zero load current. Figures 15A-15B illustrate simultaneous ultra-slow firing on the 3 low-side transistors (15A) or on the 3 high-side transistors (15B) within a three-phase power inverter. Such a control strategy prevents current flow in the fired transistors. [Fig. 16] illustrates the use of a current sensor 43 on one phase of a motor to synchronize the ultra-slow measurement around the zeroing of the load current;

[0081] - a reduced supply voltage of the driver 12 (VDDi in [Fig.17]), for example in less than or equal to 10V; whereas a nominal or "normal" voltage of driver 12, for example between 15V and 20V, is higher than this reduced value. Indeed, as explained above, at a reduced supply voltage VDo, the minimum value of the dip tends towards the intrinsic threshold value of the transistor. In other words, the dip, an indicator of health, then approaches VTh and thus the physical phenomenon of charge trapping; this indicator then becomes all the more relevant. But this requires an adjustable supply voltage VDd, which means the use of additional components: the implementation is therefore more complex.

[0082] At nominal VDD (“20V; in this case, VDd is not reduced”), the variations of this dip (represented as a function of time in [Fig.3] on which curve I represents these variations for a new transistor, with healthy oxide and curve II for a stressed transistor, with aged oxide) follow relatively the variations of VTH and thus also give an indication of the state of degradation of the gate oxide layer.

[0083] Analog implementations of trough tracking on the grid voltage are proposed below.

[0084] A first implementation, with direct sampling, is based on a derivative of V GS: the amplitude of the plateau on VGs will increase over time according to the trapping state of the oxide layer but its overall dynamics will remain unchanged, as shown in [Fig.3], which allows comparison of VGs waveforms between a new component with healthy oxide (curve I) and a stressed component with aged oxide (after 24 hours of stress at VGS = 35 V, curve II).

[0085] The zeroing of the derivative of VGS thus appears as a means of detecting the appearance of the trough. Comparing this derivative to a threshold, preferably adjustable, allows the control signal for a sample-and-hold circuit to be generated for VGS. This method makes it possible to sample and store the value of VGS at the instant its derivative intersects with a threshold.

[0086] A diagram of a circuit or device 10 implementing this solution is given in [Fig. 4], on which:

[0087] - means 8 (control isolator, optocoupler) isolate the commands from digital control of the rest of the electronic circuit; these means 8 interface or link between the digital control commands and the electronic components of the circuit; they provide the "ultra slow" priming control signal; the control signal to activate these means is sent by digital control means, for example an FPGA;

[0088] - means 12 (or buffer) control the transistor under test 32 and allow to prime it slowly; the gate control signal comes from means 12, passes through the external gate resistor 12', the VGs signal which comes out of 12' contains information on the health status of the transistor under test;

[0089] - means 34 forming an instrumentation amplifier (these means 34 allowing to copy and isolate the signal), which allow VGS to be read, reconstructed, and processed via impedance matching; indeed, under such a high gate resistance (10kΩ), even the slightest gate leakage path becomes non-negligible. A simple resistive voltage divider to capture VGS is therefore not feasible here due to current leakage at low total resistance of such a divider, and its sensitivity to noise at high resistance;

[0090] - a derivative calculation stage 14 is then applied to the image of VGS obtained in exit of resources 12;

[0091] - a 16-stage comparison to a threshold allows the derivative to be compared to a pre-specified threshold determined ;

[0092] - means 18 forming a seesaw allow to generate and maintain at a certain state a control front from the result of comparing the threshold and the derivative.

[0093] The output of means 18, as well as the VGS data obtained from the output of means 12, are applied to the input of a sample-and-hold circuit 20. The value(s) of Vcreux can then:

[0094] - to be used as an index of the evolution of the aging of transistor 32:

[0095] - and / or be digitized by an analog-to-digital converter (ADC) to be processed and possibly stored in a digital control unit (of the FPGA type for example);

[0096] - to be compared over time to track the evolution of the health status of transistor 32 tested.

[0097] Examples of implementation of the various means 12-23 are given in figures 11 and 12 and below, in connection with these figures 11 and 12.

[0098] A simulation using "LTspice" software using ideal components (which come directly from the LTspice library provided with the software) was carried out.

[0099] The results of this simulation are illustrated in Figures 5A and 5B. An "Ultra-Slow" firing under a very high external gate resistance RG (for example, 1000 times greater than the normal or nominal resistance, which generally has a value around 10Ω), R3, R4 (as already explained above) respecting the previously established condition (factor, for example, 1000 already mentioned above), for example RG = 10kΩ, was carried out on a test bench. The load curve of VGS (whose time evolution is shown in [Fig. 5A]) is extracted from the oscilloscope as a point file and then imported into the simulation software as a voltage source profile. [Fig. 5B] represents the time evolution of the derivative of VGS (derivative obtained at the output of the differentiator stage 14).

[0100] As shown in Figures 5A and 5B, comparing the derivative of VGS to a 0V threshold carries a risk of false triggering and the generation of unwanted edges, particularly in the plateau region. Therefore, a negative safety threshold is chosen (for example, -0.6V). This establishes a safety margin relative to the 0V threshold, thus preventing false triggering and ensuring clean intersections with the negative portion of the derivative. This negative portion corresponds to the beginning of the trough in the decreasing region of VGS.

[0101] The waveform 21 at the output of the sample-and-hold circuit 23 (EB) is shown in figures 6A and 6B. Its output performs a value hold (around the trough) when it receives a control edge on its clock input.

[0102] It therefore appears that the output of the sample-and-hold circuit 23 is maintained at a voltage value close to that of the trough. This "direct" method has the advantage of relying on a small number of components. However, in order to obtain the most accurate measurement possible, the aim is to ensure that the control edge of the sample-and-hold circuit appears at the minimum of the trough. This is achievable by adjusting the threshold and the bandwidth of the differentiator stage 14.

[0103] Another implementation, with trough memorization, relies on automatic memorization of the minimum trough value. It is shown in Figures 7A-9.

[0104] Figure 7A schematically represents means 22a for storing the dip. These means comprise two diodes 221, 223 arranged in reverse and in parallel, and a capacitor 224 for storing the value of the dip.

[0105] Initially ([Fig.7A], [Fig.7Al]), the representative signal of VGS charges the capacitance 224, until the end of the Miller plateau.

[0106] In a second step ([Fig.7B], [Fig.7Bl]), the voltage across the capacitor 224 decreases, which corresponds to the dip that follows the Miller plateau.

[0107] Finally, in a 3rd step ([Fig.7C], [Fig.7Cl]), the capacitance 224 is recharged through the direct diode 221 during the rise of VGS.

[0108] In other words, means 22a do not allow the correct memorization of the hollow because the 224 CMEM memory capacity is recharged through the direct diode 221 during the VGS ascent.

[0109] Therefore, as illustrated in [Fig. 8], means 22 comprising means forming a switch 226 upstream of the forward diode 221 are used; these means 226 allow the circuit to be dynamically opened to prevent this undesirable recharging of the capacitance 224 CMEM and so that the voltage across the latter is maintained (within leakage limits) at the trough value. As can be understood from [Fig. 711], the control for opening the means 226 occurs preferably before zone 3 and as long as VGs > Vtrough-

[0110] As shown in [Fig. 9], the switch opening command will be generated by the flip-flop 18 of the trigger chain. [Fig. 8] shows the contents of the means 22 forming the trough storage block of [Fig. 9]. The other elements of this [Fig. 9] have already been described above, with reference numeral 32 again designating the transistor under test.

[0111] In this configuration, the input of the sample-and-hold circuit 23 (EB) is now the voltage of the CMem memory capacitor, which corresponds to the minimum value of the dip. Compared to the "direct" solution described above in relation to [Fig. 4], an analog pre-processing stage is added (for storing the dip) and makes the dip value available as an input to the sample-and-hold circuit 23. Once the dip value is stored by CMem, the sample-and-hold circuit 23 receives a blocking edge, and its output is held at a value as close as possible to the true dip value.

[0112] The diodes 221, 223 used in the trough memorization stage are preferably op-amp (operational amplifier) ​​compensated diodes to eliminate their threshold voltage.

[0113] The simulation results in Figures 10A–10C show that the CMEM voltage correctly replicates VGS and remains at the trough value. As seen in [Fig. 1OB], the switch opening command (to prevent VMEM from rising) is sent at the beginning of the trough. A delay (see [Fig. 1OA]) can be introduced (analogously, for example with an RC-type delay circuit, or digitally (flip-flops and digital control element) at the level of the digital control element) on the same signal that is sent to the hold port of the sample-and-hold circuit 23 so that VMEM has time to decrease to VCrough-

[0114] Figure 11 shows a detailed analog implementation of an analog dip tracking circuit 10 on VGS. Figure 12 shows a detailed analog implementation of an analog dip tracking circuit 20 on VGS, with dip value storage.

[0115] In these figures 11 and 12:

[0116] - the means 18 forming a toggle allow the control edge to be generated the sample hold 23 ([Fig. 11]), the control order of the analog switch of the dip storage block 22 ([Fig. 12]) and the control edge of the "Sample_Ready" signal (figures 11, 12) through an isolator 27 indicating to a digital control unit (for example an FPGA) that it can start the acquisition of the dip value extracted at the output of the chain;

[0117] - The pit tension extraction chains are illustrated with a buffer 12 of 32 high grid resistance power MOSFET grid control;

[0118] - a controlled and regulated current source 25 (2mA) allows for the realization of a priming, in order to be able to accurately measure CGD, which is proportional to the duration of the plateau;

[0119] - the state of the means 18 forming a toggle switch is initialized from the signal of the means 8 Ultra-Slow priming;

[0120] - the derivative comparator stage 16 is equipped with hysteresis means to avoid possible rebounds;

[0121] - reference 32 designates a transistor under test;

[0122] - reference numeral 34 designates an amplifier disposed at the input of the means 14 forming comparator.

[0123] An implementation of the measurement of the trough voltage according to the invention within a Pulse Width Modulation (PWM) control frame is described below in relation to figures 13A-14B.

[0124] Under no-load conditions, with zero load current, an "Ultra-Slow" measurement (according to the invention) of the trough voltage under high gate resistance can be performed intermittently within a PWM frame during active high-duty-ratio ignition switching to allow sufficient time for the slowed charging of VGs and the trough measurement. An example of an Ultra-Slow measurement on a high-side component is given in Figure 13A.

[0125] To perform a measurement on a low-side component ([Fig.13B]), half a modulation period is expected so that the duty cycle of the "low-side" is at its maximum.

[0126] To minimize the measurement time and limit the impact on the PWM control frame, a measurement using switched grid resistors is shown in Figures 14A-14B. With this method, only the area of ​​interest, the plateau and the trough, is slowed down and lengthened to facilitate measurement and extraction, and also to increase the signal-to-noise ratio of this area. Such "Ultra-Slow" switching (according to the invention), referred to as condensed switching, makes it possible to perform a trough measurement within a single switching period (for example, if the switching frequency fDEC = 20 kHz, then the period TDEC = 50 ps, ​​the measurement can be performed in a maximum of 20 ps, ​​see Figures 6A-7C).

[0127] Figures 15A, 15B and 16, discussed below, illustrate implementations of health status monitoring within a three-phase power converter, allowing measurement at zero load current.

[0128] In connection with figures 15A - 15B, an application of a measurement according to the invention to common mode control on a three-phase inverter (at zero speed) is presented.

[0129] A trigger switching operation according to the invention (called "Ultra-Slow") is performed simultaneously on the three "low-side" MOSFETs 422, 424, 426 ([Fig. 15A]) and then on the three "high-side" MOSFETs 421, 423, 425 ([Fig. 15B]). This allows the trigger switching to be performed without a load current that would interfere with the dip measurement. It also allows information on the health status of three MOSFETs to be obtained at the same time.

[0130] More specifically, when a motor 40 is connected to an inverter 42 (comprising transistors 42r426), the current in the phases of the motor can be canceled so as to reduce to the case explained above in relation to figures 13A - 14B.

[0131] To achieve this, a zero-sequence (or common-mode) control is applied to the transistors 42r426 so as to cancel all the line voltages across the motor 40 and to reduce the phase current to zero. The motor has previously been brought to a standstill. As soon as the currents are canceled, a procedure identical or similar to that explained above with reference to Figures 13A - 14B can be implemented; a device such as the one described above, for example with reference to Figures 11 or 12, is then applied to each of the transistors 42r426.

[0132] Figure 16 shows an application of monitoring according to the invention to an "Ultra-Slow" switching around the zero crossing of the load current: in the case of a running motor 40 and with currents present in the phases, it is possible to perform the "Ultra-Slow" switching as described above by synchronizing this procedure with the zero crossing of the current: a measurement according to the invention (called "ultra-Slow") is synchronized with a current sensor 43. Figure 19 represents an implementation of the synchronization of a measurement according to the invention, as described above, with such a current sensor 43. The signal from the latter is compared to a threshold by comparison means 45, then a control edge is generated by means 47 and sent to digital control means 49. The other components 8, 12 of this figure have already been described above, as has the measuring chain 10 ([Fig. 11]) or 20 ([Fig. 12]).Reference 32 still designates the transistor under test.

Claims

Demands

1. A device for monitoring the health status of a power MOSFET transistor (32) comprising: - first means (8, 12) for applying a trigger voltage (VGS) to a power MOSFET transistor, these means (8, 12) comprising at least one resistor (R3, R4), forming an external gate resistance, of at least 1000kΩ; - means (12-22) for measuring the trough of the gate voltage (VGS) which follows the Miller plateau.

2. Device according to claim 1, comprising a stage (14) for detecting the cancellation of the derivative of the grid voltage (VGS).

3. Device according to claim 2, comprising a comparison stage (16), for comparing the value of the derivative of VGS to a comparison threshold value.

4. Device according to claim 3, the threshold value for comparison being negative.

5. Device according to any one of claims 3 or 4, the comparison stage (16) comprising hysteresis-forming means (161).

6. Device according to any one of claims 1 to 5, comprising means (23, 22, 22a) for memorizing a value of said hollow.

7. Device according to claim 6, comprising at least one sampler-blocker (23) for maintaining said hollow value.

8. Device according to any one of claims 6 or 7, means for memorizing a minimum value of said hollow comprising a capacity (224).

9. Device according to claim 8, the means for memorizing a minimum value of said hollow comprising means (226) forming a switch.

10. Device according to any one of claims 1 to 9, further comprising second means (15) for applying a voltage to a power MOSFET transistor (32), these means comprising at least one resistance (Ri, R2) of low value compared to said resistance forming external gate resistance (R3, RJ).

11. Device according to claim 10, further comprising control means for the first means (8, 12) and the second means (15) with Pulse Width Modulation (PWM).

12. A device according to any one of claims 1 to 9, further comprising means (45, 47, 49) of synchronization with a current sensor (43).

13. Method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN type or of a MOSFET-Si type power transistor, implementing a device according to one of the preceding claims.

14. Power converter or module comprising several power transistors (42r426) and at least one device according to any one of claims 1 to 12 coupled to at least one of the transistors.

15. Aircraft comprising at least one converter or power module according to claim 14.

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