Circuit suitable for implementing stress testing of power transistor gates

Abstract

Circuit suitable for implementing stress testing of power transistor gates The present description relates to a power electronic circuit (100) comprising at least one power transistor (102, 106) whose gate is coupled to a control circuit (104, 108) and whose source is coupled to a first contact pad (114, 124), in which the control circuit (104, 108) is coupled to a second contact pad (116, 126), and in which the first and second contact pads (114, 116, 124, 126) are configured to be decoupled from each other when the power electronic circuit (100) is in a stress testing configuration of the gate of the power transistor (102, 106) and configured to be coupled to each other when the power transistor (102, 106) and the control circuit are in a stress testing configuration. command (104, 108) are encapsulated. Figure for abstract: Fig. 1

Description

Title of the invention: Circuit adapted for the implementation of stress testing of power transistor gates Technical field

[0001] The present description relates generally to the field of power electronic circuits comprising power transistors, in particular that of DC-DC converters, or direct-direct converters. Prior art

[0002] When producing power circuits such as DC-DC converters, the power transistors of these circuits (for example forming the switching cells in the case of a converter) are tested in order to discard circuits comprising transistors that do not comply with the required specifications and to use those comprising transistors that comply with these specifications. One of these tests, called a gate stress test, consists of applying a high voltage, called a stress voltage, between the gate and the source of the power transistor subjected to this test. For example, this stress voltage can be equal to 11 V and can be applied for a duration of 200 ms. For a PMOS transistor, the stress voltage applied between the gate and the source of the transistor is negative to avoid PBTI (positive bias temperature instability) type degradation.

[0003] This stress voltage is much higher than the nominal supply voltage, for example 5V or 7V, applied during “conventional” use in switching, or in operation, of these transistors. This stress test of the gates of the power transistors makes it possible to identify the presence of defects in the tested transistors, for example in their gate oxide, which can generate significant leakage currents after a short time of use of the transistors (for example after approximately one year). Leaks in transistors exhibiting such defects therefore appear during the stress test and the power circuits comprising these defective transistors can thus be identified and discarded without waiting for the appearance of such leaks during their use.

[0004] During stress testing, other circuit components coupled to the connections to which the stress voltages are applied, including components of the power transistor control circuits, are protected so that they are not destroyed by the stress voltages. For example, in the case of a switching circuit comprising a CMOS inverter, this protection can be achieved by adding an additional transistor coupled to an electrical resistor in inverter output.

[0005] Additionally, dedicated internal contact pads are used during transistor stress testing to measure leakage currents, as well as for applying the stress voltage for the power transistors on the low-side of the circuit.

[0006] Finally, because the drains of the power transistors on the low side and the high side of the circuit are coupled to the same contact pad on which the output signal of the power transistors is recovered, it is not possible to simultaneously test the power transistors on the high side and those on the low side of the power circuit. Summary of the invention

[0007] There is a need to propose a solution that does not have at least some of the drawbacks of existing solutions.

[0008] One embodiment overcomes all or part of the drawbacks of the known solutions and proposes a power electronic circuit comprising at least one power transistor whose gate is coupled to a control circuit and whose source is coupled to a first contact pad, in which the control circuit is coupled to a second contact pad, and in which the first and second contact pads are configured to be decoupled from each other when the power electronic circuit is in a stress test configuration of the gate of the power transistor and configured to be coupled to each other when the power transistor and the control circuit are encapsulated.

[0009] According to one embodiment, the power transistor and the control circuit are high-side components of the power electronic circuit, and the first and second contact pads are configured so that different supply electrical potentials are applied to each of them when the power electronic circuit is in the stress test configuration of the gate of the power transistor.

[0010] According to one embodiment, the power transistor and the control circuit are low-side components of the power electronic circuit, and the first and second contact pads are configured so that different reference electrical potentials are applied to each of them when the power electronic circuit is in the stress test configuration of the gate of the power transistor.

[0011] According to one embodiment:

[0012] - the power transistor, called the first power transistor, and the circuit of control, called the first control circuit, are high-side components of the power electronic circuit, and

[0013] - the electronic power circuit further comprises a second transistor of power whose gate is coupled to a second control circuit and whose source is coupled to a third contact pad, the second control circuit being coupled to a fourth contact pad, the second power transistor and the second control circuit corresponding to low-side components of the power electronic circuit, and

[0014] - the first and second contact pads are configured so that potentials different power supply voltages are applied to each of them when the power electronic circuit is in a stress test configuration of the gates of the first and second power transistors, and

[0015] - the third and fourth contact pads are configured to be decoupled from each other of the other and for different reference electrical potentials to be applied to each of them when the power electronic circuit is in the stress test configuration of the gates of the first and second power transistors, and configured to be coupled to each other when the first and second power transistors and the first and second control circuits are encapsulated.

[0016] According to one embodiment, the drain of the first power transistor is coupled to a first switching pad and the drain of the second power transistor is coupled to a second switching pad, and the first and second switching pads are configured to be decoupled from each other when the power electronic circuit is in the stress test configuration of the gates of the first and second power transistors and configured to be coupled to each other when the first and second power transistors and the first and second control circuits are encapsulated.

[0017] According to one embodiment, the control circuit, or each of the first and second control circuits, comprises a CMOS inverter whose output is coupled to the gate of the power transistor or of one of the first and second power transistors, and / or the power transistor, or each of the first and second power transistors, corresponds to a MOSFET.

[0018] According to one embodiment, the power electronic circuit includes an encapsulation element.

[0019] According to one embodiment, the power electronic circuit further comprises a first electrical connector electrically coupling the first and second contact pads together, and, when the power electronic circuit comprises third and fourth contact pads, a second electrical connector coupling the third and fourth contact pads together.

[0020] According to one embodiment, the electronic power circuit comprises the first and second switching pads and a third electrical connector coupling the first and second switching pads together.

[0021] According to one embodiment, the electronic power circuit corresponds to a DC-DC converter.

[0022] A method for producing and encapsulating at least one power electronic circuit is also proposed, comprising at least the following steps:

[0023] - production of the electronic power circuit as previously described;

[0024] - implementation of a stress test of the gate(s) of the transistor(s) of power of the power electronic circuit;

[0025] - encapsulation of the power transistor(s) and the control circuit(s) of the power electronic circuit.

[0026] According to one embodiment, the stress test of the gate(s) of the power transistor(s) comprises a measurement of a leakage current on the first contact pad and / or on the third contact pad.

[0027] According to one embodiment, the encapsulation of the power transistor(s) and the control circuit(s) comprises a production of a first electrical connector electrically coupling together the first and second contact pads of the power electronic circuit, and, when the power electronic circuit comprises third and fourth contact pads, a production of a second electrical connector coupling together the third and fourth contact pads of the power electronic circuit.

[0028] According to one embodiment, the encapsulation of the power transistor(s) and the control circuit(s) further comprises a production of a third electrical connector coupling together the first and second switching pads of the power electronic circuit. Brief description of the drawings

[0029] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0030] - [Fig.l] schematically represents an example of a part of an electrical circuit power electronics according to a particular embodiment, in a stress test configuration of the gates of the power transistors of the circuit;

[0031] - [Fig.2] schematically represents an example of a part of an electrical circuit power electronics according to a particular embodiment, after interconnection of the contact pads of the circuit;

[0032] - [Fig.3] schematically represents an electronic power circuit whose components are encapsulated, according to a particular embodiment. Description of the embodiments

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, various elements and components of the power electronic circuit are not detailed. Those skilled in the art will be able to produce these elements in detail from the description given here.

[0035] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected or coupled to each other, this means that these two elements can be connected or be linked via one or more other elements. In addition, the term "coupled" is used here to designate an electrical coupling between several electrical and / or electronic elements (components, circuits, etc.). The same applies to the term "uncoupled".

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0037] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0038] A power electronic circuit 100 according to a particular embodiment is described below in connection with [Fig.l]. Only a portion of the elements and components of the circuit 100 are described below and visible in [Fig.l].

[0039] The circuit 100 comprises electrical and / or electronic elements or components of a high-side portion of the circuit 100, to which at least one electrical supply potential of the circuit 100 is intended to be applied. The circuit 100 also comprises electrical and / or electronic elements or components of a low-side portion of the circuit 100, to which at least one reference electrical potential, serving for example as ground, of the circuit 100 is intended to be applied.

[0040] In the exemplary embodiment described, the circuit 100 comprises one or more first power transistors 102, as well as one or more first control circuits 104 forming part of the high side of the circuit 100. The first control circuits 104 are configured to control the switching of the first power transistors 102. When the circuit 100 comprises several first power transistors 102, the gate of each of these first power transistors 102 is coupled to the output of a first control circuit 104 dedicated to the control of this transistor.

[0041] The circuit 100 also comprises one or more second power transistors 106, and one or more second control circuits 108 forming part of the low side of the circuit 100. The second control circuits 108 are configured to control the switching of the second power transistors 106. When the circuit 100 comprises several second power transistors 106, the gate of each of these second power transistors 106 is coupled to the output of a second control circuit 108 dedicated to the control of this transistor.

[0042] In [Fig. 1], a single first power transistor 102, a single first control circuit 104, a single second power transistor 106 and a single second control circuit 108 are shown. The characteristics described below for each of these components may also apply to the other power transistors and control circuits of the circuit 100 not shown in [Fig.l].

[0043] In the described embodiment, the power transistors 102, 106 and the transistors of the control circuits 104, 108 correspond to MOSFETs. Alternatively, other types of transistors may be used to form the power transistors 102, 106 and / or the transistors of the control circuits 104, 108.

[0044] In the example of [Fig.l], the first power transistor 102 corresponds to a PMOS transistor whose gate is coupled to the first control circuit 104. More particularly, in the exemplary embodiment described, the gate of the first power transistor 102 is coupled to the output of a first CMOS inverter 109 of the first control circuit 104 (this output being coupled to the drains of the NMOS and PMOS transistors of the first CMOS inverter 109). In the example of [Fig.l], the input of the first CMOS inverter 109 (which is coupled to the gates of the NMOS and PMOS transistors of the first CMOS inverter 109) is coupled to two inverters 110, 112 coupled in series with each other.

[0045] The source of the first power transistor 102 is coupled to a first contact pad 114, and the first control circuit 104 is coupled to a second contact pad 116. In the example of [Fig.l], it is the source of the PMOS transistor of the first CMOS inverter 109 which is coupled to the second contact pad 116. In this example, the source of the NMOS transistor of the first CMOS inverter 109 is coupled to a floating ground 118. Finally, the drain of the first power transistor 102 is coupled to another contact pad called first switching pad 120.

[0046] In the example of [Fig. 1], the second power transistor 106 corresponds to an NMOS transistor whose gate is coupled to the second control circuit 108. More particularly, in the exemplary embodiment described, the gate of the second power transistor 106 is coupled to the output of a second CMOS inverter 119 of the second control circuit 108 (this output being coupled to the drains of the NMOS and PMOS transistors of the second CMOS inverter 119). In the example of [Fig. 1], the input of the second CMOS inverter 119 (which is coupled to the gates of the NMOS and PMOS transistors of the second CMOS inverter 119) is coupled to an inverter 122.

[0047] The source of the second power transistor 106 is coupled to a third contact pad 124, and the second control circuit 108 is coupled to a fourth contact pad 126. In the example of [Fig.l], it is the source of the NMOS transistor of the second CMOS inverter 119 which is coupled to the fourth contact pad 126. In this example, the source of the PMOS transistor of the second CMOS inverter 119 is coupled to a floating supply electrical potential 128. Finally, the drain of the second power transistor 106 is coupled to another contact pad called the second switching pad 130.

[0048] In the example of [Fig.l], the components of the circuit 100 are not yet encapsulated. The circuit 100 is therefore in a configuration in which the connections between the pads 114 and 116, between the pads 124 and 126, and between the pads 120 and 130 are not yet made, and therefore in a configuration in which stress tests of the gates of the power transistors 102, 106 can be implemented. In this test configuration, the first and second contact pads 114, 116 are decoupled from each other.Thus, during stress tests of the power transistors, different electrical supply potentials can be applied to each of the first and second contact pads 114, 116, which makes it possible to apply to the first control circuit 104 a lower electrical supply voltage than the stress voltage applied between the gate and the source of the first power transistor 102, and thus avoid damage to the first control circuit 104 which would be due to the application of the stress voltage to the first control circuit 104.

[0049] For example, during a stress test of the first power transistor 102, a first electrical supply potential, for example equal to 11 V, can be applied to the first contact pad 114, and a second electrical supply potential lower than the first electrical supply potential, for example equal to 5 V, can be applied to the second contact pad 116. The electrical potential of the floating ground 118 can be equal to 0 V. In this case, by applying a electrical potential corresponding to a logic '1' at the input of the inverter 110, for example equal to 5 V, the electrical potential obtained at the output of the first CMOS inverter 109 and applied to the gate of the first power transistor 102 is zero. Another electrical supply potential equal to the first electrical potential can be applied to the first switching pad 120 during the stress test of the first power transistor 102.

[0050] Similarly, in this stress test configuration, the third and fourth contact pads 124, 126 are decoupled from each other. Thus, during stress testing of the power transistors, different reference electrical potentials can be applied to each of the third and fourth contact pads 124, 126, which makes it possible, as for the components on the high side of the circuit 100, to apply to the second control circuit 108 a lower electrical supply voltage than the stress voltage applied between the gate and the source of the second power transistor 106.

[0051] For example, during a stress test of the second power transistor 106, a first reference electrical potential equal to -6 V may be applied to the third contact pad 124, and a second reference electrical potential greater than the first reference electrical potential, for example equal to 0 V, may be applied to the fourth contact pad 126. The floating supply electrical potential 128 may be equal to 5 V. In this case, by applying an electrical potential corresponding to a logic '1' at the input of the inverter 122, for example equal to 5 V, the electrical potential obtained at the output of the second CMOS inverter 119 and applied to the gate of the second power transistor 106 is equal to 5 V. Another reference electrical potential equal to the first reference electrical potential may be applied to the second switching pad 130 during the stress test of the second power transistor 106.

[0052] In this test configuration as shown in [Fig. 1], the first and second switching pads 120, 130 are decoupled from each other. Thus, it is possible to simultaneously perform the stress tests of the first and second power transistors 102, 106.

[0053] During stress testing of the power transistors 102, 106, a leakage current from the first power transistor 102 may be measured on the first contact pad 114, and / or a leakage current from the second power transistor 106 may be measured on the third contact pad 124. Alternatively, it is possible for the first power transistor 102 to include a Kelvin source connection allowing the measurement of a possible leakage current, with in this case the output of the first CMOS inverter 109 placed in a high-impedance configuration during the stress testing of this transistor, and / or for the second power transistor 106 has a Kelvin source connection allowing the measurement of a possible leakage current, with in this case the output of the second CMOS inverter 119 put in a high-impedance configuration during the stress test of this transistor.

[0054] The implementation described above of the stress tests of the gates of the power transistors 102, 106 makes it possible to highlight whether one or more of these power transistors 102, 106 have defects generating leakage currents. In the presence of such defects, the circuit 100 is discarded and is not used. Thanks to the structure of the circuit 100, the stress tests of the power transistors 102, 106 can be implemented without subjecting the control circuits 104, 108 to the high stress voltages used during these tests, thus protecting them from these voltages without having to resort to additional components dedicated to the protection of the control circuits 104, 108.Furthermore, due to the fact that the first and second switching pads 120, 130 are not coupled to each other during stress testing of the power transistors 102, 106, these transistors can be tested at the same time during the same stress testing phase. Furthermore, with this configuration of the circuit 100, it is not necessary to provide contact pads dedicated solely to the measurement of possible leakage currents and / or the application of stress voltages. Finally, due to the absence of electronic components dedicated to the protection of the control circuits 104, 108, the performance of the circuit 100, in particular its operating speed, is not impaired by the presence of these protection components.

[0055] The circuit 100 is also suitable for implementing stress tests on the drains of the power transistors 102 and 106. Furthermore, due to the disconnection of the contact pads 114 and 116, 124 and 126, and 120 and 130 when the components of the circuit 100 are not yet encapsulated, it is possible to implement these tests in parallel on the power transistors 102 and 106.

[0056] After the implementation of the stress tests of the gates of the power transistors 102, 106, the components of the circuit 100 are encapsulated. In the exemplary embodiment described here, this encapsulation is carried out so as to couple together:

[0057] - the first and second contact pads 114, 116;

[0058] - the third and fourth contact pads 124, 126;

[0059] - the first and second switching pads 120, 130.

[0060] [Fig. 2] schematically represents the components of the circuit 100 after the interconnection of the contact pads 114, 116, 120, 124, 126 and 130 carried out during the encapsulation of the components of the circuit 100. In addition to the components of the circuit 100 previously described, the circuit 100 also comprises analog components and digital logic components designated together by the reference 202 for the high side of the circuit 100 and by the reference 204 for the low side of the circuit 100. output signals from these components are sent to the input of the control circuits 104, 108 through level converter circuits 206, 208, making it possible in particular to control the control circuits 104, 108. These components are also encapsulated.

[0061] The implemented encapsulation forms a first electrical connector 210 coupling the first and second contact pads 114, 116 together. The implemented encapsulation also forms a second electrical connector 212 coupling the third and fourth contact pads 124, 126 together. In the example of [Fig. 2], the encapsulation also forms a third electrical connector 214 coupling the first and second switching pads 120, 130 together. Furthermore, in the described embodiment, the implemented encapsulation also forms a fourth electrical connector 216 allowing the application of a reference electrical potential to the first control circuit 104 (through the floating ground 118) and to the components 202, as well as a fifth electrical connector 218 allowing the application of a supply electrical potential to the second control circuit 108 (through the floating supply 118) and on components 204..

[0062] According to an exemplary embodiment, the electrical connectors 210 to 218 are of the DCI (“Direct Copper Interconnection” or direct copper interconnection) type, allowing for connections of low electrical resistance with the pads 114, 116, 120, 124, 126 and 130. The production of such connections between the electrical connectors 210 to 218 and the pads 114 and 116, 124 and 126, and 120 and 130, can be carried out at the scale of a panel, or PLP (“Panel Level Process” or “Panel Level Packaging”).

[0063] As a variant of the embodiment described above, the components of the high side and / or the low side of the circuit 100 could be different from those previously described.

[0064] [Fig. 3] schematically represents an exemplary embodiment in which the power electronic circuit 100 corresponds to a step-down DC-DC converter. In this figure, an encapsulation element 200 of the circuit 100, for example an encapsulation box or any other encapsulation means adapted to the circuit 100, is symbolically represented. The various components other than those previously described are not described in detail.

[0065] The power electronic circuit 100 can be applied in particular to the automotive field.

[0066] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0067] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A power electronic circuit (100) comprising at least one power transistor (102, 106) having its gate coupled to a control circuit (104, 108) and having its source coupled to a first contact pad (114, 124), wherein the control circuit (104, 108) is coupled to a second contact pad (116, 126), and wherein the first and second contact pads (114, 116, 124, 126) are configured to be decoupled from each other when the power electronic circuit (100) is in a stress test configuration of the gate of the power transistor (102, 106) and configured to be coupled to each other when the power transistor (102, 106) and the control circuit (104, 108) are encapsulated.

2. The power electronic circuit (100) of claim 1, wherein the power transistor (102) and the control circuit (104) are high-side components of the power electronic circuit (100), and wherein the first and second contact pads (114, 116) are configured so that different supply electrical potentials are applied to each of them when the power electronic circuit (100) is in the stress test configuration of the gate of the power transistor (102).

3. The power electronic circuit (100) of claim 1, wherein the power transistor (106) and the control circuit (108) are low-side components of the power electronic circuit (100), and wherein the first and second contact pads (124, 126) are configured so that different reference electrical potentials are applied to each when the power electronic circuit (100) is in the stress test configuration of the gate of the power transistor (106).

4. The power electronic circuit (100) of claim 1, wherein: - the power transistor (102), called the first power transistor, and the control circuit (104), called the first control circuit, are high-side components of the power electronic circuit (100), and - the power electronic circuit (100) further comprises a second power transistor (106) whose gate is coupled to a second control circuit (108) and whose source is coupled to a third contact pad (124), the second control circuit (108) being coupled to a fourth contact pad (126), the second power transistor (106) and the second control circuit (108) corresponding to low-side components of the power electronic circuit (100), and - the first and second contact pads (114, 116) are configured so that different supply electrical potentials are applied to each of them when the power electronic circuit (100) is in a stress test configuration of the gates of the first and second power transistors (102, 106), and - the third and fourth contact pads (124,126) are configured to be decoupled from each other and to have different reference electrical potentials applied to each of them when the power electronic circuit (100) is in the stress test configuration of the gates of the first and second power transistors (102, 106), and configured to be coupled to each other when the first and second power transistors (102, 106) and the first and second control circuits (104, 108) are encapsulated.,

5. The power electronic circuit (100) of claim 4, wherein the drain of the first power transistor (102) is coupled to a first switching pad (120) and the drain of the second power transistor (106) is coupled to a second switching pad (130), and wherein the first and second switching pads (120, 130) are configured to be decoupled from each other when the power electronic circuit (100) is in the stress test configuration of the gates of the first and second power transistors (102, 106) and configured to be coupled to each other when the first and second power transistors (102, 106) and the first and second control circuits (104, 108) are encapsulated.

6. A power electronic circuit (100) according to any preceding claim, wherein the control circuit (104, 108), or each of the first and second control circuits (104, 108), comprises a CMOS inverter (109, 119) whose output is coupled to the gate of the power transistor (102, 106) or of one of the first and second power transistors (102, 106), and / or wherein the power transistor (102, 106), or each of the first and second power transistors (102, 106), corresponds to a MOSFET.

7. A power electronic circuit (100) according to any preceding claim, including an encapsulation element (200).

8. The power electronic circuit (100) of claim 7, further comprising a first electrical connector (210) electrically coupling the first and second contact pads (114, 116) together, and, when the power electronic circuit (100) comprises third and fourth contact pads (124, 126), a second electrical connector (212) coupling the third and fourth contact pads (124, 126) together.

9. A power electronic circuit (100) according to claim 8, comprising the first and second switching pads (120, 130) and a third electrical connector (214) coupling the first and second switching pads (120, 130) together.

10. Power electronic circuit (100) according to claim 9, corresponding to a DC-DC converter.

11. Method for producing and encapsulating at least one power electronic circuit (100), comprising at least the following steps: - producing the power electronic circuit (100) according to any one of claims 1 to 6; - carrying out a stress test of the gate(s) of the power transistor(s) (102, 106) of the power electronic circuit (100); - encapsulating the power transistor(s) (102, 106) and the control circuit(s) (104, 108) of the power electronic circuit (100).

12. The method of claim 11, wherein the stress testing of the gate(s) of the power transistor(s) (102, 106) comprises measuring a leakage current on the first contact pad (114) and / or on the third contact pad (124).

13. A method according to any one of claims 11 or 12, wherein the encapsulation of the one or more power transistors (102, 106) and of the control circuit(s) (104, 108) comprises an embodiment of a first electrical connector (210) electrically coupling together the first and second contact pads (114, 116) of the power electronic circuit (100), and, when the power electronic circuit (100) comprises third and fourth contact pads (124, 126), an embodiment of a second electrical connector (212) coupling together the third and fourth contact pads (124, 126) of the power electronic circuit (100).

14. The method of claim 13, wherein the encapsulation of the power transistor(s) (102, 106) and the control circuit(s) (104, 108) further comprises providing a third electrical connector (214) coupling together the first and second switching pads (120, 130) of the power electronic circuit (100).

Images