Bias circuit

Abstract

Bias circuit The present description relates to a bias circuit (202) comprising: a PMOS current source (116) (P1); a current mirror (204) comprising: - a first NMOS transistor (N5) connected to the current source a first resistor (R7) connected to a first node (206), and - a second NMOS transistor (N6) receiving a supply potential (VDDvco), mounted as a mirror of the first NMOS transistor (N5) and coupled to a third node (209) by a second resistor (R8); a capacitor (Cd1) connected between the second node (206) and a reference potential (GND); and a capacitor (Cd2) connected between the third node (210) and the reference potential, the second and third nodes being connected to a node (208) providing a bias current (Ib). Figure for abstract: Fig. 1

Description

Title of the invention: Bias circuit Technical field

[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits and for example radiofrequency electronic circuits. The present description relates more particularly to a biasing circuit configured to provide a biasing current to a circuit to be biased. Prior art

[0002] Known bias circuits comprise a bias terminal configured to receive a bias current, and another terminal configured to be connected to a reference potential. In these known circuits, the bias terminal is at a positive potential and referenced to the reference potential, for example ground. Oscillators, for example radio frequency oscillators, are examples of bias circuits as described above.

[0003] Known bias circuits are configured to provide a bias current to the bias terminal of a circuit to be biased as described above, from a PMOS current source. By PMOS current source, here is meant a current source comprising a PMOS transistor whose source is coupled to a node configured to receive a supply potential from the current source and whose drain is configured to provide the output current of the current source.

[0004] For example, the bias circuit comprises a band gap circuit coupled to the PMOS current source. The PMOS current source and the band gap circuit are, for example, configured so that the output current of the current source, which is delivered by its PMOS transistor, is a copy of a current flowing in the band gap circuit.

[0005] For example, the bandgap circuits are configured to implement a temperature-stable (or constant) voltage source. These bandgap circuits may comprise a resistive element across which the temperature-stable voltage or a voltage proportional to the absolute temperature (PTAT) is applied. The resistive element may have a value independent of the temperature or, on the contrary, dependent on the temperature, the current flowing in this resistive element then being able to be a temperature-stable type current, a type complementary to the absolute temperature (CTAT) or proportional to the absolute temperature (PTAT).

[0006] For example, the current source, for example when coupled to a bandgap circuit, is configured to deliver a temperature-stable current, a PTAT current, a CTAT current or a current corresponding to a combination of currents of at least two types among the three types of currents defined above.

[0007] The known bias circuits described above have various drawbacks. There is therefore a need for a bias circuit of the type described above which overcomes all or part of the drawbacks of the known bias circuits described above. Summary of the invention

[0008] One embodiment overcomes all or part of the drawbacks of known bias circuits of the type described above.

[0009] One embodiment provides a biasing circuit comprising: a current source comprising a PMOS transistor having its source coupled to a first node configured to receive a first supply potential, and its drain configured to provide an output current from the current source; a current mirror comprising: - a first NMOS transistor having its drain coupled to its gate and to the drain of the PMOS transistor, and its source coupled to a second node by a first resistor, and - a second NMOS transistor having its drain coupled to a third node configured to receive a second supply potential, its gate coupled to the gate of the first NMOS transistor, and its source coupled to a fourth node by a second resistor; a decoupling capacitor connected between the second node and a node configured to receive a reference potential; and a decoupling capacitance connected between the third node and a node configured to receive the reference potential, wherein the second and third nodes are connected to an output node configured to be connected to a first terminal of a circuit to be biased configured to receive a bias current on its first terminal and the reference potential on a second terminal of the circuit to be biased.

[0010] According to one embodiment, the current mirror comprises an RC filter between the drain of the first NMOS transistor and the output node or between the gate of the first NMOS transistor and the output node.

[0011] According to one embodiment, the RC filter comprises a resistor connected between the gate of the first NMOS transistor and the gate of the second NMOS transistor, and a capacitor connected between the gate of the second NMOS transistor and the output node.

[0012] According to one embodiment, the first and second supply potentials are positive compared to the reference potential.

[0013] According to one embodiment, the first supply potential is greater than the second supply potential, preferably by at least one MOS transistor gate-source voltage.

[0014] According to one embodiment, the bias circuit comprises a bandgap circuit coupled to said current source, the bandgap circuit and the current source being configured so that the output current of the current source is determined by a current flowing in the bandgap circuit, for example, so that the output current is a temperature-stable current, an absolute temperature-proportional current, an absolute temperature-complementary current, or a combination of several temperature-stable and / or absolute temperature-proportional and / or absolute temperature-complementary currents.

[0015] According to one embodiment, dimensions of the second NMOS transistor and dimensions of the first NMOS transistor are configured so that the current in the second NMOS transistor is equal to N times the current in the first NMOS transistor, with N strictly greater than 1, for example greater than 10.

[0016] One embodiment provides a device comprising a biasing circuit as above, and a circuit to be biased comprising a first terminal connected to the output node of the biasing circuit, and a second terminal connected to the reference potential.

[0017] According to one embodiment, the circuit to be polarized is configured to be powered by a potential difference between its first and second terminals resulting from the supply of the polarization current by the polarization circuit on the first terminal of the circuit to be polarized.

[0018] According to one embodiment, the circuit to be polarized is a radiofrequency circuit configured to operate at frequencies greater than 1 GHz, preferably greater than 10 GHz, or even greater than or equal to 20 GHz.

[0019] According to one embodiment, the circuit to be polarized comprises a filtering inductance connected between its first terminal and an internal node of the circuit to be polarized, the internal node being coupled to the first terminal of the circuit to be polarized.

[0020] According to one embodiment, the circuit to be polarized is an oscillator comprising: a filtering inductance connected between its first terminal and an internal node of the circuit to be polarized; a third NMOS transistor and a fourth NMOS transistor identical to the third NMOS transistor, the sources of the third and fourth transistors being connected to the internal node of the circuit to be biased, the gate of the third NMOS transistor being connected to the drain of the fourth NMOS transistor, and the gate of the fourth transistor NMOS being connected to the drain of the third NMOS transistor; a first inductor connected between the first terminal and the drain of the third NMOS transistor; a second inductor connected between the first terminal and the drain of the fourth NMOS transistor; and a capacitive element connected between the drains of the third and fourth NMOS transistors. Preferably, the first and second inductors and the filter inductor of the oscillator are each implemented by a corresponding conductive line portion.

[0021] According to one embodiment, the capacitive element of the oscillator comprises a voltage-controlled value capacitor.

[0022] According to one embodiment, the device further comprises a buffer circuit comprising: a filter inductor connected between a node configured to receive the reference potential and a first internal node of the buffer circuit; a fifth NMOS transistor and a sixth NMOS transistor that are identical and each have their source connected to the first internal node, the gate of the fifth NMOS transistor being connected to the drain of the third NMOS transistor and the gate of the sixth NMOS transistor being connected to the drain of the fourth NMOS transistor; a seventh NMOS transistor and an eighth identical NMOS transistor each having their drain connected to a node configured to receive a supply potential from the buffer circuit, the seventh NMOS transistor having its source connected to the drain of the fifth NMOS transistor and its gate coupled to the gate of the sixth NMOS transistor by a capacitor and to a second internal node of the buffer circuit by a resistor, the eighth NMOS transistor having its source connected to the drain of the sixth NMOS transistor and its gate coupled to the gate of the fifth NMOS transistor by another capacitor and to the second internal node by another resistor, the second internal node being configured to receive a bias potential.

[0023] According to one embodiment, the bias circuit comprises a portion of conductive line having one end connected to the decoupling capacitor connected to the second node of the bias circuit and another end connected to the decoupling capacitor connected to the third node of the bias circuit, said portion of conductive line comprising the second and third nodes and the output node of the bias circuit. Brief description of the drawings

[0024] These and other features and advantages will be set forth in detail in the following description of particular embodiments made without limitation in relation to the attached figures among which:

[0025] [Fig.l] represents an example of a device comprising a circuit to be biased and a biasing circuit;

[0026] [Fig.2] shows an example of a device comprising an exemplary embodiment of a biasing circuit and a circuit to be biased; and

[0027] [Fig. 3] represents, schematically and in the form of blocks, a device comprising a circuit to be polarized and the polarization circuit of [Fig. 2]. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0033] [Fig.l] represents an example of a device 100. The device 100 comprises a biasing circuit 102 of the type described above, and a biasing circuit 104.

[0034] In this example, the circuit to be polarized 102 is an oscillator, for example a radiofrequency oscillator configured to provide a radiofrequency signal at a frequency greater than 1 GHz, for example greater than 10 GHz, preferably greater than or equal to 20 GHz.

[0035] The oscillator 102 comprises a terminal 106 connected to a reference potential such as ground GND. The oscillator 102 further comprises a bias terminal 108. Terminal 108 is configured to receive a bias current Ib. Oscillator 102 is configured to be powered by the current Ib received by its terminal 108. This current Ib and the configuration of oscillator 102 cause the potential on terminal 108 to be positive and referenced to the reference potential GND. In other words, circuit 102 is configured so that, when it receives a bias current Ib on its terminal 108, a potential difference is created between its terminals 108 and 106.

[0036] More particularly, terminal 108 of oscillator 102 is configured to be coupled to a supply potential VDDvco, positive and referenced to ground GND. Potential VDDvco corresponds to the supply potential of oscillator 102. To limit the consumption of oscillator 102, it is sought to reduce the value of potential VDDvco.

[0037] The oscillator 102 comprises an inductance L1, for example implemented by a portion of conductive line, connected between terminal 108 and a node 110 of the oscillator 102. For example, one end of the inductance L1 is connected to node 110 and the other end of the inductance L1 is connected to terminal 108. The oscillator 102 further comprises an N-channel MOS (Metal Oxide Semiconductor) transistor, or NMOS transistor, NI. The transistor NI is connected between node 110 and a node 112 of the oscillator 102. For example, the drain of the transistor NI is connected to node 110 and the source of the transistor NI is connected to node 112.

[0038] Symmetrically, the oscillator 102 comprises an inductor L2, for example identical to the inductor L1, connected between the terminal 108 and a node 114 of the oscillator 102. For example, one end of the inductor L2 is connected to the node 114 and the other end of the inductor L2 is connected to the terminal 108. The oscillator 102 further comprises an NMOS transistor N2. The transistor N2 is connected between the node 114 and the node 112. For example, the drain of the transistor N2 is connected to the node 114 and the source of the transistor N2 is connected to the node 112.

[0039] The gate of transistor N1 is connected to drain 114 of transistor N2, the gate of transistor N2 being connected to drain 110 of transistor NI. In other words, transistors NI and N2 form a pair of cross-coupled NMOS transistors.

[0040] Nodes 110 and 114 then constitute the outputs of oscillator 102, that is to say that a differential periodic signal is available between nodes 110 and 114.

[0041] The oscillator comprises a capacitive element C connected between nodes 110 and 114. For example, a first terminal of the capacitive element C is connected to node 110, a second terminal of the element C being connected to node 114.

[0042] Oscillator 102 further comprises an inductor L3 connected between node 112 and terminal 106. Inductor L3 has one terminal connected to terminal 106, and its other terminal connected to node 112, the latter being coupled to terminal 108. Inductance L3 is for example implemented by a portion of conductive line. This inductance L3 is configured to filter the second harmonics in oscillator 102. This filtering inductance L3 is commonly referred to by the English term "stub".

[0043] The oscillator 102 is, in this example, implemented from a pair of cross-coupled NMOS transistors (NI and N2 in [Fig.l]) rather than from a pair of cross-cutting PMOS transistors, which allows the frequency of the oscillator 102 to be higher, for example greater than or equal to 10 GHz.

[0044] Furthermore, in oscillator 102, the provision of filtering inductance L3 requires that the current bias of oscillator 102 be made on its terminal 108.

[0045] In this example, the bias circuit 104 is configured to supply the current Ib to the terminal 108 of the circuit to be biased 102.

[0046] Circuit 104 includes a PMOS current source 116. Current source 116 is configured to provide a current II.

[0047] For example, circuit 104 includes a bandgap circuit coupled to current source 116. Current source 116 and bandgap circuit are, for example, configured so that current II is independent of temperature. However, in alternative examples, current source 116 and bandgap circuit are configured so that current II is a PTAT type current, a CTAT type current, or a current corresponding to a combination of several temperature-stable and / or PTAT type and / or CTAT type currents. In the case where the circuit to be polarized 102 is a radiofrequency oscillator of the LC type, for example voltage controlled, it is preferable that the current II delivered by the current source 116, therefore the current Ib, is a current of the PTAT type so as to compensate for the reduction in the quality factor Q of the oscillator 102 with the increase in temperature.

[0048] The current source 116 comprises a P-channel MOS transistor, or PMOS, PL. The transistor PI has its source coupled to a node 118 configured to receive a supply potential VDD and its drain 117 configured to provide the output current II of the current source 116. For example, the current source 116 comprises a resistor RI coupling the source of the transistor PI to the node 118. For example, the resistor RI has one terminal connected to the node 118 and another terminal connected to the source of the transistor PL.

[0049] Preferably, although this is not detailed in [Fig.l], the current source 116 is referenced to the GND potential. The potential VDD is higher than the potential VDDvco, which makes it possible to have a resistance RI of higher value compared to the case where the potential VDD would have been equal to the potential VDDvco. Furthermore, although this is not detailed in [Fig.l], the transistor PI is part of a current mirror in which the 1 / f noise decreases when the value of the resistance RI is increased, this resistance RI being, for example, called degeneration resistance. The 1 / f noise is the low frequency noise ("flicker noise" in English) which decreases in l / (fa) with f the frequency and has a coefficient between 0.8 and 1.3 for example and determined empirically.

[0050] In order to produce the current Ib from the current II, the bias circuit 104 comprises a current mirror 120 with NMOS transistors, and a current mirror 122 with PMOS transistors.

[0051] The mirror 120 is configured to provide, to the current mirror 122, a copy 12 of the current II, the current mirror 122 being configured to provide the current Ib from the current 12, the current Ib being a copy of the current 12.

[0052] In the present description, a second current is considered to be a copy of a first current, for example, when the second current is provided by a current mirror from the first current and the second current is equal to K times the first current, with K a positive factor. The factor K is, for example, determined by a size ratio between the transistors of the current mirror, and, when the mirror comprises degeneration resistors, by the inverse of the ratio of the values ​​of the degeneration resistors.

[0053] For example, the current mirror 120 comprises an NMOS transistor N3 having its drain connected to the current source 116 so as to receive the current II, and its source coupled to the node 106 by a resistor R3. For example, the drain of the transistor N3 is connected to the drain 117 of the transistor PL. For example, the resistor R3 has one terminal connected to the node 106 and another terminal connected to the source of the transistor N3. The transistor N3 is connected as a diode, and therefore has its gate coupled, for example connected, to its drain. The current mirror 120 further comprises an NMOS transistor N4 mounted as a mirror of the transistor N3. The transistor N4 has its gate connected to the gate of the transistor N3, its drain configured to supply the current I2, and its source coupled to the node 106 by a resistor R4. For example, resistor R4 has one terminal connected to the source of transistor N4, and another terminal connected to node 106. In the example of [Fig.l], transistors N3 and N4 have the same dimensions and degeneration resistors R3 and R4 have the same dimensions, from which it follows that current II is equal to current 12. .

[0054] For example, current mirror 122 includes a PMOS transistor P2 having its drain connected to current mirror 120 so as to receive current 12, and its source coupled to a node 124 by a resistor R5, the node 124 being configured to receive the supply potential VDDvco. For example, the drain of transistor P2 is connected to the drain of transistor N4. For example, resistor R5 has one terminal connected to node 124 and another terminal connected to the source of transistor P2. The Transistor P2 is mounted as a diode, and therefore has its gate coupled, for example connected, to its drain. Current mirror 122 further comprises a PMOS transistor P3 mounted as a mirror of transistor P2. Transistor P3 has its gate connected to the gate of transistor P2, its drain configured to provide current Ib, and its source coupled to node 124 by a resistor R6. For example, resistor R6 has one terminal connected to the source of transistor P3, and another terminal connected to node 124. In the example of [Fig.l], transistor P3 is K times larger than transistor P2 and the value of degeneration resistor R6 is K times smaller than that of degeneration resistor R5, from which it follows that current Ib is equal to K times current I2, with K strictly greater than 1.

[0055] In the device 100, the voltage dynamics Dv available between the main conduction terminals (source and drain) of the transistor N4 is expressed as follows: Dv = VDDvco - R5*I2 - VsgP2 - R4*I2, with VsgP2 the source-gate voltage of transistor P2.

[0056] Because we are trying to reduce the value of the potential VDDvco to limit the consumption by the oscillator 102, this tends to reduce the value of the dynamic voltage Dv which must however remain sufficiently high for the current mirror 120 to be functional. As a result, we tend to reduce the value of the degeneration resistors R4 and R5, which tends to increase the 1 / f noise. However, it is desirable to reduce the 1 / f noise.

[0057] To overcome the drawbacks of the device 100, and in particular the drawbacks of its bias circuit 104, a bias circuit is proposed here comprising a current mirror with NMOS transistors referenced to the potential of the node to which the bias circuit supplies the bias current Ib. One branch of the current mirror is connected to the PMOS current source 116, and is therefore powered by the potential VDD, the other branch of the mirror being connected to the potential VDDvco.

[0058] [Fig.2] shows an example of a device 200 comprising an exemplary embodiment of a biasing circuit 202 and the circuit to be biased 102.

[0059] The device 200 includes many elements in common with the device 100, and only the differences between these two devices are highlighted here. Thus, unless otherwise indicated, everything that has been described for an element in relation to [Fig. 1] applies to this element when it is part of the device of [Fig. 2].

[0060] More particularly, the device 200 differs from the device 100 in that the bias circuit 104 is replaced therein by a bias circuit 202.

[0061] Circuit 202 includes current source 116 configured to provide current II.

[0062] For example, the circuit 202 comprises a bandgap circuit coupled to the current source 116. The bandgap circuit and the current source 116 are, for example, configured so that the current II is a CTAT type current, a PT AT type current, a temperature stable type current, or a combination of several currents of at least two types among the three current types defined above.

[0063] By way of example, the bandgap circuit and / or the current source 116 are, for example, configured so that the output current II of the current source 116 is a copy of a current Vbg / R, Vptat / R or Vbg / Rcst of the bandgap circuit, with Vbg / R a current flowing in a resistor R across which a temperature-stable voltage Vbg is applied, Vptat / R a current flowing in a resistor R across which a voltage proportional to the absolute temperature Vptat is applied, and Vbg / Rcst a current flowing in a resistor Rcst across which a temperature-stable voltage Vbg is applied, the resistor R having a temperature-dependent value, and the resistor Rcst having a temperature-stable value. Current II can also be a copy of a combination of at least two of the currents Vbg / R, Vptat / R and Vbg / Rcst.

[0064] The circuit 202 further comprises a current mirror 204. The current mirror 204 is configured to receive the current II and to supply the current Ib to the node 108 of the circuit to be biased 102.

[0065] The circuit 204 comprises an NMOS transistor N5 having its drain connected to the output of the current source 116, i.e. to the drain 117 of the transistor PI, so as to receive the current II. The drain 205 of the transistor N5 is coupled to the gate of the transistor N5, for example connected to the gate of the transistor N5 in the example of [Fig.2]. The transistor N5 has its source coupled to a node 206 by a resistor R7. The node 206 is connected to an output node 208 of the circuit 202, this node 208 being configured to be connected to a bias terminal of a circuit to be biased, for example to be connected to the terminal 108 of the circuit 102 as shown in [Fig.2]. For example, the resistor R7 has one terminal connected to the source of the transistor N5 and another terminal connected to the node 206.

[0066] Circuit 204 further includes an NMOS transistor N6 having its drain coupled, preferably connected, to node 124 configured to receive potential VDDvco, and its source coupled to a node 210 by a resistor R8. Node 210 is connected to node 208. For example, resistor R8 has one terminal connected to the source of transistor N6 and another terminal connected to node 210.

[0067] Transistor N6 is configured so that a current 13 copy of current II flows between these main conduction terminals. Thus, circuit 202 provides current Ib which is then equal to the sum of currents II and 13.

[0068] Transistor N6 therefore has its gate coupled to the gate of transistor N5. In addition, the The values ​​of resistors R8 and R7 relative to each other are determined by the size ratio of transistors N5 and N6. For example, when transistor N6 is N times larger than transistor N5, with N strictly greater than 1, for example greater than 10, the value of resistor R8 is N times smaller than that of resistor R7, so that current I3 is equal to N times current II and current Ib is equal to N+1 times current II.

[0069] According to one embodiment, the current mirror 204 comprises an RC filter 212 between the drain 205 or the gate of the transistor N5 and the node 208. This RC filter 212 makes it possible to filter, i.e. reduce, the noise coming from the bias circuit 202.

[0070] For example, in [Fig.2], the filter 212 is connected between the gate of the transistor N5 (therefore the drain of the transistor N5) and the node 208. The filter 212 comprises a capacitive element Cf connected between the gate of the transistor N6 and the node 208, and a resistive element Rf connected between the gate of the transistor N6 and the gate of the transistor N5, the element Rf having, for example, a terminal connected to the gate of the transistor N5 and another terminal connected to the element Cf and to the gate of the transistor N6.

[0071] As an alternative example, the filter 212 is connected between the drain of the transistor N5 and the node 208. The resistive element Rf of the filter 212 is then connected between the drain 205 and the gate of the transistor N5, and the gate of the transistor N5 is connected to the capacitive element Cf and to the gate of the transistor N6, the capacitive element Cf being connected between the gate of the transistor N5 and the node 208. In this alternative example, the filter 212 makes it possible, for example, to filter the noise transmitted through the transistor N5 and the resistor R7, for example by moving the resistive element Rf between the drain and the source of the transistor N5 and by adding an additional filtering capacitance between the drain 205 of the transistor N5 and the node 207.

[0072] According to an alternative embodiment, the filter 212 is omitted.

[0073] Furthermore, to stabilize the value of the potential of the node 208 (or 108) with respect to which the current mirror 204 is referenced, the biasing circuit 202 comprises a decoupling capacitor Cd1 connected between the node 206 and a node 207, and a decoupling capacitor Cd2 connected between the node 210 and a node 209, each of the nodes 207 and 209 being configured to receive the reference potential GND.

[0074] By way of example, the circuit 202 comprises a portion of conductive line having one end connected to the capacitor Cd1 and another end connected to the capacitor Cd2, and the nodes 206, 208 and 210 belong to this portion of conductive line. For example, the node 208 is arranged in the middle of this portion of conductive line, the nodes 206 and 210 being for example arranged on either side of the node 208, preferably at the same distance from the node 208.

[0075] In the device 100, the correct operation of the bias circuit 104 was limited by the voltage dynamics Dv available for the output transistor N4 of the current mirror 120. In the device 200, the correct operation of the bias circuit 202 is limited by the voltage dynamics Dv' available for the transistor PI of the current source 116, this dynamics Dv' being expressed: Dv' = VDD - I1*R1 - VgsN5 - I1*R7 - VgsN2, with VgsN5 the gate-source voltage of transistor N5 and VgsN2 the gate-source voltage of transistor N2.

[0076] Taking equal resistance values ​​for the resistors RI (figures 1 and 2), R5 ([Fig.l]), R4 ([Fig.l]) and R7 ([Fig.2]), the voltages VgsN5, VsgP2 and VgsN2 equal or almost equal to a value Vgs, and the currents II and I2 equal, we obtain: Dv' - Dv = VDD - VDDvco - Vgs.

[0077] It follows that if VDD is greater than VDDvco by at least the value Vgs, the available dynamic range Dv' for the transistor PI of the bias circuit 202 is greater than the available dynamic range Dv for the transistor N4 of the bias circuit 104.

[0078] Further, bias circuit 202 is more compact than bias circuit 104.

[0079] Furthermore, since the bias circuit 202 comprises one less current mirror than the bias circuit 104, the circuit 202 is less noisy than the circuit 104.

[0080] According to one embodiment, the dimensions of transistor N6 are controllable, which allows the ratio N of current mirror 204 to be controllable, and therefore the value of current Ib to be controllable. In this case, the value of resistor R8 is also controllable so that current I3 remains equal to N times current II, with the value of N determined by the dimensions of transistor N6. For example, transistor N6 is composed of N transistors in parallel, each having the same dimensions as transistor N5, and resistor R8 is composed of N resistors in parallel, each having the same value as resistor R7, and the number N of transistors in parallel and resistors in parallel is controllable.

[0081] According to one embodiment, the capacitive element C of the oscillator 102 comprises a voltage-controlled value capacitor, whereby the frequency of the oscillator 102 is voltage-controllable. In other words, the oscillator 102 is then a voltage-controlled oscillator. For example, the capacitive element C comprises a fixed-value capacitor and at least one voltage-controllable value capacitor, for example a first voltage-controllable value capacitor allowing coarse adjustment of the capacitance value of the element C, and a second voltage-controllable value capacitor allowing fine adjustment of the capacitance value of the element C.

[0082] According to one embodiment, when the circuit 102 of the device 200 is an oscillator as described in relation to the exemplary embodiment of [Fig. 2], the device 200 may comprise a buffer circuit 214 as is illustrated in [Fig.2].

[0083] The circuit 214 is connected to the outputs 110 and 114 of the oscillator 102, and is configured to provide, between two output nodes 216 and 218 of the circuit 214, an image of the signal available between the nodes 110 and 114, and, on an output node 220 of the circuit 214, a signal at a frequency twice as high as that of the output signal of the oscillator 102.

[0084] The circuit 214 includes a bias terminal 222 configured to receive a supply potential VDDbuff from the circuit 214, and a terminal 224 configured to receive the reference potential GND. The potential VDDbuff is positive and referenced to the reference potential GND.

[0085] In the example of [Fig.2], the circuit 214 comprises a filtering inductor L4, for example similar or identical to the inductor L3. Preferably, the inductor L4 is matched to the inductor L3. The inductor L4 is connected between the terminal, or node, 224 and the output node 220 of the circuit 214, this node 220 corresponding to an internal node of the circuit 214. The circuit 214 further comprises two identical NMOS transistors N7 and N8, each having their sources connected to the node 220. Preferably, the transistors N7 and N8 are matched to the transistors N1 and N2. The gate of transistor N7 is connected to node 110 of oscillator 102, the gate of transistor N8 being connected to node 114 of oscillator 102. The drain of transistor N7 is coupled, preferably connected, to node 216, the drain of transistor N8 being coupled, preferably connected, to node 218.Circuit 214 also includes two identical NMOS transistors N9 and N10. The drains of both transistors N9 and N10 are connected to terminal, or node, 222 configured to receive the supply potential of circuit 214. The source of transistor N10 is coupled, preferably connected, to node 218, with the source of transistor N9 being coupled, preferably connected, to node 216. The source of transistor N10 is further coupled to the gate of transistor N7 by a capacitor C1, with the source of transistor N9 being coupled to the gate of transistor N8 by a capacitor C2. For example, capacitor C1 has one terminal connected to the gate of transistor N10 and another electrode connected to the gate of transistor N7, and capacitor C2 has one terminal connected to the gate of transistor N9 and another terminal connected to the gate of transistor N8.The gate of transistor N9, respectively N10, is further coupled to a node 224 by a resistor R9, respectively RIO, the node 224 being configured to receive a bias potential Vbias. For example, the resistor R9 has one terminal connected to the gate of transistor N9 and another terminal connected to node 224, the resistor RIO having one terminal connected to the gate of transistor N10 and another terminal connected to node 224.

[0086] In Figures 1 and 2, the circuit to be polarized is an oscillator, for example a bone radio frequency oscillator. However, the bias circuit 202 can be used to provide a bias current to circuits to be biased other than an oscillator, provided that this bias current must be provided to a bias terminal of the circuit to be biased which is at a positive potential relative to the reference potential applied to another terminal of this circuit to be biased.

[0087] [Fig. 3] represents, schematically and in the form of blocks, a device 300 comprising a polarization circuit 302 and the polarization circuit 202.

[0088] The circuit 202 comprises the current source 116, the current mirror 204 and the decoupling capacitors Cdl and Cd2. For example, the circuit 202 comprises a bandgap circuit as described in relation to [Fig.2].

[0089] The output 117 of the current source 116 is connected to the node 205 of the current mirror. The current source is connected to the node 118 receiving the potential VDD.

[0090] The current mirror 204 is connected to the node 124 configured to receive the potential VDDvco. The nodes 206 and 210 of the current mirror 204 are connected to the respective capacitors Cdl and Cd2, the capacitors Cdl and Cd2 coupling the respective nodes 206 and 210 to the respective nodes 207 and 209. The node 208 of the current mirror 204 is connected to a bias terminal 304 of the circuit to be biased 302.

[0091] The circuit to be biased 302 further comprises a terminal 306 configured to receive the reference potential GND. The circuit 302 is configured to be powered by the current Ib received on its terminal 304, which results in the presence of a positive potential on its terminal 304, therefore a potential difference between its terminals 304 and 306.

[0092] According to one embodiment, the circuit to be polarized 302 is a radiofrequency circuit, that is to say a circuit configured to operate at frequencies greater than 1 GHz, for example greater than 10 GHz, preferably greater than or equal to 20 GHz.

[0093] Although not illustrated in [Fig. 3], the circuit to be biased 302 comprises, for example, a filter inductor connected between the terminal or node 306 and an internal node of the circuit 302, this internal node being coupled to the terminal 304 of the circuit 302. As already indicated previously, the presence of such a filter inductor ("stub" in English) makes it impossible to supply a bias current to the circuit 302 on its terminal 306. However, in other examples, the circuit to be biased 302 does not comprise such a filter inductor, but must be biased by a PMOS current source supplying the bias current on the terminal 304 of the circuit 302, for example because the terminal 306 of the circuit 302 must be connected directly to the reference potential, for example the GND ground. Thus, circuit 302 may be a circuit other than a voltage-controlled oscillator or not.

[0094] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. job.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A bias circuit (202) comprising: a current source (116) comprising a PMOS transistor (PI) having its source coupled to a first node (118) configured to receive a first supply potential (VDD), and its drain configured to provide an output current (II) from the current source; a current mirror (204) comprising: - a first NMOS transistor (N5) having its drain coupled to its gate and to the drain of the PMOS transistor, and its source coupled to a second node (206) by a first resistor (R7), and - a second NMOS transistor (N6) having its drain coupled to a third node (124) configured to receive a second supply potential (VDDvco), its gate coupled to the gate of the first NMOS transistor, and its source coupled to a fourth node (210) by a second resistor (R8); a decoupling capacitor (Cdl) connected between the second node (206) and a node configured (207) to receive a reference potential (GND);and a decoupling capacitor (Cd2) connected between the third node (210) and a node (209) configured to receive the reference potential, wherein the second and third nodes (206, 210) are connected to an output node (208) configured to be connected to a first terminal (108; 304) of a circuit to be biased (102; 302) configured to receive a bias current (Ib) on its first terminal and the reference potential on a second terminal (106; 306) of the circuit to be biased.;

2. A biasing circuit according to claim 1, wherein the current mirror (204) comprises an RC filter (212) between the drain of the first NMOS transistor (N5) and the output node (208) or between the gate of the first NMOS transistor (N5) and the output node (208).

3. A biasing circuit according to claim 2, wherein the RC filter (212) comprises a resistor (Rf) connected between the gate of the first NMOS transistor (N5) and the gate of the second NMOS transistor (N6), and a capacitor (Cf) connected between the gate of the second NMOS transistor (N6) and the output node (208).

4. A biasing circuit according to any one of claims 1 to 3, wherein the first and second supply potentials (VDD, VDDvco) are positive with respect to the reference potential (GND).

5. A bias circuit according to claim 4, wherein the first supply potential (VDD) is higher than the second supply potential (VDDvco), preferably by at least one MOS transistor gate-source voltage.

6. The bias circuit of claim 5, wherein the bias circuit (202) comprises a bandgap circuit coupled to said current source (116), the bandgap circuit and the current source being configured such that the output current (II) of the current source (116) is determined by a current flowing in the bandgap circuit, for example, such that the output current (II) is a temperature-stable current, an absolute-temperature-proportional current, an absolute-temperature-complementary current, or a combination of several temperature-stable and / or absolute-temperature-proportional and / or absolute-temperature-complementary currents.

7. A bias circuit according to any one of claims 1 to 6, wherein dimensions of the second NMOS transistor (N6) and dimensions of the first NMOS transistor (N5) are configured so that the current (13) in the second NMOS transistor (N6) is equal to N times the current (II) in the first NMOS transistor (N5), with N strictly greater than 1, for example greater than 10.

8. Device (200; 300) comprising: a biasing circuit (202) according to any one of claims 1 to 7; and a circuit to be biased (102; 302) comprising a first terminal (108; 304) connected to the output node (208) of the biasing circuit (202), and a second terminal (106; 306) connected to the reference potential (GND).

9. Device according to claim 8, in which the circuit to be polarized (102; 302) is configured to be supplied by a potential difference between its first and second terminals (108, 106; 304, 306) resulting from the supply of the polarization current (Ib) by the polarization circuit (202) on the first terminal (108; 304) of the circuit to be polarized (102; 302).

10. Device according to claim 8 or 9, in which the circuit to be biased (102; 302) is a radiofrequency circuit configured to operate at frequencies above 1 GHz, preferably above 10 GHz, or even greater than or equal to 20 GHz.

11. Device according to any one of claims 8 to 10, in which the circuit to be polarized (102; 302) comprises a filtering inductance (L3) connected between its first terminal (106; 306) and an internal node (112) of the circuit to be polarized, the internal node (112) being coupled to the first terminal (108; 304) of the circuit to be polarized.

12. Device according to any one of claims 8 to 10, wherein the circuit to be biased (102) is an oscillator comprising: a filter inductance (L3) connected between its first terminal (106) and an internal node (112) of the circuit to be biased; a third NMOS transistor (NI) and fourth NMOS transistor (N2) identical to the third NMOS transistor, the sources of the third and fourth transistors (NI, N2) being connected to the internal node (112) of the circuit to be biased, the gate of the third NMOS transistor (NI) being connected to the drain of the fourth NMOS transistor (N2), and the gate of the fourth NMOS transistor (N2) being connected to the drain of the third NMOS transistor (NI); a first inductance (L1) connected between the first terminal and the drain of the third NMOS transistor (NI); a second inductance (L2) connected between the first terminal and the drain of the fourth NMOS transistor (N2);and a capacitive element (C) connected between the drains (110, 114) of the third and fourth NMOS transistors, wherein, preferably, the first and second inductances (L1, L2) and the filter inductance (L3) of the oscillator (102) are each implemented by a corresponding conductive line portion.;

13. Device according to claim 12, in which the capacitive element (C) of the oscillator (102) comprises a voltage-controlled value capacitor.

14. Device according to claim 12 or 13, wherein the device (200) further comprises a buffer circuit (214) comprising: a filter inductor (L4) connected between a node (224) configured to receive the reference potential (GND) and a first internal node (220) of the buffer circuit; a fifth NMOS transistor (N7) and a sixth NMOS transistor (N8) identical and each having their source connected to the first internal node (220), the gate of the fifth NMOS transistor (N7) being connected to the drain (110) of the third NMOS transistor (NI) and the gate of the sixth NMOS transistor (N8) being connected to the drain (114) of the fourth NMOS transistor (N2); a seventh identical NMOS transistor (N9) and an eighth identical NMOS transistor (N 10) each having their drain connected to a node (222) configured to receive a supply potential (VDDbuff) from the buffer circuit, the seventh NMOS transistor (N9) having its source connected to the drain (216) of the fifth NMOS transistor (N7) and its gate coupled to the gate of the sixth NMOS transistor (N8) by a capacitor (C2) and to a second internal node (224) of the buffer circuit (Vbias) by a resistor (R9), the eighth NMOS transistor (N10) having its source connected to the drain (218) of the sixth NMOS transistor (N8) and its gate coupled to the gate of the fifth NMOS transistor (N7) by another capacitor (Cl) and to the second internal node (224) by another resistor (RIO), the second internal node (224) being configured to receive a bias potential (Vbias).

15. Device according to any one of claims 8 to 14, wherein the bias circuit (202) comprises a conductive line portion having one end connected to the decoupling capacitor (Cd1) connected to the second node (206) of the bias circuit and another end connected to the decoupling capacitor (Cd2) connected to the third node (210) of the bias circuit, said conductive line portion comprising the second and third nodes (206, 210) and the output node (208) of the bias circuit.

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