Test vehicle and test method for microelectronic devices

Abstract

Test vehicle and test method for microelectronic devices The invention relates to a test structure (1) for a transistor with a buried gate (23), comprising: - a substrate (20), - a gate (23) partly (24) buried in the substrate (20), - a gate dielectric (25) insulating the gate (23) from the substrate (20), - a first contact (21) having a first end (201) connecting a conduction path (C) in the substrate (20), - a second contact (22) having a second end (202) connecting the conduction path (C), - at least one independent field plate (231, 211, 221), not connected to the gate (23) or to the first contact (21) or to the second contact (22), and arranged above the conduction path (C). A test method is also provided. Figure for abstract: Fig. 2

Description

Title of the invention: Test vehicle and test method for microelectronic devices Technical field

[0001] The present invention relates to the field of microelectronics. It finds a particularly advantageous application in the electrical characterization of power transistors. A particular example of application concerns the failure analysis of buried gate power transistors with two-dimensional electron gas (2DEG). STATE OF THE ART

[0002] Lateral metal-oxide-semiconductor (MOS) transistor structures generally have a buried or semi-buried gate whose sides participate in the conduction path. The sides of the gate may typically be inclined or vertical.

[0003] Different architectures of lateral power transistors based on silicon, silicon carbide or gallium nitride are for example disclosed in the documents "SiC Trench MOSFET With Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss, IEEE Electron Device Letters, Volume: 37, Issue: 10, Oct. 2016 p.1324 - 1327" and "The trench power MOSFET: Part I - History, technology, and prospects, IEEE Transactions on Electron Devices, Volume: 64, Issue: 3, Tuesday 2017 p. 674 - 691". To improve the voltage resistance of these power transistors, field plates connected respectively to the gate, the source and the drain of the transistor are generally used.

[0004] Despite these structural elements, the high voltage constraints applied to these power transistors, for example a blocking state voltage of the order of 300V to 400V for several tens of minutes, can lead to failures. Charge trapping, structural degradation within the transistor can generate different leakage currents, or even a breakdown of the transistor, when using these transistors under severe operating conditions.

[0005] The study and understanding of the mechanisms leading to the failure of power transistors are important issues for the development of these technologies.

[0006] Conventional methods for electrical characterization of power transistors are notably based on monitoring the threshold voltage and any drifts in this threshold voltage over time, and on measuring dynamic resistance in the on state.

[0007] These methods do not allow us to clearly determine the phenomena of trapping of parasitic charges within the transistor. They also do not allow the local origin of the breakdown in the transistors to be identified. It is difficult to dissociate and study the different failure mechanisms separately with these methods.

[0008] An object of the present invention is to provide a test method and structure overcoming the above-mentioned drawbacks.

[0009] In particular, an object of the present invention is to provide a test structure for determining the local origin and nature of failure mechanisms in a lateral power transistor.

[0010] Another object of the present invention is to propose a test method implementing such a test structure.

[0011] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0012] To achieve this objective, according to one embodiment, a test structure is provided comprising a buried gate transistor, said transistor comprising: - A substrate based on at least one semiconductor material, - A gate having a part buried in the substrate, - A gate dielectric electrically insulating the gate from the substrate, - A first contact, for example a source, located on a first side of the gate and having a first end connecting a conduction path in the substrate, - A second contact, for example a drain, located on a second side of the gate, opposite the first side, and having a second end connecting the conduction path in the substrate,

[0013] Advantageously, the test structure comprises at least one independent field plate, called a test plate, not connected to the grid or to the first contact or to the second contact, separated from the substrate and arranged above the conduction path between the first and second contacts.

[0014] The independent field plate(s) make it possible to locally modulate the electrostatic field appearing in the transistor during operation. This makes it possible to electrically probe different areas of the transistor, in particular along the conduction path. This makes it possible to measure the electrostatic field distribution within the transistor, in particular from the measurement of the leakage currents through the independent field plates, which have known current / field characteristics. In contrast, the state of the art is generally based solely on finite element simulations to estimate the distribution of the electrostatic field within the transistor.

[0015] Each independent field plate can advantageously be biased independently of the contacts and the gate of the transistor. This makes it possible to study separately the effects linked to each independent field plate. Leakage currents, parasitic charges and more generally transistor instabilities can be studied and measured locally.

[0016] The polarization of one or more independent field plates can also make it possible to reproduce the signature of a failure, and to trace the local origin of this failure.

[0017] The test structure according to the invention therefore advantageously makes it possible to locally determine the origin and nature of the failure mechanisms in a lateral power transistor.

[0018] According to another aspect of the invention, a test method is provided implementing a test structure according to the embodiment set out above, comprising the following steps: - Polarize the grid and the first and second contacts, so as to reproduce a real-life situation of use of the transistor, - Polarize at least one test plate so as to locally modulate the electrostatic field in the test structure, - Vary the polarization of at least one test plate in order to reproduce or study a situation of degradation or breakdown of the transistor.

[0019] The advantages of the test structure cited above apply mutatis mutandis to the test method. BRIEF DESCRIPTION OF THE FIGURES

[0020] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of embodiments thereof which are illustrated by the following accompanying drawings in which:

[0021] [Fig-1] [Fig.l] schematically illustrates, in transverse section, a gate transistor buried comprising field plates according to the prior art.

[0022] [Fig.2] [Fig.2] schematically illustrates, in cross-section, a test structure according to an embodiment of the present invention.

[0023] [[Fig.3] [Fig.3] schematically illustrates, in cross-section, a structure of test according to another embodiment of the present invention.

[0024] [Fig.4] [Fig.4] schematically illustrates, in top view, a test structure according to another embodiment of the present invention.

[0025] [Fig.5] [Fig.5] schematically illustrates, in top view, a buried gate transistor comprising field plates according to the prior art.

[0026] [Fig.6][Fig.7][Fig.8][Fig.9] Figures 6 to 9 schematically illustrate, with a view to above, a test structure according to different embodiments of the present invention.

[0027] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers, and the dimensions of the different patterns (grid, source, drain etc.) are not representative of reality. DETAILED DESCRIPTION

[0028] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0029] According to one example, the test structure comprises a plurality of independent field plates, called test plates, not connected to the gate or to the first contact or to the second contact, separated from the substrate and arranged regularly above the conduction path between the first and second contacts so as to mesh the test structure. This mesh of independent field plates makes it possible to precisely probe the distribution of the electrostatic field in the test structure comprising the transistor to be studied. This also makes it possible to locally modulate the electrostatic field and to locally generate degradations or failures, for example in order to reproduce the signature of a failure in a given usage situation of the transistor.

[0030] According to one example, each test plate is connected to a dedicated test contact. This allows each test plate to be independently biased.

[0031] According to one example, each test plate is configured to locally modulate the electrostatic field distribution under said test plate.

[0032] According to one example, at least one of the gate and the first and second contacts is connected to at least one so-called device field plate. The test structure aims to reproduce the characteristics of an actual lateral power transistor, which generally comprises such field plates connected to the gate and the contacts.

[0033] According to one example, the first contact is connected to a first device plate, the second contact is connected to a second device plate, and the gate is connected to a third device plate.

[0034] According to one example, the at least one test plate is located at least partially under the first and / or second device plates. This allows access to a local field distribution, near the conduction path of the transistor, which is generally masked by the device plates.

[0035] According to one example, the at least one test plate and the third device plate are located on the same plane, typically on different portions of the gate dielectric. The third device plate is for example "broken up" so as to form the at least one test plate. The at least one test plate is as close as possible to the conduction path, at the same level as the third device plate.

[0036] According to one example, the test structure comprises - a first test plate disconnected from the first contact, configured to at least partially replace a first device plate connected to the first contact, - a second test plate disconnected from the second contact, configured to at least partially replace a second device plate connected to the second contact, - a third test plate disconnected from the grid, configured to at least partially replace a third device plate connected to the grid.

[0037] The test structure may typically retain the design of the first and second device plates to form the first and second test plates, electrically isolating the first and second device plates from the first and second contacts, respectively.

[0038] According to one example, the first test plate at least partially reproduces the shape of the first device plate. According to one example, the second test plate at least partially reproduces the shape of the second device plate. According to one example, the third test plate at least partially reproduces the shape of the third device plate. The test structure aims to reproduce as best as possible the real transistor structure, so as to study behaviors similar to those occurring during real operating situations.

[0039] According to one example, the buried gate transistor comprises a barrier layer on the substrate configured to form a two-dimensional electron gas (2DEG) confined beneath said barrier layer, in the substrate.

[0040] According to one example, the 2DEG gas forms the conduction path, the first and second contacts of the transistor passing through said barrier layer. The buried gate transistor is typically of the HEMT type.

[0041] According to one example, the substrate is based on GaN and the barrier layer is based on AIN and / or AlGaN.

[0042] According to an alternative example, the substrate is based on silicon or silicon carbide.

[0043] According to one example, the set of test plates is located between the gate and the second contact. The transistor is generally not symmetrical, and the portion of the The conduction path between the gate and the drain is generally the one where most failures associated with the flow of drain current occur.

[0044] According to one example, the actual use situation of the transistor is a situation of blocking the electric current between the first and second contacts. This corresponds to the use of a “normally off” power transistor.

[0045] According to one example, the at least one test plate comprises a plurality of test plates distributed between the gate and the second contact. According to one example, each test plate is biased independently of the other test plates, the bias of each of the test plates being modulated over time so as to locally determine an occurrence of one or more transistor degradation phenomena.

[0046] Unless incompatibility exists, technical features described in detail for a given embodiment may be combined with the technical features described in the context of other embodiments described by way of example and not limitation, so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0047] In the context of the present invention, the power transistor architectures envisaged are typically with a gate buried in the substrate. They are sometimes referred to as "lateral" or refer to "lateral power transistors". Some of these architectures are more particularly based on a principle of conduction by two-dimensional electron gas (2DEG).

[0048] Such a transistor architecture includes the superposition of two semiconductor layers having different band gaps which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons.

[0049] HEMT (High Electron Mobility Transistor) type transistors, sometimes also referred to as heterostructure field effect transistors, are examples of transistors based on this two-dimensional electron gas architecture.

[0050] For reasons of power handling (in particular at high voltage) and temperature, the semiconductor material of these transistors is preferably chosen so as to have a wide forbidden energy band. Among the HEMT transistors with a wide forbidden energy band, transistors based on gallium nitride are generally preferred.

[0051] In the context of the present invention, the passage of current is typically controlled by a grid polarized positively with respect to the source.

[0052] This gate can be of the MOS or MOSFET type (English acronym for “Metal Oxide Semiconductor Field Effect Transistor”). In this case, the metal gate is electrically insulated from the semiconductor layers by a gate dielectric. Others gate compositions can be envisaged. A particularity of the transistor architectures according to the present invention is that the gate crosses the quantum well at which the two-dimensional electron gas is confined. The continuity of the two-dimensional electron gas is thus broken by a trench in which the MOS gate of the transistor is made.

[0053] Generally, if the gate of the transistor is set to a voltage greater than a threshold voltage, the source and drain are connected by the two-dimensional gas of electrons and the transistor is said to be on.

[0054] If the gate of the transistor is set to a voltage lower than the threshold voltage, the source and the drain are no longer connected and the transistor is said to be blocked.

[0055] The buried gate HEMT transistors contemplated within the scope of the invention are preferably in the off state when the gate is not biased. This type of transistor operation is commonly referred to as "normally off".

[0056] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0057] For example, and in a manner known per se in the field of GaN-based HEMT type transistors, a thin layer of AIN can be intercalated between two semiconductor layers of GaN and AlGaN.

[0058] A layer may also be composed of several sub-layers of the same material or of different materials.

[0059] A substrate, a stack, a layer, “based” on a material A, is understood to mean a substrate, a stack, a layer comprising this material A only or this material A and possibly other materials, for example alloying elements and / or doping elements.

[0060] The doping ranges associated with the different types of doping possibly indicated in the present application are as follows: - P++ or n++ doping: greater than 1 x 1020cm3 - p+ or n+ doping: 1 x 1018 cm3 to 9 x 1019 cm3 - p or n doping: 1 x 1017 cm3 to 1 x 1018 cm3 - intrinsic or non-intentionally doped doping: 1.1015 cm 3 to 1.1017 cm 3

[0061] In the present application, “test structure” and “test vehicle” are used in synonyms.

[0062] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0063] In the present patent application, the thickness of a layer is taken along a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms “on”, “overcomes”, “under”, “underlying” refer to positions taken along the z direction.

[0064] The terms “vertical”, “vertically” refer to a direction along z. The terms “horizontal”, “horizontally” refer to a direction in the xy plane.

[0065] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

[0066] An example of a known buried gate transistor T is illustrated in Figures 1 and 5, respectively in cross-section and in top view. The general architecture of this HEMT type transistor T comprises a first contact, for example a source 21 and a second contact, for example a drain 22 formed on either side of a gate pattern or gate 23. The gate 23 extends partly through a stack of layers 32, 31, into the substrate 20. This transistor T is based on a principle of conduction by two-dimensional electron gas (2DEG). Other types of buried gate transistors are also conceivable.

[0067] The substrate 20 may be a GaN-based substrate. Known GaN-on-sapphire or GaN-on-silicon substrates may typically be used. The support 10 may thus comprise, in a known manner, a solid silicon portion and one or more buffer layers interposed between the silicon portion and the GaN-based substrate 20. The substrate 20 is typically not intentionally doped.

[0068] A barrier layer 31, typically based on AlGaN, is directly arranged on the surface of the substrate 20. This barrier layer 31 has a thickness for example between 20 nm and 100 nm.

[0069] In a known manner, a two-dimensional electron gas is formed under the AlGaN-based barrier layer 31, in the GaN-based substrate 20. The two-dimensional electron gas 2DEG is typically confined to the interface between the AlGaN-based barrier layer 31 and the GaN-based substrate 20. This two-dimensional electron gas 2DEG forms a conduction path C in the substrate 20.

[0070] A passivation layer 32, for example based on silicon nitride SiN, is typically arranged on the barrier layer 31.

[0071] An encapsulation layer 33, for example based on silicon oxide SiO2, can typically be formed on layer 32, between contacts 21, 22 and gate 23, so as to insulate the contacts and the gate from each other, and to planarize the structure.

[0072] The gate 23 is typically arranged on this stack of layers 31, 32, and comprises a portion 24 passing through the stack and extending into the substrate 20, called the buried portion 24. The buried portion 24 typically has substantially vertical sides. The gate 23, 24 may be based on a metal alloy, for example based on gold and / or platinum and / or titanium.

[0073] A gate dielectric 25 typically separates the gate 23, 24 from the stack of layers 31, 32 and from the substrate 20. This gate dielectric 25 is for example based on alumina A12O3, and has a thickness of the order of a few nanometers to a few tens of nanometers, for example of the order of 30 nm.

[0074] The buried portion 24 of the gate 23 is configured to interrupt the two-dimensional electron gas along the conduction path C. Control of the gate voltage Vg allows the passage of electrons from the two-dimensional electron gas on either side of the gate 23 to be authorized or blocked. The gate voltage Vg allowing the passage of electrons is here typically positive, for example between 0V and 15V. In the absence of biasing of the gate 23, this type of transistor T is configured so that the passage of electrons is blocked. This type of transistor T is said to be “normally off”.

[0075] The source and drain contacts 21, 22 respectively have an end 201, 202 directly in contact with the substrate 20.

[0076] In the known transistor T, the source contact 21 is typically connected to one or more field plates 210. The drain contact 22 is typically connected to a field plate 220. The gate 23 is typically connected to a field plate 230 ([Fig.5]).

[0077] The gate 23 and the field plate(s) 230 typically form a T in cross-section, as illustrated in [Fig.l]. The field plate(s) 210 of the source contact 21 partly cover the conduction path C and partly surmount the field plates 230 of the gate 23. This makes it possible to improve the voltage resistance of the transistor T. The field plate(s) 220 of the drain contact 22 partly cover the conduction path C, and partly surmount the field plate 210 of the source contact 21 and the field plate 230 of the gate 23, between the gate 23 and the drain 22. This makes it possible to further improve the voltage resistance of the transistor T.

[0078] As illustrated in [Fig.2], a test structure 1 dedicated to the study of failure phenomena in the transistor T is proposed. This test structure 1 substantially reproduces the design of the transistor T and comprises independent field plates 211, 221, 231. According to one possibility, the plate 210 of the transistor T illustrated in [Fig.l] is disconnected from the source contact 21 to form the independent field plate 211. The plate 220 of the transistor T illustrated in [Fig.l] is disconnected from the drain contact 22 to form the independent field plate 221. The plate 230 of the transistor T illustrated in [Fig.l] is broken up to form the independent field plate 231.

[0079] In this configuration, the independent field plate 211 retains the design of the plate 210 that it replaces. The independent field plate 221 retains the design of the plate 220 that it replaces. The independent field plate 231 completes the initial design of the plate 230. The test structure 1 thus retains a design very close to that of the transistor T illustrated in [Fig.l]. This makes it possible to reproduce as best as possible the behavior of the transistor T in operation. The analysis of the failures in operation of the transistor T, via the test structure 1, is reliable and representative of real failure situations.

[0080] The independent field plates 211, 221, 231 are typically connected to dedicated test contacts (not shown). This makes it possible to independently polarize each of the independent field plates 211, 221, 231. It is thus possible to modulate the electrostatic field distribution to detect and determine a type of fault, for example trapping or breakdown, and to locate it. In particular, the breakdown can result in the detection of a leakage current through one of the independent field plates 211, 221, 231. A first location of the breakdown is thus possible. The trapping of parasitic charges, which is linked to the presence of traps in the structure and to the distribution of the electrostatic field with respect to these traps, can be more easily studied via the test structure 1.More generally, the effects of each field plate 210, 220, 230 on the instabilities and failures observed during the operation of the power transistor can be monitored and analyzed by substitution by the independent field plates 211, 221, 231.

[0081] The test structure 1 proposed in the present application is therefore both versatile and effective for locally determining the breakdown or trapping zone(s), and for improving the design of the power transistor.

[0082] [Fig. 3] illustrates another embodiment where a plurality of independent field plates 211, 221, 231, 232, 233, 234, 235 are integrated into the test structure 1. This makes it possible to probe and / or modulate the electrostatic field within the test structure 1 more finely. According to one possibility illustrated in [Fig. 3], the independent field plate 231 is duplicated to form the independent field plates 232, 233, 234, 235 regularly distributed along the conduction path, between the gate 23 and the drain 22. This makes it possible to mesh the test structure 1 with greater resolution. The electrostatic field distribution can thus be better understood, and / or better exploited to detect or reproduce certain failure mechanisms. The possible polarization combinations increase by increasing the number of independent field plates 211, 221, 231, 232, 233, 234, 235.This makes it possible, for example, to simulate or reproduce a failure signature observed in a . real power transistor.

[0083] [Fig.4] illustrates in top view another embodiment of the test structure 1 also comprising a plurality of independent field plates 211, 231, 232, 233, 234, 235. In this embodiment, it appears that all the independent field plates 211, 231, 232, 233, 234, 235 do not necessarily have the same dimension along y. In particular, the independent field plate 231 here resembles a small complementary portion of the field plate 230. It can be used for example for detection while the other independent field plates 232, 233, 234, 235 can be used for modulation of the electrostatic field.

[0084] Figures 6 to 9 illustrate in top view other embodiments of the test structure 1 also comprising a plurality of independent field plates 211, 231, 232, 233, 234, 235. The arrangement and shape of these independent field plates 211, 231, 232, 233, 234, 235 may vary depending on the testing or study needs. The independent field plates 232, 233, 234, 235 may be arranged transversely to the x direction, as illustrated in [Fig.7], or longitudinally, as illustrated in [Fig.8]. They may mesh more or less "pointwise" the active zone where the conduction path is formed in the substrate, as illustrated in [Fig.9].

[0085] The test structure 1 can advantageously be implemented to study different degradation mechanisms. Different tests can in particular be carried out.

[0086] According to one possibility, the source, drain, gate contacts 21, 22, 23 of the power transistor are biased so that the transistor is in a blocking situation. The independent field plates 211, 221, 231, 232, 233, 234, 235 are then simply used to monitor the leakage currents, and / or to locally measure the electrostatic potential values.

[0087] Another possibility consists in polarizing certain independent field plates 211, 221, 231, 232, 233, 234, 235 so as to deliberately generate a localized degradation in the test structure comprising the transistor. This makes it possible to study certain degradation mechanisms more precisely, for example by combining this electrical method with other physical characterization methods.

[0088] Another possibility is to bias the independent field plates 211, 221, 231, 232, 233, 234, 235 so as to reproduce the signature of a failure, for example a degradation of the on-state resistance, observed on a real power transistor. This comparative approach also makes it possible to know the origin of the failure.

[0089] For example, to study the impact of the grid voltage on the plates of field 211, 221, 231, 232, 233, 234, 235, drain 22, source 21, gate 23 and field plates 211, 221, 231, 232, 233, 234, 235 are first held at ground. One of the field plates 211, 221, 231, 232, 233, 234, 235 is then biased for a variable time, typically between Ips and several hundred seconds, at a voltage typically between -10 V and +10 V. The differences in operation of the test structure in the on state, before and after biasing, are then studied comparatively to evaluate the loading effects.

[0090] According to another example, to study the impact of the drain voltage on the charging effects in a targeted field plate, the source is held at ground, the gate is biased to a voltage typically between 0 and -2V (off state), one of the field plates 211, 221, 231, 232, 233, 234, 235 is held at the source potential (ground) and the other field plates 211, 221, 231, 232, 233, 234, 235 are floating, the drain is biased to a voltage between 10V and 600V (or the maximum determined by the voltage withstand of the device). This state is maintained for a variable time typically between Ips and several hundred seconds. The differences in operation of the test structure in the on-state, before and after biasing, are then studied comparatively to evaluate the loading effects. It appears that test structure 1 allows to advantageously and in a versatile and versatile manner study different operating and failure mechanisms of lateral power transistors.

[0091] The invention is not limited to the embodiments previously described.

Claims

Claims

1. Test structure (1) comprising a transistor with a buried gate (23), said transistor comprising: - A substrate (20) based on at least one semiconductor material, - A gate (23) having a portion (24) buried in the substrate (20), - A gate dielectric (25) electrically insulating the gate (23) from the substrate (20), - A first contact (21), for example a source, located on a first side of the gate (23) and having a first end (201) connecting a conduction path (C) in the substrate (20), - A second contact (22), for example a drain, located on a second side of the gate (23), opposite the first side, and having a second end (202) connecting the conduction path (C) in the substrate (20), Said test structure (1) being characterized in that it comprises: - At least one independent field plate (231, 211, 221), called test,not connected to the gate (23) or to the first contact (21) or to the second contact (22), separated from the substrate (20) and arranged above the conduction path (C) between the first and second contacts (21, 22).,

2. Test structure (1) according to the preceding claim comprising a plurality of independent field plates (231, 232, 233, 234, 235, 211, 221), called test plates, not connected to the grid (23) or to the first contact (21) or to the second contact (22), separated from the substrate (20) and arranged regularly above the conduction path (C) between the first and second contacts (21, 22) so as to mesh the test structure.

3. A test structure (1) according to any preceding claim wherein each test plate (231, 232, 233, 234, 235, 211, 221) is connected to a dedicated test contact.

4. Test structure (1) according to any one of the preceding claims- preceding in which each test plate (231, 232, 233, 234, 235, 211, 221) is configured to locally modulate the electrostatic field distribution under said test plate.

5. Test structure (1) according to any one of the preceding claims wherein at least one of the grid (23) and the first and second contacts (21, 22) is connected to at least one so-called device field plate (210, 220, 230).

6. Test structure (1) according to the preceding claim wherein the first contact (21) is connected to a first device plate (210), the second contact (22) is connected to a second device plate (220) and the grid (23) is connected to a third device plate (230), and wherein the at least one test plate (231, 211, 221) is located at least partly under the first and / or second device plates (210, 220).

7. Test structure (1) according to the preceding claim in which the at least one test plate (231) and the third device plate (230) are located on the same plane, typically on different portions (250, 251, 252, 253, 254) of the gate dielectric (25).

8. Test structure (1) according to any one of the preceding claims comprising: • a first test plate (211) disconnected from the first contact (21), configured to replace at least in part a first device plate (210) connected to the first contact (21), • a second test plate (221) disconnected from the second contact (22), configured to replace at least in part a second device plate (220) connected to the second contact (22), • a third test plate (231) disconnected from the grid (23), configured to replace at least in part a third device plate (230) connected to the grid (23).

9. Test structure (1) according to the preceding claim in which the first test plate (211) reproduces at least in part the shape of the first device plate (210), and / or the second test plate (221) reproduces at least in part the shape of the second device plate (220), and / or the third test plate (231) reproduces at least in part the shape of the less in part the shape of the third device plate (230).

10. Test structure (1) according to any one of the preceding claims wherein the buried gate transistor (23) comprises a barrier layer (31) on the substrate (20) configured to form a two-dimensional electron gas (2DEG) confined under said barrier layer (31), in the substrate (20), in which the 2DEG gas forms the conduction path (C), the first and second contacts (21, 22) passing through said barrier layer (31).

11. Test structure (1) according to the preceding claim in which the substrate (20) is based on GaN and the barrier layer (31) is based on AIN and / or AlGaN.

12. Test structure (1) according to any one of the preceding claims in which the set of test plates (231, 232, 233, 234, 235, 211, 221) is located between the grid (23) and the second contact (22).

13. Test method implementing a test structure (1) according to any one of the preceding claims, comprising the following steps: - Polarizing the gate (23) and the first and second contacts (11, 12), so as to reproduce a real use situation of the transistor, - Polarizing the at least one test plate (231, 232, 233, 234, 235, 211, 221) so as to locally modulate the electrostatic field in the test structure (1), - Varying the polarization of the at least one test plate (231, 232, 233, 234, 235, 211, 221) so as to reproduce or study a situation of degradation or breakdown of the transistor.

14. Method according to the preceding claim in which the actual use situation of the transistor is a situation of blocking of the electric current between the first and second contacts (21, 22).

15. A method according to any one of the two preceding claims wherein the at least one test plate comprises a plurality of test plates (231, 232, 233, 234, 235, 211, 221) distributed between the grid (23) and the second contact (22), and wherein each test plate is polarized independently of the other test plates, the polarization of each of the test plates being modulated in time of way of locally determining the appearance of one or more transistor degradation phenomena.

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