Electronic circuit for testing a digital circuit

Abstract

Electronic circuit for testing a digital circuit The present description relates to an electronic circuit for testing (200) a digital circuit (104, 110), comprising a multiplexer (310) having: a first input (A) intended to receive a signal from the digital circuit to be tested; a second input (Te) configured to receive a test mode activation signal (Scan_mode); a third input (Ti); a first output (Z) intended to receive a state of the third input (Ti) when the second input (Te) is activated and a state of the first input (A) when the second input (Te) is deactivated; a second output (NSZ) intended to receive a state of the signal present on the first input (A) or to be set to zero when the second input (Te) is respectively activated or deactivated. Figure for abstract: Fig. 3

Description

Title of the invention: Electronic circuit for testing a digital circuit Technical field

[0001] The present description relates generally to electronic circuits for testing digital circuits. Prior art

[0002] Electronic circuits, such as digital circuits, must be able to be tested during manufacturing or during the life of the circuit. For this, parts of test circuits are developed in conjunction with the circuits to be tested (design for test in English). Summary of the invention

[0003] There is a need to obtain a test circuit capable of testing a maximum of signals of the associated digital circuit.

[0004] One embodiment overcomes all or part of the drawbacks of known test circuits.

[0005] One embodiment provides an electronic circuit for testing a digital circuit, comprising a multiplexer having: - a first input intended to receive a signal from the digital circuit to be tested; - a second input configured to receive a test mode activation signal; - a third entrance; - a first output intended to receive a state of the third input when the second input is activated and a state of the first input when the second input is deactivated; - a second output intended to receive a state of the signal present on the first input or to be set to zero when the second input is respectively activated or deactivated.

[0006] According to one embodiment, the state of the signal present on the second output comes from an AND type logic function between the state of the test activation signal and the state of the signal present on the first input (A) of the multiplexer.

[0007] According to one embodiment, the test circuit comprises a scanning flip-flop comprising: - a multiplexing stage having: a first input connected to the second output of the multiplexer, a second input configured to receive the state of the mode activation signal of shift, a third entrance, an output intended to receive the state of the signal present on the first input of the multiplexing stage when its second input is in a first state and to receive the state of the signal present on the third input of the multiplexing stage when its second input is in a second state; and - a D-type flip-flop with a data input connected to the output of the multiplexing stage.

[0008] According to one embodiment, the first output of the multiplexer is connected to an analog block and the state of the signal on the third input of the multiplexer is maintained at a constant state, low or high, at least when the test mode is activated.

[0009] According to one embodiment, the first input of the multiplexer is connected to an output of a synchronization cell and the third input of the multiplexer is intended to receive a reset test signal generated outside the digital block.

[0010] According to one embodiment, the first output of the multiplexer is connected to an output of a clock signal division block and the third input of the multiplexer is intended to receive a clock test signal generated outside the digital block.

[0011] According to one embodiment, the multiplexer comprises a first and a second branch each connecting a first node to a second node;

[0012] the first branch being composed of: first two PMOS transistors in series between the first node and a third node, first two NMOS transistors in series between the third node and the second node, and a second PMOS transistor in series with a second NMOS transistor, a conduction node of the second PMOS transistor being connected to a conduction node common to the first two PMOS transistors, and a conduction node of the second NMOS transistor being connected to a conduction node common to the first two NMOS transistors; the second branch being composed of two third PMOS transistors in series between the first node and the third node, and two third NMOS transistors in series between the third node and the second node;

[0013] the multiplexer further comprising a fourth PMOS transistor connecting the first node to a conduction node common to the second PMOS and NMOS transistors.

[0014] According to one embodiment, the multiplexer comprises a first inverter circuit configured to provide a state inverse to the state of the test mode activation signal on : the control node of one of the first NMOS transistors connecting the third node to the conduction node common to the first two NMOS transistors, the control node of the second PMOS transistors, and the control node of the third PMOS transistor which is connected to the third node.

[0015] According to one embodiment, the multiplexer comprises a second inverter circuit connecting the conduction node, common to the second PMOS and NMOS transistors, and the second output.

[0016] According to one embodiment, the multiplexer comprises a third inverter circuit connecting the third node and the first output.

[0017] According to one embodiment, the control node of one of the first PMOS transistors having a conduction node connected to the first node, and the control node of one of the first NMOS transistors having a conduction node connected to the second node are intended to receive the state of the signal present on the first input of the multiplexer.

[0018] According to one embodiment, the control node of one of the first PMOS transistors having a conduction node connected to the third node,

[0019] the control node of the fourth PMOS transistor,

[0020] the control node of one of the third NMOS transistors connected to the third node, and

[0021] the control node of the second NMOS transistor,

[0022] are intended to receive the state of the test activation signal.

[0023] According to one embodiment, the control node of one of the third PMOS transistors, a conduction node of which is connected to the first node, and the control node of one of the third NMOS transistors connected to the second node, are intended to receive the state of the signal present at the third input of the multiplexer.

[0024] According to one embodiment, the state of the signal present on the third input of the multiplexer comes from a test vector generator.

[0025] According to one embodiment, the electronic test circuit and the digital circuit are arranged on the same chip. Brief description of the drawings

[0026] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0027] [Fig.l] very schematically represents in block form an example of an integrated circuit of the type to which the embodiments apply;

[0028] [Fig.2] very schematically represents an example of a circuit of [Fig. 1];

[0029] [Fig.3] represents an example of a circuit of [Fig.l] according to a mode of realization lization;

[0030] [Fig.4] schematically represents a circuit of [Fig.3] according to one embodiment;

[0031] [Fig.5] schematically represents a circuit of [Fig.l] according to one embodiment;

[0032] [Fig.6] schematically represents a circuit of [Fig.l] according to one embodiment; and

[0033] [Fig.7] schematically represents a circuit of [Fig.l] according to one embodiment. Description of the embodiments

[0034] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0036] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0039] [Fig.l] very schematically represents in block form an example of an integrated circuit 100 of the type to which the embodiments apply.

[0040] The circuit 100 comprises for example a processing unit 102 (CTRL) comprising one or more processors for example under the control of instructions stored in an instruction memory (not illustrated).

[0041] The circuit 100 further comprises a module 120 (REF) having a generation block reference clock signal comprising an oscillator generating a reference frequency.

[0042] The circuit 100 can integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, other processing units, an I / O input / output interface), symbolized by a block 106 (FCT) in [Fig.l].

[0043] The blocks 102, 106 and 120 are, for example, connected to each other and / or to the rest of the integrated circuit 100 via a bus 140 carrying the required signals.

[0044] The module 106 or the blocks 102 and / or 120 further comprise, for example, other functional blocks.

[0045] Blocks 102, 106 and / or block 120 comprise, for example, one or more digital circuits represented in the form of blocks 104, 110 (DIG). Block 106, or each of blocks 102, 106, 120 also comprise, for example, parts 108 (ANALOG) dedicated to analog operation and which are, for example, in communication with the respective digital blocks.

[0046] There is a need to test the digital circuits 104, 110 whether during manufacturing or during the life of the circuit 100. Defects or faults or errors can be tested if there is a well-specified procedure for exposing it in the actual silicon. To do this, test circuits are designed and for example integrated into the circuit 100 to test signals of the circuits 104, 110. This makes it possible to observe internal nodes so that the embedded functions can also be tested.

[0047] Detectable faults or errors are, for example, the sticking of a signal to a given value (0 or 1), a logic error, or even a clock frequency error.

[0048] [Fig. 2] very schematically represents an example of a circuit 210 of [Fig. 1].

[0049] More particularly, the circuit 210 is a multiplexer forming part of a test circuit 200 of one of the digital circuits 104, 110.

[0050] In the example shown, the multiplexer 210 is placed in series on a path to be tested of the digital circuit 104,110 so as to receive on an input a signal to be tested (Functional_sig) and to have an output Z,205 connected to the rest of the digital circuit 104,110.

[0051] The multiplexer 210 comprises a first input A,204 which is placed in the circuit 104,110 to receive a state of a signal Functional_sig of the digital circuit to be tested.

[0052] The multiplexer 210 further comprises a second input Te, 207, intended to receive a state of a Scan_mode signal which, depending on its value, activates or deactivates the transition of the circuit 104, 110 to a test mode.

[0053] The multiplexer 210 also comprises a third input Ti,206 configured to receive a state of a test signal Scan_sig. In other words, the signal Scan_sig will replace the Functional_sig signal to be tested when the second input is activated by the Scan_mode signal. The Scan_sig signal can take different forms depending on the nature of the Functional_sig signal to be tested.

[0054] The output Z,205 is configured to receive the state of the signal Scan_sig when the second input Te is activated and a state of the signal Functional_sig from the first input A,204 when the second input Te is deactivated. The signal Out on the output Z,205 then propagates to the rest of the digital circuit.

[0055] In the text, an enabled input means that it receives a signal in the high state (or 1) and disabled means that it receives a signal in the low state (or 0). It is nevertheless possible to implement an inverse solution.

[0056] The Out signal is then found in the rest of the digital circuit and its state can be stored in a flip-flop to allow its observation during testing. In order to be able to observe the effect of replacing the Functional_sig signal with the Signal_sig, the flip-flops which are part of the circuit 104,110 are of a different type from standard flip-flops. These flip-flops, called tested flip-flops, can be placed in a test mode or scan mode when the Scan_mode signal is in the high state for example so that the state of the signal which they have stored can be observed on their output during a subsequent clock signal pulse. In the test mode, all the flip-flops which can be tested are put in series, the output of one flip-flop being linked or connected to a test input (Ti) of the next, so as to form a shift register.By injecting an appropriate test vector (i.e. a series of 0s or 1s each separated by a clock tick) into the chain of serial flip-flops during the test mode, it is thus possible to test whether faults are present on different portions of the circuit. These test vectors can be calculated, for example, with an Automatic Test Pattern Generator.

[0057] When the test begins, the Scan_mode signal goes high for example and the Scan_sig signal is found on output Z,205. By doing this, it is possible to test the rest of the circuit connected to output Z for example by simulating the expected Out signal with the Scan_sig signal or by setting this signal to a given value.

[0058] Nevertheless, the Functional_sig signal is then no longer observed. It follows that the test coverage rate becomes in this case limited to less than 70% for the multiplexer 210. The objective of the test designs being to achieve a test coverage close to or greater than 99%, it is necessary to envisage a solution to increase this test coverage and in particular to allow the observation of the input A,204 during the test mode.

[0059] One solution could be to use a second additional multiplexer, similar to the first, but with input A of the first multiplexer connected, preferably tially connected, to the input Ti of the second multiplexer and the input Ti of the first multiplexer connected, preferentially connected, to the input A of the second multiplexer. This would make it possible to obtain observability of the state of the signal of the input A,204 of the first multiplexer through the output Z of the second multiplexer.

[0060] However, such a solution requires an increase in the number of transistors implemented for the test, as well as an increase in chip area and power consumption. In one example, twenty-four transistors are required to implement two multiplexers 210.

[0061] Furthermore, in this solution, even if it increases the test coverage, for example to around 80% for the two multiplexers, it does not make it possible to achieve the coverage of almost 99% which is targeted.

[0062] To overcome these problems, the embodiments provide that the electronic test circuit 200 of the digital circuit 104, 110, comprises a multiplexer having: - the first input A intended to receive a signal from the digital circuit to be tested; - the second input Te configured to receive a test activation signal; - the third entrance Ti; - the first output Z intended to receive a state of the third input Ti when the second input Te is activated and a state of the first input A when the second input Te is deactivated; and - a second NSZ output intended to receive a state of the signal present on the first input A or to be set to zero when the second input Te is respectively activated or deactivated.

[0063] The state of the signal on the first input A being accessible on the new output NSZ when the test mode is activated, that is to say when the second input Te is activated, the test coverage rate is thus increased.

[0064] This makes it possible to limit the chip surface area consumed compared to a solution with two 210 multiplexers while increasing the test coverage to more than 99% and limiting consumption.

[0065] [Fig.3] represents an example of a circuit of [Fig.l] according to one embodiment.

[0066] More particularly, [Fig.3] represents a part of the test circuit 200 of the digital circuit 104,110.

[0067] In the example shown, the test circuit 200 comprises a multiplexer 310. The multiplexer 310 is similar to the multiplexer 210 except that it comprises an additional output NSZ,312.

[0068] The output NSZ,312 is configured to on the one hand receive a signal state Functional_sig present on the first input A,204 when the second input Te is activated and on the other hand be set to zero when the second input Te is deactivated.

[0069] In one example, the state of the signal present on the second output NSZ,312 comes from a logic function of type AND between the state of the signal Scan_mode present on the input Te,207 and the state of the signal present on the first input A,204 of the multiplexer 310.

[0070] In order to be able to observe the state of the signal on the second output NSZ,312, the latter is connected, preferably connected, to a flip-flop 302 which can be switched into a test mode. In the rest of the text, flip-flops which can be put into a test mode are called scanning flip-flops.

[0071] In the example shown, the scanning flip-flop 302 comprises a multiplexing stage 320, in other words a multiplexer 320, having a first input 315 configured to receive the state of the signal present on the second output NSZ,312 of the multiplexer 310. The multiplexing stage 320 also comprises an input Te,322 configured to receive the state of the shift signal during the scanning test. The multiplexing stage 320 further comprises another input 324 intended to receive the state of a signal Scan_sig2.

[0072] The multiplexing stage 320 further comprises an output 332 configured to receive the state of the signal present on the input 315 of the multiplexing stage 320 when its second input 322 is in a first state, for example deactivated, and to receive the state of the signal present on the input 324 of the multiplexing stage 320 when its second input 322 is in a second state, for example activated. The first state and the second state can be inverted as required.

[0073] In the example shown, the scanning flip-flop 302 further comprises a D-type flip-flop,330, a data input D,331 of which is connected, preferably connected, to the output 332 of the multiplexing stage 320, a clock input CP,336 is configured to receive a clock signal CK and an output Q,334 configured to receive and maintain the state of the input D until the next clock pulse of the signal CK. The information of the signal Functional_sig can thus also be observed at output 334 of the flip-flop 330 when the test mode is in progress.

[0074] [Fig.4] schematically represents a circuit of [Fig.3] according to one embodiment. More particularly, [Fig.4] represents one embodiment of the multiplexer 310.

[0075] In the example shown, the multiplexer 310 comprises a first branch and a second branch 401, 402 each connecting a first node NI to a second node N2.

[0076] The first branch 401 is composed of two first PMOS transistors 410,412 in series between the first node NI and a third node N3. It is also composed of two first NMOS transistors 414,416 in series between the third node N3 and the second node N2. The first branch 401 further comprises a second PMOS transistor 402 in series with a second NMOS transistor 404. A conduction node of the second PMOS transistor 402 is connected to a conduction node N6 common to the first two PMOS transistors 410,412. A conduction node of the second NMOS transistor 404 is connected to a conduction node N8 common to the first two NMOS transistors 414,416. The second branch 402 is composed of two third PMOS transistors 418,420 in series between the first node NI and the third node N3, and two third NMOS transistors 422,424 in series between the third node N3 and the second node N2.

[0077] The multiplexer 310 further comprises a fourth PMOS transistor 428 connecting the first node N1 to a conduction node N7 common to the second PMOS and NMOS transistors 402, 404.

[0078] The state of the signal on input A is found on the control nodes of transistors 410 and 416. The signal state at input Te is found at the control nodes of transistors 404, 412, 422 and 428. The signal state on input Ti is found on the control nodes of transistors 418 and 424.

[0079] The circuit 200 comprises for example an inverter 426 configured to provide the inverse state NTe of the Scan_mode signal on the control nodes of the transistors 414, 420 and 402. In one example, the inverter 426 is integrated into the multiplexer 310. In the example shown, the multiplexer 310 further comprises an inverter 430 configured to provide the inverse state of the signal present on the third node N3 to the output Z,205.

[0080] In the example shown, the multiplexer 310 also comprises an inverter circuit 456 connecting the conduction node N7, common to the second PMOS and NMOS transistors 402, 404, and the second output NSZ.

[0081] As described in the example of [Fig.2], in the test mode, all flip-flops, including flip-flop 302, are connected in series, in the scan shift mode, the output of one flip-flop being connected to a test input Ti of the next, so as to form a shift register.

[0082] The multiplexer in [Fig.4] comprises seventeen transistors, which is much lower than the number of transistors required in a two-multiplexer solution.

[0083] [Fig. 5] schematically represents a circuit of [Fig. 1] according to one embodiment. More particularly, [Fig. 5] represents an example of implementation of the multiplexer 310.

[0084] In the example shown, the digital circuit 110 is connected, preferably connected to analog circuit 108.

[0085] In this case, in order to protect the circuit 108 during the test mode, the input Ti,206 receives the signal Scan_sig which is at a given level for example 0. This level 0 is found on the output Z and the circuit 108 is thus protected.

[0086] In the example of [Fig.5], the signal Functional_sig comes for example from a combinational logic block connected, preferably connected, at the input to for example three flip-flops 512, 514 and 516.

[0087] When the test mode is activated, the Functional_sig signal is observable on the scan flip-flop 302.

[0088] [Fig. 6] schematically represents a circuit of [Fig. 1] according to one embodiment. More particularly, [Fig. 6] represents another example of implementation of the multiplexer 310.

[0089] In the example shown, the signal received on input A,204 comes from a reset signal resynchronization cell 610.

[0090] This resynchronization cell is for example composed of two or more D flip-flops in series and having their reset inputs connected together and receiving a reset signal which can be desynchronized Asynchronous_Functional_reset. At the output of this cell 610, the reset signal Synchronous_Functional_reset is resynchronized to be distributed to one or more flip-flops similar to the scanning flip-flop 302. In this example, the signal Synchronous_Functional_reset is, in this example, the signal Functional_sig. The input A,204 of the multiplexer 310 receives the reset signal Syn-chronous_Functional_reset.

[0091] When the test mode is activated, a reset signal Scan_reset, similar to that provided by a Power On Reset cell and synchronized, is generated for example by a block external to the block 104,110 and is sent to the input Ti,206. The signal Scan_sig is, in this example, the signal Scan_reset. The state of the signal Scan_reset is found on the output Z and is distributed to the other flip-flops 302 of the circuit 104,110. The state of the signal Syn-chronous_Functional_reset is found on the second output NSZ and can be observed on the respective scan flip-flop 302.

[0092] [Fig.7] schematically represents a circuit of [Fig.l] according to one embodiment.

[0093] More particularly, [Fig.7] represents another example of implementation of the multiplexer 310.

[0094] In the example shown, the signal Div_CK received on the input A,204 comes from a block 710 for dividing the clock signal frequency. The signal Div_CK is, in this example, the signal Functional_sig. The block 710 is for example composed of one or several D flip-flops. A clock signal Functional_clock is injected on the clock input CP of the flip-flop of block 710 and the output QN of the flip-flop is connected to the data input D of block 710. At the output of block 710, the clock signal Functional_clock becomes the signal Div_CK having a frequency divided with respect to that of the signal Functional_CK.

[0095] The input Ti,206 of the multiplexer 310 receives a Scan_clock signal generated for example outside the block 104,110 and which allows the testing of the flip-flop logic. The Scan_sig signal is, in this example, the Scan_clock signal.

[0096] When the test mode is activated, by setting the Scan_mode signal to the high state for example, the state of the Div_CK signal is observable on the flip-flop 302 connected to the second NSZ input of the multiplexer 310. In other words, the NSZ output, in this case, provides observability on the clock pin.

[0097] In this test mode, the Scan_clock signal is found on the output Z and can be distributed in the rest of the circuit 104,110 for example to other scanning type flip-flops 302.

[0098] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art, in particular the multiplexer 310 may include other outputs than the Z and NSZ outputs, if these outputs allow the observation of signals that escape the test coverage.

[0099] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the flip-flops 302, used in the blocks 104, 110 may be of another architecture than that proposed in [Fig. 3] as long as they are configured to be able to select a signal from a Scan_sig type signal and a Functional_sig type signal depending on the activation or deactivation of the test mode.

Claims

Claims

1. Electronic test circuit (200) of a digital circuit (104,110), comprising a multiplexer (310) having: - a first input (A) intended to receive a signal from the digital circuit to be tested; - a second input (Te) configured to receive a test mode activation signal (Scan_mode); - a third input (Ti); - a first output (Z) intended to receive a state of the third input (Ti) when the second input (Te) is activated and a state of the first input (A) when the second input (Te) is deactivated; - a second output (NSZ) intended to receive a state of the signal present on the first input (A) or to be set to zero when the second input (Te) is respectively activated or deactivated.

2. Circuit according to claim 1, in which the state of the signal present on the second output (NSZ) comes from an AND type logic function between the state of the test activation signal and the state of the signal present on the first input (A) of the multiplexer (310).

3. Circuit according to claim 1 or 2, wherein the test circuit comprises a scanning flip-flop (302) comprising: - a multiplexing stage (320) having: a first input (315) connected to the second output (NSZ) of the multiplexer (310), a second input (322) configured to receive the state of the shift mode activation signal (Scan_enable), a third input (324), an output (332) intended to receive the state of the signal present on the first input (315) of the multiplexing stage (320) when its second input (322) is in a first state and receive the state of the signal present on the third input (324) of the multiplexing stage (320) when its second input (322) is in a second state; and - a D-type flip-flop (330) of which a data input (331) is connected to the output (332) of the multiplexing stage (320).

4. Circuit according to claim 1 to 3, in which the first output (Z) of the multiplexer (310) is connected to an analog block (108) and the state of the signal on the third input (Ti) of the multiplexer (310) is maintained at a constant state, low or high, at least when the test mode is activated.

5. Circuit according to claim 1 to 4, in which the first input (A) of the multiplexer (310) is connected to an output of a synchronization cell (610) and the third input (Ti) of the multiplexer (310) is intended to receive a reset test signal (Scan_reset) generated outside the digital block (104,110).

6. Circuit according to any one of claims 1 to 5, in which the first output (A) of the multiplexer (310) is connected to an output of a clock signal division block (710) and the third input (Ti) of the multiplexer (310) is intended to receive a clock test signal (Scan_clock) generated outside the digital block (104,110).

7. A circuit according to any one of claims 1 to 6, wherein the multiplexer (210) comprises first and second branches (401, 402) each connecting a first node (NI) to a second node (N2); the first branch being composed of: two first PMOS transistors (410, 412) in series between the first node (NI) and a third node (N3), two first NMOS transistors (414, 416) in series between the third node (N3) and the second node (N2), and a second PMOS transistor (402) in series with a second NMOS transistor (404), a conduction node of the second PMOS transistor being connected to a common conduction node (N6) of the two first PMOS transistors (410, 412), and a conduction node of the second NMOS transistor being connected to a conduction node (N8) common to the two first NMOS transistors (414, 416);the second branch being composed of two third PMOS transistors (418,420) in series between the first node (NI) and the third node (N3), and two third NMOS transistors (422,424) in series between the third node (N3) and the second node (N2); the multiplexer (310) further comprising a fourth PMOS transistor (428) connecting the first node (NI) to a conduction node (N7) common to the second PMOS and NMOS transistors (402,404).;

8. Circuit according to claim 7, in which the multiplexer (310) comprises a first inverter circuit (426) configured to provide a state (NTe) inverse to the state of the test mode activation signal (Scan_mode) on: the control node of one of the first NMOS transistors (414) connecting the third node (N3) to the conduction node (N8) common to the first two NMOS transistors (414,416), the control node of the second PMOS transistor (402), and the control node of the third PMOS transistor (420) which is connected to the third node (N3).

9. Circuit according to claim 7 or 8, in which the multiplexer (210) comprises a second inverter circuit (456) connecting the conduction node (N7), common to the second PMOS and NMOS transistors (402,404), and the second output (NSZ).

10. A circuit according to any one of claims 7 to 9, wherein the multiplexer (310) comprises a third inverter circuit (430) connecting the third node (N3) and the first output (Z).

11. Circuit according to any one of claims 7 to 10, in which the control node of one of the first PMOS transistors (410) having a conduction node connected to the first node (NI), and the control node of one of the first NMOS transistors (416) having a conduction node connected to the second node (N2) are intended to receive the state of the signal present on the first input (A) of the multiplexer (310).

12. A circuit according to any one of claims 7 to 11, wherein: the control node of one of the first PMOS transistors (412) having a conduction node connected to the third node (N3), the control node of the fourth PMOS transistor (428), the control node of one of the third NMOS transistors (422) connected to the third node (N3), and the control node of the second NMOS transistor (404), are intended to receive the state of the test activation signal.

13. Circuit according to any one of claims 7 to 12, in which the control node of one of the third PMOS transistors (418) of which a conduction node is connected to the first node (NI) and the control node of one of the third NMOS transistors (424) connected to the second node (N2), are intended to receive the state of the signal present at the third input (Ti) of the multiplexer (310).

14. Circuit according to any one of claims 1 to 13, in which the state of the signal present on the third input (Ti) of the multiplexer (310) comes from a test vector generator (ATPG).

15. Circuit according to any one of claims 1 to 14, in which the electronic test circuit (200) and the digital circuit (104,110) are arranged on the same chip (100).

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