Control circuit of a transistor

Abstract

Control circuit of a transistor The present description relates to a control circuit (102) for a transistor, configured to be connected to a transistor (110) and to lower a voltage applied to the gate (Vgs) of the transistor (110) when a current (Ig) delivered to said gate is greater than a first threshold for a first duration. Figure for the abstract: Fig. 1

Description

Title of the invention: Control circuit for a transistor Technical field

[0001] The present description relates generally to transistor control circuits and corresponding methods. Prior art

[0002] When a transistor, especially a power transistor, experiences a short circuit, it can be damaged. Some standards require that transistors remain viable, at least for a minimum duration, when a short circuit occurs. Summary of the invention

[0003] There is a need to protect transistors, particularly power transistors, when a short circuit occurs while complying with certain standards.

[0004] One embodiment overcomes all or part of the drawbacks of known circuits.

[0005] One embodiment provides a transistor control circuit, configured to be connected to a transistor and to lower a voltage applied to the gate of the transistor when a current delivered to said gate is greater than a first threshold for a first duration.

[0006] One embodiment provides a method for controlling a transistor comprising lowering a voltage applied to the gate of said transistor by a control circuit of said transistor when a current delivered to said gate is greater than a first threshold for a first duration.

[0007] According to one embodiment, the control circuit is configured to maintain the voltage applied to the lowered gate for a second duration.

[0008] According to one embodiment, the voltage applied to the gate of the transistor is lowered so that the transistor changes conduction state.

[0009] According to one embodiment, the first threshold is greater than or equal to 100pA.

[0010] According to one embodiment, the first threshold is greater than or equal to 400 pA.

[0011] According to one embodiment, the first duration is equal to or greater than 100 nanoseconds.

[0012] According to one embodiment, the second duration is equal to or greater than 200 nanoseconds.

[0013] According to one embodiment, the control circuit (102) comprises: - a first and a second node for applying a control voltage, the second node for applying the control voltage being configured to be connected to the source of the transistor; - a high-pass circuit connecting the first control voltage application node to a first terminal of a first switch, a second terminal of which is connected to an output node of the control circuit, said output node being configured to be connected to the gate of said transistor; and - a second switch connecting said output node to the second control voltage application node, the first and second switches being configured to be controlled by complementary signals.

[0014] According to one embodiment, the control circuit comprises a second capacitor connecting said first node and the second control voltage application node.

[0015] According to one embodiment, the control circuit comprises: - a first and a second node for applying a control voltage, the second node for applying the control voltage being configured to be connected to the source of the transistor; - a low-pass circuit between the first control voltage application node and a third node connected to a first terminal of a first switch, a second terminal of the first switch being connected to an output node of the control circuit configured to be connected to the gate of said transistor; - a Zener diode connecting said third node to the second control voltage application node; and - a second switch connecting said output node to the second control voltage application node, the first and second switches being configured to be in a conduction state opposite to each other.

[0016] According to one embodiment, the low-pass circuit comprises: - a resistor connecting the first control voltage application node and the third node; and - a capacitance connecting the third node and the second control voltage application node.

[0017] According to one embodiment, the control circuit comprises a high-pass circuit connecting the third node to said first terminal of the first switch.

[0018] According to one embodiment, the high-pass circuit is composed of a resistor in parallel with a capacitor.

[0019] According to one embodiment, the second terminal of the first switch is connected to the output node of the control circuit via a resistor.

[0020] One embodiment provides a control device comprising at least one control circuit as described and at least one transistor such that the control circuit is connected to the gate of said transistor.

[0021] According to one embodiment, said transistor is a high electron mobility transistor.

[0022] According to one embodiment, the transistor is based on a GaN alloy.

[0023] One embodiment provides a system comprising a motor and at least one device as described, said motor being controlled by said at least one device. Brief Description of the Drawings

[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0025] [Fig.l] represents very schematically and in the form of blocks an example of a system to which the embodiments apply;

[0026] [Fig.2] represents a timing diagram of the operation of the system of [Fig.l];

[0027] [Fig.3] represents an embodiment of a block of [Fig.l];

[0028] [Fig.4] represents an embodiment of a block of [Fig.3];

[0029] [Fig.5] represents an embodiment of a block of [Fig.3];

[0030] [Fig.6] represents an embodiment of a block of [Fig.3];

[0031] [Fig.7] represents a timing diagram of the operation of the block of [Fig.4];

[0032] [Fig.8] represents a timing diagram of the operation of the block of [Fig.5]; and

[0033] [Fig.9] represents an embodiment of the system of [Fig.l]. Description of the embodiments

[0034] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0036] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0039] [Fig.l] represents very schematically and in the form of blocks an example of a system 100 to which the embodiments apply.

[0040] The system 100 comprises for example one or more transistors 110 (TRANSISTOR) which are controlled by one or more control circuits 102 (GATE DRIVER). The transistor(s) 110 control for example the power supply of an object such as a motor 120 (MOTOR).

[0041] The control circuit controls the conduction state (conducting or open) of the transistors 110 by varying a voltage Vgs applied between the gate and the source of the transistors.

[0042] The transistors 110 are for example characterized by a gate current Ig which can pass through the gate. In other words, a gate current is a current delivered to the gate by the control circuit and which is due to leaks between the gate and the source for example when applying the voltage Vgs.

[0043] [Fig.2] represents a timing diagram of the operation of the system of [Fig.l].

[0044] More particularly, [Fig.2] represents the voltage Vgs applied to the gate of the transistor(s) as a function of time t, indicated in seconds, as well as the current Ig, called gate current or leakage current, necessary to charge or discharge the gate voltage.

[0045] In the example shown, the voltage Vgs is in the form of square waves and alternates for example every lOps between a high level which is maintained for example at 6V for 5ps and a low level which is maintained for example at 0V (or a negative voltage) for 5ps. When the voltage Vgs goes from the low level to the high level, a peak 220 of the current Ig occurs for a few nanoseconds for example five nanoseconds at 0.6A. The same is true when the voltage Vgs goes from the high level to the low level but with a gate current in the opposite direction. These current peaks 220 are part of the operation of the system and it may be advantageous to keep them.

[0046] Standards, for example in the automotive world, require that control transistors remain viable even when subjected to Ops at least 60% of the maximum permissible drain-source voltage. To perform this type of test, a voltage of 400V for example is applied to the open transistor 110 which is connected in parallel with a capacitor. Then a short circuit is created by applying a suitable voltage Vgs to close the transistor, for example 6V. The large energy stored in the capacitor is then very quickly discharged into the transistor. This makes it possible to reproduce a short circuit occurring for example in the object, such as the motor, which is controlled with the transistor 110.

[0047] Different solutions are envisaged to ensure the robustness of the transistors with respect to short circuits occurring in real conditions or those generated for the standards.

[0048] A first solution is to increase the resistivity in the on state (Ron measured in Q.cm2) of the transistor. However, this affects the other performances of the circuit. This solution is also costly in terms of development time and penalizes the efficiency of the transistor during normal operation.

[0049] A second solution is to detect the short circuit and then protect the transistor. In this case, it is necessary to use an extremely fast sensor that must measure the voltage across the transistor after the transistor's conduction state has changed, or to measure the main current and then use a feedback circuit to turn off the transistor.

[0050] The second solution requires a measurement with a very wide bandwidth with very fast reaction times to avoid destruction of the transistor.

[0051] To overcome these drawbacks, the embodiments provide that the control circuit of the transistor is configured to lower the voltage applied to the gate Vgs of said transistor when the current Ig, i.e. the gate current, delivered to said gate, is greater than a first threshold for a first duration.

[0052] The embodiments advantageously use the fact that when the temperature increases rapidly, which is the case during a short circuit, the gate current Ig increases. In power applications, the transistors used are, for example, high electron mobility transistors (HEMTs), manufactured from GaN and / or GaN alloys. For this type of transistor, the gate current can increase from a value of less than 600 pA for temperature ranges below 150°C to values ​​of more than 100 mA for higher temperatures reached during short circuits.

[0053] Furthermore, the condition that the gate current must be greater than the first threshold during the first duration makes it possible not to lower the voltage applied to the gate when the current peaks 220 occur.

[0054] The control circuit can thus open the transistor when the gate current increases, which prevents the temperature from increasing further during a short circuit. The short-circuit current passing between the drain and source of the transistor is thus stopped, which prevents damage to the transistor.

[0055] [Fig. 3] represents an embodiment of the system of [Fig. 1]. More particularly, [Fig. 3] represents an example of the control circuit 102.

[0056] The example of control circuit 102 shown applies for example to the control of a transistor 110 whose gate current changes substantially (for example of the order of or greater than 1pA / °C) with the temperature. In one example, the circuit control circuit 102 is configured to control one or more high-speed electronic transistors and / or transistors based on GaN and / or GaN alloys. In one example, the one or more transistors comprise a junction of GaN and AlGaN which forms a two-dimensional electron gas. The high-speed electronic transistors are turned off for gate-source voltages below a threshold.

[0057] In the example shown, the control circuit comprises one or more circuits 302 (GATE VOLTAGE LIMITATION BASED ON GATE CURRENT AND TIME) configured to lower the voltage applied to the gate Vgs of the transistor when the gate current Ig delivered to said gate of the transistor is greater than a first threshold for a first duration.

[0058] In one example, the first threshold is equal to or greater than 100pA or more particularly equal to or greater than 400pA.

[0059] In another example, the first duration is equal to or greater than 100ns, more particularly equal to or greater than 200ns.

[0060] If a current peak 220 occurs, the gate voltage is not lowered, because the peak has a duration less than the first duration, which ensures normal operation of the circuit outside short-circuit conditions.

[0061] During a short circuit, the temperature of the transistor increases drastically in a few tens of nanoseconds, which in turn increases the gate current. If the gate current exceeds the first threshold for the entire first duration, then the gate voltage is lowered, for example, to the saturation value of the gate voltage. The transistor then changes, for example, its conduction state, which protects it when changing from a closed state to an open state.

[0062] In one example, the control circuit 102 is configured to maintain the gate voltage lowered to a low level, for example to a level where the conduction state of the transistor is off, and this for a second duration. This allows for example that the situation which led to the short circuit can disappear before the transistor resumes standard operation.

[0063] [Fig.4] represents an embodiment of a block of [Fig.3]. More particularly, [Fig.4] represents an example of the control circuit 102.

[0064] In the example shown, the control circuit 102 comprises an electrical power source 410 applying a control voltage Vg+ between a node NI and a node NS. The node NS is configured to be connected, preferably connected, to the source of the transistor 110 to be controlled.

[0065] In the example shown, the control circuit 102 further comprises a high-pass circuit 406, in other words a high-pass filter, connecting the node NI to a first terminal NVD of a first switch (or commutator) SW1. A second terminal NM1 of the first switch SW 1 is connected to an output node NG of the circuit of control 102 via a resistor Rg. The output node NG is configured to be connected to the gate of the transistor 110 to be controlled.

[0066] In the example shown, the control circuit 102 comprises a second switch (or commutator) SW2 connecting the node NG to the node NS. In one example, the first and second switches are configured to be in a conduction state opposite to each other. In another example, the switch SW1 is an NMOS transistor and the transistor SW2 is a PMOS transistor. In one example, the switch SW1 is a PMOS transistor and the transistor SW2 is an NMOS transistor. The control signals of these two switches are for example opposed by using for example an inverter circuit on one of the control signals IN of the switches. The circuit formed by the two switches is a “push-pull” type circuit which makes it possible to amplify for example and create a square or square wave signal between the nodes NG and NS.

[0067] In the example shown, the control circuit 102 further comprises a second, optional capacitor C2 connecting the node NI and the node NS. In this example, the role of the capacitor C2 is to provide the current peaks 220.

[0068] In one example, the high-pass circuit 406 is formed by a capacitor Cl in parallel with a resistor RI between the nodes NVD and NI.

[0069] In one example, the resistance RI has for example a value of the order of ten Ohms, C2 is of the order of pF and Cl of the order of ten nF.

[0070] In operation, the current peaks 220 are of the order of a few nanoseconds, which corresponds to frequencies greater than or equal to 10 MHz for example. These current peaks will flow in the high-pass circuit 406 from the capacitor C1, and optionally also from the capacitor C2, and not or only slightly through RI, which will create a low impedance path. The gate current due to the short circuit, and delivered to the gate from the power supply source 410, is not in the form of peaks and therefore corresponds to lower frequencies of the order of a few hundred kHz. This gate current will flow through Cl and in addition RI which forms a higher impedance path which attenuates the voltage Vg+ delivered by the power supply source 410. The voltage Vgs delivered to the gate is therefore automatically attenuated until, for example, it falls below the conduction threshold of the transistor.

[0071] In the example shown, the values ​​of Cl, and possibly C2, and RI will be chosen so as not to attenuate frequencies above 10 MHz and to attenuate frequencies of the order of a few hundred kHz. The higher the value of RI, the higher the voltage drop applied to the gate of the transistor during a short circuit will be.

[0072] The example of [Fig.4] allows the gate voltage to be automatically lowered when the gate current exceeds the first threshold for the first duration without the need for measurement or feedback loop. This increases the speed to protect the transistor and reduces the implementation cost while limiting the impact on performance.

[0073] [Fig. 5] represents an embodiment of a block of [Fig. 3]. More particularly, [Fig. 5] represents an example of the control circuit 102.

[0074] In the example shown, the control circuit 102 comprises the power source 410 as well as the nodes NI, NS which are similar to those of [Fig.4]. The two switches SW1 and SW2 as well as the resistor Rg are also similar to those of [Fig.4]. The control circuit 102 further comprises a low-pass circuit 506, in other words a low-pass filter, between the node NI and a node NVZ connected to the first terminal of the first switch SW1. The control circuit 102 also comprises a Zener diode ZI connecting the node NVZ to the node NS with the cathode of the diode ZI oriented towards the node NVZ. In the example shown, the low-pass filter 506 is implemented with a resistor R2 which connects the node NI and the node NVZ; and with the capacitor C2 which this time connects the node NVZ and the node NS.

[0075] In the example of [Fig.5], the high-pass filter 406 is optional and it can be implemented, in one example, between the NVZ node and the NVD node.

[0076] In an example of [Fig.5], the capacitance C2 is of the order of 100OnF, the capacitance Cl is approximately 10OnF, the resistance RI approximately 10 Ohms and R2 approximately 500 Ohms.

[0077] In operation, the low-pass filter slowly charges the capacitor C2 through the resistor R2. Since the Zener diode ZI is present in antiparallel with the capacitor C2, the resistor R2 can be chosen to be large enough, of the order of several hundred Ohms, to ensure normal operational conditions. During a short circuit, the operation is similar to that of [Fig.4] except that the voltage Vgs is maintained below a low level, for example below the conduction threshold of the transistor, for a duration greater than lOps for example, which makes it possible not to reset the short circuit too quickly. This also allows time to warn a control unit of a motor for example connected, preferably connected, to the transistor.

[0078] [Fig. 6] represents an embodiment of a block of [Fig. 3]. More particularly, [Fig. 6] represents an example of the control circuit 102.

[0079] In the example shown, the control circuit 102 comprises the power source 410 which is similar to that of [Fig.4]. The power source is referenced to the local ground. The node NS is, in this example, connected to the local ground via a measuring resistor Rth. The two switches SW1 and SW2 as well as the resistor Rg are also similar to those of [Fig.4]. In the example shown, switch SW1 is connected directly to the power source.

[0080] In the example shown, the voltage limiting circuit 302 further comprises the measurement resistor Rth, and a low-pass circuit referenced to ground, in other words a low-pass filter, between the node NS and a negative input, denoted “-” of a comparator 620. The low-pass circuit is, in the example shown, composed of a resistor R3 connecting the node NS to the “-” input of the comparator 620, and a capacitor C3 connecting the “-” input of the comparator 620 to ground. A positive input of the comparator 620, denoted “+”, is connected to a voltage rail configured to receive a threshold voltage TH1. The output of the comparator is connected to an input of a logic gate 630 of the “AND” type. Another input of logic gate 630 is configured to receive a control signal IN from control circuit 102. The control signals of switches SW1 and SW2 are inverted with respect to each other and are derived from the signal present at the output of logic gate 630.

[0081] In operation, the measuring resistor Rth transforms the gate current Ig into a voltage proportional to the value of the resistor Rth. The low-pass filter, composed of R3 and C3, slowly charges the capacitor C3 through the resistor R3. In the event of current peaks 220, the negative voltage of the comparator does not reach the level of the imposed threshold voltage TH1 and the comparator 620 imposes the logic level 1 to the logic gate "AND" 630. In the event of a short circuit and an increase in the gate current, the negative voltage of the comparator reaches the threshold voltage TH1 and the comparator 620 imposes the logic level 0 to the logic gate "AND" 630 which triggers the switch SW2 and will impose a zero voltage Vgs which stops the short-circuit current.

[0082] In one example, the value of Rth is about 2Q, R3 is about 50 Q, Cl is about InF, and the threshold voltage TH1 is about 0.1V.

[0083] [Fig.7] represents a timing diagram of the operation of the block of [Fig.4]. More specifically, [Fig.7] represents the voltage Vgs, a voltage Vd between the node NVD and the node NS, the gate current Ig, and the drain current ID which flows through the drain of the transistor, as a function of time t expressed in seconds.

[0084] The beginning of the example in [Fig.7] is similar to the operation in [Fig.2]. The voltage Vgs follows square waves between approximately 6V and a low level at 0V or negative for example. At each passage from one level to another, a current peak 220 occurs.

[0085] At the beginning of the third pulse, at about 25ps, a short circuit occurs, for example due to too high a current being demanded by a connected motor, preferably connected to the transistor. The drain current ID of the transistor increases, during the short circuit, outside the normal operating range of the transistor. The temperature thus increases within the transistor, which increases the gate current flowing from a level close to zero to about 200mA. In response, the control circuit 102 lowers the voltage Vgs from 6V to 2V in a few hundred nanoseconds, for example 300ns. The voltage Vd is also lowered rapidly from 6 to 4V which differs for example from the usual behavior of the control circuits which is represented by the dotted line and which maintain the voltage Vd regardless of the value of the gate current Ig.

[0086] At the end of the third pulse, around 30 ps, ​​the level of Vgs is brought back to the low level by the push-pull circuit and therefore the transistor becomes non-conducting, the gate current returns to a low level and the voltage Vd returns to 6V.

[0087] [Fig.8] represents a timing diagram of the operation of the block of [Fig.5].

[0088] More particularly, [Fig.8] represents the voltage Vgs, a voltage Vz between the NVZ node and NS node, the gate current Ig, and the drain current ID which flows through the drain of the transistor, as a function of time t expressed in seconds.

[0089] Between 0 and 15ps, the example in [Fig.8] is similar to that in [Fig.2] or 7. When the second Vgs pulse goes from 0 to 6V, at 15ps, a short circuit occurs (symbolized by an arrow). The drain current ID increases outside the normal operating range of the transistor. The gate current then increases very quickly. In return, the voltage Vz drops in less than a hundred nanoseconds from 6V to about 4V and then drops a little less quickly to 2V towards the end of the second pulse at about 20ps. The voltage Vgs follows the same behavior but drops quickly from 6 to 2V and then more slowly to about 0.5V until the end of the second pulse. The drain current ID is completely blocked when the voltage Vgs is below the transistor's conduction threshold. The gate current also drops accordingly.

[0090] From the end of the second 20ps slot, the voltage Vz rises slowly, for example linearly.

[0091] Unlike the example in [Fig.7], in the example in [Fig.8], the voltage Vgs thus takes longer, for example 30ps, before returning above the level making the transistor conductive, which creates a masking time which can last the time of one or more other slots.

[0092] The example of [Fig.8] makes it possible to quickly stop the short circuit and allows the transmission of information about the presence of a short circuit before allowing the transistor to be turned on again.

[0093] [Fig.9] represents an embodiment of the system of [Fig.l].

[0094] In the example shown, the system 100 comprises a motor control circuit for controlling the motor 120. The motor control circuit comprises, for example, several branches B1, B2, B3 connected in parallel between a node N0 and a node N2. In this example, a capacitor C also connects the nodes N0 and N2.

[0095] In each branch, a first transistor has its drain connected, preferably connected, to node NO and its source connected, preferably connected, to a node NM2, and a second transistor has its drain connected, preferably connected, to node NM2 and its source connected, preferably connected, to node N2.

[0096] Each of the transistors of each branch is controlled by a control circuit 102 such as that of figures 4 or 5. Each control circuit of a branch has its node NG connected, preferably connected, to the gate of a transistor and its node NS connected, preferably connected, to the source of the respective transistor.

[0097] In the example shown, the node NM2 of each branch B1, B2 or B3 is connected, preferably connected, to a supply phase of the motor 120 via a smoothing inductance L1, L2, L3 respectively.

[0098] In the example of [Fig.9], the system 100 also comprises a control unit 910 (Control System (MCU)) configured for example to generate the control signal for the switches SW1 and SW2 of each control circuit 102.

[0099] The system 100 of [Fig.9] makes it possible to obtain motor control transistors which are more effectively protected against short circuits and which make it possible to meet the standards.

[0100] The examples of control circuits presented can be applied for example in the automotive industry, in radio frequency applications, radar systems or microwave amplifiers, in audio amplifiers or radio frequency transmitters, as well as for the electrification of vehicles, in particular electric and hybrid vehicles, or in light-emitting diode lighting systems for the management of currents and voltages as well as for the improvement of efficiency and performance.

[0101] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, the values ​​of the resistors RI, R2, of the capacitors Cl or C2 may be modified by those skilled in the art to allow a more or less rapid lowering of the voltage Vgs after detection of an increase in the gate current beyond a threshold for a given duration as well as to modify the masking period.

[0102] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above. In particular, the control circuits described can be used to control different types of transistors other than HEMT transistors and / or based on GaN alloys, and in particular transistors whose gate current at the gate varies substantially with temperature. Additionally, with regard to filters high-pass and low-pass, the person skilled in the art will be able to implement other implementations of these filters than those presented with the resistors RI and Cl or R2 and C2. Furthermore, even if the examples given in the figures apply for example to the case of a motor control, the control circuit described may be applied to other applications.

Claims

Claims

1. Control circuit (102) for a transistor, configured to be connected to a transistor (110) and to lower a voltage applied to the gate (Vgs) of the transistor (110) when a current (Ig) delivered to said gate is greater than a first threshold for a first duration.

2. The circuit of claim 1, wherein the control circuit (102) is configured to maintain the voltage applied to the gate (Vgs) lowered for a second duration.

3. A circuit according to claim 1 or 2, wherein the voltage applied to the gate of the transistor is lowered so that the transistor changes conduction state.

4. A circuit according to any one of claims 1 to 3, wherein the first threshold is greater than or equal to 100pA.

5. The circuit of claim 4, wherein the first threshold is greater than or equal to 400pA.

6. A circuit according to any one of claims 1 to 5, wherein the first duration is equal to or greater than 100 nanoseconds.

7. A circuit according to any one of claims 3 to 6 as dependent on claim 2, wherein the second duration is equal to or greater than 200 nanoseconds.

8. Circuit according to any one of claims 1 to 7, wherein the control circuit (102) comprises: - a first and a second node (NI,NS) for applying a control voltage (Vg+), the second node (NS) for applying the control voltage being configured to be connected to the source of the transistor; - a high-pass circuit (406) connecting the first node (NI) for applying the control voltage to a first terminal (NVD) of a first switch (SW1) of which a second terminal (NM1) is connected to an output node (NG) of the control circuit (102), said output node (NG) being configured to be connected to the gate of said transistor; and - a second switch (SW2) connecting said output node (NG) to the second node for applying the control voltage (NS), the first and second switches being configured to be controlled by complementary signals.

9. Circuit according to claim 8, wherein the control circuit comprises a second capacitor (C2) connecting said first node (NI) and the second node (NS) for applying control voltage.

10. Circuit according to any one of claims 1 to 9, wherein the control circuit (102) comprises: - a first and a second node (NI,NS) for applying a control voltage (Vg+), the second node (NS) for applying the control voltage being configured to be connected to the source of the transistor; - a low-pass circuit (506) between the first node (NI) for applying the control voltage and a third node (NVZ) connected to a first terminal (NVD) of a first switch (SW1), a second terminal (NM1) of the first switch (SW1) being connected to an output node (NG) of the control circuit configured to be connected to the gate of said transistor; - a Zener diode (Zl) connecting said third node (NVZ) to the second node (NS) for applying the control voltage;and - a second switch (SW2) connecting said output node (NG) to the second control voltage application node (NS), the first and second switches being configured to be in a conduction state opposite to each other.;

11. Circuit according to claim 10, wherein the low-pass circuit (506) comprises: - a resistor (R2) connecting the first node (NI) for applying control voltage and the third node (NVZ); and - a capacitor (C2) connecting the third node (NVZ) and the second node (NS) for applying control voltage.

12. A circuit according to claim 10 or 11, wherein the control circuit comprises a high-pass circuit (406) connecting the third node (NVZ) to said first terminal (NVD) of the first switch (SW1).

13. A circuit according to any one of claims 8, 9 or 12, wherein the high-pass circuit is composed of a resistor (RI) in parallel with a capacitor (Cl).

14. A circuit according to any one of claims 7 to 13, wherein the second terminal (NM1) of the first switch (SW1) is connected

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19. to the output node (NG) of the control circuit via a resistor (Rg). A control device comprising at least one control circuit (102) according to any one of claims 1 to 14, and at least one transistor (110) such that the control circuit (102) is connected to the gate of said transistor (110). The device of claim 15, wherein said transistor (110) is a high electron mobility transistor. Device according to claim 15 or 16, wherein the transistor (110) is based on a GaN alloy. A system comprising a motor (120) and at least one device according to any one of claims 15 to 17, wherein said motor is controlled by said at least one device. Method for controlling a device according to any one of claims 15 to 17, comprising lowering a voltage applied to the gate (Vgs) of said transistor by a control circuit of said transistor when a current (Ig) delivered to said gate is greater than a first threshold for a first duration.

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