Lateral power microelectronic devices

Abstract

Title: Lateral Power Microelectronic Devices The invention relates to a microelectronic device comprising: - A substrate (1), - A GaN-based island (2) protruding above the substrate, - At least one first contact (31), for example a drain or a cathode, on the upper face (200) of the island (2), - At least one second contact (32), for example a source or anode, disposed on the upper face (200) of the island (2) and along an edge (202) of said upper face (200). The second contact (32) at least partially surrounds the first contact (31). Advantageously, the second contact (32) and the substrate (1) are configured to be biased with the same polarization during device operation. A method for manufacturing such a device is also proposed. Figure for the abstract: Fig. 2B

Description

Title of the invention: Lateral power microelectronic devices Technical field

[0001] The present invention relates to the field of microelectronics. It finds a particularly advantageous application in the design of GaN-based power transistors and side-conducting power diodes. STATE OF THE ART

[0002] So-called "lateral" architectures aim to control the passage of current laterally between two contacts arranged substantially on the same face. In gallium nitride (GaN), this current corresponds to a two-dimensional (2DEG) electron gas confined under an interface with a barrier layer generally based on AlGaN. In the case of a lateral power transistor, a gate, which can be buried or semi-buried, is typically interposed in the conduction path of the 2DEG gas between the source and the drain. In the case of a lateral power diode, the anode typically forms a Schottky contact with the GaN, at the level of the 2DEG gas. The document "Performance enhancement of CMOS compatible 600V rated AlGaN / GaN Schottky diodes on 200mm Silicon wafers," J.Biscarrat et al, Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs, May 13-17, 2018, Chicago, USA, discloses such a GaN-based side-conducting power diode architecture. This type of side-conducting architecture allows for improved integration of power components.

[0003] These lateral architectures, however, exhibit a limited maximum operating voltage. The thin GaN layer associated with this type of lateral architecture results in a relatively low breakdown voltage, on the order of a few tens to a few hundred volts, typically less than 900V. Various alternative power device architectures have been developed to overcome this drawback.

[0004] The document “1900V, 1.6mQcm2 AIN / GaN-on-Si power devices realized by local substrate removal, Nicolas Herbecq et al, Applied Physics Express 7, 034103 (2014)” discloses a lateral architecture of a power transistor in which the silicon substrate supporting the IILV material layers has been locally removed beneath the transistor's conduction path between the gate and the drain. This limits the leakage current and consequently increases the component's voltage rating. The component is partially suspended, which makes it more mechanically fragile. Furthermore, the integration of such a component is limited.

[0005] The document "Selective-area growth study of GaN micropillars for quasi-vertical Schottky diodes, A Debald et al, Semicond. Sci. Technol. 36 (2021) 034005" discloses a diode architecture described as "vertical" or "quasi-vertical." In this type of vertical architecture, the GaN thickness is greater, and the component's voltage rating is improved. However, this type of architecture is bulky. Furthermore, the appearance of a leakage current limits the lon / Ioff ratio (on-state current Ion vs. off-state current loff). Managing the electric fields at the edges of the mesa structure is complex, which also limits the on-state current.

[0006] An object of the present invention is to propose a power device architecture that overcomes the disadvantages mentioned above.

[0007] In particular, an object of the present invention is to propose a lateral architecture of power devices exhibiting improved voltage withstand.

[0008] Another object of the present invention is to propose a method for manufacturing such a lateral architecture of power devices.

[0009] The other objects, features and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0010] To achieve this objective, according to one embodiment, a microelectronic device is provided comprising: - A substrate based on at least one semiconductor material, - An island made of gallium nitride (GaN) protruding above the substrate, and having a so-called upper face and flanks surrounding the island, - At least one initial contact point, for example a drain or a cathode, on the upper surface of the islet, - At least one second contact, for example a source or anode.

[0011] Advantageously, at least one second contact is disposed on the upper face of the island and along an edge of said upper face, such that at least one second contact at least partially surrounds at least one first contact. Advantageously, at least one second contact and the substrate are configured to be polarized with the same polarization during operation of the device.

[0012] The microelectronic device thus features a lateral architecture, where all the contacts are arranged on the upper face of the island. The device benefits in particular from the advantages of such a lateral architecture, for example, high energy efficiency and a high operating frequency. The lateral architecture notably enables high electron mobility thanks to the two-dimensional electron gas. The manufacturing technology of the components at Lateral architecture is also more mature than other GaN architectures, particularly vertical or quasi-vertical architectures. The formation of the different layers of a lateral architecture is faster than the formation of the different layers of a vertical architecture because it is not necessary to manage very low levels of doping, as is the case for components with a vertical architecture.

[0013] Furthermore, the placement of the second contact at the edge of Pilot, polarized in the same way as the substrate, makes it possible to limit or even eliminate leakage currents along the sides of Pilot. The voltage withstand capability of the lateral architecture device is thus improved.

[0014] According to one possibility, the GaN-based Pilot has a height of several micrometers, typically greater than or equal to 5 µm. This also helps to increase the voltage resistance of the device.

[0015] Another aspect of the invention relates to a system comprising a plurality of devices adjacent to one another and sharing the same substrate. Advantageously, the islands of the devices are separated from one another by a distance of less than 10 pm between two flanks of two adjacent islands. The system is compact. The integration of the devices is thus improved.

[0016] According to another aspect of the invention, a method for manufacturing at least one microelectronic device as described above is provided. This method includes, in particular, the following steps: - To form, by localized epitaxy, at least one GaN-based island on a substrate based on at least one semiconductor material, - To form at least one initial contact on the upper surface of said at least one island, - Form at least one second contact on the upper face, at the edge of said at least one island.

[0017] The lateral architecture of the microelectronic device is particularly well-suited for one or more islands formed by localized epitaxy. Localized epitaxy typically allows for the creation of a plurality of islands arranged in a compact lattice, with each GaN-based island having a height of several micrometers. Combining such a fabrication process with a lateral architecture advantageously yields microelectronic devices exhibiting improved voltage stability and high integration density. BRIEF DESCRIPTION OF THE FIGURES

[0018] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0019] [Fig.1A] [Fig.1B] Figures IA, IB schematically illustrate, respectively in top view and in cross-section, a power microelectronic device comprising Schottky diodes, according to an embodiment of the present invention.

[0020] [Fig.2A] [Fig.2B] Figures 2A, 2B schematically illustrate, respectively in top view and in cross-section, a power microelectronic device comprising HEMT transistors, according to another embodiment of the present invention.

[0021] [Fig.3] Fig.3 schematically illustrates, in cross-section, a step of formation by localized epitaxy of islands based on GaN, according to an embodiment of the present invention.

[0022] [Fig.4A] [Fig.4B] Figures 4A, 4B correspond to top-view scanning electron microscopy images of GaN-based islands obtained by localized epitaxy, according to an embodiment of the present invention.

[0023] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] [Fig.ll] [Fig.12] [Fig.13] [Fig.14] [Fig. 15] [Fig. 16] Figures 5 to 16 schematically illustrate, in cross-section, manufacturing steps of a power microelectronic device comprising HEMT transistors, according to an embodiment of the present invention.

[0024] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, in the schematic diagrams, the thicknesses of the different layers and the dimensions of the different elements (islands, contacts, etc.) are not representative of reality. DETAILED DESCRIPTION

[0025] Before proceeding to a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0026] According to one example, the device further comprises a barrier layer, for example based on AlGaN, on the upper face of the island. This allows the formation of a 2DEG gas under the barrier layer, within the GaN-based island. The electron mobility is improved.

[0027] According to one example, the island is based on carbon-free GaN. This improves the dynamic resistance of the device in the on-state.

[0028] According to one example, at least one first contact and at least one second contact are arranged on the barrier layer. According to another example, one of the first and second contacts passes partially or completely through the barrier layer. Different types of contacts, for example ohmic contacts or Schottky contacts, may These contacts can be formed on the GaN-based island. When the contacts, typically the anodes, form a Schottky contact, partially penetrating the barrier layer lowers the threshold voltage. When the contacts, typically the cathodes, form an ohmic contact, partially penetrating the barrier layer results in a contact resistance independent of the barrier thickness.

[0029] According to one example, at least one second contact completely surrounds at least one first contact and forms a closed contour around the at least one first contact. The management of the electric field at the edge of the island is thus optimized. Leakage currents are reduced or eliminated.

[0030] According to one example, the island has a height greater than or equal to 5 pm, preferably greater than or equal to 10 pm. This improves the voltage resistance of the device.

[0031] According to one example, the device comprises a plurality of first contacts and a plurality of second contacts, the first and second contacts being arranged concentrically on the upper face of the island. This allows for the formation of different nested side-conducting structures, typically in parallel with each other. Each structure benefits from the advantages of the device's island configuration, with optimized electric field management.

[0032] According to one example, the first contact corresponds to a cathode and the second contact corresponds to an anode and forms a Schottky contact with the island. The device thus comprises at least one Schottky diode-type structure.

[0033] According to one example, the device comprises at least one first anode at the center of the island and, concentrically, a first cathode completely surrounding the first anode, a second anode completely surrounding the first cathode, a second cathode completely surrounding the second anode, and a third anode arranged along the edge of the upper face of the island and completely surrounding the second cathode. The device thus comprises four concentric lateral Schottky diodes, which can be interconnected in parallel.

[0034] According to one example, the device includes at least one third contact, for example a grid, disposed on the upper face of the island between at least one first contact and at least one second contact. The device thus includes at least one transistor-type structure.

[0035] According to one example, the device comprises a plurality of first, second, and third contacts arranged concentrically on the upper face of the island. The device thus comprises at least two lateral transistors in parallel, which can be interconnected via at least one of the first and second contacts.

[0036] According to one example, the edge of the island forms a hexagonal outline for the top face of the island. Such a hexagonal shape can typically be obtained by GaN epitaxy, in particular by localized epitaxy. GaN-based islands can have a height of several micrometers with the crystalline quality required for power microelectronics applications. The hexagonal shape also allows for a compact tiling of islands on the substrate. This enables good integration of the devices into a larger system.

[0037] In one example, the system comprises a plurality of devices adjacent to one another, the substrate being common to all the devices in the system. The islands of the devices are separated from one another by a distance of less than 10 pm between two flanks of two adjacent islands. In one example, the islands have a hexagonal shape and are arranged on the substrate in a hexagonal tiling.

[0038] According to one example, the localized epitaxial formation is configured so that at least one island has a height greater than or equal to 5 pm, preferably greater than or equal to 10 pm.

[0039] According to one example, the at least one islet comprises a plurality of islets separated from each other by a distance of less than 10 pm, between two flanks of two adjacent islets. The formation by localized epitaxy is all the more controlled the smaller the distance between the islets.

[0040] There is typically a synergy between the localized epitaxial fabrication process and a plurality of thick islands arranged in a compact network. This directly benefits the device and the system resulting from this fabrication process. The lateral architecture of the device, perfectly suited to this type of island, also allows the advantages of the fabrication process to be exploited. The various aspects of the invention make it possible to design power microelectronic devices with optimized performance and voltage handling.

[0041] Except where incompatibility exists, it is understood that all the above optional features and / or the indicated variants may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features of one aspect of the invention, for example the device, system, or method, may be adapted mutatis mutandis to another aspect of the invention.

[0042] In the context of the present invention, the envisaged power device architectures are referred to as "lateral". Some of these architectures are more particularly based on a two-dimensional electron gas (2DEG) conduction principle.

[0043] HEMT type transistors (acronym for "High Electron Mobility Transistor") are examples of transistors based on this two-dimensional electron gas architecture. For reasons of power handling (especially at high voltage) and temperature resistance, the semiconductor material of these transistors is preferably chosen to exhibit a wide band gap. Among HEMT transistors with a wide band gap, gallium nitride-based transistors are generally preferred.

[0044] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0045] For example, and in a way known per se in the field of GaN-based HEMT transistors, a thin AIN layer can be intercalated between two GaN and AlGaN semiconductor layers.

[0046] A layer may also be composed of several sub-layers of the same material or of different materials.

[0047] A substrate, stack, layer, "based" on a material A means a substrate, stack, layer comprising only that material A or that material A and possibly other materials, for example alloying elements and / or dopant elements.

[0048] The doping ranges associated with the different types of doping possibly indicated in this application are as follows: - P++ or n++ doping: greater than 1 x 102°cm3 - p+ or n+ doping: 1 x 10¹⁸ cm³ to 9 x 10¹⁹ cm³ - Doping p or n: 1 x 1017 cm3 to 1 x 1018 cm3 - Intrinsic doping or unintentional doping: 1.10 cm to 1.10 cm

[0049] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures. When only one coordinate system is shown on the same sheet of figures, this coordinate system applies to all the figures on that sheet.

[0050] In the present patent application, the height of an element, typically an island projecting from a substrate, is taken along z. The thickness of a layer is taken along a direction normal to the principal extension plane of that layer. Thus, a layer can typically have a thickness along z. The relative terms “on”, "overcomes", "under", "underlying", "superior", "inferior" refer to positions taken along the z direction.

[0051] The terms "vertical" and "vertically" refer to a direction along z. The terms "lateral" and "laterally" refer to a direction in the xy plane.

[0052] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically in the figures.

[0053] The terms "approximately", "about", "on the order of" mean "to within 10%" or, when referring to an angular orientation, "to within 10°" and preferably "to within 5°". Thus, a direction substantially normal to a plane means a direction having an angle of 90+10° with respect to the plane.

[0054] Figures IA and IB illustrate, respectively, in top view and cross-section, several adjacent power devices according to a first embodiment of the invention. Figures 2A and 2B illustrate, respectively, in top view and cross-section, several adjacent power devices according to a second embodiment of the invention. In these embodiments, each device comprises a GaN-based island 2, 2A, 2B, 2C, and contacts 31, 32, 33 on the upper face 200 of the island 2A, 2B, 2C.

[0055] The devices are supported by a substrate 1 which is typically of the GaN-on-silicon type. The substrate 1 can thus comprise, in a known manner, a bulk silicon portion 10 and one or more layers 11 based on GaN and / or AlGaN. The layers 11 can be buffer and / or nucleation layers.

[0056] The islands 2A, 2B, 2C are positioned above the substrate 1, projecting from the buffer layers 11. They form separate mesa-like structures, isolated from one another. The islands 2A, 2B, 2C are typically in epitaxial relationship with the underlying layer(s) 11. They are based on one or more epitaxially grown GaN layers. They may include carbon-doped GaN (GaN:C), which improves the tensile strength of the devices in a known manner. They include at least one surface portion of unintentionally doped GaN. According to one possibility, the islands 2A, 2B, 2C do not include carbon, contrary to what is generally recommended. This allows for improved on-state dynamic strength of the devices.

[0057] The islands 2A, 2B, 2C typically have a height along z of several micrometers, for example, between 5 µm and 25 µm. Such GaN thicknesses advantageously allow the fabrication of power devices with high operating voltages. The greater the GaN thickness, the higher the breakdown voltage and the higher the operating voltage. A GaN thickness of 10 µm typically allows a device operating voltage of the order of 1200 V. A GaN thickness of 20 pm typically allows a device operating voltage of the order of 2200 V.

[0058] The islands 2A, 2B, 2C have a y-dimensional dimension of several tens or hundreds of micrometers, for example, between 50 pm and 500 pm, typically on the order of 200 pm. The islands 2A, 2B, 2C are delimited in the xy plane by flanks 201 joining the edges 202. The islands 2A, 2B, 2C can typically have a hexagonal shape in the xy plane. This shape can be obtained naturally during the epitaxial growth of GaN, which has a hexagonal crystallographic structure. The hexagonal shape advantageously allows the surface of the substrate 1 to be tiled compactly. A separation distance on the order of 8 to 10 pm between the flanks 201 of two adjacent islands 2A, 2B is typically achievable. This allows for approximately 95% coverage of the substrate 1 surface. The integration density of islands 2A, 2B, and 2C can therefore be high. Other shapes of islands 2A, 2B, and 2C, such as square or polyhedral, are nevertheless possible.

[0059] A barrier layer 22, typically based on AlGaN, is preferably disposed on the upper face 200 of each island 2A, 2B, 2C. This barrier layer 22 has a thickness, for example, between 20 nm and 100 nm. The barrier layer 22 has a principal portion at the top of the island. This principal portion is typically oriented along polar crystallographic planes of the hexagonal structure. This allows the formation, in a known manner, of a two-dimensional electron gas beneath the principal portion of the AlGaN-based barrier layer 22, within the underlying GaN-based island 2. The two-dimensional electron gas 2DEG is typically confined to the interface between the AlGaN-based barrier layer 22 and the GaN-based island 2. This 2DEG gas can be advantageously used in power devices. The barrier layer 22 may also have portions of layer 22 located on the flanks 201.These portions are typically oriented along semi-polar crystallographic planes of the hexagonal structure.

[0060] In the first embodiment (Figures IA, IB), each device comprises first and second contacts 31, 32 on the upper face 200 of the island 2A, 2B, 2C. Each device thus comprises at least one lateral Schottky diode formed between the contacts 31, 32. The first contacts 31 correspond here to cathodes and the second contacts 32 correspond here to anodes. The anodes 32 form a Schottky contact with the GaN of the island 2. The cathodes 31 and the anodes 32 can be arranged on the surface of the barrier layer 22. Alternatively, the cathodes 31 and / or the anodes 32 can partially or completely penetrate the barrier layer 22.

[0061] As illustrated in Figures IA, IB, at least one anode 32 is disposed at the edge 202 of the upper surface 200 of each island 2. Preferably, this anode 32 forms a closed contour along the edge 202, as illustrated in [Fig. 1A]. The anode 32 This allows the anode 32 to surround the cathode 31. The current injection is thus better distributed, optimizing current transport. The anode 32's position along the edge 202 advantageously applies the same polarization to the anode 32 and the substrate 1, effectively limiting or eliminating leakage currents. The portion(s) of the AlGaN-based barrier layer 22 located on the flanks 201 also limit the occurrence of leakage currents. This is due to the crystallographic orientation of the AlGaN on the flanks 201, which lacks electrical conductivity. The breakdown voltage of the device is increased.

[0062] In the illustrated example, each device comprises several anodes 32 and cathodes 31 arranged concentrically on the upper surface 200 of the island 2. In particular, a "central" anode 32a is located at the center of the island; a cathode 31a surrounds this central anode 32a; an anode 32b surrounds the cathode 31a; a cathode 31b surrounds the anode 32b; and an anode 32c, substantially coinciding with the edge 202, surrounds the cathode 31b. In the illustrated example, each device thus comprises four concentric power diodes interconnected in parallel.

[0063] The cathodes 31 can be connected to the metal tracks 310 via vias 311, in a conventional manner. The anodes 32 can be connected to the metal tracks 320 via vias 321, in a conventional manner. The metal tracks 310 and 320 connecting the various diodes of the different devices can be interdigitated.

[0064] A dielectric encapsulation layer 4 isolates the diodes from each other and facilitates the integration of the devices in a known manner. This dielectric encapsulation layer 4 typically fills the space between the flanks 201 of two adjacent islands 2A, 2B. The isolation between two adjacent devices is improved.

[0065] In the second embodiment (Figures 2A, 2B), each device comprises at least one first contact 31, at least one second contact 32, and at least one third contact 33 interposed between the first and second contacts 31, 32. The first, second, and third contacts 31, 32, 33 are arranged on the upper face 200 of the island 2A, 2B, 2C. The features and advantages described for the first embodiment also apply to this second embodiment, mutatis mutandis. Only the features that differ from the first embodiment are detailed below.

[0066] In particular, in this second embodiment, each device comprises at least one lateral power transistor, of the HEMT type. The first contacts 31 correspond here to drains and the second contacts 32 correspond here to sources. The third contacts 33 correspond here to the gates of the lateral HEMT transistors.

[0067] In the example illustrated in Figures 2A, 2B, each device island comprises four concentric HEMT power transistors interconnected in parallel.

[0068] In the same way as for the first embodiment, a source 32 is arranged along the edge 202 of the upper surface 200 of each island 2. This advantageously allows the same bias to be applied to the source 32 and the substrate 1. The breakdown voltage of the device is increased.

[0069] The drains 31 can be connected to the metal tracks 310 via vias 311, as before. The sources 32 can be connected to the metal tracks 320 via vias 321, as before. The gates 33 can be connected to the metal tracks 330 via vias 331, in a conventional manner. The metal tracks 310 and 320 connecting the different transistors of the different devices can be interdigitated. The metal tracks 330 connecting the gates of the different transistors can be located on a different metal layer than the metal tracks 310 and 320.

[0070] Figures 3 and 5 to 16 schematically illustrate different manufacturing stages of power devices according to the second embodiment, comprising lateral HEMT transistors.

[0071] As illustrated in [Fig. 3], a first step consists of forming the islands 2 on the substrate 1. The formation of the islands 2 is advantageously carried out by localized GaN epitaxy on the layers 11. Localized epitaxy is also known by the acronyms SAE or SAG ('Selective Area Epitaxy' or 'Selective Area Growth'). A mask 12 is formed, for example by lithography, on the layers 11. The GaN epitaxy takes place on the exposed areas of the layers 11. A plurality of adjacent islands 2, delimited by the mask 12, is thus formed. The GaN can be doped during one or more phases of the epitaxy. According to one example, a first layer 20 based on GaN:C can be formed by epitaxy, followed by a second layer 21 based on GaN that is not intentionally doped. Island 2 thus comprises the first and second layers 20, 21. The first layer 20 can have a thickness of several micrometers, for example on the order of 7 pm.The second layer 21 can be a few hundred nanometers thick, for example, on the order of 400 nm. The first layer 20, however, is only optional. A single thick layer 21 based on unintentionally doped GaN can be epitaxially grown to form island 2. Other GaN-based layers can also be considered to form island 2. After the successive epitaxies, island 2 has a height h2 advantageously greater than 5 pm, for example, on the order of 10 pm or 20 pm. This improves the voltage resistance of devices subsequently fabricated on these islands 2.

[0072] A barrier layer 22 based on AlGaN can then be formed by epitaxy on each of the islands 2. This barrier layer 22 typically has an aluminum concentration of between 20% and 30% at. It can have a thickness of a few tens of nanometers, for example on the order of 20 nm. The barrier layer 22 typically comprises main parts 22a on the vertices of the islands 2, and semi-polar parts 22b on the flanks 201 of the islands 2. The semi-polar parts 22b can bear on the mask 12. Other layers, not shown, can be re-epitaxed on the barrier layer 22. In the case of p-GaN gate transistors, a 100 nm thick p-GaN-based layer can typically be formed on the barrier layer 22.

[0073] Figures 4A and 4B are scanning electron microscopy images obtained after the localized epitaxial formation of GaN-based islands 2, 2A, 2B, and 2C, prior to the formation of barrier layer 22. The islands 2, 2A, 2B, and 2C, viewed from above, have a well-defined hexagonal shape, with an x-dimension on the order of 200 pm. The hexagonal islands 2, 2A, 2B, and 2C are densely distributed over the surface of substrate 1.

[0074] As illustrated in [Fig. 5], after the formation of the islands 2A, 2B, the barrier layer 22, and any upper layers, a filler layer 40 is deposited over all the islands 2A, 2B. An intermediate arrest layer (not shown), for example, a 20 nm thick SiN-based layer, is preferably formed prior to the deposition of the filler layer 40. This facilitates the subsequent partial removal of the layer 40. The filler layer 40 is preferably SiO2-based. It is, for example, formed by low-pressure SACVD (sub-atmospheric chemical vapor deposition) from a TEOS (tetraethyl orthosilicate) precursor, advantageously with a low residual stress level. Details of this type of known deposition process can be found, for example, in the document "C. Chang et al., Microsystem Technologies 10 (2004) 97-102 Springer-Verlag 2004".The filling layer 40 makes it possible in particular to fill the spaces between the sides 201 of the islets 2A, 2B. .

[0075] As illustrated in [Fig. 6], the excess thickness of the filler layer 40 is then removed, for example and in a known manner, by chemical-mechanical polishing (CMP) with a stop on the SiN-based stop layer. Only the portions of layer 40 located between the flanks 201 of the islands 2A, 2B are retained after the CMP process.

[0076] As illustrated in [Fig. 7], the gates 33 can then be formed on the surface of the islands 2A, 2B. The gates 33 can result from etching the p-GaN-based layer present on the barrier layer 22 (as in the case of p-GaN gate transistors). Alternatively, the gates 33 can be formed by depositing a gate metal followed by lithography / etching steps. According to one possibility, trenches can be pre-formed through the barrier layer 22, down into the GaN of the islands 2A, 2B, and then lined with a gate dielectric before the gate metal is deposited in the trenches. Buried or semi-buried gates can thus be produced. (case of buried gate MOS transistors). Other gate structures 33 can be considered, depending on the targeted lateral transistor architectures.

[0077] As illustrated in [Fig.8], the source 32 and drain 31 contacts are then formed on either side of the grids 33. The formation of the sources and drains 31, 32 can be done in a conventional way by Ti / Al deposition followed by annealing and lithography / etching.

[0078] As illustrated in [Fig. 9], a SiO2-based layer 41 is then deposited to insulate the contacts 31, 32, 33 from each other. A planarization step by CMP is preferably also carried out.

[0079] As illustrated in [Fig.10], via openings 410 are then formed by engraving layer 41 directly above grids 33.

[0080] As illustrated in [Fig. 1 1], the via openings 410 are then filled with a metal to form the vias 331. Metallic tracks 330 connecting the vias 331 are also formed on the surface of the layer 41. The formation of the vias 331 and the metallic tracks 330 can be done by a single step of metal deposition, followed by lithography / etching to define the metallic tracks 330.

[0081] As illustrated in [Fig.12], a SiO2-based layer 42 is then deposited on the layer 41 and on the metal tracks 330, to isolate the metal tracks 330. A planarization step by CMP is preferably also carried out.

[0082] As illustrated in [Fig. 13], via openings 421 are then formed by engraving layers 42, 41 directly above drains 31. Via openings 422 are also formed by engraving layers 42, 41 directly above sources 32.

[0083] As illustrated in [Fig. 14], the via openings 421, 422 are then filled with metal to form vias 311, 321, respectively. Vias 311 connect drains 31, and vias 321 connect sources 32. Excess metal can be removed by CMP before the formation of metal traces 310, 320.

[0084] As illustrated in [Fig.15], metallic tracks 310, 320 connecting the vias 311, 321 respectively are then formed on the surface of the layer 42. According to one possibility, when the height or aspect ratio of the vias 311, 321 allows it, the formation of the vias 311, 321 and the metallic tracks 310, 320 can be done by a single step of metal deposition, followed by lithography / etching to define the metallic tracks 310, 320.

[0085] As illustrated in [Fig. 16], a SiO2-based layer 43 is then deposited on the layer 42 and on the metal tracks 310, 320, to isolate the metal tracks 310, 320. A planarization step by CMP is preferably also carried out.

[0086] Power devices, here concentric lateral HEMT transistors, are thus advantageously formed on islands 2A, 2B. The voltage withstand capability of these power devices is improved. The fabrication and integration of these power devices can advantageously be carried out by standard processes of the microelectronics industry. The invention is not limited to the embodiments described above.

Claims

Demands

1. A microelectronic device comprising: - A substrate (1) based on at least one semiconductor material, - An island (2) based on gallium nitride (GaN) protruding from the substrate and having a so-called upper face (200) and flanks (201) surrounding the island, - At least one first contact (31), for example a drain or a cathode, on the upper face (200) of the island (2), - At least one second contact (32), for example a source or an anode, the device being characterized in that the at least one second contact (32) is disposed on the upper face (200) of the island (2) and along an edge (202) of said upper face (200), such that the at least one second contact (32) at least partially surrounds the at least one first contact (31), and in that the at least one second contact (32) and substrate (1) are configured to be polarized according to the same polarization during operation of the device.

2. Device according to the preceding claim further comprising a barrier layer (22), for example based on AlGaN, on the upper face (200) of the island (2).

3. Device according to the preceding claim in which at least one first contact (31) and at least one second contact (32) are disposed on the barrier layer (22).

4. Device according to any one of the preceding claims wherein the at least one second contact (32) totally surrounds the at least one first contact (31) and forms a closed contour around the at least one first contact (31).

5. Device according to any one of the preceding claims wherein the island (2) has a height h2 greater than or equal to 5 pm, preferably greater than or equal to 10 pm.

6. Device according to any one of the preceding claims comprising a plurality of first contacts (31) and a plurality of second contacts (32), the first and second contacts (31, 32) being arranged concentrically on the upper face (200) of the island (2).

7. Device according to any one of the preceding claims wherein the first and second contacts (31, 32) correspond respectively to a cathode and an anode, and the second contact (32) forms a Schottky contact with the island (2), so that the device comprises at least one Schottky diode-type structure.

8. Device according to the preceding claim comprising at least a first anode (32a) at the center of the island and, concentrically, a first cathode (31a) totally surrounding the first anode (32a), a second anode (32b) totally surrounding the first cathode (31a), a second cathode (31b) totally surrounding the second anode (32b), and a third anode (32c) disposed along the edge (202) of the upper face (200) of the island and totally surrounding the second cathode (31b), so that the device comprises four concentric lateral Schottky diodes, interconnected in parallel.

9. Device according to any one of claims 1 to 6 comprising at least one third contact (33), for example a grid, disposed on the upper face (200) of the island (2) between at least one first contact (31) and at least one second contact (32), so that the device comprises at least one transistor-type structure.

10. Device according to the preceding claim comprising a plurality of first, second and third contacts (31, 32, 33) arranged concentrically on the upper face (200) of the island, such that the device comprises at least two parallel lateral transistors interconnected via at least one of the first and second contacts (31, 32).

11. Device according to any one of the preceding claims wherein the edge (202) of the island forms a hexagonal contour for the upper face (200) of the island.

12. System comprising a plurality of devices according to any one of the preceding claims, adjacent to each other, wherein the substrate (1) is common to all the devices and the islands (2A, 2B, 2C) of the devices are separated from each other by a distance of less than 10 pm, between two flanks (201) of two adjacent islands (2A, 2B).

13. System according to the preceding claim in which the islands (2A, 2B, 2C) have a hexagonal shape, and are arranged on the substrate (1) according to a hexagonal tiling.

14. A method for manufacturing at least one device according to any one of claims 1 to 11, comprising the following steps: - Forming by localized epitaxy at least one GaN-based island (2A, 2B, 2C) on a substrate (1) based on at least one semiconductor material, - Forming at least one first contact (31) on the upper face (200) of said at least one island, - Forming at least one second contact (32) on the upper face (200), at the edge of said at least one island (2A, 2B, 2C)

15. A method according to the preceding claim in which the localized epitaxial formation is configured so that at least one island (2A, 2B, 2C) has a height h2 greater than or equal to 5 pm, preferably greater than or equal to 10 pm.

16. A method according to any one of the two preceding claims wherein the at least one island comprises a plurality of islands (2A, 2B, 2C) separated from each other by a distance of less than 10 pm, between two flanks (201) of two adjacent islands (2A, 2B).

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