CFET-type transistor device

Abstract

CFET-type transistor device This description relates to a CFET transistor device (100), comprising: - a substrate (102); - a first semiconductor nanosheet (104) and a second semiconductor nanosheet (106); - an insulating layer (108) disposed between the first and second nanosheets; - a first gate (110) disposed around a first part (112) of the first nanosheet, and a second gate (114) disposed around a first part (116) of the second nanosheet; - first internal spacers (128) disposed against second parts (130) of the first nanosheet between which the first part of the first nanosheet is disposed, and - second internal spacers (132) disposed against second parts (134) of the second nanosheet between which the first part is disposed;and in which the first and second internal spacers comprise first and second dielectric materials with low permittivity and different from each other. Figure for the abstract: Fig. 1;

Description

Title of the invention: CFET-type transistor device technical field

[0001] This description relates generally to the field of CFET type transistor devices (“Complementary Field-Effect Transistor” in English, or complementary field-effect transistor). Previous technique

[0002] A CFET transistor device comprises N-type and P-type FET transistors stacked one above the other, or one above the other, and whose channels are formed by stacked semiconductor nanosheets. The gates of these transistors surround the portions of the semiconductor nanosheets that form the transistor channels, in a manner analogous to GAA (Gate-Around) transistors.

[0003] Such CFET transistor devices are, for example, made from a stack of layers comprising alternating first and second layers of materials that can be selectively etched relative to each other, for example, first layers of silicon and second layers of SiGe. An insulating layer is disposed between those intended to form part of the N-type transistor(s) and those intended to form part of the P-type transistor(s). Selective etching is implemented such that remaining portions of the first or second layers are intended to form the channels of the transistors as well as interface regions, or LDD (Lightly Doped Drain) and LDS (Lightly Doped Source) regions intended to be disposed between the channels and the source or drain regions that are subsequently fabricated.In such transistors, internal spacers are formed around these interface regions. Such transistors are described, for example, in documents US 2021 / 265345 AL and US 2022 / 020646 AL.

[0004] However, the structures of the CFET transistor devices described above have the drawback that the N-type and P-type transistors have channels made of the same semiconductor material. Furthermore, in these structures, the electrostatic properties of the P-type transistors are necessarily similar to those of the N-type transistors, given the manufacturing process used. Finally, the two transistors, N-type and P-type, also have the same crystallographic orientation, which does not allow for the optimization of both electron transport for the N-type transistor and hole transport for the P-type transistor. Summary of the invention

[0005] There is a need to propose a CFET transistor device that does not have at least some of the above disadvantages, and in particular allows a dissociation of the electrical and / or electrostatic properties of the N-type transistor(s) from those of the P-type transistor(s).

[0006] One embodiment overcomes all or part of these drawbacks and proposes a complementary field-effect transistor device, comprising:

[0007] - a substrate;

[0008] - at least a first semiconductor nanosheet and at least a second semiconducting nanosheet, the first semiconducting nanosheet being arranged between the second semiconducting nanosheet and the substrate;

[0009] - an insulating layer disposed between the first and second semi- nanosheets drivers;

[0010] - a first grid arranged around a first part of the first nanosheet semiconductor, and a second grid arranged around a first part of the second semiconductor nanosheet;

[0011] - of the first internal spacers arranged against the second parts of the first semiconductor nanosheet between which is arranged the first part of the first semiconductor nanosheet, and

[0012] - second internal spacers arranged against second parts of the second semiconductor nanosheet between which is arranged the first part of the second semiconductor nanosheet;

[0013] and wherein the first and second internal spacers comprise respectively first and second dielectric materials with low permittivity, the first and second dielectric materials being different from each other.

[0014] According to a particular embodiment, the first and second semiconductor nanosheets comprise first and second semiconductor materials that are different from each other.

[0015] According to a particular embodiment, the first and second grids respectively comprise first and second metallic materials different from each other.

[0016] According to a particular embodiment, at least a part of the first grid is in contact with at least a part of the second grid, or the first and second grids are dissociated and isolated from each other.

[0017] According to a particular embodiment, when the first and second grids are dissociated and isolated from each other, each of the first and second grids has a comb-like shape.

[0018] A method for implementing a complementary field-effect transistor device is also proposed, comprising at least:

[0019] - realization of a structure comprising at least one substrate, first and second semiconducting nanosheets, the first semiconducting nanosheet being arranged between the second semiconducting nanosheet and the substrate, and an insulating layer arranged between the first and second semiconducting nanosheets;

[0020] - realization of first internal spacers arranged against second parts of the first semiconductor nanosheet, and of second internal spacers arranged against second parts of the second semiconductor nanosheet, the first and second internal spacers comprising respectively first and second dielectric materials with low permittivity, the first and second dielectric materials being different from each other, and such that the first internal spacers are made before or after the second internal spacers;

[0021] - creation of a first grid around a first part of the first a semiconducting nanosheet arranged between the second parts of the first semiconducting nanosheet, and a second grid around a first part of the second semiconducting nanosheet arranged between the second parts of the second semiconducting nanosheet.

[0022] According to a particular embodiment, the construction of the structure comprises at least:

[0023] - realization of a first stacking of layers comprising at least a first semiconducting layer arranged between two first sacrificial layers of material suitable for being selectively etched with respect to the first semiconducting layer, and comprising a first dielectric layer;

[0024] - realization of a second stacking of layers comprising at least one second semiconductor layer disposed between two sacrificial second layers of material suitable for being selectively etched with respect to the second semiconductor layer, and comprising a second dielectric layer;

[0025] - bonding of the first and second dielectric layers to each other and together forming the insulating layer.

[0026] According to a particular embodiment, the construction of the structure further comprises, after the joining of the first and second dielectric layers to each other, an engraving of at least one trench carried out through the first and second stacks of layers and the insulating layer.

[0027] According to a particular embodiment, the implementation of the second internal spacers comprises at least:

[0028] - construction of a sacrificial grid in the trench and on remaining portions of the structures obtained after the trench engraving, then

[0029] - fabrication of grid spacers around the sacrificial grid, then

[0030] - engraving parts of the remaining portions of the structure not covered by the grid sacrificial and grid spacers, through the layers of the second stack and a first part of the insulating layer without crossing a bonding interface between the first and second dielectric layers, then

[0031] - engraving of parts of remaining portions of the second sacrificial layers arranged against the second parts of the second semiconductor nanosheet, then

[0032] - fabrication of a layer of the second low permittivity dielectric material such that portions of this layer arranged against second parts of the second semiconductor nanosheet form the second internal spacers.

[0033] According to a particular embodiment, the fabrication of the first internal spacers comprises at least, after the fabrication of the layer of the second low permittivity dielectric material:

[0034] - engraving of parts of the remaining portions of the structure not covered by the sacrificial grid, grid spacers and by parts of the second layer of low permittivity dielectric material which rest on a second part of the insulating layer comprising the bonding interface and which cover the ends of the second parts of the second semiconductor nanosheet, through the layers of the first stack and the second part of the insulating layer, then

[0035] - engraving of parts of remaining portions of the first sacrificial layers arranged against the second parts of the first semiconductor nanosheet, then

[0036] - fabrication of a layer of the first low permittivity dielectric material such that portions of this layer arranged against second parts of the first semiconductor nanosheet form the first internal spacers.

[0037] According to a particular embodiment, the method further comprises, between the realization of the first and second internal spacers and the realization of the first and second grids:

[0038] - creation of initial source or drain regions against the ends of the second parts of the first semiconductor nanosheet, then

[0039] - removal of parts of the layer of the second dielectric material with low permittivity covering the ends of the second parts of the second semiconductor nanosheet, then

[0040] - creation of second source or drain regions against the ends of the second parts of the second semiconductor nanosheet.

[0041] According to a particular embodiment, the realizations of the first and second source or drain regions each include the implementation of an epitaxy, and the process further includes, between the realizations of the first and second source or drain regions, a deposit of an insulating material covering at least the first source and drain regions.

[0042] According to a particular embodiment, the process further comprises, between the making of the first and second internal spacers and the making of the first and second grids or during the making of the first and second grids, an engraving of the remaining portions of the first and second sacrificial layers.

[0043] According to a particular embodiment, the making of the first and second grids comprises an engraving of the sacrificial grid, then successive deposits of at least one first metallic material forming the first grid and of at least one second metallic material different from the first metallic material and forming the second grid, and such that at least a part of the first grid is in contact with at least a part of the second grid.

[0044] According to a particular embodiment, the construction of the first and second grids comprises:

[0045] - an engraving of a first part of the sacrificial grid so as to form a access to the first part of the second semiconductor nanosheet, then

[0046] - a deposit of materials forming the second grid, then

[0047] - an engraving of a second part of the sacrificial grid so as to form a access to the first part of the first semiconductor nanosheet, then

[0048] - a deposit of materials forming the first grid such as the first and second grids should be separated and isolated from each other. Brief description of the drawings

[0049] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0050] - Fig. 1 schematically represents a perspective and cross-sectional view of a CFET transistor device according to a first embodiment;

[0051] - Figure 2 schematically represents a perspective and cross-sectional view of a CFET transistor device according to a second embodiment;

[0052] - [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9], [Fig.10], [Fig.11], [Fig.12], [Fig.13], [Fig.14], [Fig.15], [Fig.16], [Fig. 17], [Fig. 18] and [Fig. 19] represent steps in a process for making a CFET transistor device according to the first embodiment;

[0053] - Fig. 20, Fig. 21, Fig. 22 and Fig. 23 represent part of the steps of a method for making a CFET transistor device according to the second embodiment. Description of the implementation methods

[0054] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0055] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0056] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0057] Throughout the document, the terms "conductor" and "insulator" are used to refer to electrical conduction and electrical insulation, respectively.

[0058] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation as shown in the figures, in a normal operating position of the device.

[0059] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0060] An example of an embodiment of a CFET transistor device 100 according to a first embodiment is described below in relation to [Fig.1].

[0061] The device 100 comprises a substrate 102 on which the various parts and elements of the device 100 are arranged. For example, the layer of the substrate 102 on which the various parts and elements of the device 100 are arranged may correspond to the buried dielectric layer, or BOX (Buried Oxide), of a semiconductor-on-insulator substrate, for example SOI (Silicon on Insulator), or to a Shallow Trench Isolation (STI) region formed, for example, in a bulk semiconductor substrate, for example, silicon. Alternatively, another type of substrate 102 may be used for the embodiment of the device 100.

[0062] The device 100 further comprises at least one first semiconductor nanosheet 104 and at least one second semiconductor nanosheet 106 such that the first semiconductor nanosheet 104 is disposed between the second semiconductor nanosheet 106 and the substrate 102. In the example of [Fig. 1], the device 100 comprises several stacks of several first semiconductor nanosheets 104, above each of which is disposed a stack of several second semiconductor nanosheets 106. In the example of [Fig. 1], the stacks of the first and second semiconductor nanosheets 104, 106 are arranged, in a plane of the face of the substrate 102 on which the stacks of semiconductor nanosheets 104, 106 are disposed, in lines (for example, parallel to the X-axis of the [Fig.l]) and in columns (for example parallel to the Y axis of the [Fig.l]).

[0063] According to one embodiment, the first and second semiconductor nanosheets 104, 106 comprise first and second semiconductors that are different from each other, respectively. For example, the first semiconductor may be silicon, and the second semiconductor may be SiGe. The first and second semiconductor nanosheets 104, 106 may, however, comprise other examples of semiconductors, such as Ge, GeSn, or semiconductor oxides (IGZO, IWO, ITO, etc.) or other III-V materials (InAS, InGaAs, for example). According to another embodiment, the first and second semiconductor nanosheets 104, 106 comprise identical first and second semiconductors.

[0064] In a particular configuration, the crystal orientations of the first and second semiconductors may be different from each other. For example, when the first semiconductor of the first semiconductor nanosheets 104 is intended to form the channel of at least one NFET transistor, its crystal orientation may be along the (100) plane and the

[100] direction, which promotes electron transport in this first semiconductor. When the second semiconductor of the second semiconductor nanosheets 106 is intended to form a PFET transistor, its crystal orientation may be along the (110) plane and the

[110] direction, which promotes hole transport in this second semiconductor.

[0065] According to one embodiment, the thickness (dimension parallel to the Z-axis in the example of [Fig. 1]) of each of the first and second semiconductor nanosheets 104, 106 can be between 5 nm and 20 nm. Furthermore, the length (dimension parallel to the Y-axis in the example of [Fig. 1]) of each of the first and second semiconductor nanosheets 104, 106 can be between 15 nm and 50 nm. Finally, the width (dimension parallel to the X-axis in the example of [Fig. 1]) of Each of the first and second semiconducting nanosheets 104, 106 can be between 10 nm and 150 nm.

[0066] The device 100 also includes an insulating layer 108 disposed between the first and second semiconductor nanosheets 104, 106. In the example of [Fig. 1], the insulating layer 108 is disposed between the stacks of the first semiconductor nanosheets 104 and the stacks of the second semiconductor nanosheets 106. According to one embodiment, the insulating layer 108 may comprise SiO2 and have a thickness (dimension parallel to the Z-axis in the example of [Fig. 1]) for example between 10 nm and 100 nm. Alternatively, the insulating layer 108 may comprise other examples of dielectric material and / or a thickness different from that indicated above.

[0067] The device 100 also includes a first gate 110 arranged around a first portion 112 of the first semiconductor nanosheet 104, and a second gate 114 arranged around a first portion 116 of the second semiconductor nanosheet 106. In the example of [Fig. 1], the first gate 110 is arranged around the first portions 112 of each of the first semiconductor nanosheets 104, and the second gate 114 is arranged around the first portions 116 of each of the second semiconductor nanosheets 106. The first portions 112, 116 of the first and second semiconductor nanosheets 104, 106 form the channels of the transistor(s) of the device 100. The first and second gates 110, 114 can be viewed as forming at least partially enclosing gates.

[0068] In the described embodiment, the first and second grids 110, 114 respectively comprise first and second metallic materials 118, 120 of a different nature. In the first embodiment described, the first and second metallic materials 118, 120 are specifically such that they exhibit a different work function.

[0069] In the example of [Fig. 1], portions 122 of the first gate 110 are in contact with portions 124 of the second gate 114, these portions 122, 124 serving to provide electrical access to the gates 110, 114. In the example of [Fig. 1], these portions 122, 124 are located between the rows and columns of stacks of the first and second semiconductor nanosheets 104, 106. In this example, because the portions 122, 124 of the gates 110, 114 are in contact with each other, they form a common gate for the transistors of the device 100. The first and second metallic materials 118, 120 may comprise TiN and W respectively, or any other suitable material such as at least one of the following materials: Al, Ni, Ti, TaN, TiC, TaC, etc.

[0070] Following the example of [Fig. 1], the first and second grids 110, 114 also include a grid dielectric 126 interposed between the first and second metallic materials 118, 120 and the other elements of the device 100. In the described embodiment, the grid dielectric 126 is common to the first and second grids 110, 114. Alternatively, the grid dielectric of the first grid 110 could be formed from distinct portions that are not continuous with respect to those of the grid dielectric of the second grid 114. For example, the grid dielectric 126 could comprise a high-permittivity dielectric material such as HfSiO4, HfO2, La2O3, LaAlO3, ZrO2, ZrSiO4, Ta2O5, TiO2, SrTiO3, AlO2O3. A high-permittivity dielectric material ("High k dielectric") could correspond to a dielectric material whose dielectric permittivity is greater than that of SiO2, for example, greater than 3.9.

[0071] The device 100 also includes first internal spacers 128 arranged against second parts 130 of the first semiconductor nanosheet 104 (of each of the first semiconductor nanosheets 104 in the example of [Fig.1]) between which is arranged the first part 112 of the first semiconductor nanosheet 104 (of each of the first semiconductor nanosheets 104 in the example of [Fig.1]). The device 100 further includes second internal spacers 132 arranged against second parts 134 of the second semiconductor nanosheet 106 (of each of the second semiconductor nanosheets 106 in the example of [Fig. 1]) between which is arranged the first part 116 of the second semiconductor nanosheet 106 (of each of the first semiconductor nanosheets 106 in the example of [Fig. 1]). In the example of [Fig.[l], the first and second parts 112, 130 of each first semiconductor nanosheet 104 and the first and second parts 116, 134 of each second semiconductor nanosheet 106 are symbolically separated by dashed lines. In addition, in the example of [Fig.l], the first internal spacers 128 are arranged around the second parts 130 of each of the first semiconductor nanosheets 104, and the second internal spacers 132 are arranged around the second parts 134 of each of the second semiconductor nanosheets 106.

[0072] The first and second internal spacers 128, 132 comprise, respectively, first and second low-permittivity dielectric materials ("low k dielectric") that are different from each other, i.e., dielectric materials whose permittivity is less than or equal to that of silicon nitride. For example, the internal spacers 128, 132 may comprise at least one of the following materials: SiN, SiOCN, SiBCN, SiOC, SiCN, SiO2. The use of such low-permittivity dielectric materials for the fabrication of the internal spacers 128, 132 has the advantage of reducing the parasitic capacitances of the transistors of device 100.

[0073] As in [Fig. 1], the device 100 also includes first source or drain regions 136 extending from the ends of the second parts 130 of the first semiconductor nanosheets 104, and second source or drain regions 138 extending from the ends of the second parts 134 of the second semiconductor nanosheets 106. For example, the first or second source or drain regions 136, 138 may include phosphorus-doped silicon when intended to be part of an N-type transistor, or may include boron-doped SiGe when intended to be part of a P-type transistor.

[0074] As in [Fig. 1], the device 100 also includes gate spacers 137, as well as an insulating material 139 arranged between the stacking rows of semiconductor nanosheets 104, 106. The internal spacers 128, 132 are arranged directly above the gate spacers 137. The gate spacers 137 may include a low permittivity dielectric material, for example, identical or different from that of the internal spacers 128, 132, thus contributing to the reduction of parasitic capacitances of the transistors in the device 100. As an example, the insulating material 139 may include a dielectric material such as SiO2 or SiN.

[0075] Following the example of [Fig. 1], the first semiconductor nanosheets 104, the first gate 110, the first internal spacers 128, and the first source or drain regions 136 form at least one first FET transistor of a first type of conductivity, for example, an NFET transistor. Furthermore, the second semiconductor nanosheets 106, the second gate 114, the second internal spacers 132, and the second source or drain regions 138 form at least one second FET transistor of a second type of conductivity opposite to the first type of conductivity, for example, a PFET transistor.

[0076] An example of an embodiment of a CFET 100 transistor device according to a second embodiment is described below in relation to [Fig.2].

[0077] Unlike the first embodiment, the first and second grids 110, 114 are here dissociated and isolated from each other. In other words, the first and second grids 110, 114 are not in contact with each other. This dissociation and isolation are achieved by making the portions 122, 124 serving for the electrical contact of these grids 110, 114 in different trenches formed between the rows or columns of the stacks of the semiconductor nanosheets 104, 106 (between the columns of the stacks of the semiconductor nanosheets 104, 106 in the example of [Fig. 2]). In this configuration, insulating portions 135, including for example SiN or any other suitable dielectric material, allow to electrically isolate part 122 of the first grid 110 from the second semiconducting nanosheets 106.

[0078] In this second embodiment, the first and second gates 110, 114 can be comb-shaped, as in the example in [Fig. 2], with the semiconductor nanosheets 104, 106 arranged between the teeth of these combs. Furthermore, in this configuration, for each transistor, one side of the channel is not covered by the gate 110, 114 of that transistor.

[0079] The other features and elements of the device 100 according to the second embodiment are similar or identical to those of the first embodiment.

[0080] An example of a method for implementing device 100 according to the first embodiment is described below in relation to figures 3 to 19.

[0081] First, a structure 140 comprising at least the substrate 102, the first and second semiconducting nanosheets 104, 106 and the insulating layer 108 is made.

[0082] This structure 140 can be obtained by first creating a first stack of layers comprising at least one first semiconductor layer 142 arranged between two first sacrificial layers 144 of material suitable for selective etching with respect to that of the first semiconductor layer 142, the first stack also comprising a first dielectric layer 143. The first dielectric layer 143 comprises, for example, SiO2 obtained by thermal oxidation. In the example described, since the device 100 is intended to comprise several stacked first semiconductor nanosheets 104, the first stack comprises several first semiconductor layers 142 from which the first semiconductor nanosheets 104 are intended to be produced, each of the first semiconductor layers 142 being arranged between two first sacrificial layers 144.Furthermore, in this embodiment example, this first stacking is carried out on the substrate 102 such that the first semiconducting layers 142 and the first sacrificial layers 144 are arranged between the substrate 102 and the first dielectric layer 143.

[0083] In this example, a second stack of layers comprising at least one second semiconductor layer 146 disposed between two sacrificial second layers 148 of material suitable for selective etching with respect to that of the second semiconductor layer 146 is also made, the second stack also comprising a second dielectric layer 150. The second dielectric layer 150 comprises, for example, SiO2 obtained by thermal oxidation. In the example described, given that the device 100 is intended to comprise several second stacked semiconductor nanosheets 106, the second stack comprises several second semiconductor layers 146 from which the second semiconductor nanosheets 106 are intended to be made, each of the second semiconductor layers 146 being disposed between two sacrificial second layers 148. According to one example, this second stack can be made on another substrate such that the second semiconductor layers 146 and the second sacrificial layers 148 are disposed between this other substrate and the second dielectric layer 150.

[0084] According to a particular embodiment, the first sacrificial layers 144 may comprise SiGe, and the first semiconductor layers 142 may comprise silicon or SiGe with a germanium concentration lower than that of the SiGe in the first sacrificial layers 144. For example, the first sacrificial layers 144 may comprise SiO,7Geo,3 and the first semiconductor layers 142 may comprise Si. Furthermore, the second sacrificial layers 148 may comprise SiGe, and the second semiconductor layers 146 may comprise silicon or SiGe with a germanium concentration lower than that of the SiGe in the second sacrificial layers 148. For example, the second sacrificial layers 148 may comprise SiO,4Ge,6 and the second semiconductor layers 146 may comprise SiO > 7GeO > 3.These examples allow, in particular, the implementation of selective etching of the first sacrificial layers 144 with respect to the first semiconductor layers 142, and selective etching of the second sacrificial layers 148 with respect to the second semiconductor layers 146. Alternatively, other materials that can be selectively etched with respect to each other can be used for the layers of the first and second stacks.

[0085] In this particular embodiment of the structure 140, the first and second dielectric layers 143, 150 are then bonded together to form the insulating layer 108. The bonding interface between the first and second dielectric layers 143, 150 is designated by reference numeral 152. The substrate used for the second stacking can then be removed, and the substrate 102 is retained to serve as support. The layer stack obtained at this stage of the process is shown in [Fig. 3].

[0086] The resulting layer stack can then be etched to form trenches 154 through the layer stacks 142, 144, 146, 148 and the insulating layer 108 and to delimit the semiconducting nanosheets 104, 106 in a first direction (along the X-axis in the example described). This etching is stopped on the substrate 102. The resulting structure 140 is shown in [Fig. 4].

[0087] The process then involves the successive realization of the first and second internal spacers 128, 132. In the described embodiment example, the second internal spacers 132 are realized before the first internal spacers 128.

[0088] To produce the second internal spacers 132, a sacrificial grid 156 is first created on the remaining portions of the structure 140 obtained after the etching process carried out through the stacks of layers 142, 144, 146, 148 and the insulating layer 108. For example, the sacrificial grid 156 can be produced by first depositing an oxide, for example SiO2, followed by a deposit of polysilicon or amorphous silicon. These layers can then be etched according to the desired pattern for the sacrificial grid 156. An etching mask 158 comprising, for example, SiN can be used for this etching. The assembly obtained at this stage of the process is shown in [Fig. 5].

[0089] The grid spacers 137 can then be formed around the sacrificial grid 156. The material deposited to form the grid spacers 137, which covers parts of the stack not intended to be covered by the grid spacers, can then be removed by etching, for example by using a dry etching process such as anisotropic plasma etching with at least one of the following gases: CF4 / O2 / N2, CF4 / CH4, SFf / CH4, NF3 / CH4. The remaining material then forms the grid spacers 137.

[0090] In the described embodiment, etching of portions of the remaining sections of the structure 140 not covered by the sacrificial grid 156 and the grid spacers 137 can then be carried out through the second semiconductor layers 146 and the second sacrificial layers 148 and a first part of the insulating layer 108 without crossing the bonding interface 152. This etching makes it possible to form, in particular, the second semiconductor nanosheets 106, each arranged between two remaining portions 160 of the second sacrificial layers 148. The fact that the etching is not carried out through the bonding interface 152 avoids, in particular, exposing this interface to the etching chemistries used subsequently. The structure obtained at this stage of the process is shown in [Fig. 6].

[0091] In the described embodiment, an etching of portions of the remaining portions 160 of the second sacrificial layers 148 arranged against the second portions 134 of the second semiconductor nanosheets 106 is then carried out. Moreover, this etching is carried out here in such a way that it is selective with respect to the second semiconductor nanosheets 106. This etching forms cavities 162 in which the second internal spacers 132 will subsequently be made. Furthermore, the duration of this etching determines the lengths of the cavities 132 along the second semiconductor nanosheets 106, and also the channel length formed by these second semiconducting nanosheets 106. The structure obtained at this stage of the process is shown in [Fig.7].

[0092] In the described embodiment, a layer 164 of the second low-permittivity dielectric material is deposited such that portions of this layer 164, positioned against second portions 134 of the second semiconducting nanosheets 106, i.e., within the cavities 162, form the second internal spacers 132. Depending on the nature of the material deposited to form this layer 164, the deposit may, for example, be of the ALD (Atomic Layer Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), or PECVD (Plasma-Enhanced Chemical Vapor Deposition) type. The second low-permittivity dielectric material of the layer 164 may be the same as, or different from, that used to fabricate the gate spacers 137.

[0093] Anisotropic etching can then be carried out to remove parts of layer 164 deposited on the insulating layer 108. This etching corresponds, for example, to dry etching carried out using, for example, a gas mixture of the type CH2F2 / O2 / CH4 / Ar or a plasma of the type CH3F / O2 / He. Alternatively, it is possible to carry out anisotropic modification of layer 164 by an H2 or He type plasma, followed by wet etching carried out using, for example, hydrofluoric acid, or Hf in vapor form, or an NH3 / NF3 type plasma. It is also possible to implement a second isotropic etching in order to reduce the thickness of the layer 164, for example a wet etching using a dilute solution of hot hydrofluoric acid or phosphoric acid, this second isotropic etching being implemented without uncovering the second semiconductor nanosheets 106.

[0094] The structure obtained at this stage of the process is shown in [Fig.8].

[0095] The first internal spacers 128 are then made. For this purpose, in the example of embodiment described, an etching of parts of the remaining portions of the structure not covered by the sacrificial grid 156, by the grid spacers 137 and by parts of the layer 164 of the second low permittivity dielectric material can be carried out through the layers 142, 144 and a second part of the insulating layer 108 including the bonding interface 152 (see [Fig.9]).

[0096] An etching of parts of the remaining portions 166 of the first sacrificial layers 144 arranged against the second parts 130 of the first semiconductor nanosheets 104 can then be carried out. This etching is implemented here in such a way that it is selective with respect to the first semiconductor nanosheets 104. This etching forms cavities 168 in which the first spacers internal 128 will be produced subsequently. In addition, the duration of this etching determines the lengths of the cavities 168 along the first semiconductor nanosheets 104, and also the channel length formed by these first semiconductor nanosheets 104. In particular, it is possible that the channel length formed by the first semiconductor nanosheets 104 is different from that of the channel formed by the second semiconductor nanosheets 106. The structure obtained at this stage of the process is shown in [Fig. 10].

[0097] In the described embodiment, a layer of the first low-permittivity dielectric material is deposited such that portions of this layer, positioned against second portions 130 of the first semiconductor nanosheets 104, i.e., in the cavities 168, form the first internal spacers 128. Depending on the material used to form the first internal spacers 128, the deposited material may, for example, be of the ALD, LPCVD, or PECVD type. The first low-permittivity dielectric material used may be the same as, or different from, that used to fabricate the gate spacers 137 and that used to fabricate the second internal spacers 132.

[0098] An isotropic etching can then be implemented to remove the parts of the layer of the first low permittivity dielectric material that are outside the cavities 168 and that do not form the first internal spacers 128 (see [Fig. 11]).

[0099] Thus, the various elements present above the insulating layer 108, in particular the second semiconducting nanosheets 106 and the second internal spacers 132, are protected during the steps implemented for the realization of the first internal spacers 128 since the parts of the layer 164 located outside the cavities 162 are preserved and protect these elements.

[0100] In the described embodiment, the first source or drain regions 136 are then made in contact with the ends of the second portions 130 of the first semiconductor nanosheets 104 (see [Fig. 12]). In the described example, these first source or drain regions 136 are made by implementing epitaxy. This epitaxy does not impact the second semiconductor nanosheets 106 or the portions 160 because of the layer 164 covering them during the implementation of this epitaxy.

[0101] In the described example, a dielectric layer intended to form the insulating material 139 is then deposited in the trenches 154, covering the first source or drain regions 136. An etching is then carried out to remove the parts of this layer in contact with the layer 164. Alternatively, thermal oxidation of the first source or drain regions 136 can be carried out. A partial etching of the layer 164 is then carried out so as to retain only the second internal spacers 132 and in particular remove the parts of this layer 164 covering the ends of the second semiconducting nanosheets 106 (see [Fig. 13]).

[0102] In the example described, the second source or drain regions 138 are then made in contact with the ends of the second parts 134 of the second semiconducting nanosheets 106. As with the first source or drain regions 136, the second source or drain regions 138 can be obtained by implementing epitaxy.

[0103] A dielectric layer intended to form the insulation material 139 can then be deposited in the remaining empty spaces of the trenches 154, thus covering the second source or drain regions 138. A chemical-mechanical planarization (CMP) of the material deposited outside the trenches 154 can be implemented with a stop on the mask 158 (see figures 14 and 15).

[0104] In the example described, the mask 158 is then removed, for example by implementing a dry or wet etching process. A portion of the sacrificial grid 156 located at a level above the bonding interface 152 can then be removed. In the example described, only the polysilicon or amorphous silicon of the sacrificial grid 156 is removed, the oxide of the sacrificial grid 156 being retained (see [Fig. 16]).

[0105] The oxide of the sacrificial grid 156 which is no longer covered by the polysilicon or amorphous silicon of the sacrificial grid 156 can then be etched, and then the remaining polysilicon or amorphous silicon of the sacrificial grid 156 can be etched (see [Fig.17]).

[0106] In the described embodiment, the remaining portions 160 of the second sacrificial layers 148 are selectively etched with respect to the second semiconductor nanosheets 106 (see [Fig. 18]). During this etching, the first semiconductor nanosheets 104 and the remaining portions 166 of the first sacrificial layers 144 are protected by the remaining oxide of the sacrificial grid 156 covering these elements.

[0107] A protective layer 170 can then be formed around the second semiconductor nanosheets 106. This protective layer 170 can correspond to a thin layer of semiconductor formed by epitaxy, for example comprising the same material as that of the first semiconductor nanosheets 104. Alternatively, this protective layer 170 can be produced by thermal oxidation. The remaining oxide of the sacrificial grid 156 can then be etched, and then the remaining portions 166 of the first sacrificial layers 144 can be selectively etched with respect to the first semiconductor nanosheets 104 ([Fig. 19]).

[0108] The first and second grids 110, 114 are then produced. In the example described, the grid dielectric 126 is first deposited, for example by applying one of the following deposition methods is used: CVD (Chemical Vapor Deposition), LPCVD, APCVD (Atmospheric Pressure Chemical Vapor Deposition), PECVD, or ALD. The first metallic material 118 can then be deposited. Wet or dry etching can then be used to remove the portions of the first metallic material that are not intended to form the first grid 110. The second metallic material 120 is then deposited to complete the formation of the second grid 114. CMP can then be used to remove unwanted portions of the deposited second metallic material 120. The deposition methods used to deposit the first and second metallic materials 118 and 120 can be of the CVD, LPCVD, APCVD, PECVD, or ALD type. The resulting device 100 corresponds to the one previously described in relation to [Fig. 1].

[0109] An example of a method for implementing device 100 according to the second embodiment is described below with reference to Figures 20 to 23.

[0110] Steps analogous to those previously described in connection with Figures 1 to 15 are first implemented. In this example, the first and second semiconductor nanosheets 104, 106 are formed from a stack of layers comprising a single first semiconductor layer 142 and a single second semiconductor layer 146.

[0111] A first part of the sacrificial grid 156 is etched so as to form an access to the first part 112 of the first semiconducting nanosheet 104. In the example described, this etching is implemented for first parts of the sacrificial grid 156 located between two lines of semiconducting nanosheets 104, 106 and by not etching the parts of the sacrificial grid 156 located between the lines adjacent to them (see [Fig.20]).

[0112] Etching of the remaining portions 160 of the second sacrificial layers 148, selectively with respect to the second semiconductor nanosheets 106, can be carried out (see [Fig. 21]). During this etching, the first semiconductor nanosheets 104 and the remaining portions 166 of the first sacrificial layers 144 are protected by the portions of the sacrificial grid 156 covering these elements.

[0113] The second grid 114 is then produced by depositing the grid dielectric 126 and the second metallic material 120, for example identical to those previously described for the first embodiment. A CMP can then be implemented to remove the excess portions of these deposited materials.

[0114] The portions of the sacrificial grid 156 occupying the spaces in which the first grid 110 is intended to be made can then be removed until the level at which the stacking of the first semiconductor nanosheets 104 and the remaining portions 166 is located is reached. The insulating portions 135 can then be made, then the last remaining parts of the sacrificial grid 156 can be engraved (see [Fig.23]).

[0115] In the described embodiment, the first grid 110 is then produced by depositing the grid dielectric 126 and the second metallic material 120, completed by CMP. The resulting device 100 corresponds to that shown in [Fig. 2].

[0116] In the various examples described, examples of etching implementations of low permittivity dielectric materials are given in US document 2013 / 252430 Al and can be used in the process described above.

[0117] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0118] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above. For example, the nature of the deposits and engravings used can be chosen according to, in particular, the material(s) to be deposited or engraved.

Claims

Demands

1. A complementary field-effect transistor device (100) comprising: - a substrate (102); - at least one first semiconductor nanosheet (104) and at least one second semiconductor nanosheet (106), the first semiconductor nanosheet (104) being disposed between the second semiconductor nanosheet (106) and the substrate (102); - an insulating layer (108) disposed between the first and second semiconductor nanosheets (104, 106); - a first gate (110) disposed around a first part (112) of the first semiconductor nanosheet (104), and a second gate (114) disposed around a first part (116) of the second semiconductor nanosheet (106);- first internal spacers (128) arranged against second parts (130) of the first semiconducting nanosheet (104) between which is arranged the first part (112) of the first semiconducting nanosheet (104), and - second internal spacers (132) arranged against second parts (134) of the second semiconducting nanosheet (106) between which is arranged the first part (116) of the second semiconducting nanosheet (106); and wherein the first and second internal spacers (128, 132) comprise respectively first and second dielectric materials with low permittivity, the first and second dielectric materials being different from each other.;

2. Device (100) according to claim 1, wherein the first and second semiconductor nanosheets (104, 106) respectively comprise first and second semiconductor materials different from each other.

3. Device (100) according to any one of the preceding claims, wherein the first and second grids (110, 114) respectively comprise first and second metallic materials (118, 120) different from each other.

4. Device (100) according to any one of the preceding claims, wherein at least a part (122) of the first grid (110) is in contact with at least a part (124) of the second grid (114), or wherein the first and second grids (110, 114) are dissociated and isolated from each other.

5. Device (100) according to claim 4, wherein, when the first and second grids (110, 114) are dissociated and isolated from each other, each of the first and second grids (110, 114) has a comb shape.

6. Method of making a device (100) with complementary field-effect transistors, comprising at least: - making a structure (140) comprising at least a substrate (102), first and second semiconducting nanosheets (104, 106), the first semiconducting nanosheet (104) being disposed between the second semiconducting nanosheet (106) and the substrate (102), and an insulating layer (108) disposed between the first and second semiconducting nanosheets (104, 106);- fabrication of first internal spacers (128) arranged against second parts (130) of the first semiconducting nanosheet (104), and of second internal spacers (132) arranged against second parts (134) of the second semiconducting nanosheet (106), the first and second internal spacers (128, 132) comprising respectively first and second dielectric materials with low permittivity, the first and second dielectric materials being different from each other, and such that the first internal spacers (128) are fabricated before or after the second internal spacers (132);- realization of a first grid (110) around a first part (112) of the first semiconducting nanosheet (104) arranged between the second parts (130) of the first semiconducting nanosheet (104), and of a second grid (114) around a first part (116) of the second semiconducting nanosheet (106) arranged between the;

7.

8.

9. second parts (134) of the second semiconducting nanosheet (106). A method according to claim 6, wherein the embodiment of the structure (140) comprises at least: - realization of a first stack of layers comprising at least a first semiconducting layer (142) disposed between two first sacrificial layers (144) of material suitable for being selectively etched with respect to the first semiconducting layer (142), and comprising a first dielectric layer (143); - realization of a second stack of layers comprising at least one second semiconducting layer (146) disposed between two second sacrificial layers (148) of material suitable for being selectively etched with respect to the second semiconducting layer (146), and comprising a second dielectric layer (150); - bonding of the first and second dielectric layers (143, 150) against each other and together forming the insulating layer (108). Method according to claim 7, wherein the realization of the structure (140) further comprises, after the joining of the first and second dielectric layers (143, 150) to each other, an engraving of at least one trench (154) implemented through the first and second stacks of layers (142, 144, 146, 148) and the insulating layer (108). A method according to claim 8, wherein the implementation of the second internal spacers (132) comprises at least: - construction of a sacrificial grid (156) in the trench (154) and on remaining portions of the structure (140) obtained after the engraving of the trench (154), then - creation of grid spacers (137) around the artificial sacrificial grid (156), then - engraving of parts of the remaining portions of the structure (140) not covered by the sacrificial grid (156) and the grid spacers (137), through the layers (146, 148) of the second stacking and a first part of the insulating layer (108) without crossing a bonding interface (152 ) between the first and second dielectric layers (143, 150), then - etching of parts of remaining portions (160) of the second sacrificial layers (148) arranged against the second parts (134) of the second semiconductor nanosheet (106), then - realization of a layer (164) of the second dielectric material with low permittivity such that portions of this layer (164) arranged against second parts (134) of the second semiconducting nanosheet (106) form the second internal spacers (132).

10. A method according to claim 9, wherein the fabrication of the first internal spacers comprises at least, after the fabrication of the layer (164) of the second low permittivity dielectric material: - etching of parts of the remaining portions of the structure (140) not covered by the sacrificial grid (156), the grid spacers (137) and by parts of the layer (164) of the second low permittivity dielectric material which rests on a second part of the insulating layer (108) including the bonding interface (152) and which cover the ends of the second parts (134) of the second semiconducting nanosheet (106), through the layers (142, 144) of the first stack and the second part of the insulating layer (108), then - etching of parts of remaining portions (166) of the first sacrificial layers (144) arranged against the second parts (130) of the first semiconductor nanosheet (104), then - realization of a layer of the first low permittivity dielectric material such that portions of this layer disposed against second parts (130) of the first semiconducting nanosheet (104) form the first internal spacers (128).

11. A method according to claim 10, further comprising, between the making of the first and second internal spacers (128, 132) and the making of the first and second grids (110, 114): - fabrication of first source or drain regions (136) against ends of second parts (130) of the first semiconducting nanosheet (104), then - removal of parts of the layer (164) of the second low permittivity dielectric material covering the ends of the second parts (134) of the second semiconducting nanosheet (106), then - fabrication of second source or drain regions (138) against ends of the second parts (134) of the second semiconducting nanosheet (106).

12. A method according to claim 11, wherein the embodiments of the first and second source or drain regions (136, 138) each include the implementation of an epitaxy, and further comprising, between the embodiments of the first and second source or drain regions (136, 138), a deposit of an insulating material (139) covering at least the first source and drain regions (136).

13. A method according to any one of claims 10 to 12, further comprising, between the making of the first and second internal spacers (128, 132) and the making of the first and second grids (110, 114) or during the making of the first and second grids (110, 114), an engraving of the remaining portions (160, 166) of the first and second sacrificial layers (144, 148).

14. A method according to any one of claims 9 to 13, wherein the making of the first and second grids (110, 114) comprises an engraving of the sacrificial grid (156), then successive deposits of at least a first metallic material (118) forming the first grid (110) and of at least a second metallic material (120) different from the first metallic material (118) and forming the second grid (114), and such that at least a part (122) of the first grid (110) is in contact with at least a part (124) of the second grid (114).

15. A method according to any one of claims 6 to 13, wherein the fabrication of the first and second grids (110, 114) comprises: an etching of a first part of the sacrificial grid (156) so as to form an access to the first part (116) of the second semiconductor nanosheet (106), then a deposition of materials forming the second grid (114), then an etching of a second part of the sacrificial grid (156) so as to form an access to the first part (112) of the first semiconducting nanosheet (104), then a deposition of materials forming the first grid (110) such that the first and second grids (110, 114) are dissociated and isolated from each other.

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