Automatic data routing module for SIMD architecture computers

Abstract

Automatic Data Routing Module (ARA) for a computer with a "single instruction, multiple data" architecture comprising several elementary processors, each associated with a local memory, the routing module comprising: An input interface comprising several input buffers, each intended to receive data read from a respective local memory; An output interface comprising several output buffers, each intended to transmit data to be written to a respective local memory; For each input buffer, a selector (SEL) configured to select one or more data items contained in the input buffer; At least one assembler (ASB) configured to group the data selected by at least two selectors (SELs) into an assembly buffer; A transfer module (MTR) for each assembler.configured to transfer data from the assembler's assembly buffer to at least one output buffer for writing to at least one local memory location. Figure 3,

Description

Title of the invention: Automatic data routing module for a SIMD architecture computer

[0001] The invention relates to the field of SIMD (Single Instruction Multiple Data) or "single instruction, multiple data" computers, for example computers intended to implement artificial intelligence algorithms such as deep neural networks, image processing algorithms or more generally computers intended to implement calculations on very large volumes of data.

[0002] The invention relates more specifically to an automatic data routing module configured to move data in local memories reliably and quickly in order to meet the computational needs applied to large volumes of data.

[0003] Computers with SIMD architecture are notably used to implement deep neural networks or image processing devices. For this type of application, the issue of data movement is of great importance. Deep neural networks are machine learning models that require a considerable volume of data to perform complex tasks such as image recognition, object detection, or anomaly detection.

[0004] Data movement refers to the manipulation and transfer of data from one memory location to another. This presents several challenges in the context of deep neural networks. The massive volume of data used by these models requires adequate storage and processing resources to efficiently handle movement operations. Data must be transferred quickly and reliably to minimize waiting times and optimize neural network performance.

[0005] Furthermore, deep neural networks incorporate a wide variety of operations. These require different data distributions. In this context, a rearrangement of data in nearby memory during computations may be necessary. Without dedicated hardware, this type of operation can significantly degrade overall performance (execution time and energy consumption).

[0006] For these reasons, there is a need for an automatic data routing mechanism that is fast, scalable, and adaptable to the intended application. Generally, such a routing module is necessary to manage data movement for any type of computer implementing operations applied to large volumes of data, including convolutional operations such as those implemented by deep neural networks.

[0007] European patent EP3335107 describes a computing device for image processing applications. The device is capable of rearranging video data to produce contiguous pixels. To do this, it uses additional buffer memories connected to the data stream arriving from a sensor (camera).

[0008] This solution only supports one type of pixel reordering in a contiguous manner. Furthermore, buffers are required. Therefore, this solution is not optimal in terms of memory usage and is neither scalable nor modular.

[0009] US patent US6735647 describes a device and method for rearranging data on the fly in a communication network. This involves communication between remote units and manipulation of data within the frames that carry the data.

[0010] This solution involves only one data source and only covers transfers via network frames. It is therefore not applicable to computers implementing a deep neural network. It is neither scalable nor modular.

[0011] Fig. 1a represents an architecture of a computing system based on a hardware accelerator according to the prior art.

[0012] Such a system comprises a host processor PROC, a hardware accelerator ACC, a level 2 global memory MEM2 and an interconnection bus BUS.

[0013] The host processor PROC is a central processing unit that manages the overall execution of the system, including communication with the hardware accelerator ACC.

[0014] The ACC hardware accelerator is specifically designed to accelerate specific types of computations, such as machine learning operations or intensive computations. It comprises a global controller CTRL and a set of computation blocks BCN (e.g., neural network computations). Each BCN comprises a Level 1 BMEM memory and a set of PE computing units. The Level 1 BMEM memory is typically decomposed into at least one source memory block and at least one destination memory block to manage data rearrangement in memory during computations.

[0015] The level 2 memory MEM2 corresponds to the main memory of the embedded system.

[0016] The interconnection bus BUS allows communication between the central host processor PROC, the hardware accelerator ACC and the level 2 memory MEM2.

[0017] In [Fig. 1b], an example of data rearrangement in memory is shown, consisting of moving from a first memory placement 101 with a data interleave of an interleave step equal to 2 to a second memory placement 102 with a data interleave of an interleave step equal to 16.

[0018] To accelerate computation, the placement of data in memory must meet certain constraints to achieve optimal performance. The specific data access capabilities and functionalities of the ACC accelerator (e.g., access to neighboring BCNs) and the data distribution associated with the operation must be considered when placing data in memory.

[0019] Therefore, it may be necessary to modify this data placement in memory during the execution of a complete application. Indeed, this implies different constraints at the level of operations and the associated data distribution.

[0020] When the ACC accelerator does not have a dedicated function for this type of processing, the host processor PROC must read the data from the BCN calculation blocks and perform a series of data manipulations before transferring it to the BCN calculation blocks with the new data arrangement. This processing involves executing a complex routine that is particularly costly in terms of latency and energy. Furthermore, it involves transferring the data to level 2 memory, which breaks the parallelism of the calculations and introduces additional latency.

[0021] The invention proposes integrating an automatic data routing module into the ACC hardware accelerator to automatically perform data placement and rearrangement operations for any application. The proposed solution is compatible with SIMD computing architectures incorporating distributed memory and is scalable and modular. It also results in low processing latency.

[0022] The invention relates to an automatic data routing module for a computer with a "single instruction, multiple data" architecture comprising several elementary processors, each associated with a local memory, the routing module comprising: - An input interface comprising several input buffers, each designed to receive data read from its respective local memory, - An output interface comprising several output buffers, each intended to transmit data to be written to a respective local memory, - For each input buffer, a selector is configured to select one or more data points contained in the input buffer. - At least one assembler configured to group data selected by at least two selectors into an assembly buffer, - a transfer module for each assembler, configured to transfer data from the assembly buffer of said assembler to at least one output buffer to write them to at least one local memory.

[0023] In one embodiment, the routing module according to the invention further comprises a control unit comprising at least three identical controllers respectively configured to drive all the selectors, an assembler and a transfer module, each controller being configured to generate a drive signal according to a set of signals with specific configurations.

[0024] According to a particular aspect of the invention, a controller includes at least one counter and one shift unit configured from the set of configuration signals to generate a drive signal.

[0025] According to a particular aspect of the invention, the configuration signal set comprises: an initial value of the pilot signal, a count length value, a loop value and an offset value, the value of the pilot signal being offset by the offset value when the counter reaches the count length value, the value of the pilot signal being reset to its initial value when it reaches the loop value.

[0026] According to a particular aspect of the invention, the configuration signal set includes an offset enable value to enable or disable the offset of the pilot signal.

[0027] According to a particular aspect of the invention, the offset of the transfer module's control signal is disabled.

[0028] According to a particular aspect of the invention, the control signal of the set of selectors is configured to indicate to each selector which data to select from the input buffer among several concatenated data.

[0029] According to a particular aspect of the invention, the assembler's control signal is configured to tell the assembler which selectors to choose as input.

[0030] According to a particular aspect of the invention, the drive signal of the transfer module is configured to indicate to the transfer module in which output buffer to transfer the data from the assembly buffer.

[0031] According to a particular aspect of the invention, the values ​​of the configuration signals are defined so that the routing module is configured to receive data read from local memories in interleaved form according to a first interleaving configuration, the input buffers being sized to receive a concatenation of several data from a line of a local memory.

[0032] According to a particular aspect of the invention, the values ​​of the configuration signals are defined so that the routing module is configured to provide, in the output buffers, data intended to be written to local memories in interleaved form according to a second interleaving configuration different from the first interleaving configuration.

[0033] In one embodiment, the routing module according to the invention comprises several assemblers and several transfer modules and a decision body to manage the transfer priorities of the outputs of the transfer modules to the output buffers.

[0034] The invention also relates to a computer with a "single instruction, multiple data" architecture comprising a host processor and a hardware accelerator comprising several computing blocks, each computing block comprising a local memory and at least one elementary processor, a global controller and an automatic data routing module according to the invention configured to modify the placement of data in local memories according to a placement instruction generated by the global controller, the global controller being configured to define the configuration signals of the control unit of the automatic routing module from the placement instruction.

[0035] According to one embodiment, the calculator according to the invention further comprises an address generator configured to generate a read address in the local memories to read the data to be transferred to the automatic routing module and a write address in the local memories to write the data provided by the automatic routing module.

[0036] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0037] [Fig.la] represents an architecture of a computer comprising a parallel computing accelerator according to the prior art,

[0038] [Fig. 1b] represents an example of data rearrangement in memory from a 2-interleave to a 16-interleave,

[0039] [Fig.2] represents an architecture of a computer comprising an automatic routing module according to an embodiment of the invention,

[0040] [Fig.3] represents an architecture of a data arranger according to an embodiment of the invention,

[0041] [Fig.4] represents an architecture of a multitransfer module according to an embodiment of the invention,

[0042] [Fig.5] represents an architecture of a control and shift unit according to an embodiment of the invention,

[0043] [Fig.6a] illustrates an application of the invention to perform a data rearrangement from a 2-memory interleave to a 16-memory interleave,

[0044] [Fig.6b] illustrates an example of data rearrangement in memory from a 2-interleave to a 16-interleave,

[0045] [Fig.7] illustrates the configuration of the automatic routing module to perform the data rearrangement illustrated in [Fig.6b],

[0046] [Fig.8] illustrates the generation of the first output buffer,

[0047] [Fig.9] illustrates the generation of the second output buffer,

[0048] [Fig. 10] illustrates the generation of the third output buffer,

[0049] [Fig. 11] illustrates the generation of the fourth output buffer,

[0050] [Fig. 12a] illustrates an application of the invention for performing a data rearrangement from a 2-digit memory interleave to a 4-digit memory interleave,

[0051] [Fig. 12b] illustrates an example of data rearrangement in memory from a 2-fold interleave to a 4-fold interleave,

[0052] [Fig. 13] illustrates the configuration of the automatic routing module to perform the data rearrangement illustrated in [Fig. 12b],

[0053] [Fig. 14] illustrates the generation of the first output buffer for the application of [Fig.12a],

[0054] [Fig. 15] illustrates the generation of the second output buffer for the application of [Fig.12a],

[0055] [Fig. 16a] illustrates another example of configuring the automatic routing module according to another embodiment of the invention,

[0056] [Fig. 16b] illustrates an example of data rearrangement in memory from a 2-fold interleave to an 8-fold interleave,

[0057] Figure 2 shows a schematic of a computer architecture comprising an automatic routing module according to an embodiment of the invention. The computer in Figure 2, like that in Figure 11, comprises a host processor PROC and a hardware accelerator ACC including a global controller CTRL, several computing blocks BCN each comprising a memory block BMEM and several computing units PE, as well as an automatic routing module ARA according to the invention.

[0058] The ARA automatic routing module is configured for advanced routing from N sources to M destinations with automatic on-the-fly data rearrangement. This device is suitable for SIMD (Single Instruction Multiple Data) computing architectures incorporating distributed memory.

[0059] The BCN computing blocks include BMEM memories which are connected to the ARA automatic routing module.

[0060] Each BMEM memory block comprises at least one readable source memory and one writeable destination memory.

[0061] The ARA automatic routing module includes an input interface which includes as many input buffers as source memories and an output interface which includes as many output buffers as destination memories.

[0062] The useful data coming from or going to the memories are encapsulated in the input buffers (eBUFFER) or output buffers (sBUFFER) according to a given assembly. For example, a buffer with a width of 32 bits encapsulates four 8-bit data points. More generally, a buffer encapsulates multiple data points of the same size.

[0063] The ARA automatic routing module includes as many SEL selectors as input buffers and output buffers, an ASB assembler, an MTR multitransfer module and three DECi, DEC2, DEC3 control and offset units that are physically identical but independently configurable.

[0064] The SEL selectors implement the first level of routing, responsible for selecting one or more data items from each input buffer. All SEL selectors are connected at their output to the input of the ASB assembler, which is responsible for composing the destination buffer. Finally, the MTR multitransfer module allows the destination buffer to be written to one or more memories via the output buffers.

[0065] Each of the aforementioned sub-modules incorporates a control and shifting unit DECi, DEC2, and DEC3, which is configured and synchronized by the global controller CTRL of the hardware accelerator ACC via CFG configuration and ACT activation signals. In other words, the global controller CTRL manages the activation and configuration of the routing module. Once configured, routing is performed automatically on the fly. The CFG configuration signals depend on the intended application and the specific routing function to be implemented. The control signals delivered at the output of the control and shifting units DECi, DEC2, and DEC3 are used to control the respective operation of the selectors SEL, the assembler ASB, and the multi-transfer module MTR.

[0066] This ARA routing device allows for efficient, automated, on-the-fly data rearrangement, with the ability to produce an output buffer at each cycle. Furthermore, it is a scalable and modular device that adapts according to the size of the memory buffers, the payload data, and the number of connected computing blocks.

[0067] Fig. 3 represents an example of an embodiment of the ARG data arranger module according to the invention which includes several SEL data selectors and an ASB assembler.

[0068] The ARG arranger module has as many SEL selectors as there are eBUFFER input buffers. Each SEL selector is controlled by the same selection signal delivered by the DECi control unit, which tells it which data to read from the input buffer containing multiple encapsulated data. The selection signal has, for example, a size equal to the number of data encapsulated in a buffer.

[0069] The selected data is placed in an intermediate buffer iBUFFER provided as input to the ASB assembler.

[0070] The ASB assembler is driven by a selection signal delivered by the DEC2 control unit which tells it which intermediate buffers associated with which selectors it should select in order to concatenate the data from the selected intermediate buffers into an output buffer sBUFFER.

[0071] The ASB assembler selection signal has, for example, a size equal to the number of SEL selectors.

[0072] Each selector SEL includes an EXP demultiplexer configured to demultiplex the concatenated data in the input buffer eBUFFER and an EXT multiplexer driven by the select signal select which selects the data or data to be supplied in the intermediate buffer iBUFFER.

[0073] The ARG arranger module is scalable and can adapt to the desired number of external connections. For each external connection, an SEL selector must be instantiated and an additional input must be provided to the ASB assembler.

[0074] The SEL selector is scalable in that the size of the input buffer eBUFFER and the number of data points it encapsulates, as well as their resolution, are configurable. For example, the SEL selector is configurable for a 32-bit input buffer containing 4 data points with an 8-bit resolution.

[0075] Figure 4 shows an example of an embodiment of the MTR multitransfer module. This module includes a REG register for storing data from the ARG arranger module. The register output is simultaneously routed to the output buffers of the routing module as defined by a drive signal in the form of a write mask generated by the DEC3 control unit. The number of outputs and the size of the associated write mask are scalable according to the number of connected BCN computing blocks. As with the other modules, the buffer size is also scalable according to the needs of the associated architecture.

[0076] The write mask signal has a size that depends on the number Nb of BCN of connected BCN calculation blocks.

[0077] Figure 5 represents an example of an embodiment of a DEC control and offset unit. The three control and offset units comprising the automatic routing module have an identical architecture but are configured via a set of configuration signals specific to each unit.

[0078] The DEC control and offset unit includes a CPT counter configured to generate an offset via the DECAL register after a delay defined by the counter's length. The counting is triggered by the active_cpt signal generated by the global controller CTRL at each access to the ARA automatic routing module. The offset is achieved, in particular, via a COMP comparator associated with a loopback value which, once reached, forces a return to the initial value.

[0079] The collaboration of the counter and the shift register allows the automation of the control of the various data routing elements.

[0080] More precisely, the output signal of the CPT counter is supplied to the input of an AND logic gate, which receives the shift activation signal at its other input. If the shift is activated, the output signal of the CPT counter is propagated from the output of the AND gate to the DECAL shift register, which shifts the value contained in this register by a number of bits equal to the shift value contained in the CFG3 configuration register.

[0081] A comparator COMP compares the value of the DECAL shift register with the loopback value stored in the CFG2 configuration register. The output of the comparator COMP and a reset signal RAZ are provided as inputs to an OR gate. The output of the OR gate is a select signal that drives a MUX multiplexer. The MUX multiplexer receives as input the value of the DECAL shift register and the initial value stored in the CFG4 configuration register. This mechanism allows the MUX multiplexer to select the initial value when the value of the shift register reaches the loopback value. Otherwise, the value of the shift register is provided to the SELECT select register. The output of this register is then fed back to the DECAL shift register for the next shift operation.

[0082] Without departing from the scope of the invention, other implementations can be considered to realize the initial value shift function as explained above.

[0083] The configuration signals include the following signals.

[0084] The signal v_length_cpt stored in the configuration register CFG1 gives the counting length of the CPT counter which triggers the shift, via the DECAL register, of the initial value stored in the configuration register CFG4 if it is activated via the activation signal active_shift.

[0085] The active_offset signal enables the offset, which can be deactivated. In this case, the "select" output signal remains constant.

[0086] The v_bouclage signal gives a loop value which corresponds to the limit value before returning to the initial value.

[0087] The raz signal triggers the reset of the counter and forces the SELECT register to the initial value.

[0088] The v_decalage signal gives the offset value of the selection signal which is stored in the configuration register CFG3.

[0089] The initial v_signal gives the initial value loaded into the SELECT register during the reset or loopback.

[0090] An example of implementing the ARA automatic routing module according to the invention for rearranging data in the memory blocks of the BCN calculation blocks is now described with reference to Figures 6a and 6b. In this example, the data is arranged in the source memories of the BCN calculation blocks with a interleaving of 2. We wish to rearrange the data in the destination memories with an interleaving of 16 for specific needs of the calculations to be performed.

[0091] Interlaced data storage is a well-known principle in image processing. It consists of placing the data (which corresponds, for example, to pixels) in columns. The interlacing value corresponds to the number of pixels placed in a column.

[0092] In the example of [Fig. 6a], the ACC hardware accelerator comprises 8 computing blocks connected to the ARA routing device. The input buffers are 32 bits in size, while the data is encoded on 8 bits. Each input buffer therefore contains 4 pieces of 8-bit data.

[0093] The original data placement is a set 101 of 64 pixels distributed across the 8 memory locations of the BCN calculation blocks with an interleave of 2 pixels. The intended data rearrangement consists of an interleave 102 of 16 pixels in the first BCN calculation block.

[0094] Each memory of a calculation block is organized into 32-bit lines that can include 4 8-bit data points. Each line has an address.

[0095] Fig. 6b shows the memory placement of the 64 pixels via the pixel number (varying from 0 to 63) in the corresponding memory location of the source memory 101 and the destination memory 102.

[0096] Fig.7 illustrates the configuration of the ARA automatic routing module to perform the data rearrangement illustrated in Fig.6b.

[0097] The SEL selector drive signal generated by the first DECi control unit is a 4-bit signal enabling the selection of the four 8-bit data points from the BCN calculation blocks present in the input buffers. For example, the 1 bits of the drive signal indicate the index of the data to be selected from the input buffer.

[0098] The ASB assembler control signal generated by the second DEC2 control unit is an 8-bit signal that allows the selection of the outputs of the 8 SEL selectors. For example, the 1 bits of this control signal indicate the index of the selectors to be selected.

[0099] The MTR multitransfer module's control signal is an 8-bit signal corresponding to a write mask indicating the parallel routing of the module's output to the 8 output buffers corresponding to the 8 BCN calculation blocks. For example, the 1 bits of this control signal indicate the index of the output buffers to which the data is transferred.

[0100] The configuration of the control and automatic shift units is as follows.

[0101] DEC! Unit - Initial value: 0001 - Offset: activated - Meter length: 2 - Offset value: 1 - Loop value: 1000

[0102] DEC2 Unit - Initial value: 0101 _0101 - Offset: activated - Meter length: 8 - Offset value: 1 - Loopback value: 1010_ 1010

[0103] DEC3 Unit - Initial value: 0000_0001 - Offset: disabled - Meter length: NA - Offset value: NA - Loop value: NA

[0104] Figures 8 to 11 illustrate the generation of the first four output buffers of the automatic routing module.

[0105] Fig. 8 illustrates the generation of the first output buffer.

[0106] Table 801 gives the sequence of values ​​for the three control signals (respectively in the columns "SELECTOR", "ASSEMBLER", and "MULTITRANSFER") for placing the 64 pixels into memory, along with the addresses of the source memory SRCMEM@ and the destination memory DESTMEM@. These two read and write addresses are managed directly by the global controller via the implementation of an address generator. For example, French patent FR2202150 of the Applicant describes an address generator for a SIMD computing architecture that can be used in this context.

[0107] The data rearrangement operation in the destination memories is carried out in 16 cycles detailed on the 16 lines of table 801 reproduced below.

[0108] CONTROLLER AUTOMATIC CONTROL OESTMEM^ MULTiTRANSFER ASSEMBLER SELECTOR 0 Û 0YES ÛW1_OW1 9000_0Û01 1 œoi CL01_ 0101 œæjw 0 ■■ 2 œw CIÛ1 0101 »00 »0 1 1 3 0010 0101 J)W1 0001 WlOJiOW W00JM»! 1 9 0001 ÜQ0QJW1 o 10 œio 1010^1010 0000^0001 1 11 0010 W10J010 »oojwi 0 12 0100 1010^1010 œOQ^ODOl 1 13 OlOO 1X0^1310' x»_œci 0 14 wœ 1 15 1000 W1Û..W10 WhereùQ^ûôul

[0109] Fig. 8 illustrates the first cycle more precisely.

[0110] For this first cycle, each input buffer contains the 32-bit value read from address SRCMEM@=0 of each source memory of each BCN calculation block. The selector drive signal is 0001, so the first data item in each input buffer is selected. This corresponds to pixels with respective indices 0, 8, 16, 24, 32, 40, 48, and 56.

[0111] The ASB assembler is driven by a selection signal which is 0101_0101, so the outputs of the selectors of index 0,2,4 and 6 are read and grouped in the intermediate buffer 802 which contains the pixels of indices 0,16,32 and 48 concatenated in a 32-bit word.

[0112] Finally, the MTR multitransfer module is driven by a write mask equal to 0000_0001 which implies the routing of the intermediate buffer 802 to the first output buffer 803 corresponding to the first calculation block BCN0.

[0113] This 32-bit word is then written to the destination memory of the calculation block BCN0 at the destination address DESTMEM@=0.

[0114] Figure 9 illustrates the execution of the second cycle of the sequence. The data inputs are read at source address SRCMEM@=1 of each source memory of each calculation block.

[0115] The selector drive signal is always 0001, so the first data item in each input buffer is selected. This corresponds to pixels with respective indices 1, 9, 17, 25, 33, 41, 49, 57.

[0116] The ASB assembler is driven by a selection signal which is 0101_0101, so the outputs of the selectors of index 0,2,4 and 6 are read and grouped in the intermediate buffer 802 which contains the pixels of indices 1,17,33 and 49 concatenated in a 32-bit word.

[0117] Finally, the MTR multitransfer module is driven by a write mask equal to 0000_0001 which implies the routing of the intermediate buffer 802 to the first output buffer 803 corresponding to the first calculation block BCN0.

[0118] This 32-bit word is then written to the destination memory of the calculation block BCN0 at the destination address DESTMEM@=1.

[0119] Figure 10 illustrates the execution of the third cycle of the sequence. The input data is read from the source address SRCMEM@=0 of each source memory of each computation block.

[0120] The selector drive signal is 0010, so the second data item in each input buffer is selected. This corresponds to pixels with respective indices 2, 10, 18, 26, 34, 42, 50, 58.

[0121] The ASB assembler is driven by a selection signal which is 0101_0101, so the outputs of the selectors of index 0,2,4 and 6 are read and grouped in the intermediate buffer 802 which contains the pixels of indices 2,18,34,50 concatenated in a 32-bit word.

[0122] Finally, the MTR multitransfer module is driven by a write mask equal to 0000_0001 which implies the routing of the intermediate buffer 802 to the first output buffer 803 corresponding to the first calculation block BCN0.

[0123] This 32-bit word is then written to the destination memory of the calculation block BCN0 at the destination address DESTMEM@=2.

[0124] Figure 11 illustrates the execution of the fourth cycle of the sequence. The input data is read from the source address SRCMEM@=1 of each source memory of each computation block.

[0125] The selector drive signal is 0010, so the second data item in each input buffer is selected. This corresponds to pixels with respective indices 3, 11, 19, 27, 35, 43, 51, 59

[0126] The ASB assembler is driven by a selection signal which is 0101_0101, so the outputs of the selectors of index 0,2,4 and 6 are read and grouped in the intermediate buffer 802 which contains the pixels of indices 3,19,35,51 concatenated in a 32-bit word.

[0127] Finally, the MTR multitransfer module is driven by a write mask equal to 0000_0001 which implies the routing of the intermediate buffer 802 to the first output buffer 803 corresponding to the first calculation block BCNO.

[0128] This 32-bit word is then written to the destination memory of the BCNO calculation block at destination address DESTMEM@=3.

[0129] The sequence continues with the following cycles illustrated in Table 801 until placement in destination memory is achieved with a data interleaving of 16.

[0130] Table 801 shows the operation of the offsets applied to the selector and assembler drive signals and the write mask which drives the multitransfer module implemented by the control and offset units as described in [Fig.5].

[0131] In this example, the selector control signal (DECO unit) is initialized to the value 0001. This value is shifted by a value of 1 bit every 2 cycles since the counter length is equal to 2. This value is reset to the initial value 0001 when the signal value reaches the loopback value 1000.

[0132] The assembler control signal (DEC2 unit) is initialized to the value 0101_0101. This value is shifted by a value of 1 bit every 8 cycles since the length of the counter is equal to 8. This value is reset to the initial value after reaching the loopback value 1010_1010.

[0133] The control signal of the multitransfer module (DEC3 unit) is initialized to the value 0000_0001 and remains constant since the offset is disabled for this unit.

[0134] Figures 12a to 15 illustrate another example of application of the automatic routing module according to the invention.

[0135] In the example in [Fig. 12a], the ACC hardware accelerator comprises four BCN compute blocks. The compute block memories, as well as the input and output buffers of the ARA routing module, are 32 bits in size to encapsulate eight 4-bit encoded data items. [Fig. 12b] shows the data placement in memory for this example.

[0136] In the example of [Fig. 12b], the placement of data in the source memories 1001 is carried out according to an interleaving of 2 pixels.

[0137] The ARA routing module is configured to perform data placement in destination memories 1002 according to an interleaving of 4 pixels.

[0138] In the example of [Fig. 12b], a set of 64 pixels is thus distributed in the 4 source memories of the 4 BCN calculation blocks. The data rearrangement consists of distributing these 64 pixels in two destination memories of the first two BCN calculation blocks, BCN0 and BCN1, according to an interleaving of 4 pixels.

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[0149] [Fig. 13] illustrates the configuration of the ARA automatic routing module to perform the data rearrangement shown in [Fig. 12b]. The SEL selector control signal generated by the first DECi control unit is an 8-bit signal enabling the selection of the 8 4-bit data from the BCN calculation blocks and present in the input buffers. The ASB assembler control signal generated by the second DEC2 control unit is a 4-bit signal enabling the selection of the outputs of the 4 SEL selectors. The control signal of the MTR multitransfer module is a 4-bit signal which corresponds to a write mask indicating the parallel routing of the module's output to the 4 output buffers corresponding to the 4 BCN calculation blocks. The configuration of the control units and automatic shifting is as follows. DECI Unit - Initial value: 0101 _0101 - Offset: activated - Meter length: 2 - Offset value: 1 - Loopback value: 1010_ 1010 Unit DEC2 - Initial value: 0011 - Offset: activated - Meter length: 4 - Offset value: 2 - Loop value: 1100 Unit DEC3 - Initial value: 0001 - Offset: activated - Meter length: 4 - Offset value: 1 - Loop value: 0010 Figures 14 and 15 illustrate the generation of two output buffers of the automatic routing module. Figure 14 illustrates the generation of the first output buffer. Table 1401 shows the sequence of values ​​for the three control signals used to place the 64 pixels into memory, along with the addresses of the source memory SRCMEM@ and the destination memory DESTMEM@. These two read and write addresses are managed directly by the global controller via the implementation of a multi-dimensional address generator.

[0150] The data rearrangement operation in the destination memories is performed in 8 detailed cycles on the 8 lines of table 1401 reproduced below. 101511 s................................................................................................................................................................................................... CONTROLLER | AUTOMATIC CONTROL SRÇMÊW SELECTOR ASSEMBLER MULTITRANSFER 1 1 0101 01O1 A'11 "<'1 a 1 2 N * 0001 1^3 10 W 1C10 OC A GWt oo oimjnoi me so 1 1 o101,O101 lldv CC__' 0 J ZI < .L.ÙI.iJ 1.Ü.4.Ù < vb'XV i | 3 [ wiCLWw | 1100 | œio

[0152] For the first cycle, each input buffer contains the 32-bit value read from address SRCMEM@=0 of each source memory of each BCN calculation block. The selector drive signal is 0101_0101, so every other data point is read from each input buffer as represented on the outputs of the SEL selectors.

[0153] The ASB assembler is driven by a selection signal which is 0011, so the outputs of the selectors of index 0 and 1 are read and grouped in the intermediate buffer 1402 which contains the pixels of indices 0,4,8,12,16,20,24,28 concatenated in a 32-bit word.

[0154] Finally, the MTR multitransfer module is driven by a write mask equal to 0001 which implies the routing of the intermediate buffer 1402 to the first output buffer 1403 corresponding to the first calculation block BCN0.

[0155] This 32-bit word is then written to the destination memory of the calculation block BCN0 at the destination address DESTMEM@=0.

[0156] Fig. 15 illustrates the generation of the fifth output buffer corresponding to the 5th cycle of sequence 1401.

[0157] For the 5th cycle, each input buffer contains the 32-bit value read from address SRCMEM@=0 of each source memory of each BCN calculation block. The selector drive signal is 0101_0101, so every other data point is read from each input buffer as represented on the outputs of the SEL selectors.

[0158] The ASB assembler is driven by a selection signal which is 1100, so the outputs of the selectors of index 2 and 3 are read and grouped in the intermediate buffer 1402 which contains the pixels of indices 32,36,40,44,48,52,56,60 concatenated in a 32-bit word.

[0159] Finally, the MTR multitransfer module is driven by a write mask equal to 0010 which implies the routing of the intermediate buffer 1402 to the second output buffer 1404 corresponding to the second calculation block BCN1.

[0160] This 32-bit word is then written to the destination memory of the calculation block BCN0 at the destination address DESTMEM@=0.

[0161] The other operating cycles of the ARA routing module are carried out in accordance with the control signals described in Table 1401.

[0162] Table 1401 shows the operation of the offsets applied to the selector and assembler drive signals and the write mask which drives the multitransfer module implemented by the control and offset units as described in [Fig.5].

[0163] In this example, the selector control signal (DECO unit) is initialized to the value 0101_0101. This value is shifted by a value of 1 bit every 2 cycles since the counter length is equal to 2. This value is reset to the initial value after the signal value reaches the loopback value 1010_1010.

[0164] The assembler control signal (DEC2 unit) is initialized to the value 0011. This value is shifted by a value of 2 bits every 4 cycles since the counter length is equal to 4. This value is reset to the initial value after reaching the loopback value 1100.

[0165] The control signal of the multitransfer module (DEC3 unit) is initialized to the value 0011. This value is shifted by a value of 1 bit every 4 cycles since the length of the counter is equal to 4. This value is reset to the initial value after reaching the loopback value 0010.

[0166] In general, the ARA automatic routing module according to the invention is configurable to perform various data rearrangement functions. In particular, it is configurable, via the configuration signals of the control and shift units, to perform any rearrangement from a memory location according to a first interleaving level to a memory location according to a different second interleaving level. The size of the input buffers as well as the data size is also configurable. The module can be adapted to different numbers of computation blocks by modifying the number of inputs / outputs and selectors.

[0167] Figures 16a and 16b represent another embodiment of the automatic routing module according to the invention comprising several assemblers ASB1,ASB2 and several multitransfer modules MTR1,MTR2.

[0168] In this embodiment, an ORG decision body is connected to the outputs of the multitransfer modules in order to implement a priority management mechanism for routing the output buffers of these modules to the output buffers of the routing module.

[0169] Each assembler and each multitransfer module is associated with a control and shift unit. Thus, in the example of [Fig. 16a], the ARA routing module comprises 5 units DEC1, DEC2, DEC3, DEC4, DEC5.

[0170] Such an embodiment has the advantage of increasing the parallelism of the treatments.

[0171] The embodiment of [Fig. 16a] can be configured to perform the same types of routing or rearrangement of data in memory as those described previously.

[0172] For example, it can perform a data rearrangement from a data placement in source memory with an interleave of 2 to a data placement in destination memory with an interleave of 8, as illustrated in [Fig. 16b] by the source memory table 1601 and the destination memory table 1602. The data is encoded on 8 bits and the buffers are 32 bits in size. The number of computation blocks is 8.

[0173] In [Fig. 16a], the first operating cycle of the ARA routing module is shown.

[0174] The configuration of the control and automatic shift units is as follows.

[0175] DEC! Unit - Initial value: 0001 - Offset: activated - Meter length: 2 - Offset value: 1 - Loop value: 1000

[0176] DEC2 Unit - Initial value: 0000_l 111 - Offset: disabled - Meter length: NA - Offset value: NA - Loop value: NA

[0177] DEC3 Unit - Initial value: 0000_0001 - Offset: disabled - Meter length: NA - Offset value: NA - Loop value: NA

[0178] Unit DEC4 - Initial value: 1111_0000 Offset: Disabled Counter Length: N / A Offset Value: N / A Loopback Value: N / A

[0179] Unit DEC5 Initial value: 0000_0010 Offset: disabled Meter length: NA Offset value: NA Loop value: NA

[0180] For this first cycle, each input buffer contains the 32-bit value read from address SRCMEM@=0 of each source memory of each BCN calculation block. The selector drive signal is 0001, so the first data item in each input buffer is selected. This corresponds to pixels with respective indices 0, 8, 16, 24, 32, 40, 48, and 56.

[0181] The first ASBi assembler is driven by a selection signal which is 0000_l 111, so the outputs of the selectors of index 0,1,2,3 are read and grouped in the intermediate buffer 1603 which contains the pixels of indices 0,8,16,24 concatenated in a 32-bit word.

[0182] The second assembler ASB2 is driven by a selection signal which is 1111_0000, so the outputs of the selectors of index 4,5,6,7 are read and grouped in the intermediate buffer 1604 which contains the pixels of indices 32,40,48,56 concatenated in a 32-bit word.

[0183] The first MTRi multitransfer module is driven by a write mask equal to 0000_0001 which implies the routing of the intermediate buffer 1603 to the first output buffer 1605 corresponding to the first calculation block BCN0.

[0184] The second multitransfer module MTR2 is driven by a write mask equal to 0000_0010 which implies the routing of the intermediate buffer 1604 to the second output buffer 1606 corresponding to the second calculation block BCN1.

[0185] The ORG decision body implements a priority rule which gives, for example, write priority to the first MTRi multitransfer module in case of a write conflict between the MTRi and MTR2 multitransfer modules.

[0186] The invention can be implemented using hardware and / or software elements.

[0187] In particular, the automatic routing module according to the invention can be implemented in a hardware accelerator made using one or more elements from an embedded processor or a specific device. The processor can be a generic processor, a specific processor, or an integrated circuit specific to a The device according to the invention can use one or more dedicated electronic circuits or a general-purpose circuit. The invention can be implemented on a reprogrammable computing machine (such as a processor or microcontroller) executing a program comprising a sequence of instructions, or on a dedicated computing machine (such as an array of logic gates like an FPGA or ASIC, or any other hardware module).

Claims

Demands

1. Automatic Data Routing Module (ARA) for a computer with a "single instruction, multiple data" architecture comprising several elementary processors, each associated with a local memory, the routing module comprising: - An input interface comprising several input buffers, each intended to receive data read from a respective local memory, - An output interface comprising several output buffers, each intended to transmit data to be written to a respective local memory, - For each input buffer, a selector (SEL) configured to select one or more data items contained in the input buffer, - At least one assembler (ASB) configured to group the data selected by at least two selectors (SELs) into an assembly buffer, - a transfer module (MTR) for each assembler,configured to transfer data from the assembler's assembly buffer to at least one output buffer for writing to at least one local memory location.

2. Automatic data routing module according to claim 1 further comprising a control unit comprising at least three identical controllers (DEC1, DEC2, DEC3) respectively configured to drive all selectors (SEL), an assembler (ASB) and a transfer module (MTR), each controller being configured to generate a drive signal based on a set of signals with specific configurations.

3. Automatic data routing module according to claim 2 wherein a controller (DECi,DEC2,DEC3) includes at least one counter (CPT) and one offset unit configured from the configuration signal set to generate a drive signal.

4. Automatic data routing module according to claim 3, wherein the configuration signal set comprises: an initial value of the drive signal, a length value counting, a loop value and an offset value, the value of the pilot signal being offset by the offset value when the counter reaches the counting length value, the value of the pilot signal being reset to its initial value when it reaches the loop value.

5. Automatic data routing module according to any one of claims 3 or 4 wherein the configuration signal set includes an offset enable value for enabling or disabling the driver signal offset.

6. Automatic data routing module according to claim 5 wherein the offset of the transfer module (MTR) drive signal is disabled.

7. Automatic data routing module according to any one of claims 2 to 6 wherein the drive signal of the set of selectors is configured to indicate to each selector which data to select from the input buffer among several concatenated data.

8. Automatic data routing module according to any one of claims 2 to 7 wherein the assembler's drive signal is configured to tell the assembler which selectors to choose as input.

9. Automatic data routing module according to any one of claims 2 to 8 wherein the drive signal of the transfer module is configured to instruct the transfer module to which output buffer to transfer data from the assembly buffer.

10. Automatic data routing module according to any one of claims 2 to 9 wherein the values ​​of the configuration signals are defined so that the routing module is configured to receive data read from local memories in interleaved form according to a first interleaving configuration, the input buffers being sized to receive a concatenation of several data from a line of local memory.

11. Automatic data routing module according to claim 10, wherein the values ​​of the configuration signals are defined such that the routing module is configured to provide, in the output buffers, data intended to be written to local memories in interleaved form according to a second different interleaving configuration from the first interleaving configuration.

12. Automatic data routing module according to any one of the preceding claims comprising several assemblers (ASBi,ASB2) and several transfer modules (MTRi,MTR2) and a decision body (ORG) for managing the transfer priorities of the outputs of the transfer modules to the output buffers.

13. A single-instruction, multiple-data type computer architecture comprising a host processor (PROC) and a hardware accelerator (ACC) comprising multiple compute blocks (BCNs), each compute block (BCN) comprising a local memory (BMEM) and at least one elementary processor (PE), a global controller (CTRL) and an automatic data routing module (ARA) according to any one of the preceding claims configured to modify the placement of data in local memories according to a placement instruction generated by the global controller, the global controller being configured to set the configuration signals of the control unit of the automatic routing module from the placement instruction.

14. Calculator according to claim 13 further comprising an address generator configured to generate a read address in local memories to read the data to be transferred to the automatic routing module and a write address in local memories to write the data provided by the automatic routing module.

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