Method for making a CFET transistor device

Abstract

Method for manufacturing a CFET transistor device. This description relates to a method for manufacturing a CFET transistor device, comprising: - fabrication of a first semiconductor superlattice (102) surmounted by a first dielectric layer (110); - fabrication of a second semiconductor superlattice (112) surmounted by a second dielectric layer (120); - bonding of the first and second dielectric layers to each other; - consolidation treatment carried out at a first temperature below 500°C; - etching of at least one trench (122) through at least the second semiconductor superlattice, the second dielectric layer, and at least a portion of the thickness of the first dielectric layer; - annealing carried out at a second temperature greater than or equal to 500°C. Figure for the abstract: Fig. 4

Description

Title of the invention: Method for implementing a CFET transistor device. Technical field

[0001] This description relates generally to the field of semiconductor device manufacturing, and more particularly to the realization of CFET (Complementary Field-Effect Transistors) devices. Previous technique

[0002] A CFET transistor device comprises, on a substrate, superimposed semiconductor nanosheets forming the active regions of transistors of different conductivity types, nMOS and pMOS. The nanosheets forming the active regions of the nMOS transistors are separated from those forming the active regions of the pMOS transistors by dielectric material.

[0003] The nanosheet stacks used for the realization of a CFET transistor device can be manufactured in two different ways: monolithic or sequential.

[0004] The sequential fabrication of these stacks consists of separately producing, on different substrates, the stacks of layers used to create the active regions of different types of transistors in the form of two independent and distinct structures, and then joining them by bonding. One of the two substrates used is then removed, leaving only one to support the resulting assembly.

[0005] Compared to monolithic manufacturing in which the layers used to create the active regions of the two types of transistors are made successively one on top of the other in the form of a single stack on the same substrate, sequential manufacturing of super-networks makes it possible to optimize each of them separately before bonding, and thus consider obtaining more efficient CFET transistors.

[0006] The bonding is carried out between two dielectric layers, each formed at the top of one of the fabricated superlattices. Ideally, the thicknesses of these dielectric layers are small, typically such that the total thickness of the dielectric material between the superlattices is less than 50 nm. The bonding is generally a direct hydrophilic bond. A consolidation anneal at a temperature of 500°C or higher is then performed.

[0007] However, it is very difficult to achieve direct hydrophilic bonding with such thin dielectric layers because defects will be generated at the bonding interface during the annealing process used to consolidate the interface. Indeed, defects appear at the bonding interface when the consolidation annealing is carried out at a temperature of 500°C or higher, particularly when the thin dielectric layers are produced by thermal oxidation of a semiconductor. These defects are created due to water trapped at the bonding interface, which passes through the dielectric layers and reacts with the semiconductor against which the dielectric layers are placed. This reaction generates hydrogen gas, which becomes trapped and leads to the formation of bubbles at the bonding interface. Summary of the invention

[0008] There is a need to propose a method for implementing a CFET transistor device that does not have the disadvantages of known methods of implementation.

[0009] An embodiment overcomes all or part of the drawbacks of known methods and proposes a method for implementing a CFET transistor device, comprising at least:

[0010] - realization, on a first substrate, of a first stack comprising at a first semiconductor layer and a second semiconductor layer arranged one on top of the other, one of the first and second semiconductor layers being configured to be selectively etched with respect to the other, a first dielectric layer being then made on the first stack;

[0011] - realization, on a second substrate, of a second stack comprising at least one third semiconductor layer and one fourth semiconductor layer arranged one on top of the other, one of the third and fourth semiconductor layers being configured to be selectively etched with respect to the other, a second dielectric layer being then made on the second stack;

[0012] - bonding of the first and second dielectric layers to each other;

[0013] - consolidation treatment implemented at a first temperature below 500°C;

[0014] - engraving of at least one trench through at least the second stack, the second dielectric layer and at least part of the thickness of the first dielectric layer;

[0015] - annealing carried out at a second temperature greater than or equal to 500°C.

[0016] According to a particular embodiment, the bonding of the first and second dielectric layers to each other involves a direct hydrophilic bonding of the first and second dielectric layers against each other.

[0017] According to a particular embodiment, the first and second dielectric layers are made such that the total thickness of the first and second dielectric layers bonded to each other is less than or equal to 50 nm.

[0018] According to a particular embodiment, the first dielectric layer is made by implementing a thermal oxidation of the first semiconducting layer, and / or the second dielectric layer is made by implementing a thermal oxidation of the third semiconducting layer.

[0019] According to a particular embodiment, the first and third semiconductor layers comprise silicon, and / or the second and fourth semiconductor layers comprise SiGe.

[0020] According to a particular embodiment, the consolidation treatment corresponds to a first annealing, and the annealing carried out after the etching corresponds to a second annealing.

[0021] According to a particular embodiment, the first substrate corresponds to a bulk silicon substrate, and / or in which the second substrate corresponds to an SOI substrate.

[0022] According to a particular embodiment, the first temperature is between 200°C and 300°C, and / or the second temperature is between 550°C and 700°C.

[0023] According to a particular embodiment, the first stack comprises several first semiconductor layers and several second semiconductor layers arranged alternately on top of each other, and / or the second stack comprises several third semiconductor layers and several fourth semiconductor layers arranged alternately on top of each other.

[0024] According to a particular embodiment, the process further comprises, between the bonding of the first and second dielectric layers to each other and the engraving of the trench, the removal of at least a part of the second substrate.

[0025] According to a particular embodiment, the second substrate corresponds to an SOI substrate, and the removal of said at least a part of the second substrate corresponds to the removal of a massive layer and a buried oxide layer of the SOI substrate.

[0026] According to a particular embodiment, the trench is engraved through the entire thickness of the first dielectric layer and also through the first stack.

[0027] According to a particular embodiment, several trenches are engraved, between the consolidation treatment and the annealing, through the first and second stacks such as remaining portions of the first or second semiconductor layers and remaining portions of the third or fourth semiconductor layers form nanosheets configured to form the active regions of CFET transistors.

[0028] According to a particular embodiment, the method further comprises, after annealing, etching remaining portions of the first or second semiconductor layer and / or etching remaining parts of the third or fourth semiconductor layer, and deposition of a gate dielectric and a gate conductive material around first parts of the remaining portions of the semiconductor layers forming channels of the CFET transistors, and doping of second parts of the remaining portions of the semiconductor layers forming source and drain regions of the CFET transistors. Brief description of the drawings

[0029] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0030] Fig. 1, Fig. 2, Fig. 3 and Fig. 4 schematically represent steps of an example of a process for making a CFET transistor device according to a particular embodiment. Description of the implementation methods

[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional, and material properties. In the figures, to facilitate their reading, the different elements and the different material layers are not shown at the same scale relative to each other.

[0032] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various steps implemented after the second annealing and relating to the fabrication of CFET transistor components other than nanosheets are not detailed. Those skilled in the art will be able to implement such steps based on the description given here.

[0033] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0034] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative terms, such as "above," "below," "superior," "inferior," etc., or orientation qualifiers, such as "horizontal," "vertical," etc., refer, unless otherwise specified, to the orientation of the figures in a normal operating position. However, these terms do not imply the actual position and orientation of the device during use.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0036] An example of a method for making a CFET transistor device is described below in relation to figures 1 to 4.

[0037] A first stack 102 comprising at least one first semiconductor layer 104 and at least one second semiconductor layer 106 arranged one on top of the other is carried out on a first substrate 108, for example by epitaxy. The first stack 102 forms a first super-lattice of semiconductor layers 104, 106 arranged on the first substrate 108. The first substrate 108 corresponds, for example, to a bulk semiconductor substrate or SOI (Silicon-On-Insulator), or any type of substrate suitable for carrying out the first stack 102.

[0038] According to a particular embodiment, the first substrate 108 corresponds to a bulk silicon substrate. For example, its diameter is approximately 300 mm and its thickness is approximately 775 µm. Prior to the realization of the first stack 102 on the first substrate 108, the first substrate 108 can be cleaned, for example with ozonated water containing 15 ppm of ozone dissolved in deionized water, then with SCI (a mixture of 30% ammonia, 30% hydrogen peroxide and water in proportions of 1:1:5), followed by SC2 (a mixture of 30% hydrochloric acid, 30% hydrogen peroxide and water in proportions of 1:1:5).

[0039] When the first semiconductor layer(s) 104 are intended for use in the realization of active regions of nMOS transistors, the first substrate 108 may comprise silicon with a crystalline orientation (100). When the first semiconductor layer(s) 104 are intended for use in the realization of active regions of pMOS or nMOS transistors, the first substrate 108 may comprise silicon with a crystalline orientation (110). When the first substrate 108 is of the bulk type, the entire semiconductor, for example silicon, of the first substrate 108 may have this crystalline orientation. When the first substrate 108 is of the SOI type, the semiconductor of the surface semiconductor layer of the first substrate 108 may have this crystalline orientation, although the orientation of the semiconductor of the bulk layer of the SOI substrate may or may not be different.

[0040] In the example described, because the semiconductor layers 104, 106 of the first stack 102 are made by epitaxy from the top face of the first substrate 108, the crystalline orientation of the semiconductor from which the epitaxy is implemented is also that of the semiconductors of these layers 104, 106. Thus, electron mobility is favored when the active regions of nMOS transistors are made from crystalline orientation semiconductor (100), and hole mobility is favored when the active regions of pMOS transistors are made from crystalline orientation semiconductor (110).

[0041] The semiconductors of the first and second layers 104, 106 are such that one of the first and second layers 104, 106 can be selectively etched with respect to the other. This etching selectivity will subsequently be used to etch the second layer 106, in particular when creating a gate around a portion of the first layer 104 intended to form the channel of one of the CFET transistors, or to etch the first layer 104, in particular when creating a gate around a portion of the second layer 106 intended to form the channel of one of the CFET transistors. In the example described, the first stack 102 is made such that the first layer 104 contains silicon and the second layer 106 contains SiGe. Conversely, it is possible that the first layer 104 contains SiGe and the second layer 106 contains silicon.For example, the second 106 layer contains SiO,25Geo,75 and is approximately 10 nm thick, while the first 104 layer contains silicon and is approximately 17.5 nm thick. More generally, the thickness of the first 104 layer can range from approximately 5 nm to 22.5 nm, and / or the thickness of the second 106 layer can range from approximately 5 nm to 22.5 nm. Furthermore, when the second 106 layer contains SiGe, the germanium content of this SiGe can range from 20% to 35%.

[0042] The number of first layers 104 and second layers 106 of the first stack 102 depends on the number of nanosheets intended to form the active regions of the transistors that will subsequently be fabricated from these nanosheets. Advantageously, the first stack 102 comprises several first layers 104 and several second layers 106 arranged alternately on top of each other. In the example of [Fig. 1], the first stack 102 comprises three first layers 104 and three second layers 106. For example, the first stack 102 may comprise a total number of first layers 104 and second layers 106 ranging from two to six.

[0043] A first dielectric layer 110 is formed at the top of the first stack 102, that is, on the last of the first layers 104 in the example described here (or on the first layer 104 when the first stack 102 has only one first layer 104). For example, the first dielectric layer 110 may correspond to a layer of SiO2 formed by thermal oxidation and whose thickness is approximately 5 nm. The implementation of this thermal oxidation This process can consume a thickness of approximately 2.5 nm in the last of the first layers 104, leaving a remaining thickness of approximately 15 nm in the last of the first layers 104 after this thermal oxidation. This oxidation can be carried out under a humid atmosphere, for example at a temperature of approximately 700°C in a water (H2O) atmosphere. A cleaning process similar to that previously described for the first substrate 108 can be performed after the first dielectric layer 110 has been formed.

[0044] Alternatively, the first dielectric layer 110 may comprise an oxide formed by deposition, for example based on TEOS (tetraethyl orthosilicate) or silane. According to another embodiment, the first dielectric layer 110 may comprise silicon nitride, for example deposited by LPCVD (low-pressure chemical vapor deposition). According to yet another embodiment, the first dielectric layer 110 may comprise a so-called "low-k" dielectric material, or one with low permittivity, such as SiOCH, or a so-called "high-k" dielectric material, or one with high permittivity, such as HfO2.

[0045] Alternatively, the first dielectric layer 110 can correspond to a stack of several superimposed layers made of different dielectric materials.

[0046] As an alternative to the example described above, the first stack 102 may include additional layers of materials in addition to those described above.

[0047] A second stack 112 comprising at least a third semiconductor layer 114 and at least a fourth semiconductor layer 116 arranged one on top of the other is fabricated on a second substrate 118, for example by epitaxy. The second stack 112 forms a second super-lattice of semiconductor layers 114, 116 arranged on the second substrate 118. The second substrate 118 corresponds, for example, to a bulk semiconductor substrate or a SOI (Silicon-On-Insulator) substrate, or any type of substrate suitable for fabricating the second stack 112.

[0048] According to a particular embodiment, the second substrate 118 may correspond to a SOL substrate. For example, its diameter is approximately 300 mm. This SOI substrate comprises, for example, a bulk silicon layer approximately 775 pm thick, a buried oxide layer approximately 145 nm thick, and a surface silicon layer approximately 15 nm thick. Prior to the realization of the second stack 112 on the second substrate 118, the second substrate 118 may be cleaned in a manner similar to the cleaning of the first substrate 108 described above.

[0049] When the third semiconductor layer(s) 114 are intended to be used for the realization of active regions of nMOS-type transistors, the second substrate 118 may include crystalline orientation silicon (100). When the third semiconductor layer(s) 114 are intended for use in the realization of active regions of pMOS-type transistors, the second substrate 118 may include crystalline orientation silicon (110). When the second substrate 118 is of the bulk type, the entire semiconductor, for example silicon, of the second substrate 118 may have this crystalline orientation. When the second substrate 118 is of the SOI type, the semiconductor of the surface semiconductor layer of the second substrate 118 may have this crystalline orientation, while the orientation of the semiconductor of the bulk layer of the SOI substrate may or may not be different.

[0050] The semiconductors of the third and fourth layers 114, 116 are such that one of the third and fourth layers 114, 116 can be selectively etched with respect to the other. This etching selectivity will subsequently be used to etch the fourth layer 116 when fabricating a gate around a portion of the third layer 114 intended to form the channel of one of the CFET transistors, or to etch the third layer 114, in particular, when fabricating a gate around a portion of the fourth layer 116 intended to form the channel of one of the CFET transistors. In the described embodiment, the second stack 112 is constructed such that the third layer 114 comprises silicon and the fourth layer 116 comprises SiGe. Conversely, it is possible for the third layer 114 to comprise SiGe and the fourth layer 116 to comprise silicon.For example, the fourth layer 116 contains Si0.25Ge0.75 and is approximately 10 nm thick, while the third layer 114 contains silicon and is approximately 17.5 nm thick. More generally, the thickness of the third layer 114 can range from approximately 5 nm to 22.5 nm, and / or the thickness of the fourth layer 116 can range from approximately 5 nm to 22.5 nm. Furthermore, when the fourth layer 116 contains SiGe, the germanium content of this SiGe can range from 20% to 35%.

[0051] The number of third layers 114 and fourth layers 116 of the second stack 112 depends on the number of nanosheets intended to form the active regions of the transistors that will subsequently be fabricated from these nanosheets. Advantageously, the second stack 112 comprises several third layers 114 and several fourth layers 116 arranged alternately on top of each other. In the example of [Fig. 1], the second stack 112 comprises three third layers 114 and three fourth layers 116. For example, the second stack 112 may comprise a total number of third layers 114 and fourth layers 116 of between two and six, this number of layers being either the same as or different from the number of layers in the first stack 102.

[0052] A second dielectric layer 120 is made on top of the second stack 112, that is to say on the last of the third layers 114 in the example described here (on the third layer 114 when the second stack 112 has only one third layer 114). For example, the second dielectric layer 120 is similar to the first dielectric layer 110, obtained by thermal oxidation. A cleaning similar to that previously described for the first substrate 108 can be carried out after the fabrication of the second dielectric layer 120.

[0053] The embodiment variants previously described for the first dielectric layer 110 can be applied to the second dielectric layer 120.

[0054] In the example described, the thicknesses of the first and second dielectric layers 110, 120 are such that the sum of these thicknesses is less than or equal to 50 nm, or advantageously less than or equal to 30 nm, or 20 nm, or 15 nm, or 10 nm. For example, the thickness of each of the first and second dielectric layers 110, 120 can be about 5 nm, or even about 3 nm.

[0055] As an alternative to the example described above, the second stack 112 may include additional layers of materials to those previously described.

[0056] The structures obtained at this stage of the process are shown schematically in [Fig.1].

[0057] The first and second dielectric layers 110, 120 are then bonded together. In the described embodiment, this bonding is achieved by implementing a direct hydrophilic bonding of the first and second dielectric layers 110, 120 together.

[0058] According to a particular example, before implementing this bonding, one or more cleaning and / or preparation and / or treatment steps for the surfaces of the first and second dielectric layers 110, 120 to be bonded together may be carried out. For example, particulate cleaning of the first and second dielectric layers 110, 120, for example using a very high frequency ultrasonic generator, or megasound, with a frequency, for example, of 1 MHz, in liquid phase with a 1% solution of diluted ammonia, at a power of 2 W / cm² and for a duration of 60 s, may be carried out. Subsequently, a plasma treatment, for example at 0.3 mbar of oxygen with two electrodes at 397 kHz and 40 kHz with a power of 75 and 100 W and for a duration of 30 s, may be performed on each surface to be bonded.For example, at least one of the following plasmas can be used: O2, N2, CF4 0.2% in O2 or N2, SF6 0.2% in O2 or N2. A single-electrode plasma treatment chamber operating at 13.56 MHz can be used, for example. Finally, an ethalonamine-based solution with a concentration of 10⁴ M is spread, for example, on the surfaces to be bonded. Alternatively, ethalonamine can be replaced, for example, by diethylethalonamine, sodium hydroxide, or hydrazine. Plasma treatment as described above will allow... to strengthen the bonding achieved subsequently. Such plasma treatment is optional; treatment with ethalonamine can be implemented alone.

[0059] Other types of treatment, cleaning and / or preparation of surfaces to be bonded may be carried out before bonding.

[0060] The bonding is then carried out between the upper surfaces of the first and second dielectric layers 110, 120, for example under vacuum.

[0061] The structure obtained at this stage of the process is shown in [Fig.2].

[0062] A bond consolidation treatment applied between the first and second dielectric layers 110, 120 is then carried out at a first temperature TL. A waiting period between bonding and the application of this treatment is preferably between 0 and 2 hours. In the described embodiment, this consolidation treatment is a first annealing. The first temperature TL can be strictly less than 500°C, or less than or equal to 450°C, or 400°C, or 300°C, or 200°C, or even equal to 150°C or 100°C. Preferably, the first temperature is between 200°C and 300°C. This treatment is, for example, carried out for a period of between approximately 10 minutes and 2 hours, or between 30 minutes and 1 hour, and, for example, equal to approximately two hours. Furthermore, this treatment can, for example, be carried out under a nitrogen atmosphere.Alternatively, by implementing plasma treatment and using an ethalonamine solution, it is possible to leave the treated assembly at room temperature for several days, for example at least 15 days, preferably 30 days or even 60 days, before continuing with the implementation of the following steps.

[0063] The value of the temperature Tl with which the consolidation treatment is implemented is strictly less than 500°C, which avoids the appearance of defects at the bonding interface formed by the first and second dielectric layers 110, 120, between the first and second stacks 102, 112.

[0064] In the described embodiment, at least part of the second substrate 118 is removed. When the second substrate 118 is an SOI substrate, this removal may involve removing the bulk layer of the SOI substrate, for example by lapping or mechanical thinning, followed by wet etching with TMAH (at a concentration of 25%) at 70°C, or dry etching, using the buried oxide layer as a stop layer. The buried oxide layer is then removed, for example with a 10% HF solution.

[0065] The structure obtained at this stage of the process is shown in [Fig.3], on which the reference 121 designates the silicon surface layer of the second substrate 118 which is retained on the second stack 112.

[0066] At least one trench 122 is then etched through at least the second stack 112, the second dielectric layer 120 and at least part of the thickness of the first dielectric layer 110. In the example described, the trench or trenches 122 are etched through the entire thickness of the first dielectric layer 110 and also through the first stack 102 and part of the thickness of the first substrate 108. For example, a step of deposition of a hard mask, then photolithography and ion etching can define several trenches 122 such that remaining portions of the first and second stacks 102, 112 and of the dielectric layers 110, 120 form fins, or fins, of a width, for example, of a few tens of nanometers.The remaining portions of the first and third layers 104, 114 form, in this example, stacks of nanosheets configured to form the active regions of the CFET transistors of the device. The width of the etched trenches 122, corresponding to the distance between adjacent remaining portions of the first and second stacks 102, 112 and the dielectric layers 110, 120, is, for example, at least 50 pm or at least 200 pm, for example, depending on the temperature ramp used for the consolidation annealing subsequently implemented.

[0067] The structure obtained at this stage of the process is shown in [Fig.4].

[0068] A consolidation anneal for the bond between the first and second dielectric layers 110, 120 is then carried out at a second temperature T2 greater than or equal to 500°C. Whereas the previous consolidation treatment corresponds to a first anneal carried out at a temperature below 500°C, this consolidation anneal carried out here corresponds to a second consolidation anneal carried out at a temperature greater than or equal to 500°C. The second temperature T2 of this anneal can be greater than or equal to 600°C, or 650°C, and for example, between 550°C and 1100°C. This anneal is, for example, carried out for a duration of between approximately 30 minutes and 2 hours. Advantageously, this anneal is carried out at a temperature between 550°C and 700°C, and for example, equal to 650°C, for approximately 30 minutes. In addition, this annealing is for example carried out under an atmosphere of N2 or Ar.

[0069] By way of example, annealing can be carried out under a humid atmosphere, for example in an autoclave at a temperature of 500°C under a pressure of 250 bars where the water is then a supercritical fluid.

[0070] During this annealing, given the high temperature involved, gas is generated in the first and second dielectric layers 110, 120. However, thanks to the previously engraved trench(s) 122, the flanks of the remaining portions of the stacks 102, 112 form, at the level of the first and second dielectric layers 110, 120, free surfaces allowing the generated gas to escape and no defects are formed at the interfaces with the stacks 102, 112 nor at the bonding interface between the dielectric layers 110, 120.

[0071] The consolidation treatment makes it possible to strengthen the bonding interface sufficiently to allow the removal, for example by mechano-chemical thinning, of at least part of the second substrate, while remaining at a temperature low enough not to generate a defect at the bonding interface or at the interfaces between the dielectric layers 110, 120 and the stacks 102, 112.

[0072] CFET transistors are completed from the obtained nanosheet stacks. The steps implemented to complete the realization of CFET transistors are, for example, similar to those described in the document by S. Liao et al., “Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Eogic Technology Scaling” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, or in the document “3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling”, C.-Y. Huang et al., Technical Digest, International Electron Devices Meeting, IEDM, 2020, pp. 20.6.1-20.6.4.In general, the fabrication of CFET transistors from the structure obtained after annealing at temperature T2 involves at least the fabrication of the gates, which includes selective etching of the remaining portions of the second and fourth semiconductor layers 106, 116 relative to the 104, 114 layers, and the deposition of a gate dielectric and a gate conductor around the remaining portions of the first and third semiconductor layers 104, 114, and the implementation of selective epitaxies to form the sources and drains of the transistors. Other steps, not detailed here, are also implemented to complete the fabrication of the CFET transistors.

[0073] Alternatively, the fabrication of CFET transistors from the structure obtained after annealing at temperature T2 may at least include the fabrication of gates which includes selective etching of the remaining portions of the first and third semiconductor layers 104, 114 with respect to the layers 106, 116, and deposition of a gate dielectric and a gate conductive material around a portion of the remaining portions of the second and fourth semiconductor layers 106, 116, and the implementation of selective epitaxies to form the source and drain of the transistors. Other steps not detailed here are also implemented to complete the fabrication of the CFET transistors.If selective etching of layers 106 and 114 with respect to layers 104 and 116, or selective etching of layers 104 and 116 with respect to layers 106 and 114 is desirable, it is possible to carry out this selective etching in two stages, by alternately protecting the sides of the parts of the fins formed by the remaining portions of the first and second. stacks 102, 110 and other layers which must be preserved during each of these engravings.

[0074] The process for making the device described above makes it possible to obtain, between the first and second stacks 102, 112, a dielectric portion of small thickness, for example less than 50 nm, consolidated and without defects at the bonding interface.

[0075] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0076] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Method of making a CFET transistor device, comprising at least: - making, on a first substrate (108), a first stack (102) comprising at least a first semiconductor layer (104) and a second semiconductor layer (106) arranged one on top of the other, one of the first and second semiconductor layers (104, 106) being configured to be selectively etched with respect to the other, a first dielectric layer (110) being made then on the first stack (102);- fabrication, on a second substrate (118), of a second stack (112) comprising at least a third semiconducting layer (114) and a fourth semiconducting layer (116) arranged one on top of the other, one of the third and fourth semiconducting layers (114, 116) being configured to be etched selectively with respect to the other, a second dielectric layer (120) being then fabricated on the second stack (112); - bonding of the first and second dielectric layers (110, 120) to each other; - consolidation treatment carried out at a first temperature below 500°C; - etching of at least one trench (122) through at least the second stack (112), the second dielectric layer (120) and at least a part of the thickness of the first dielectric layer (110); - annealing carried out at a second temperature greater than or equal to 500°C.;

2. A method according to claim 1, wherein the bonding of the first and second dielectric layers (110, 120) to each other comprises a direct hydrophilic bonding of the first and second dielectric layers (110, 120) against each other.

3. A method according to any one of the preceding claims, wherein the first and second dielectric layers (110, 120) are made such that the total thickness of the first and second dielectric layers (110, 120) bonded to each other with a thickness of less than or equal to 50 nm.

4. A method according to any one of the preceding claims, wherein the first dielectric layer (110) is made by implementing a thermal oxidation of the first semiconducting layer (104), and / or wherein the second dielectric layer (120) is made by implementing a thermal oxidation of the third semiconducting layer (114).

5. A method according to any one of the preceding claims, wherein the first and third semiconductor layers (104, 114) comprise silicon, and / or wherein the second and fourth semiconductor layers (106, 116) comprise SiGe.

6. A method according to any one of the preceding claims, wherein the consolidation treatment corresponds to a first annealing, and wherein the annealing carried out after etching corresponds to a second annealing.

7. A method according to any one of the preceding claims, wherein the first substrate (108) corresponds to a bulk silicon substrate, and / or wherein the second substrate (118) corresponds to an SOI substrate.

8. A method according to any one of the preceding claims, wherein the first temperature is between 200°C and 300°C, and / or wherein the second temperature is between 550°C and 700°C.

9. A method according to any one of the preceding claims, wherein the first stack (102) comprises several first semiconductor layers (104) and several second semiconductor layers (106) arranged alternately on top of each other, and / or wherein the second stack (112) comprises several third semiconductor layers (114) and several fourth semiconductor layers (116) arranged alternately on top of each other.

10. A method according to any one of the preceding claims, further comprising, between the bonding of the first and second dielectric layers (110, 120) to each other and the engraving of the trench (122), the removal of at least a portion of the second substrate (118).

11. A method according to claims 7 and 10, wherein the second substrate (118) corresponds to an SOI substrate, and wherein the removal of said at least a part of the second substrate (118) corresponds to the removal of a bulk layer and a buried oxide layer of the SOI substrate.

12. A method according to any one of the preceding claims, wherein the trench (122) is engraved through the entire thickness of the first dielectric layer (110) and also through the first stack (102).

13. A method according to claim 12, wherein several trenches (122) are etched, between the consolidation treatment and the annealing, through the first and second stacks (102, 112) such that remaining portions of the first or second semiconductor layers (104, 106) and remaining portions of the third or fourth semiconductor layers (114, 116) form nanosheets configured to form the active regions of CFET transistors.

14. A method according to any one of the preceding claims, further comprising, after annealing, etching remaining portions of the first or second semiconductor layer (104, 106) and / or etching remaining portions of the third or fourth semiconductor layer (112, 114), and deposition of a gate dielectric and a gate conductive material around first portions of the remaining semiconductor layer portions forming channels of the CFET transistors, and doping of second portions of the remaining semiconductor layer portions forming source and drain regions of the CFET transistors.

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