A method for generating a task-specific adapted topology for circuit quantum electrodynamics (cQED)-based hardware, and a cQED hardware fabrication system implementing such a method.

Abstract

The invention relates to a method for generating a task-specific adapted topology for circuit quantum electrodynamics (cQED)-based hardware, characterized in that it comprises the iterative steps of: - determining an error made by a circuit initially obtained by transpiling an agnostic M qubit generated from a client task, - comparing said transpiled circuit error to an error threshold corresponding to said circuit of agnostic M qubits, - if said transpiled circuit error is greater than said error threshold, modifying certain of said hardware specifications to be addressed in the transpilation step, - if said transpiled circuit error is less than said error threshold, providing said transpiled circuit as a task-specific adapted topology to a chip design and nanofabrication unit. Figure to be published with the abstract: Fig. 1

Description

Title of the invention: A method for generating a task-specific adapted topology for a quantum electrodynamics (cQED)-based hardware and a manufacturing system implementing such a method FIELD OF INVENTION

[0001] The present invention relates to a method for generating a task-specific adapted topology for circuit and cavity quantum electrodynamics (cQED)-based hardware. It also relates to a cQED hardware fabrication system implementing such a method.

[0002] DEFINITIONS

[0003] Agnostic circuit: A quantum circuit is said to be agnostic when it is written as a circuit model that ignores any hardware specificities and requirements. It focuses solely on the manipulation of quantum information.

[0004] All-to-all connectivity (ATA): The connectivity of a processor that is represented using a complete graph is said to be all-to-all.

[0005] Connectivity: by representing a processor as a graph in which nodes represent qubits and edges represent a physical link between qubits, the connectivity of a quantum processor refers to the connectivity (in graph theory) of the graph.

[0006] Coupling map: A coupling map refers to the graphical representation of a quantum processor.

[0007] cQED material: Quantum electrodynamics-based circuit (or cavity) (cQED) material.

[0008] cQED material with long-range interaction: Quantum electrodynamics-based circuit (or cavity) (cQED) material implementing two-qubit gates with long-range interaction, for example mediated by a resonator.

[0009] Crosstalk: the effect of residual physical coupling between qubits when they are not expected to undergo an operation together.

[0010] Crosstalk and routing compromise: Compromise between crosstalk errors occurring in cQED hardware cavity-mediated two-qubit gates and intermediate gate errors for routing information around the processor.

[0011] Fidelity: In quantum computing, Fidelity quantifies how well the actual state or operation aligns with the expected or ideal state or operation.

[0012] Gate set: The set of gates that a processor can implement is called its quantum gate set.

[0013] Inactive qubit: a qubit is said to be inactive when it is not undergoing an operation.

[0014] iSWAP: an iSWAP gate is a two-qubit gate that swaps information between two different qubits with the addition of a purely complex phase when they are in two different states. The gate does not affect the qubits if they are in the same state.

[0015] Quantum circuit: A quantum circuit refers to a quantum computing model in which operations are decomposed into quantum logic gates and an algorithm, which are represented as a sequence of such gates applied to a qubit register.

[0016] Quantum gate: In digital quantum computing, a quantum gate, or quantum logic gate, refers to an elementary quantum operation on the processor.

[0017] Routing permutations: refers to permutations that are used only to bring information to a required position in the processor, but are not part of a quantum-agnostic algorithm.

[0018] Single qubit gate: a gate operating on a single qubit is called a single qubit gate.

[0019] Permutations: refers to a permutation of the state of two qubits.

[0020] Topology: by representing a processor as a graph in which nodes represent qubits and edges represent the physical link between qubits, the topology of a quantum processor refers to the connectivity (in graph theory) of the graph and the mapping of a circuit to physical qubits.

[0021] Two-qubit gate: a gate operating two qubits is called a two-qubit gate. technical background

[0022] Quantum algorithms are mostly written in a hardware-agnostic manner. For this reason, before execution on hardware, an algorithm must be transpiled [1]. In this step, the algorithm is first translated into the hardware's native gate set, then logical qubits of the algorithm are associated with physical qubits in the hardware, and, depending on the physical connections that actually exist between the physical qubits, intermediate SWAP gates are added to receive any missing direct connections.

[0023] This step is the routing [2, 3] which allows the processor topology to be received. Consequently, transpilation should depend on the hardware's natural logic gate set and its topology [4, 5] (and specific strategies even have were designed based on specific hardware [6]) the choice of which can strongly affect hardware performance when running the algorithm and considering the limitations of quantum computing today, having hardware tuned to be efficient in performing a specific task is quite sensible.

[0024] cQED hardware with long-range interaction has the very interesting property of theoretically being able to interconnect distant qubits, thus enabling, in principle, all-to-all connectivity. In other words, the qubit array can be represented as a fully connected graph. In practice, such an all-to-all connection, due to residual couplings among the qubits, induces defects in hardware operations, known as crosstalk errors.

[0025] To moderate the amount of crosstalk errors, some connections in the processor can always be removed, moving away from the all-connected processor at the cost of more complex routing. Consequently, such a processor type offers considerable freedom in the way the processor topology is constructed. Although a number of groups [7-9], such as that of Lieven Vandersypen at Delft University of Technology

[10] , have investigated crosstalk errors, and, even more so, that of Guido Burkard at the University of Konstanz [11, 12], has conducted a similar study on crosstalk errors resulting from residual couplings, until now there has been no tool available to model and predict such errors in such a simple and accurate way.

[0026] Similarly, while routing algorithms have been proposed and are widely used during the transpilation process, for example on IBM's Qiskit platform [13, 14], and noise-adaptive or optimized-mapping compilation algorithms have also been presented [13-17], so far no one has taken advantage of an adaptable topology.

[0027] The problem to be solved can be expressed as:

[0028] Given an algorithm, a circuit-agnostic CA implementation, an error threshold Ethr, and the set of allowed connected graphs G = {G(V,E)}, with sets of vertices and edges (V, E) for each graph, representing all allowed hardware topologies, find a graph G*(V,E) allowing the execution of the CA within the limits of the error threshold Ethr, i.e., such that:

[0029] (1)

[0030] where Ecirc G(V,E) is defined as the total error rate of a circuit executed on V hardware qubits with connectivity represented by the graph G(V,E). Such a total circuit error is a function of the total circuit gate and crosstalk errors, a compromise of which guides the choice of G*(V,E) within the limits of G. In Indeed, the total circuit gate error increases with the number of routing permutations, while the crosstalk error increases with processor connectivity.

[0031] For example, a high-connectivity graph reduces the required number of routing SWAP gates because, from any qubit, the distance to reach any other qubit is relatively small. However, a high-connectivity processor is then also affected by a greater amount of crosstalk errors.

[0032] On the other hand, a low-connectivity processor has few crosstalk errors since all the qubits are more isolated, but it is also likely to require a large number of routing SWAP gates for the same reason. The routing cost is easily quantified by the number of additional intermediate SWAP gates needed to connect remote qubits.

[0033] Among the cQED architectures to which the procedure can be applied, one can find semiconductor spin qubits, connected by an on-chip resonator, or Rydberg atoms, linked by a macroscopic cavity. Spin qubits can, for example, be hosted in carbon nanotubes, for example in a double quantum dot structure. A resonator-on-a-chip can, for example, be a coplanar waveguide, a ribbon line, or a microstrip. It can be made of a high-impedance material such as niobium nitride. Summary of the invention

[0034] This objective is achieved with a method for generating a task-specific adapted topology for hardware based on the quantum electrodynamics of circuits or cavities (cQED), characterized in that it further comprises iterative steps consisting of:

[0035] - to determine an error committed by said transpiled circuit,

[0036] - compare said transpiled circuit error to said error threshold,

[0037] - if said transpiled circuit error is greater than said error threshold, modify some of the aforementioned hardware specifications to be addressed in the transpilation step,

[0038] - if said transpiled circuit error is less than said error threshold, provide said transpiled circuit as a task-specific adapted topology for a unit of chip design and nanofabrication.

[0039] The method according to the invention may further include a transpilation step of the circuit of agnostic M qubits, to generate a transpiled circuit, said transpilation step implementing hardware specifications.

[0040] The method according to the invention may further include an initial step of generating, from a client task, a circuit of M agnostic qubits and a corresponding error threshold.

[0041] The hardware specifications preferably include a set of native gates and gate errors, and / or a set of allowed technologies, and / or a coupling on / off ratio.

[0042] In an advantageous embodiment of the invention, the generation process further comprises the steps of:

[0043] - to introduce input data comprising an agnostic AC circuit implementing an algorithm chosen from a set of task-adaptive topology algorithms (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold Ethr, a on / off coupling ratio, and an idle qubit fidelity Fb

[0044] - initialize, from the said input data, a translation Co of the circuit agnostic CA in a set of hardware gates, a number N of qubits in said agnostic circuit Co and a gate fidelity FG,

[0045] - if said gate fidelity FG is greater than an algorithm fidelity threshold Fthr, iteratively calculate a new number n of qubits and a circuit fidelity Fcirc for a circuit to be transpiled, until said circuit fidelity Fcirc is greater than said algorithm fidelity threshold Fthr.

[0046] In a first algorithmic embodiment, in which the input data further include a length CA of the agnostic circuit, the initialization step further includes the initialization of the length Lo of the translated circuit material, and the calculation step further includes the calculation of a length L of the circuit to be transpiled.

[0047] In a second algorithmic embodiment, in which the input data further include a predetermined optimal variation of fidelity Aopt, the method further comprises the iterative steps of:

[0048] - transpile the circuit, so as to map said circuit to hardware qubits with a coupling card and to extract a new circuit length L;

[0049] - estimating total circuit fidelities including circuit crosstalk fidelity and calculate a variation A of circuit fidelity and a decoherence AD,

[0050] - provided that the circuit fidelity Fcirc is greater than or equal to the new calculated circuit fidelity Fcircnew, increment / decrement the number n of qubits, until said circuit fidelity variation A and said decoherence AD ​​are substantially equal.

[0051] In a third algorithmic embodiment, in which the input data further include a predetermined optimal fidelity variation Aopt, the method further comprises the iterative steps of:

[0052] - transpile the circuit, so as to map said circuit to hardware qubits with a wmap coupling map and to extract a new circuit length L;

[0053] - to estimate a circuit crosstalk fidelity Fcirc,ct [G(V,E)] and a total fidelity of circuit Fcirc [G(V,E)],

[0054] - if said circuit crosstalk fidelity Fcirc,et [G(V,E)] has decreased since the step Previous, slow down the iteration and return to the wmap coupling map,

[0055] - if said circuit crosstalk fidelity Fcirc,et [G(V,E)] has increased since said Previous step, trim the edges to maximum weight and obtain a new wmapi coupling map,

[0056] - provided that said total circuit fidelity Fcirc [G(V,E)] is less than the Fidelity threshold of the Fthr algorithm, keep iterating on the steps above.

[0057] - if the accuracy Fcirc [G(V,E)] is greater than or equal to the algorithm threshold accuracy If Fthr and the optimal fidelity variation Aopt is approximately equal to 0, break the iteration and choose the wmapi coupling map,

[0058] - if the optimal variation Aopt is not equal to 0, continue the iteration until the iterative variation A! is greater than the optimal fidelity variation Aopt

[0059] The iterative steps for each algorithmic embodiment above can be implemented as a task-adaptive topology algorithm.

[0060] The task-adaptive topology can be executed on cQED hardware with long-range interaction.

[0061] The method according to the invention can be implemented to provide task-adapted topology optimized instructions for hardware nanofabrication or for quantum simulations on hardware emulators.

[0062] According to another aspect of the invention, a system is proposed for the manufacture of cQED material, implementing the process according to the invention.

[0063] The present invention thus provides three task-adaptive topology (TAT) algorithms for adjusting the topology of cQED hardware with long-range interaction to a given task, optimizing crosstalk errors, instead of considering a topology fixed a priori.

[0064] With regard to crosstalk errors, an algorithmic approach has been developed to predict the amount of crosstalk errors based on the connectivity of a processor in a cQED hardware. With such tools, each TAT algorithm chooses a topology from the set of allowed topologies in its own way, as described below.

[0065] The agnostic circuit is then transpiled to the native hardware set of gates with the chosen candidate topology. Based on the number of routing gates and our crosstalk metric, the transpiled circuit error is compared to the error threshold given by the client: if the circuit fidelity is less than a threshold (or optimized, if requested) the algorithm stops; otherwise, the procedure is repeated.

[0066] TAT algorithms can then provide task-adapted topology optimized instructions for cQED hardware fabrication, quantum simulations on hardware emulators. BRIEF DESCRIPTION OF THE FIGURES

[0067] [Fig.1] Fig.1 is a schematic functional representation of the main stages of the interaction between the customer and the hardware company in solving a given task;

[0068] [Fig.2] Figure [Fig.2] illustrates a first Q-algo that can be implemented in the process according to the invention;

[0069] [Fig.3] Figure [Fig.3] illustrates a second AQ-algo that can be implemented in the process according to the invention; and

[0070] [Fig.4] Fig.4 illustrates a third RWC-algo algorithm that can be implemented in the process according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0071] With reference to [Fig. 1], a schematic functional representation of the main stages of the interaction between the customer and the hardware company in resolving a given task, illustrates:

[0072] - in its left-hand part, a standardized process, in which the customer assigns a The task is assigned to a quantum developer who translates it into an algorithm implemented on a hardware-agnostic M qubit circuit within the limits of an error threshold provided by the client. The agnostic circuit is then transpiled to the native hardware set of gates and the pre-defined topology provided by the hardware company.

[0073] - In its right-hand part, an adaptive topology algorithm (TAT) process, in which the client assigns a task to a quantum developer who translates it into an algorithm implemented on a hardware M-agnostic qubit circuit within the limits of an error threshold given by the client.

[0074] The agnostic circuit enters the TAT algorithm: depending on the chosen algorithm, a cQED topology is selected from among the allowed topologies with a corresponding number of qubits and on / off coupling ratio, and the hardware-agnostic circuit is transpiled with such hardware specifications. This procedure is repeated until the error of the transpiled circuit is smaller than the customer error threshold (and optimized if necessary). TAT algorithms provide task-appropriate topology-optimized instructions for cQED hardware fabrication or quantum simulations on hardware emulators.

[0075] A technical solution to the problem defined above implements a mathematical formula for predicting the amount of crosstalk error as a function of the connectivity of a processor in a cQED device. In turn, various Architectures based on different connectivity among qubits are proposed. The choice of connectivity defines the hardware topology, which can be varied and fed into a quantum transpiler that translates a quantum-agnostic algorithm into the best hardware-specific algorithm.

[0076] Incorporated into an optimization algorithm that compares the ideal circuit to the transpiled one based on their operational fidelity, it is possible to deduce, from among all the proposed topologies, the one best suited to the algorithm to be executed. This tool can then lead to the production of the best available cQED hardware for a given task.

[0077] Connectivity options considered:

[0078] The different connectivity options that are explored are separated into three categories: i. Maximum connectivity: All-to-all (ATA) ii) Average connectivity: islands of n qubits connected with a variable number of "bridges" (links). The number of qubits per island, the connectivity among them, and the number of bridges per island do not necessarily have to be equal;

[0079] iii) Minimum connectivity: islands of two qubits connected by a single bridge.

[0080] Crosstalk errors

[0081] Crosstalk errors can generally be defined as errors occurring during computation due to unwanted many-body interactions within the material

[18] .

[0082] The method according to the invention can address crosstalk errors occurring within microwave cavity-mediated entanglement gates (e.g., iSWAP), due to residual couplings between inactive and active qubits. Such an error is quantified using the metric:

[0083] [Math.2]

[0084] where n is the number of inactive qubits,

[0085] [Math.3]

[0086] is the dimension of the system, Fe the entanglement fidelity, m the on / off coupling ratio between qubits integrated in the same microwave cavity, and x and Fidelity depends solely on the gate time tg (for example, for the gate time of an iSWAP,

[0087] [Math.4] yt - X'%

[0088] , we find

[0089] [Math.5]

[0090] And

[0091] [Math.6]

[0092] It should be noted that, in a case where the active qubits are coupled to different inactive qubits, the formula, thanks to the linearity of the operators involved in the fidelity calculation, can easily be modified to F'ct(n1, n2,m), where {ni, n2] are the number of inactive qubits for the first and second qubits involved in the two-qubit gate, respectively. Alternatively, the error can simply be approximated as that given by the qubit coupled to the maximum number of qubits.

[0093] Crosstalk error calculation

[0094] The following is a description of how to calculate the crosstalk error during the execution of a circuit for a given coupling map. Consider a circuit to be executed on N hardware qubits with a coupling map of fixed weight, i.e., a graph G(V,E) describing the connectivity among the qubits and such that each node is assigned a crosstalk weight based on the number of edges via Eq. (2). Let L be the number of two-qubit gates in the circuit, m the on / off coupling ratio, and assume that the errors stack independently among the different gates.

[0095] In the case of all-to-all (ATA) connectivity, the total crosstalk circuit fidelity is given by

[0096] [Math.7] .Fcin^cl ~ (Fct(N,ml)h

[0097] since any pair of qubits shares the same weight, i.e., they will be bound to the same N-2 qubits and therefore will share exactly the same crosstalk error. In the case of an arbitrary coupling board, however, there will be both pairs of qubits with identical and different weights. In this case, the total circuit fidelity can be calculated in two ways:

[0098] i) with the modified F'ct(nl, n2,m), that is

[0099] [Math. 8]

[0100] where {ni(1), n2(l)} are the numbers of inactive qubits respectively for the first and second qubits involved in the two-qubit gate 1;

[0101] ii) approximate the crosstalk error of the pair as the maximum error of the qubits in the pair, i.e.

[0102] [Math.9] =HLi

[0103] Description of task adaptive topology (TAT) algorithms implemented in the invention

[0104] Three algorithms, namely Q-algo, AQ-algo and RWC-algo, are now described.

[0105] Q-algorithm

[0106] With reference to [Fig. 2], it is assumed that an algorithm fidelity threshold Fthr and an agnostic CA circuit are provided. LA is defined as the length of CA after transpilation (translation and optimization) into the hardware gate set, defined as the number of two-qubit gates in C0. From a prediction of L0, a per-gate fidelity budget

[0107] [Math. 10] FG ~ L0 V Fthr

[0108] is predicted. It should be noted that, given that a circuit C to be implemented on a processor represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e. L = L(C,G), for the sake of brevity the length will just be indicated by L.

[0109] The maximum number of qubits per cavity n corresponding to FG is calculated.

[0110] Let N be the total number of qubits in the processor and G(V=N,E) the graph representing the connectivity of the processor. Let Fct(n) be the crosstalk fidelity of the two-qubit gate in an arrangement of n qubits per cavity and FD the gate fidelity that can be experimentally determined or theoretically predicted.

[0111] The Sabre algorithmic tool [8] and an optimizer are used to route the qubits with respect to the algorithm, then remove redundant or unnecessary gates and parallelize them if possible. The application of these two steps will be referred to as the route.

[0112] From n, the processor layout is deduced and the route is applied to extract a new circuit length L and estimate the total circuit fidelity as.

[0113] [Math. 11] W [G(WK

[0114] where Fcirc,D [G(V,E)] and Fcirc,ct [G(V,E)] are respectively the total gate and crosstalk fidelities and are approximated to be independent:

[0115] [Math 12]

[0116] (3)

[0117] with vk being the number of two-qubit gates at step k, FG the gate fidelity and FI the idle qubit fidelity, and

[0118] [Math 13]

[0119] (4)

[0120] where nk is the number of qubit islands in the processor and Fct(n) is the crosstalk fidelity estimated for n qubits per island. If Fcirc(n) < Fthr, there is a halt and the n arrangement is chosen; otherwise, there is an estimation from L of the new error budget per gate and the corresponding new n, assuming that to decrease n, L increases and iterates. Algorithm 1: Q-algo finds the available hw and cmap for a given fidelity threshold Ft-nr. Data: Agnostic circuit FA, coupling ratio on / off, gate fidelity Fd, idle qubit fidelity Fd. Result: Ideal number of qubits per cavity Translate (and optimize) by transpilation C\ to J's set of hardware gates and obtain and L,, ; Estimate the loyalty budget per door F(i ^'FF^,- ; if F(i < then i Stop; Otherwise | Estimate the corresponding number of qubits per cavity n and the gate error; | Run Route to find the actual circuit length L; 1. Calculate the total circuit fidelity Fcm. i while Fcire > F^,, perform | i Update the loyalty budget per door Fa from L; | | Update the corresponding number of qubits per cavity n and the crosstalk fidelity; 1: Execute Route to find the new circuit length L; | Calculate the new total circuit fidelity F^; ] END Return n; END

[0121] AQ-algo

[0122] With reference to [Fig. 3], a second algorithm is provided for implementation on quantum hardware with a given fidelity threshold Fthr and an agnostic CA circuit. By translating and optimizing CA to the hardware gate set, the circuit Co is obtained, and Lo is defined as the length of Co, defined as the number of two-qubit gates in Co. Let Me be the total number of qubits in Co, FD, and Fi. respectively the gate and idle qubit fidelities which can be determined experimentally or predicted theoretically.

[0123] It should be noted that, given that a circuit C to be implemented on a processor represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e. L = L(C. G), for the sake of brevity, it is simply identified by L.

[0124] From Lq a loyalty budget per door is predicted

[0125] [Math. 14]

[0126] which must be lower than FD, otherwise the fidelity threshold is set too high for the given hardware. Alternatively, one can proceed by mapping the circuit to the hardware qubits with the SABRE algorithm [8] and setting the connectivity with the formula in Eq. (2), which provides the suggested number of qubits per cavity "corresponding to Fo.

[0127] If n is close to N (for example N n < n min n, n min = 2 the minimum connectivity) we start from all-to-all connectivity, whereas if it is not we start from n. Let cmap = island cmap(N, n) be the coupling map, that is to say a graph G(V=N,E) representing the connectivity of the processor; for simplicity, island cmap(N, n) is constructed so that it starts by dividing N into N ist islands of equal size or N isl 1 islands of equal size and 1 smaller island all connected by a single connection (that is to say the nearest neighbor), for example for N = 6, island cmap(6, 2) returns three nearest neighbor islands of size two while for island cmap(6, 4) two nearest neighbor islands of size four and one of size two. It should be noted that such a function could potentially be applied recursively as a subroutine within islands to obtain a more complex coupling map.At each step, the total circuit fidelity is calculated as .

[0128] [Math. 15] ••• -A:jïÿ,sî.jOf1

[0129] where

[0130] [Math. 16]

[0131] is the total gate fidelity, vk is the number of two-qubit gates at step k, and Fcirc,ct [G(V,E)] is the total circuit crosstalk fidelity calculated in the manner described above.

[0132] It should be noted that the decoherence and crosstalk errors are approximated to be independent.

[0133] The following steps are iterated:

[0134] 1. Transpile the circuit using the SABRE algorithm to map a circuit to hardware qubits with a cmap coupling card,(n) and extract a new circuit length L t;

[0135] 2. Estimate the total errors Fcirc>DG(V, E), Fcirc>ct G(V, E) and Fcirc G(V, Ej). If Fcirc>ct If G(V, E) has decreased since the last step, we break the iteration and return cmap i (n), whereas if it has improved we define the following:

[0136] [Math 17]

[0137] (5) F^^ j {0(0)] O - (^(0)1 - ;

[0138] and as a function of A, D and A / c, we define A, :

[0139] [Math 18]

[0140] (6)

[0141] If A, is equal to the decoherence Aa we increase the number of qubits per cavity, whereas if A, is equal to the crosstalk Acrf we decrease it:

[0142] [Math 19]

[0143] (7) ? j To ■■■■■? 'f-- "" 1 ■■■:? | if A.; — ■■■ 1 -- X v

[0144] 3. If Fciic G(V, E) < Ethr we keep the iteration on the steps above. If Ecirc G(V, E) > Ethr and Aopl = 0 we stop and choose cmap i(n ,), otherwise if A,,,„ / = 0 we keep the iteration until A, > opt =0. Algorithm 2: AQ-algo finds the hw and cmap arrangement given a threshold and (if requested) further optimizes. Data: Fa, C, LA, on / off coupling ratio. Fa, F{. (-0 no opt.) Result: Coupling map and hardware layout Initialization: Translate and optimize CA to Ca: obtain L„, and the required number of qubits N; Estimate the loyalty budget per door Fç, ='tFF,b, ; Map the circuit to hardware qubits (for example with SABRE); if Fq < Fo then i Stop; Otherwise | Estimate no from ct-equation (J™ coarse estimation); yes | <V - no i < ;2 — no\ alors i | no = N (Toul-à-tout); i end | Calculate and Fcirco. i while F^-. < Fth, or Aj > A„,„ perform ii cmap-, - island_cmap(N, n,}; ; | five = TrampHer{circle, cmapi, disposition = SABRE) ; 1 i Calculate: Lh F^, ; ; Af);, — Fcl,x ù ~ Fejrc^.), Ac[; — Fclrc and; — ForC^ù-i > ; if Fom < then is paused; i ï end | | Assign A» or A,.,., to A, with Eq. (6); ii if A; -- A / >„ then i ï »<+ = 1 ; ; otherwise it ni - - 1 ; î ] end i fin ; Renvover cmap, ; end

[0145] RWC-algo

[0146] With reference to [Fig. 4], consider a third algorithm to be implemented on quantum hardware with a given fidelity threshold Fthr implemented on a CA-agnostic circuit. By translating and optimizing CA to the hardware gate set, we obtain the CO circuit and define LO as the length of CO, defined as the number of two-qubit gates in CO. Let N be the total number of qubits in CO, and FD and FI, respectively, the gate and idle qubit fidelities that can be determined experimentally or predicted theoretically.

[0147] It should be noted that, given that a circuit C to be implemented on a processor is represented by a graph G(V,E), while the number of two-qubit gates depends on both C and G, i.e., L = L(C, G), for the sake of brevity, we will simply identify it by L. From L0, we predict a fidelity budget per gate

[0148] [Math.20] FG - LO v Fthr

[0149] which must be lower than FD; otherwise, the fidelity threshold is set too high for the given hardware. Alternatively, we can proceed by mapping a circuit to hardware qubits using the SABRE algorithm [8] and set the connectivity to all-to-all.

[0150] From this, we construct a weighted wmap coupling map, that is, a graph G(V=N,E) describing the connectivity among the qubits, such that each node is assigned a crosstalk weight based on the number of edges via Eq. (2). The idea of ​​RWC is then to trim at each step the edge associated with the maximum-weight nodes. Such an operation is performed by a function eut max edge(wmap) which orders the edges associated with maximum-weight nodes, identifies

[0151] edges associated with nodes of equal weight and recursively cuts the edges until the total circuit fidelity Fcirc G(V,E) improves. Obviously, if an edge is cut and Fcirc G(V,E) decreases, such an edge is restored and the function passes by attempting to cut another edge. In the same way, we allow any type of connectivity possible within the hardware qubits.

[0152] At each step, the total circuit fidelity is calculated as Fcirc G(V,E) = Fcirc,DG(V,E) * Fcirc,et G(V,E), where Fcirc,DG(V,E) = QL k = l Fvk. D FN-2vkI is the total gate fidelity, vk is the number of two-qubit gates at step k, and Fcirc,et G(V,E) is the total circuit crosstalk fidelity, calculated in the manner described in Section III A.

[0153] It should be noted that the gate and crosstalk fidelities are approximated to be independent. Thus, we iterate through the following steps:

[0154] 1. Transpile the circuit using the SABRE algorithm to map a circuit to hardware qubits with a wmapi coupling board and extract a new length of Li circuit;

[0155] 2. Estimate the total errors Fcirc,DG(V,E), Fcirc,et G(V,E) and Fcirc G(V,E). If Fcirc,et G(V,E) has decreased since the last step, we break the iteration and return wmapi, whereas if it has improved we continue to trim the edges at maximum weight and obtain a new wmapi = eut max edge(wmapi);

[0156] 3. If Fcirc G(V, E) < Fthr we continue the iteration on the steps above. If Fcirc G(V,E) > Fthr and Aopt = 0 we stop and choose wmapi, otherwise if Aopt = 0 we continue the iteration until Ai > Aopt. Algorithm 3: RWC-algo finds the hw and c-map layout given a threshold and (if requested) further optimizes by randomly clipping the maximum weight edges Data: Ca, f i. coupling ratio on / off. Fn, F, (- 0 no opt.) Result: Coupling board and hardware layout Initialization: Translate and optimize CA to Co: obtain L„ and the number of qubits N; Estimate the loyalty budget per door Fa ^l'^Fta, ; Mapping the circuit to hardware qubits using the SABRE algorithm; if Fti < Fn then >' Stop; Otherwise § Starting from all-to-everything connectivity; i; Construct wmap from Eq, (2): Cut an edge (random)nll; Calculate Fcirc>ao and . | while [F^ < F^r or > 10'1*) perform | § wax-, = Transpiler(circri, wmap / , process, disposition = "SABRE"); ] Calculate: L„ fl™, Ai - / C™ - / Cinvi ; I; S wmap„id = wmap; ; | § map;, ji § if A. < 0 then ] If pause; s; § otherwise | § i -wmapt = eutjnaxedge^wmap:) ; f*n if J Send back w So fine END

[0157] Of course, the invention is not limited to the embodiments described above and can be applied to many types of qubit technologies, including carbon nanotube qubits, superconducting qubits, silicon qubits, trapped ion qubits or photonic qubits.

[0158] Among the cQED architectures to which the method of the invention can be applied, one can find semiconductor spin qubits, connected by a resonator on a chip, or Rydberg atoms, linked by a macroscopic cavity. Spin qubits can, for example, be hosted in carbon nanotubes, for example in a double quantum dot structure. Photonic qubits can implement microwave cavity photons. A resonator-on-a-chip can, for example, be a coplanar waveguide, a ribbon line, or a microstrip. It can be made of a high-impedance material such as niobium nitride.

[0159] Legend of variables used in the algorithms:

[0160] Problem variables

[0161] 1. CA: Agnostic circuit implementing a chosen algorithm

[0162] 2. LA: Agnostic circuit length

[0163] 3. Eth: Algorithm error threshold

[0164] 4. Fth = 1 - Eth: Algorithm fidelity threshold

[0165] Material specifications

[0166] 1. C0: Translation (and optimization) of CA in the hardware gate set

[0167] 2. LO: Length of CO

[0168] 3. N: number of qubits in CO

[0169] 4. m: on / off coupling ratio

[0170] 5. FD: Door Fidelity

[0171] 6. FI: Idle Qubit Fidelity

[0172] 7. G(V,E) graph with fixed sets of vertices and edges (V, E) representing the processor connectivity

[0173] 8. G = {G(V,E)} allowed set of graphs with sets of vertices and of fixed edges (V, E), representing all allowed hardware topologies

[0174] 9. G*(V,E): graph e G allowing the execution of CA within the limits of the threshold Ethr error

[0175] Algorithm variables

[0176] 1. Nstep: Number of algorithm steps before convergence

[0177] 2. i: algorithm step

[0178] 3. circi: circuit in step i

[0179] 4. vki: number of two-qubit gates at circuit step ki of algorithm step i

[0180] 5. Li: circuit length at step i (it is better to specify whether this refers to its size or its its depth)

[0181] 6. Nisli: number of islets at stage i

[0182] 7. nji: number of qubits per island ji at step i

[0183] 8. cmapi: graph G(V,E) describing connectivity among qubits

[0184] 9. wmapi graph G(V,E) describing the connectivity among the qubits and such that that each node is assigned a crosstalk weight based on the number of edges via Eq. (2).

[0185] 10.

[0186] [Math.21] FCi vRhr

[0187] : Budget fidelity per door at stage i

[0188] HE

[0189] [Math.22]

[0190] total circuit gate fidelity at step i

[0191] 12.

[0192] [Math.23]

[0193] : A between two total circuit gate fidelity steps

[0194] 13. Fct(nji) = Fct(nji,m): crosstalk fidelity at step i of Eq. (2)

[0195] 14. Fcirc,cti G(V,E): Crosstalk circuit fidelity for a coupling card given, see section (III A)

[0196] 15.

[0197] [Math.24] Acti - Fdracti

[0198] Total crosstalk fidelity between two stages

[0199] 16. [G(¥, EU - E|] p('VE)J:

[0200] total circuit fidelity approximated at step i (assuming that the two errors are independent, which is not true)

[0201] 17. Ai = Fcirci - Fcirci-1 Total circuit fidelity between two steps REFERENCES

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Claims

1.

2. Demands A method for generating a task-specific, customer-adapted topology for hardware based on the quantum electrodynamics of circuits or cavities (cQED), characterized in that it comprises iterative steps consisting of: - initially generate, from said client task, a circuit of M agnostic qubits and a corresponding error threshold, - transpile said initially generated agnostic M qubit circuit, to generate a transpiled circuit, said transpilation step implementing hardware specifications including a set of native gates and gate errors, - determine an error committed by said transpiled circuit, - compare said error thus committed to an error threshold corresponding to said circuit of agnostic M qubits, - if said transpiled circuit error is greater than said error threshold, modify some of said hardware specifications to be processed in the transpilation step, - if said transpiled circuit error is less than said error threshold, provide said transpiled circuit as a suitable topology specific to said customer task to a chip design and nanofabrication unit. A method according to the preceding claim, further comprising the steps of: - to introduce input data comprising a circuit of M agnostic qubits (CA) implementing an algorithm chosen from a set of client task adaptive topology algorithms (Q-Algo, AQ-Algo, RWC-algo), an algorithm error threshold (Ethr), a on / off coupling ratio and an idle qubit fidelity (FO), - to initialize from said input data, a translation (Co) of the circuit of M agnostic qubits (CA) into a set of hardware gates, a number (N) of qubits in said circuit of M agnostic qubits (Co) and a gate fidelity (FG), - if said gate fidelity (FG) is greater than an algorithm fidelity threshold (Fthr), iteratively calculate a new number n of qubits and a circuit fidelity (Fcirc) for a circuit to be transpiled, until said circuit fidelity (Fcirc) is greater than said algorithm fidelity threshold (Fthr).

3. A method according to the preceding claim, wherein the input data further include a length (LA) of the agnostic circuit, the initialization step further includes the initialization of the length (Lo) of the translated circuit material, and the calculation step further includes the calculation of a length (L) of the circuit to be transpiled.

4. A method (AQ-algo) according to the preceding claim 2 or 3, wherein the input data further comprise a predetermined optimal variation of fidelity Aopt, characterized in that it further comprises the iterative steps of: - transpiling the circuit, so as to map said circuit to hardware qubits with a coupling map and to extract a new circuit length (L;,) - estimating total circuit fidelities comprising a circuit crosstalk fidelity and calculating a variation A of circuit fidelity and a decoherence (AD), - provided that the circuit fidelity (Fcirc) is greater than or equal to the new calculated circuit fidelity (Fcircnew)à, incrementing / decrementing the number (n) of qubits, until said variation of circuit fidelity (A) and said decoherence (AD) are substantially equal.

5. A method (RCW-algo) according to the preceding claim 2 or 3, wherein the input data further include a predetermined optimal fidelity variation (Aopt), characterized in that it further comprises the iterative steps of: - transpiling the circuit, so as to map said circuit to hardware qubits with a coupling map (yvmap) and to extract a new circuit length L; - estimating a circuit crosstalk fidelity Fcirc,et [G(V,E)] and a total circuit fidelity Fcirc [G(V,E)],

6.

7.

8. - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has decreased since the previous step, break the iteration and return to the coupling map (wmap), - if said circuit crosstalk fidelity Fcirc,ct [G(V,E)] has increased since said previous step, trim the edges to maximum weight and obtain a new coupling map (wmapi), - provided that the total circuit fidelity Fcirc[G(V,E)] is less than the algorithm threshold fidelity (Fthr), maintain the iteration during the steps above, - if the fidelity Fcirc [G(V,E)] is greater than or equal to the algorithm threshold fidelity (Fthr) and the optimal variation in fidelity (Aopt) is approximately equal to 0, break the iteration and choose the coupling map (wmapi), - if the optimal variation (Aopt) is not equal to 0, keep the iteration until an iterative variation (A^ is greater than the optimal fidelity variation (Aopt). A method according to any one of the preceding claims, characterized in that it is carried out on cQED material with long-range interaction. A method according to any one of the preceding claims, implemented to provide task-appropriate topology-optimized instructions for the nanofabrication of cQED material. A method according to any one of claims 1 to 6, implemented to provide task-appropriate topology-optimized instructions for quantum simulations on emulators of cQED material.

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