METHOD FOR MANUFACTURING A SILICON SUBSTRATE FOR QUANTUM APPLICATIONS
By forming a silicon-germanium alloy layer and selectively removing donor substrate portions, the method addresses the challenge of maintaining 28Si purity and surface quality, enabling efficient production of silicon substrates for quantum applications with reduced thickness and cost.
Patent Information
- Application Number
- FR2024008487
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2026-02-06
AI Technical Summary
The existing methods for manufacturing silicon substrates for quantum applications face challenges in maintaining the isotopic purity of 28Si layers, which is necessary for long electron spin coherence, and require thick epitaxy that degrades surface quality and increases costs due to the use of high-purity precursors.
A method involving the formation of a silicon-germanium alloy layer on a donor substrate, followed by the assembly and selective removal of donor substrate portions, allowing for the creation of thin 28Si layers with high purity, using conventional semiconductor processes to minimize contamination and reduce thermal budget.
This approach maintains high isotopic purity of 28Si layers, reduces the thickness of silicon layers required, and enhances the surface quality of the substrate, making it suitable for quantum devices while minimizing the use of expensive precursors and reducing production time.
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Abstract
Description
Title of the invention: MANUFACTURING METHOD OF A SILICON SUBSTRATE IN VIEW OF QUANTUM APPLICATIONS TECHNICAL FIELD OF THE INVENTION
[0001] The invention relates to a method for forming a substrate comprising a 28Si silicon layer on an electrically insulating layer, this substrate being suitable for forming a basis for electronic devices whose operating principle is based on the manipulation of quantum objects, in particular qubits. TECHNOLOGICAL BACKGROUND
[0002] Silicon is recognized as a promising material for electronic devices based on the manipulation of electron spin, which represents their magnetic moment. Information can, in particular, be stored and manipulated by acting on electron spin, rather than by using their electric charge as in conventional electronics. Electron spin can also be used as a qubit support to put quantum information theory into practice, by exploiting superpositions of spin states with a well-defined phase. See EP 3 975 072 A1 and US 2023 / 0026518.
[0003] The duration of phase retention, and therefore of information retention, is defined by the coherence time. Long coherence times are necessary for operations on qubits to be performed or for quantum information to be stored before a read operation, during which the qubit loses its coherence and the information is lost.
[0004] Silicon has three stable isotopes: 28Si, 29Si, and 30Si, which make up approximately 92.2%, 4.7%, and 3.1% of natural silicon, respectively. One of the mechanisms that causes spin-state decoherence is the presence of 29Si isotopes of silicon, whose nuclear magnetic moment is not zero. It is therefore preferable to eliminate as much of the 29Si proportion as possible in the silicon used as the basis for qubit manipulation devices. The 30Si isotope should also be eliminated: although the 30Si isotope does not possess spin, it causes variations in the bond lengths between atoms and therefore in the local environment of the qubits. The homogeneity of the local environment should be maximized by minimizing the presence of the 30Si isotope so that the qubits exhibit characteristics as similar as possible to each other.
[0005] One solution is to use silicon enriched in 28Si isotopes. Shneider et al. (E. Schneider and J. England, "Isotopically Enriched Layers for Quantum Computers Formed by 28Si Implantation and Layer Exchange," ACS Appl. Mater. Interfaces 2023, 15, 21609-21617) propose a silicon isotope layer enrichment technique based on the ionic implantation of 28Si ions into an aluminum layer formed on a native oxide-free silicon substrate, followed by layer exchange crystallization. This results in a high-purity 28Si layer on the silicon substrate. Schneider also explains that defects at the layer interfaces of the devices necessitate high-quality dielectrics and / or techniques to distance the qubits from the interfaces and mitigate the noise they generate, depending on the qubit placement geometry, whether close to or far from the interfaces.
[0006] Spin qubit manipulation devices can be fabricated using silicon as a base and standard CMOS (Complementary Metal Oxide Semiconductor) or FD-SOI (Fully Depleted Silicon On Insulator) manufacturing processes from the semiconductor industry. FD-SOI technology, in particular, allows control over the location of the qubits, away from the interfaces between the silicon and the gate dielectric or the buried oxide layer of the substrate (BOX for Buried Oxide).
[0007] However, SOI (Silicon On Insulator) substrates with a quantum-quality thin layer of the silicon isotope 28Si are not commercially available. Here, "quantum quality" refers to 28Si layers sufficiently pure to maintain electron spin coherence for durations long enough to perform qubit operations, with a 28Si purity greater than 99.92%.
[0008] There is thus a need for silicon wafers suitable for use as a substrate for the manufacture of devices for manipulating electron spin qubits, capable of maintaining the isotopic purity of 28Si layers and allowing the manipulation of qubits at chosen locations, compatible with the type of device envisaged.
[0009] More specifically, there is a need for SOI-type substrates comprising a thin 28Si layer on a support, with an electrically insulating layer interposed between the 28Si layer and the support. It is advantageous for both the thin layer and the electrically insulating layer (the buried "BOX" mentioned above) to be sufficiently thin to allow the formation of FD-SOI or Fully Depleted SOI transistors.
[0010] Furthermore, considering that quantum applications require working at very low temperatures, for example below 3 K or on the order of 10 mK, while employing control electronics that are physically as close as possible to the supports for manipulated quantum quantities, the integration on the same substrate of FD-SOI transistors and quantum quantity manipulation devices is advantageous: FD-SOI transistors can have a low threshold voltage and operate by limiting energy dissipation in their support, thus limiting the heating problems of these quantum quantity manipulation devices.
[0011] A method for manufacturing substrates suitable for FD-SOI technology, with a surface layer of isotopically pure 28Si silicon suitable for quantum applications, is based on a layer transfer technique that requires the formation of two 28Si layers: one on a donor substrate and the other on a recipient substrate. These two substrates are typically formed from conventional bulk silicon wafers, i.e., wafers composed of different silicon isotopes and containing a proportion of impurities. In the final structure, the 28Si layer of the donor substrate constitutes the 28Si silicon surface layer and rests on a Box layer, itself separated from a bulk silicon wafer of the recipient substrate by the 28Si layer formed on the latter.The 28Si layer of the receiving substrate acts as a barrier to the diffusion of impurities and various isotopes from the bulk silicon wafer to the surface 28Si layer, thus maintaining the purity and quantum properties of this surface layer. French patent application FR2314256 describes such a manufacturing process.
[0012] As described above, the fabrication of substrates suitable for FD-SOI technology with an isotopically pure 28Si silicon surface layer and configured for quantum applications requires the use of 28Si epitaxially mounted on bulk Si wafers, both for a donor substrate and for a recipient substrate. The purity of the 28Si surface layer must be maintained (i) during the SOI fabrication process: fabrication of the composite substrate comprising a bulk silicon support, a 28Si surface layer, and a BOX layer isolating the 28Si layer from the bulk support, and (ii) during the CMOS process of fabrication of the transistors in the composite substrate.The diffusion of impurities and different silicon isotopes from the bulk silicon substrate depends on several factors: isotope and contaminant concentration, physical parameters of the SOI such as the thickness of the 28Si surface layer, the BOX, and the thickness of 28Si on which the BOX rests, and of course the thermal budget of the SOI and CMOS processes.
[0013] Consequently, to maintain a target level of purity, known manufacturing processes for the composite substrate require thick 28Si epitaxies, on the order of several hundred nanometers, typically 400 nm or more, for both the donor substrate and the recipient substrate.
[0014] However, the use of thick epitaxy implies a degradation of the surface quality of the resulting layers, for example, greater roughness and crystalline defects, which are key parameters to minimize in order to obtain SOI wafers with a high-quality surface 28Si layer. Adjusting the epitaxy process to achieve the desired quality will involve a lower thermal budget with a longer duration, which will reduce the throughput of the epitaxy tool and the additional consumption of 28Si silane, or other precursors necessary for the growth of the 28Si layers. Due to the high price and limited availability of quantum-quality precursors for 28Si epitaxy, optimizing SOI fabrication by reducing the required thickness of the 28Si layers for the donor and / or recipient substrate is of great interest. Description of the invention
[0015] The applicant's objective is to provide a method for manufacturing a semiconductor support suitable for forming a basis for obtaining devices for manipulating quantum objects, and in particular qubits formed from electron spins.
[0016] To achieve this goal, one aspect of the invention is a method for manufacturing a structure comprising a carrier substrate supporting a silicon layer, an oxide layer being interposed between the carrier substrate and the silicon layer, the method comprising the steps of forming a layer of a silicon-germanium alloy on a donor substrate; forming a first silicon layer on the silicon-germanium alloy layer, thus forming a donor structure; forming an oxide layer on at least one of the first silicon layer and a carrier structure comprising the carrier substrate; assembling the donor structure and the carrier structure, in such a way that the carrier substrate, the oxide layer, the first silicon layer, the silicon-germanium alloy layer and the donor substrate are stacked in that order;remove at least a portion of the donor substrate attached to the layer of a silicon-germanium alloy; and remove the layer of a silicon-germanium alloy, in which the first silicon layer consists of at least 99.92% of the 28Si isotope of silicon.
[0017] A first advantage of the process is that it can be implemented by methods known and common in the field of the semiconductor industry and put to use in the manufacture of quantum devices, which accelerates the technological maturity of the manufacturing process undertaken and reduces the necessary investments in time and equipment.
[0018] A second advantage of this process is that it allows for savings (i) in the use of precursor gases with a high silicon 28I isotope content and (ii) in the usage time of the epitaxial frames used for the growth of essentially silicon layers composed of the 28Si isotope of silicon. Indeed, a silicon layer of the 28Si isotope can be formed relatively thin, without having to take into account contamination by the 29Si and 30Si isotopes of silicon and impurities from a supporting substrate, contamination due to the diffusion of species caused by a thermal oxidation treatment.
[0019] According to additional non-limiting features of the support according to the invention, considered individually or in any technically feasible combination:
[0020] - the process may further include a step of forming a second layer of silicon on the carrier substrate before the step of forming the oxide layer;
[0021] - the second silicon layer may consist of at least 99.92% of the 28Si isotope silicon;
[0022] - the oxide layer can be formed by oxidation of at least one of the first silicon layer and second silicon layer;
[0023] - the oxide layer can be formed by oxidation of the first layer of silicon;
[0024] - the first silicon layer may exhibit, before the formation step of the oxide layer, with a thickness between 20 and 110 nm;
[0025] - at least one of the first silicon layer and the second layer of silicon can be formed by epitaxial growth;
[0026] - the layer of a silicon-germanium alloy may have a proportion in silicon isotope 28Si of at least 99.92%;
[0027] - the layer of a silicon-germanium alloy can be formed by growth epitaxial;
[0028] - the layer of a silicon-germanium alloy can have a thickness between between 20 and 100 m, preferably between 30 and 70 nm;
[0029] - the layer of a silicon-germanium alloy may have a content of germanium content between 15% and 30%;
[0030] - the oxide layer can have a thickness between 10 and 50 nm;
[0031] - the second silicon layer may have a thickness greater than 200 nm, preferably between 200 nm and 500 nm;
[0032] - at least one of the donor substrate and the carrier substrate may be formed of a monocrystalline silicon wafer; and
[0033] - the process may further include the steps of: before the assembly step, form a weakening plane in the donor substrate by implanting ions of a light species; and fracture the donor substrate at the level of the weakening plane, after the assembly step and before the step of removing at least part of the donor substrate, which remains attached to the layer of a silicon-germanium alloy.
[0034] The structure obtained by the above process is suitable for the formation of a quantum device and comprises: a carrier substrate; a first layer of silicon 28Si isotope; a layer of silicon oxide; and a second layer of silicon 28Si isotope. The structure is formed by the carrier substrate, the first layer of silicon 28Si isotope, the silicon oxide layer, and the second layer of silicon 28Si isotope, stacked in that order, wherein the first and second layers of silicon 28Si isotope consist of at least 99.92% silicon 28Si isotope. Preferably, the silicon oxide layer has a silicon 28Si isotope content of at least 99.92%.
[0035] A first advantage of the structure is to provide an adequate basis for the development of quantum devices by employing technologies already well mastered in the field of semiconductors.
[0036] A second advantage of the structure is that it guarantees the reliability of the resulting devices thanks to the presence of a 28Si and 28SiO2 bilayer acting as a barrier to undesirable elements contained in the substrate, such as the silicon isotopes 29Si and 30Si, or even carbon, oxygen, or nitrogen atoms. It would indeed be difficult and extremely costly to produce silicon substrates made purely of the silicon isotope 28Si. The available substrates are therefore made of natural silicon, containing at least the three silicon isotopes Si, Si, and Si, as well as impurities such as carbon, oxygen, and nitrogen. BRIEF DESCRIPTION OF THE FIGURES
[0037] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:
[0038] [Fig. 1] The [Fig. 1] illustrates a manufacturing process according to a first embodiment of the invention;
[0039] [Fig.2] The [Fig.2] illustrates the continuation of the process of the [Fig.1];
[0040] [Fig.3] Fig.3 is a diagram summarizing the manufacturing process of Figure 1 and 2;
[0041] [Fig.4] Fig.4 illustrates a manufacturing process according to a second method of putting into work of the invention; and
[0042] [Fig.5] The [Fig.5] is a diagram summarizing the manufacturing process of the [Fig.4]. DETAILED DESCRIPTION OF THE INVENTION
[0043] First embodiment
[0044] A first embodiment of the present invention is described by means of Figures 1 to 3 and the associated description below.
[0045] Figures 1 and 2 illustrate steps in a manufacturing process for the structure shown in (H) of [Fig. 2]. [Fig. 3] is a diagram showing the steps in the manufacturing process illustrated in Figures 1 and 2.
[0046] Figure 2 illustrates in (H) a Strct structure formed from a 28SiCar barrier layer, of a 28SiO2 oxide layer, and a 28SiDon surface layer, stacked in that order on a Si_WafCar carrier substrate, each of these elements preferably being in direct contact with the element or elements immediately adjacent to it.
[0047] The Si_WafCar carrier substrate is here made of a conventional single-crystal silicon wafer. The 28SiCar barrier layer and the 28SiDon surface layer are made of silicon. The 28SiO2 layer is made of a silicon oxide layer. The 28SiCar, 28SiDon, and 28SiO2 layers have, in particular, a silicon 28Si isotope purity of at least 99.92%, for example, between 99.92% and 99.995%. Thus, the 28SiCar and 28SiDon silicon layers contain less than 800 ppm of the silicon 29I isotope.
[0048] Such a structure can be used to form quantum devices on its surface, thanks to the characteristics of the 28SiDon surface layer: due to its 28Si purity, the spin coherence time of the electrons in this layer is sufficient to perform operations on qubits associated with these electrons. Integrated into a quantum device, the 28SiDon surface layer therefore represents a good qubit support.
[0049] In addition, the 28SiCar barrier layer and the 28SiO2 oxide layer prevent, or at least limit, the migration of impurities, and in particular of atoms of the 29Si isotope of silicon from the Si_WafCar support substrate to the 28Si Don surface layer. Without a barrier layer, the phenomenon of diffusion of impurities would increase the concentrations of 29Si, 30Si or dopant elements to levels incompatible with the quality required for the proper functioning of quantum devices, thus causing a reduction in coherence times and causing these devices to operate in a similar way to devices formed within conventional substrates for FD-SOI technology transistors.
[0050] During preliminary steps 110Don and 110Car of the process 100 for manufacturing the Strct structure, a donor substrate Si_WafDon and a carrier substrate Si_WafCar are provided. In this example, the substrates each consist of a single-crystal silicon wafer, but any other substrate conventionally used in the semiconductor industry could be employed.
[0051] Figure 1 illustrates in (A) the successive formation in this order (1) of an attack-stopping silicon-germanium alloy layer (SiGe) and (2) of the surface layer 28SiDon on the donor substrate Si_WafDon, during two steps successive 120Don and 130Don. The resulting so-called "donor structure" is designated by Don in the figures. The surface layer 28SiDon can be grown, for example by epitaxy, on one face of the donor substrate Si_WafDon, and then a layer of a silicon-germanium alloy SiGe can be grown on the surface layer 28SiDon thus formed.
[0052] Figure 1 illustrates in (B) the formation of the 28SiCar barrier layer and the 28SiO2 layer on the Si_WafCar support substrate during two successive steps 120Car and 130Car, respectively. The resulting "carrier structure" is designated by Car in the figures. The 28SiCar barrier layer can be grown, for example by epitaxy, on one face of the Si_WafCar support substrate during step 120Car. During step 130Car, the 28SiCar barrier layer is superficially oxidized to a certain thickness, so as to form the 28SiO2 oxide layer.
[0053] In the preceding steps, the 28SiDon, 28SiCar, and optionally SiGe layers are formed such that they have silicon isotope 28 (28Si) purities between 99.920% and 99.995%. Thus, the maximum concentrations of the silicon isotope 29 in these layers are, at least initially, between 800 and 50 ppm, concentrations low enough to allow the fabrication of spin-based quantum devices on the surface 28SiDon layer. Such compositions of the 28SiDon, 28SiCar, and SiGe layers can be achieved by using, in a conventional epitaxial growth process, silane gas of a purity corresponding to that of the 28Si layers, as the silicon precursor gas for the layers.
[0054] Although the fabrication of a SiGe layer with a silicon isotope purity of between 99.920% and 99.995% is optional, such purity prevents contamination of the 28SiDon layer by 29Si and 30Si isotopes in the epitaxial frame during its formation. In this case, the 28SiDon layer is relaxed, and the quantum confinement of a quantum device formed on this layer must be ensured by a vertical electrostatic field. Preferably, the same epitaxial frame is used for the successive formation of both the 28SiDon and SiGe layers.
[0055] Since the 28SiO2 oxide layer is obtained here by the oxidation of the 28SiCar layer, it exhibits the same 28Si purity characteristics as the latter. This oxidation operation can be carried out conventionally by applying a heat treatment under an oxygen atmosphere. The 28SiO2 layer is preferably formed by thermal oxidation so as to ensure a good interface quality between the 28SiO2 layer and each of the 28SiDon and 28SiCar layers, after assembly of the two substrates (see step 150, illustrated in (D) of [Fig. 1]). Naturally, it is a silicon oxide composed of oxygen and the 28Si isotope silicon of the 28SiCar layer - The 28SiCar layer is only oxidized over a certain thickness, strictly less than its thickness and depending on the thickness targeted for the 28SiO2 layer.
[0056] Furthermore, the 28SiO2 layer can also be formed by HDP-CVD type deposition (HDP-CVD for High Density Plasma CVD), which is carried out at a relatively low temperature compared to thermal oxidation, which advantageously limits the thermal budget imposed on the 28SiCar layer, and therefore limits the diffusion of other Si isotopes in the layer intended to contain the quantum object manipulation devices.
[0057] The thicknesses of the 28SiO2 and 28SiCar layers can be chosen to ensure an adequate barrier effect to prevent contamination of the 28SiDon surface layer by, in particular, 29Si, while limiting the thickness of the 28SiO2 layer, for example, for applications based on FD-SOI technology, which requires a thin 28SiO2 layer. Thus, the inventors were able to determine, through computer simulation, sets of thicknesses for the 28SiDon, 28SiO2, and 28SiCar layers, making it possible to guarantee a certain level of purity of the 28SiDon layer while advantageously minimizing the thickness of the 28SiCar layer for a given thickness of the 28SiO2 layer, chosen for its compatibility with conventional FD-SOI processes.
[0058] Table Tabl indicates such thickness sets for two purity levels, 99.9% and 99.99% of 28Si for the 28SiDon layer. The numerical simulations were calculated assuming that the 28SiCar layer has a purity level of 99.99% of 28Si. These calculations take into account, in particular, a thermal budget corresponding to that of the realization of the Strct structure and the conventional fabrication of an FD-SOI transistor, which is the highest thermal budget experienced by the layers, including the fabrication steps of CMOS transistors and qubit devices formed in the 28SiDon- layer. 28S thickness (after finishing) 28SiO2 thickness 28SiCar thickness for a 99.9% purity 28SiDon layer 28SiCar thickness for a 99.99% purity 28SiDon layer 16 nm 50 nm 30 nm 250 nm 16 nm 20 nm 200 nm 420 nm
[0059] Tab. 1
[0060] Before the 130Car oxidation step, the 28SiCar layer must have a thickness corresponding approximately to the sum of the targeted thickness for the 28SiO2 layer and the final targeted thickness for the 28SiCar layer of the Strct structure.
[0061] For example, one can consider the thicknesses typically used in FD-SOI type technologies, which are between 10 and 60 nm, preferably between 10 and 25 nm for the active layer (after finishing step 190, see below), which here corresponds to the 28SiDon surface layer, and between 10 and 50 nm for the 28SiO2 oxide layer, often approximately 20 nm thick. Thus, a thickness of between 20 and 110 nm can be used for the 28SiDon surface layer during its deposition, before its oxidation to form the 28SiO2 oxide layer. For the 28SiCar layer, a thickness greater than 200 nm can be used, for example, between 200 and 500 nm.
[0062] The SiGe attack arrest layer may have a thickness of between 20 and 100 nm, or preferably between 30 and 70 nm, typically 50 nm, and have a germanium content of between 15% and 30%.
[0063] Figure 1 illustrates in (C) an implantation of light species such as hydrogen, helium, or a combination of such species in the volume of the donor substrate Si_WafDon through the 28SiDon and SiGe layers, so as to form a Frgl embrittlement plane in the donor substrate Si_WafDon during a 140Don step. This implantation can correspond to an implantation of hydrogen and / or helium, that is, an ion bombardment of hydrogen and / or helium of the donor substrate Si_WafDon through the 28SiDon and SiGe layers. In a manner known per se, and as illustrated in (B), the implanted ions form a Frgl embrittlement plane. The nature and dose of the implanted species and the implantation energy are chosen according to the nature and thickness of the layers traversed, and the desired implantation depth.
[0064] Fig. 1 illustrates in (D) the assembly of the Don and Car structures, necessary for the formation of the Struct structure comprising a stack of 28SiCar, 28SiO2 and 28SiDon layers. Following the formation of the embrittlement plane Frgl, the donor structure Don is inverted and the surface layer 28SiDon is brought into intimate contact with the 28SiO2 layer of the carrier structure Car and assembled there, for example by molecular bonding or any other assembly technique by direct contact of the surfaces of the elements to be assembled, during a step 150.
[0065] Figure 1 illustrates in (E) the fracture of the Si_WafDon donor substrate at the level of the Frgl embrittlement plane obtained by ion implantation, such that a portion of Si_WafDon_2 of the Si_WafDon donor substrate is detached from the supporting structure Car, while a portion of Si_WafDon_i of the Si_WafDon donor substrate and the SiGe and 28SiDon layers remain attached to it, during a fracture and shrinkage step 160. This fracture can be obtained by heat treatment, possibly assisted by mechanical stress to initiate fracture, according to conventional transfer techniques of well-known layers in the field of microelectronics, such as the so-called "Smart Cut" process. Following the assembly and fracturing of the donor substrate, a heat treatment can be applied to consolidate the assembly and repair the assembled layers.
[0066] An alternative to the formation of a weakening plane and the fracture of the Si_WafDon substrate at this plane may consist of thinning the Si_WafDon donor substrate after its assembly, for example by etching, grinding and / or chemical mechanical polishing (CMP). This thinning may be used to completely remove the donor substrate, or only partially, for example to achieve the situation illustrated in (E) of [Fig. 1].
[0067] Fig. 2 illustrates the steps of the process necessary to go from the state illustrated in (E) to the Strct structure illustrated in (H).
[0068] Figure 2 illustrates in (F) the removal, during step 170, of the residual Si_WafDon_i layer of the Si_WafDon donor substrate that remained attached to the Car support structure after step 160. This step can be carried out by selective etching of silicon Etch(Si_WafDon_i), either wet, for example, using a chemical solution, or dry, for example, using a plasma, or by chemical mechanical polishing (CMP). Such an etch allows the removal of the residual Si_WafDon_i layer, formed of silicon, using the SiGe layer as an etching stop layer, by means of a process for selectively removing silicon from the Si_WafDon_i layer relative to the silicon-germanium alloy forming the SiGe layer.For example, one can refer to US patent documents 8,389,416 B2, US 9,984,890 B2 or US 10,934,485 B2, which describe methods for selectively attacking silicon with respect to a silicon-germanium alloy.
[0069] Figure 2 illustrates in (G) the removal, during a step 180, of the SiGe layer, released following step 170. This step can be carried out by selective etching of the silicon-germanium alloy Etch(SiGe), either wet, for example, using a chemical solution, or dry, for example, using a plasma, or by chemical mechanical polishing (CMP). Such an etching process removes the SiGe layer formed from a silicon-germanium alloy using the 28SiDon layer as an etching stop layer, employing a selective etching process of the silicon-germanium alloy of the SiGe layer relative to the silicon forming the 28SiDon layer. See, for example, US patent documents 9,236,265 B2. US 11,875,997 B2 or WO 2006 / 027332 Al, which describe processes for selectively etching silicon-germanium alloys with respect to silicon.
[0070] Regarding selective etching Etch(Si_WafDon_i), it can be considered a selective etching of silicon with respect to the silicon-germanium alloy when the etching rate of the silicon is at least twice as high as the etching rate of the silicon-germanium alloy. Conversely, regarding selective etching Etch(SiGe), it can be considered a selective etching of the silicon-germanium alloy with respect to silicon when the etching rate of the silicon-germanium alloy is at least twice as high as the etching rate of silicon. Thus, selective etching Etch(Si_WafDon_i) and Etch(SiGe) are distinct from one another.
[0071] Figure 2 illustrates in (H) a finishing step 190 of the 28SiDon surface layer obtained from the donor structure. This finishing step consists of one or more mechanical and / or chemical etchings to thin the 28SiDon surface layer to a desired thickness and polish its accessible face. The finishing step can be similar to those used in the fabrication of substrates for FD-SOI technology. Following this step, the Strct structure illustrated in Figure 2 is obtained.
[0072] A significant advantage of process 100 is that the thickness of the 28Si silicon isotope layer to be formed on the Si_WafDon donor substrate is greatly reduced compared to existing processes, potentially being limited to a thickness of 200 nm or less. This value can be compared, for example, to the 300 to 600 nm required for the 28Si silicon isotope layer of the donor substrate in the process described in French patent application FR 2314256. In this process, the oxide layer is obtained by oxidizing the 28Si silicon isotope layer formed on a donor substrate. This oxidation, achieved by heating the layer, causes diffusion of the 29Si and 30Si isotopes and impurities from the layer support. Therefore, the layer does not require a large thickness to guarantee 28Si purity on its side opposite the support.In the present application, the 28SiDon layer is not subjected to oxidation for the formation of the 28SiO2 oxide layer and therefore does not require such a large thickness.
[0073] Second embodiment
[0074] A second embodiment of the present invention is described by means of figures 4 and 5 and the associated description below.
[0075] The second embodiment represents a second process 200 which is a variant of process 100 of the first embodiment. In process 100, the oxide layer 28SiO2 is formed on the layer 28SiCar, optionally by oxidation of the latter during step 130Car- In process 200, the 28SiO2 oxide layer is formed on the 28SiDon layer, possibly by oxidation of the latter; during a step 135Don which can be implemented in the same way as step 130Car of process 100, step 135Don replacing step 130Car-
[0076] Apart from this point, the two processes 100 and 200 are identical, the Set structure being obtained by the assembly of the Don and Car structures during step 150, as illustrated by Figures 4 and 5, the subsequent steps being the same. Of course, during step 150, it is the 28SiO2 layer, formed on the 28SiDon layer, that is brought into direct contact with the 28SiCar- layer.
[0077] Another variant could consist of applying the two steps 130Car and 135Don. In this case, the two layers 28SiCar and 28SiDon are covered with a layer of 28SiO2 oxide. The assembly of step 150 is then achieved by bringing the two 28SiO2 layers into intimate contact.
[0078] Of course, in the event of the formation of oxide layers by oxidation of one, the other or both of the 28SiCar and 28SiDon layers, their respective thicknesses can be adjusted to take into account the reduction in thickness of the silicon layer concerned.
[0079] The invention is not limited to the embodiments described above and variations thereof may be made without departing from the scope of the invention as defined by the claims.
Claims
Demands
1. A method (100) for manufacturing a structure comprising a carrier substrate (Si_WafCar) supporting a silicon layer (28SiDon), an oxide layer (28SiO2) being interposed between the carrier substrate (Si_WafCar) and the silicon layer (28SiDon), the method comprising the steps of: - forming (120Don) a layer (SiGe) of a silicon-germanium alloy on a donor substrate (Si_WafDon); - forming (130Don) a first silicon layer (28SiDon) on the layer (SiGe) of a silicon-germanium alloy, thus forming a donor structure (Don); - forming (130Car; 135Don) an oxide layer (28SiO2) on at least one of the first silicon layer (28SiDon) and a carrier structure (Car) comprising the carrier substrate (Si_WafCar);- assemble (150) the donor structure (Don) and the carrier structure (Car), such that the carrier substrate (Si_WafCar), the oxide layer (28SiO2), the first silicon layer (28SiDon), the (SiGe) layer of a silicon-germanium alloy and the donor substrate (Si_WafDon) are stacked in that order; - remove (170) at least a portion (Si_WafDon_i) of the donor substrate attached to the (SiGe) layer of a silicon-germanium alloy (Etch(Si_WafDon l)); and - remove (180) the (SiGe) layer of a silicon-germanium alloy (Etch(SiGe)), in which the first silicon layer (28SiDon) consists of at least 99.92% of the 28Si isotope of silicon.
2. The method according to claim 1, further comprising a step of forming (120Car) a second silicon layer (28SiCar) on the carrier substrate (Si_WafCar) before the step of forming (130Car ; 135Don) the oxide layer (28SiO2).
3. The method according to claim 2, wherein the second silicon layer (28SiCar) is made up of at least 99.92% of the 28Si isotope of silicon.
4. 4. The process according to claim 2 or 3, wherein the oxide layer (28SiO2) is formed by oxidation of at least one of the first silicon layer (28SiDon) and second silicon layer (28SiCar)-
5. 5. The process according to claim 1, wherein the oxide layer (28SiO2) is formed by oxidation of the first silicon layer (28SiDon).
6. The method according to any one of claims 1 to 5, wherein the first silicon layer (28SiDon) has, before the step (130Car) of formation of the oxide layer (28SiO2), a thickness of between 20 and 110 nm.
7. 7. The method according to claim 1 or 5 wherein the first silicon layer (28SiDon) is formed by epitaxial growth, or according to any one of claims 2 to 4, wherein at least one of the first silicon layer (28SiDon) and, where applicable, of the second silicon layer (28SiCar), is formed by epitaxial growth.
8. 8. The method according to any one of claims 1 to 7, wherein the (SiGe) layer of a silicon-germanium alloy has a silicon 28Si isotope proportion of at least 99.92%.
9. 9. The method according to any one of claims 1 to 8, wherein the (SiGe) layer of a silicon-germanium alloy is formed by epitaxial growth.
10. The method according to any one of claims 1 to 9, wherein the (SiGe) layer of a silicon-germanium alloy has a thickness of between 20 and 100 nm, preferably between 30 and 70 nm.
11. The method according to any one of claims 1 to 10, wherein the (SiGe) layer of a silicon-germanium alloy has a germanium content of between 15% and 30%.
12. The method according to any one of claims 1 to 11, wherein the oxide layer (28SiO2) has a thickness of between 10 and 50 nm.
13. The method according to any one of claims 2 to 4 or, where applicable, according to any one of claims 6 to 12, wherein the second silicon layer (28SiCar) has a thickness greater than 200 nm, preferably between 200 nm and 500 nm.
14. The method according to any one of claims 1 to 13, wherein at least one of the donor substrate (Si_WafDon) and the carrier substrate (Si_WafCar) is formed from a single-crystal silicon wafer.
15. 15. The method according to any one of claims 1 to 14, further comprising the steps of: - before the assembly step (150), forming (140Don) a weakening plane (Fgrl) in the donor substrate (Si_WafDon) by implanting ions of a light species; and - fracturing (160) the donor substrate (Si_WafDon) at the level of the weakening plane (Frgl), after the assembly step (150) and before the step (170) removing at least a part (Si_WafDon_i) of the donor substrate, remaining attached to the layer (SiGe) of a silicon-germanium alloy.
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