Electrostatic discharge protection device

Abstract

Electrostatic Discharge Protection Device This description relates to an electronic device (300) adapted to protect an electronic component against electrostatic discharges, the electronic device comprising semiconductor regions extending deep into a semiconductor substrate (101) from a first face (101A) of said semiconductor substrate, the semiconductor regions comprising: - a first semiconductor region (103) of a first type of conductivity; and - a second semiconductor region (306) of the second type of conductivity opposite to the first type of conductivity, forming a PN junction with the first semiconductor region;the first semiconductor region being connected to a first conductive track (311B) forming a first connection pin of the electronic device, the second semiconductor region being connected to a second conductive track (312A) forming a second connection pin of the electronic device, the semiconductor substrate being between the first conductive track and the second conductive track. Figure for the abbreviation: Fig. 3A;

Description

Title of the invention: Device for protection against electrostatic discharge. Technical field

[0001] This description relates generally to electronic devices. More specifically, this description relates to devices for protecting electronic components, or integrated circuits, against electrostatic discharge. Previous technique

[0002] An unprotected integrated circuit can suffer irreversible damage in the event of electrostatic discharge, potentially causing significant malfunctions of the integrated circuit. To overcome this drawback, current integrated circuits are generally equipped with electrostatic discharge protection. Summary of the invention

[0003] There is a continuing need for more effective electrostatic discharge protection devices. In particular, there is a continuing need to improve the quality of electrostatic discharge protection to meet the increasing performance demands of high-speed and high-frequency applications.

[0004] In particular, it would be desirable to have devices for protection against electrostatic discharges which generate as little parasitic capacitance as possible.

[0005] An embodiment overcomes all or part of the disadvantages of known devices for protection against electrostatic discharge.

[0006] One embodiment provides an electronic device adapted to protect an electronic component against electrostatic discharges, the electronic device comprising semiconductor regions extending deep into a semiconductor substrate from a first face of said semiconductor substrate, the semiconductor regions comprising: - a first semiconductor region of a first type of conductivity; and - a second semiconductor region of the second type of conductivity opposite to the first type of conductivity, forming a PN junction with the first semiconductor region; the first semiconductor region being connected to a first conductive track forming a first connection pin of the electronic device, the second semiconductor region being connected to a second conductive track forming a second connection pin of the electronic device, the semiconductor substrate being between the first conductive track and the second conductive track.

[0007] According to one embodiment, the semiconductor substrate has a second face opposite to the first face, the electronic device comprising a conductive via passing through the semiconductor substrate between the first face and the second face, and connecting the second semiconductor region to the second conductive track.

[0008] According to one embodiment, the conductive via is isolated from the semiconductor substrate by an insulating trench.

[0009] According to one embodiment, the semiconductor regions are annular, for example concentric around each other.

[0010] According to one embodiment, the semiconductor regions are annular around the conducting via.

[0011] According to one embodiment, the first semiconductor region is a first semiconductor box and the second semiconductor region is located in the first semiconductor box, or the second semiconductor region is a first semiconductor box and the first semiconductor region is located in the first semiconductor box.

[0012] According to one embodiment, the first semiconductor region is a first semiconductor box and the second semiconductor region is a second semiconductor box in contact with the first semiconductor box.

[0013] According to one embodiment, the first and second conductive tracks are included in an interconnection structure comprising several metallization levels, including at least a first metallization level on the side of the first face of the semiconductor substrate and at least a second metallization level on the side of the second face of the semiconductor substrate.

[0014] According to one embodiment, the first conductive track is included in the first level of metallization, and the second conductive track is included in the second level of metallization.

[0015] According to one embodiment, the first type of conductivity is of the P type, and the second type of conductivity is of the N type.

[0016] According to one embodiment, the first type of conductivity is of the N type, and the second type of conductivity is of the P type.

[0017] According to one embodiment, the electronic device is an electrostatic discharge protection device comprising at least one elementary electronic component among a diode, a bipolar transistor, a thyristor and a triac, said at least one elementary electronic component including the semiconductor regions, the first conductive track and the second semiconductor region.

[0018] One embodiment provides for an integrated circuit comprising an electronic device as described above and an electronic component connected to said electronic device.

[0019] According to one embodiment, the integrated circuit further comprises a first terminal connected to the first connection pin of the electronic device and a second terminal connected to the second connection pin of the electronic device, at least one of the first and second terminals being connected to the electronic component.

[0020] According to one embodiment, the first and second terminals each comprise a connection pad on the side of a second face of the semiconductor substrate opposite to the first face, the second connection pin of the electronic device also being on the side of the second face. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1A] is a cross-sectional view representing an example of a device for protection against electrostatic discharges;

[0023] [Fig.1B] is a top view representing the protection device of [Fig.1A];

[0024] [Fig.1C] is a cross-sectional view representing an example of an integrated circuit including the protection device of [Fig.1A];

[0025] [Fig.2A] is a cross-sectional view representing another example of a device for protection against electrostatic discharges;

[0026] [Fig.2B] is a top view representing the protection device of [Fig.2A];

[0027] [Fig.3A] is a cross-sectional view representing a device for protection against electrostatic discharges according to one embodiment;

[0028] [Fig.3B] is a top view representing the protection device of [Fig.3A];

[0029] [Fig.3C] is a cross-sectional view representing an example of an integrated circuit comprising a device for protection against electrostatic discharge according to one embodiment;

[0030] [Fig.4A] is a cross-sectional view representing a device for protection against electrostatic discharges according to another embodiment;

[0031] [Fig.4B] is a top view representing the protection device of [Fig.4A];

[0032] [Fig.5A] is a cross-sectional view representing a device for protection against electrostatic discharges according to another embodiment;

[0033] [Fig.5B] is a top view representing the protection device of [Fig.5A]. Description of the implementation methods

[0034] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0035] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the electronic components or integrated circuits to be protected against electrostatic discharge are not detailed, as the described embodiments are compatible with electronic components and integrated circuits traditionally protected against electrostatic discharge.

[0036] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0039] In the following description, the terms "insulating" and "conducting" mean, unless otherwise specified, electrically insulating and electrically conductive respectively. This applies to the terms "insulate" and "insulated".

[0040] In the following description, unless otherwise specified, when a via is referred to, a conductive via is referred to, when a substrate is referred to, a semiconductor substrate is referred to, when a box is referred to, a semiconductor box is referred to, and when a region is referred to, a semiconductor region is referred to.

[0041] In the following description, when reference is made to a semiconductor region, it is made to any semiconductor region contained within a semiconductor substrate, and a semiconductor box is considered to be a particular semiconductor region of the semiconductor substrate.

[0042] Unless otherwise specified, when referring to a protective device, reference is made to an electronic device intended to protect an electronic component, or an integrated circuit, against electrostatic discharge. Where there is no ambiguity, the protective device may be referred to simply as a device.

[0043] Throughout this description, the term "ring" refers to a ring shape represented in the figures as a rectangle or square. This shape is not limited and may, for example, be circular, oval, or more broadly, a geometric area delimited by an inner perimeter and an outer perimeter that are substantially parallel to each other.

[0044] [Fig. 1A] is a cross-sectional view of an example of a device 100 for protection against electrostatic discharge. [Fig. 1B] is a top view of the protection device 100 of [Fig. 1A]. [Fig. 1C] is a cross-sectional view of an example of an integrated circuit 10 comprising the protection device 100 of [Fig. 1A]. [Fig. 1A] is a view along the section plane AA shown in [Fig. 1B].

[0045] In the example shown, the device 100 is formed in a semiconductor substrate 101 (PSUB). The substrate 101 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example, silicon. By way of example, the substrate 101 is doped with a first type of conductivity, for example, type P. In order not to clutter the drawing, only one protection device 100 has been illustrated in Figures IA and IB, it being understood that the substrate 101 can, in practice, contain any number of devices 100.

[0046] By way of example, the semiconductor substrate 101 is of the silicon-on-insulator (SOI) type. An SOI substrate typically comprises a support layer of a semiconductor material covering another electrically insulating layer, for example a buried oxide layer (BOX for "Buried Oxide"), itself covering yet another layer of a semiconductor material, generally silicon.

[0047] In the example shown, the protection device 100 comprises a semiconductor well 103 (PW), extending vertically through the thickness of the semiconductor substrate 101 from a face 101A of the substrate 101 (the upper face of the substrate 101, in the orientation of [Fig. 1A]). The well 103 has a height or depth, that is, a dimension measured according to an orthogonal direction to face 101A of substrate 101, less than the thickness of substrate 101. In other words, the box 103 does not open on the side of a face 101B of substrate 101 (the lower face of substrate 101, in the orientation of [Fig.1A]) opposite face 101A. The box 103 of device 100 is doped with the first type of conductivity (type P, in this example) and has a higher doping level than substrate 101.

[0048] In the example shown, the device 100 further comprises semiconductor regions 105 (P+) and 106 (N+) extending vertically through the thickness of the semiconductor substrate 101 from face 101A. The semiconductor regions 105, 106 are located in the box 103 and have a depth in the box 103 that is much less than the thickness of the box 103. The semiconductor regions 105, 106 are thus surrounded laterally and below by the box 103.

[0049] In the example shown, the semiconductor region 106 (central semiconductor region) has, in top view, a substantially rectangular shape, and is substantially centered with respect to the edges of the box 103, and the semiconductor region 105 (peripheral semiconductor region) has, in top view, a substantially annular shape around the central semiconductor region 106.

[0050] The peripheral semiconductor region 105 is doped with the first type of conductivity (type P, in this example) and has a higher doping level than the semiconductor substrate 101 and the box 103. The central semiconductor region 106 is doped with the second type of conductivity (type N, in this example) and has a higher doping level than the semiconductor substrate 101 and the box 103, for example substantially equal to that of the peripheral semiconductor region 105.

[0051] The box 103, as well as the semiconductor regions 105, 106 are for example formed in the substrate 101 by ion implantation from the face 101A of the substrate 101.

[0052] For the sake of simplification, Figures IA and IB illustrate a case in which only the semiconductor regions 105 and 106, doped respectively with the first and second type of conductivity, are formed in the box 103. However, one or more other semiconductor regions doped with the first and / or second type of conductivity may also be formed in the box 103, and / or in the substrate 101 outside the box 103. In addition, other boxes may be formed in the substrate 101.

[0053] The N-type semiconductor region 106 forms an NP-type heterojunction with the P-type housing 103, thus forming a DI diode. The P-type semiconductor region 105 forms the anode of the DI diode with the housing 103. The N-type semiconductor region 106 forms the cathode of the DI diode.

[0054] The protective device 100 is connected to conductive tracks 111, 112 forming part of several metallization levels of an interconnecting structure 110. The conductive tracks 111, 112 are positioned above the face 101A of the substrate 101 and all extend in a plane substantially parallel to the plane of the substrate 101. Two metallization levels M1, M2 are shown in [Fig. 1A], although this is not limiting, the number of metallization levels could, for example, be greater than two. The first metallization level M1 is the metallization level closest to the substrate 101, and the second metallization level M2 is a metallization level further from the substrate 101 than the first metallization level M1.

[0055] In the example shown, the conductive tracks comprise: - conductive tracks 111 which are portions of a first conductive layer, for example metallic, of the first level of metallization M1; and - conductive tracks 112 which are portions of a second conductive layer, for example metallic, of the second level of metallization M2.

[0056] The conductive tracks 111 comprise a central conductive track 111A and a peripheral conductive track 11 IB which surrounds the central conductive track 111A in a substantially annular manner and is insulated from this central conductive track. The peripheral conductive track 11 IB could be electrically connected to other conductive tracks 11 IC (visible in [Fig. 1C]) of the first metallization level M1, for example to connect the protection device 100 to an electronic component and / or to an input / output terminal as described later in connection with [Fig. 1C].

[0057] The conductive tracks 112 comprise two conductive tracks 112A and 112B connected and perpendicular to each other. This allows for four connection points of the protective device 100 to the second metallization level M2, for example to connect the protective device 100 to an electronic component and / or to an input / output terminal as described later in relation to [Fig. 1C].

[0058] Conductive vias 115, for example metallic vias, of the interconnecting structure 110 connect the central conductive track 111A to the conductive tracks 112, as well as each of the central conductive tracks 111A and peripheral 11 IB to the face 101A of the substrate 101.

[0059] More specifically, the central conductive track 11 IA is connected by vias 115 to the central semiconductor region 106 on the one hand, and on the other hand by other vias 115 to the conductive tracks 112, and the peripheral conductive track 11 IB is connected by other vias 115 to the peripheral semiconductor region 105.

[0060] The conductive tracks 111 are insulated from each other and from conductive tracks 112 by an insulating layer 116 which is generally a stack of several insulating layers, separating in particular the different levels of metallization and the different conductive tracks of the same level of metallization. The conductive tracks 111, 112 and the conductive vias 115 are embedded in the insulating layer 116. The insulating layer 116 can be made of an oxide, for example a silicon oxide.

[0061] The conductive track 11 IB is connected to the P-type semiconductor region 105 and forms an anode electrode. Each conductive track 112 is connected to the N-type semiconductor region 106 and forms a cathode electrode. It can be seen that, due to the concentric / annular configuration of the protection device 100, at least two different levels of metallization are necessary to connect the cathode and the anode in a manner isolated from each other.

[0062] Certain electronic components, such as photodiodes, are very sensitive to overvoltages and electrostatic discharges, and exhibit low robustness to these conditions, necessitating protection by electrostatic discharge protection devices. The principle of a protection device is to create a path for a discharge current so that this current does not reach the sensitive electronic component; more generally, to prevent the discharge current from reaching the sensitive electronic component. Typically, a protection device is positioned near the sensitive electronic component and / or near an input / output terminal of this electronic component.A protection device may be similar to protection device 100 in Figures IA and IB, but it may be any other more or less complex protection device based on diode(s), bipolar transistor(s), MOSFET transistor(s), thyristor(s) and / or triac(s) (from the English "triode for alternating current"), in a manner known to those skilled in the art. These components are referred to as basic electronic components in this description.

[0063] Figure IC shows an example of an integrated circuit 10 comprising an electronic component (PHOTODIODE), which is a photodiode 120, connected to the protection device 100 (ESD PROTECTION) via an input / output (FO) terminal 130A. For the sake of simplicity, only a photodiode 120 is shown, but the integrated circuit may include several photodiodes and / or several other electronic components to be protected. The ring-shaped design of the protection device 100 allows, in particular, the positioning of several electronic components to be protected around this device.

[0064] In this example, the integrated circuit 10 is of the "back-side" type, or "back-side integrated" (BSI). A back-side integrated circuit, or BSI, is an integrated circuit that includes conductive traces on its rear side (under the bottom face of the substrate), that is, on the side opposite the front side (on the top face of the substrate), which corresponds to the side on and / or from which The electronic components are arranged on this surface. The front panel, or top panel, can be referred to as "front-side" in English.

[0065] In the example shown in [Fig. IC], the interconnection structure 110 comprises the conductive tracks 111, 112 described previously, positioned above the upper face 101A of the substrate 101, and it further comprises conductive tracks 114 of a metallization level different from the first and second levels, and on the rear face, i.e., below the lower face 101B of the substrate 101. The metallization level M4 is shown, but it could be a completely different metallization level from M1 and M2, for example, the metallization level M3. The conductive tracks 114 are portions of a conductive layer, for example, a metallic layer, of the metallization level M4.The conductive tracks 114 are insulated from each other by an insulating layer 117, which is generally a stack of several insulating layers, separating on the rear face (under the lower face 101B) the different metallization levels and the different conductive tracks of the same metallization level. The insulating layer 117 may be similar to the insulating layer 116, for example be made of an oxide, for example silicon oxide.

[0066] The I / O terminal 130A is on the rear face and comprises a conductive track 114A of the metallization level M4 and a connection pad 131A (ALUCAP) positioned opposite the conductive track 114A and connected to it by conductive vias 118 of the interconnection structure 110, similar to the vias 115 on the front face described previously. The LO terminal 130A comprises a conductive via 133A passing through the substrate 101 between the upper face 101A and the lower face 101B, and connecting the conductive track 114A to a conductive track 11IC of the first metallization level M1 connected to the conductive track 11IB. Thus the I / O terminal 130A, and its connection pad 131A, are connected to the anode of the DI diode of the protection device 100. The via conductor 133A is isolated from all or part of the substrate 101, at least from the box 103, by an insulating trench 134A of the type STI, from the English Shallow Trench Isolation.

[0067] The conductive track 11 IC is also connected to an N-type doped (N+) conductive region 126 of the photodiode 120 via another conductive track 111D of the first metallization level Ml connected to the conductive track 11 IC, allowing the photodiode 120 to be connected to the I / O terminal 130A.

[0068] The integrated circuit 10 generally includes several I / O terminals, for example around the periphery of the integrated circuit.

[0069] Another I / O terminal 130B is shown on the other side of photodiode 120 with respect to I / O terminal 130A. This I / O terminal 130B is substantially similar to I / O terminal 130A, except that it connects to the second metallization level M2, is connected to the conductive track 112A and that it is isolated from the conductive tracks 11 IA, 111B, 111C, 111D.

[0070] The I / O terminal 130B is on the rear face, and it includes another conductive track 114B of the metallization level M4, isolated from the conductive track 114A. The I / O terminal 130B further includes another connection pad 13 IB (ALUCAP), isolated from the connection pad 131 A, positioned opposite the conductive track 114B and connected to it by other conductive vias 118 of the interconnection structure 110. The I / O terminal 130B includes another conductive via 133B passing through the substrate 101 between the upper face 101A and the lower face 101B, and connecting the conductive track 114B to another conductive track 111F of the first metallization level M1 isolated from the other conductive tracks of the first metallization level M1, but connected to another conductive track 112D of the second metallization level M2 by another via 115.The conductive track 112D is connected to the conductive track 112A via a conductive track 112C of the second metallization level M2, which is connected to a P-type doped (GeP+) conductive region 125 of the photodiode 120 via another conductive track 111E of the first metallization level M1, isolated from the other conductive tracks of the first metallization level ML. Thus, the photodiode 120 is connected to the I / O terminal 130B. The FO terminal 130B, and its connection pad 13 IB, are thus connected to the cathode of the DI diode of the protection device 100. The conductive via 133B is isolated from all or part of the substrate 101, in this example at least to a height corresponding to the depth of the enclosure 103, by an insulating trench 134B of the STI type.

[0071] It can be seen in [Fig.1C] by the representation of the path II that the current arriving from the terminal FO 130A can be diverted by the protection device 100 to reach the terminal I / O 130B by the second level of metallization M2 to be evacuated, without passing through the photodiode 120, which can thus be protected.

[0072] One or more protection devices 100 can be associated with the I / O terminals of the integrated circuit 10. The FO terminals can be intended to receive and / or supply input-output signals, or even to receive high (VDD) and low (VSS) supply potentials.

[0073] One problem with protection devices such as protection device 100 is that they introduce parasitic capacitances at the I / O terminals.

[0074] As can be seen in [Fig. 1A], each parasitic capacitance is due to a conductive track / insulating layer / conductive track junction. Parasitic capacitances C1 are formed at the first metallization level M1, in this example between the central conductive track 11IA and the peripheral conductive track 11IB. Other parasitic capacitances C2 are formed between the first and second metallization levels M1 and M2, in this example between the peripheral conductive track 11IB and each conductive track 112.

[0075] However, certain applications, for example photodetection or photonics applications, are very sensitive to parasitic capacitances. This is particularly critical in HF (High Frequency) applications, typically in electronic devices such as photosensors that include photodiodes. For example, parasitic capacitances can degrade the signals exchanged between the electronic device and the outside world via the I / O terminals.

[0076] Thus, in these applications, it may be sought to minimize the parasitic capacitances of the protection devices, in order to maintain the functionality of the UO terminals and the desired performance of the electronic components connected to these FO terminals, or comprising these FO terminals.

[0077] To reduce the impact of metallization, i.e. of conductive tracks in the insulating layer, one may be tempted to increase the distances between the conductive tracks of the protection device, without degrading its robustness.

[0078] A common solution is to increase the size of a protective device to increase the space between the conductive tracks. However, in the case of an annular / concentric type protective device as described above, this can considerably increase the size of the protective device.

[0079] Another solution is to add another level of metallization to the front face, as illustrated below in relation to Figures 2A and 2B.

[0080] Fig. 2A is a cross-sectional view of another example of a protective device 200 against electrostatic discharge. Fig. 2B is a top view of the protective device 200 shown in Fig. 2A. Fig. 2A is a view along section plane AA shown in Fig. 2B.

[0081] The protective device 200 of Figures 2A and 2B includes elements common to the device 100 of Figures IA and IB. These common elements will not be described again below.

[0082] The device 200 of Figures 2A and 2B differs from the device 100 of Figures IA and IB in that the interconnection structure 210 includes a conductive track 212A of the second metallization level M2, which is opposite, does not extend on either side of, the central conductive track 11 IA, and in particular does not extend over the peripheral conductive track 11 IB. The conductive track 212A is connected to the N-type semiconductor region 106, and thus to the cathode of diode D1, by the central conductive track 11IA and conductive vias 115. The interconnection of the cathode is made at a third metallization level M3 by conductive tracks 213 which are connected to the conductive track 212A by conductive vias 115, and thus to the N-type semiconductor region 106. The conductive tracks 213 comprise two connected and perpendicular conductive tracks 213A and 213B.

[0083] This configuration reduces the parasitic capacitances C2 between the first and second metallization levels M1 and M2, due to a greater distance between the peripheral conductive track 11 IB and the conductive track 212A. The parasitic capacitances C3 between the conductive track 11 IB and each conductive track 213 are reduced, since each conductive track 213 is formed at a third metallization level M3 higher than the second metallization level M2, thus increasing the distance between the conductive tracks 11 IB and 213.

[0084] However, in this configuration, parasitic capacitances are not eliminated between the different metallization levels. Moreover, this requires portions of metallization that cannot be used for another connection.

[0085] There is therefore a need for a device to protect against electrostatic discharge that generates as little parasitic capacitance as possible, without increasing the size of the protective device or degrading its performance. In particular, there is a need to avoid degrading, or even to improve, the quality of protective devices in high-speed and high-frequency applications.

[0086] It would be desirable that the electrostatic discharge protection device not require the addition of one or more levels of metallization, or one or more conductive tracks.

[0087] Figure 3A is a cross-sectional view of a protective device 300 against electrostatic discharge according to one embodiment. Figure 3B is a top view of the protective device 300 of Figure 3A. Figure 3A is a view along the section plane AA shown in Figure 3B.

[0088] The protective device 300 of Figures 3A and 3B includes elements common to the device 100 of Figures IA and IB. These common elements will not be described again below.

[0089] The protection device 300 of Figures 3A and 3B differs from the protection device 100 of Figures IA and 1B in that the anode and cathode interconnections are not made on the same face of the semiconductor substrate 101. In the example of Figures 3A and 3B, the anode is interconnected above the upper face 101A of the substrate 101 (front face), and the cathode is interconnected below the lower face 101B of the substrate 101 (rear face). In other words, the anode and cathode are interconnected on opposite sides of the substrate 101. The interconnection of the cathode on the rear face includes a conductor via 318 passing through the substrate 101 between the upper face 101A and the lower face 101B. The conductor via 318 is isolated from all or part of the substrate 101, at least from the box 103, by an insulating trench 319 of the STI type. As will be seen in the example of [Fig.3C], alternatively, the anode could be interconnected on the front face, and the cathode on the back. rear. The conductor via 318 and the insulating trench 319 are shown in dashed and transparent in [Fig.3B], being under the central conductive track 31 IA.

[0090] Back-side integrated (BSI) technology is used to interconnect the electrodes of the protection device 300, while keeping the conductive tracks forming these electrodes further apart as explained later, in order to reduce the parasitic capacitances they could generate.

[0091] The protection device 300 of Figures 3A and 3B comprises a semiconductor box 103 (PW), similar to the semiconductor box 103 of Figures IA and IB. This box extends vertically through a partial thickness of the semiconductor substrate 101 from a face 101A of the substrate 101. The box 103 is doped with the first type of conductivity (type P, in this example) and has a higher doping level than the substrate 101.

[0092] The device 300 further comprises semiconductor regions, a semiconductor region 305 (P+) and a semiconductor region 306 (N+), extending vertically through the thickness of the semiconductor substrate 101 from face 101A. The semiconductor regions 305 and 306 are located in the box 103, and their depth within the box 103 is considerably less than the thickness of the box 103. The semiconductor regions 305 and 306 are thus surrounded laterally and from below by the box 103. The semiconductor region 305 is doped with the first type of conductivity (type P, in this example) and has a doping level higher than that of the semiconductor substrate 101 and that of the box 103.Semiconductor region 306 is doped with the second type of conductivity (type N, in this example) and has a higher doping level than that of the semiconductor substrate 101, and that of the box 103, for example substantially equal to that of the semiconductor region 305.

[0093] The N-type semiconductor region 306 forms an NP-type heterojunction with the P-type housing 103, thus forming a DI diode. The P-type semiconductor region 305 forms the anode of the DI diode with the housing 103. The N-type semiconductor region 306 forms the cathode of the DI diode.

[0094] In the example shown in Figures 3A and 3B, the N-type semiconductor region 306 is a central semiconductor region which, viewed from above, has a substantially annular shape around the insulating trench 319. The semiconductor region 306 in Figures 3A and 3B is thus distinguished from the semiconductor region 106 in Figures IA and 1B by being annular, and not rectangular. This allows the conductor via 318 to pass through the substrate 101, with the insulating trench 319 around it. The P-type semiconductor region 305 is a peripheral semiconductor region, and, viewed from above, has a substantially annular shape around the N-type semiconductor region 306, similarly to the semiconductor region 105 in Figures IA and IB.

[0095] The box 103, as well as the semiconductor regions 305, 306 are for example formed in the substrate 101 by ion implantation from the face 101A of the substrate 101.

[0096] In the example shown in Figures 3A and 3B, the interconnection structure 310 comprises: - conductive tracks 311 of a metallization level Ml, similar to the conductive tracks 111 described previously in connection with figures IA and IB, positioned above the upper face 101A of the substrate 101; and - conductive tracks 312 of a metallization level different from the metallization level Ml, under the lower face 101B of the substrate 101: the metallization level M2 has been shown, but it may be a completely different metallization level than Ml, for example the metallization level M3 or M4.

[0097] The conductive tracks 311 comprise a central conductive track 31 IA and a peripheral conductive track 311B which surrounds the central conductive track 31 IA in a substantially annular manner and which is insulated from this central conductive track by an insulating layer 316 of the interconnection structure 310. The peripheral conductive track 31 IB could be electrically connected to other conductive tracks (not shown) of the metallization level M1, for example to connect the protection device 300 to an electronic component and / or to an input / output terminal.

[0098] In [Fig.3B], the conductive tracks 312 are shown in dashed lines and in transparency, being under the substrate 101. They comprise two conductive tracks 312A and 312B connected and perpendicular to each other, for example to connect the protection device 300 to an electronic component and / or to an input / output terminal, as described later in connection with [Fig.3C].

[0099] The central conductive track 31 IA is connected to the conductive tracks 312 by the conductor via 318.

[0100] The conductive tracks 311 of the metallization level M1 are insulated from each other and from the substrate 101 by the insulating layer 316, which may be similar to the insulating layer 116 of Figures IA and IB. The insulating layer 316 separates, on its front face (on the upper face 310A), the different metallization levels and the different conductive tracks of the same metallization level. The insulating layer 316 is generally a stack of several insulating layers. The insulating layer 316 may be made of an oxide, for example, silicon dioxide.

[0101] The conductive tracks 312 of the metallization level M2 are insulated from each other and from the substrate 101 by an insulating layer 317, which may be similar to the insulating layer 316. The insulating layer 317 separates on its rear face (under the lower face 101B) the different levels of metallization and the different conductive tracks of the same metallization level. The insulating layer 317 is generally a stack of several insulating layers. The insulating layer 317 can be made of an oxide, for example, silicon oxide.

[0102] The conductive track 31 IB is connected to the P-type semiconductor region 305 and forms an anode electrode. Each conductive track 312 is connected to the N-type semiconductor region 106 and forms a cathode electrode.

[0103] As can be seen in [Fig. 3A], the parasitic capacitances C2 of [Fig. 1A], which were formed between the first and second metallization levels M1 and M2, between the anode and cathode electrodes of [Fig. 1A], were eliminated without adding an additional metallization level and without increasing the size of the protection device. In the device of [Fig. 3A] and 3B, the anode electrode 31 IB and the cathode electrode 31 IA are separated from each other since they are on opposite sides of the substrate 101.

[0104] The inventors determined that the fact that the N-type semiconductor region 306 is annular to allow the via conductor 318 to pass through, and not rectangular, did not disrupt the passage of current, since the current preferentially passes around the periphery of the N-type semiconductor region, and to a lesser extent through the center of the N-type semiconductor region. Thus, the performance of the protection device is not degraded, even in high-speed and high-frequency applications.

[0105] Furthermore, in a back-side integrated circuit, a level of metallization and thus conductive traces are already present on the underside of the substrate, in addition to, generally, conductive traces on the top side of the substrate. The protection device can therefore be easily formed using a standard back-side process, or even by being integrated into the integrated circuit manufacturing process.

[0106] Figure 3C is a cross-sectional view of an example of an integrated circuit 30 comprising a protection device 300' according to one embodiment. Figure 3C shows an example of an integrated circuit 30 comprising an electronic component (photodiode), which is a photodiode 320, similar to the photodiode 120 of Figure 1C, connected to the protection device 300' (ESD protection) via an input / output (I / O) terminal 330A. For the sake of simplicity, only one photodiode 320 is shown, but the integrated circuit 30 may include several photodiodes and / or one or more other electronic components to be protected. The ring-shaped form of the protection device 300, 300' allows, in particular, the positioning of several electronic components to be protected around this protection device.

[0107] The protective device 300' of [Fig. 3C] is similar to that of Figures 3A and 3B, except that, in the enclosure 103' PW, the P-type semiconductor region 305' forming the anode is a central, rather than peripheral, semiconductor region, and the N-type semiconductor region 306' forming the cathode is a peripheral, rather than central, semiconductor region. Thus, the central conductive track 31 IA is in this case connected to the anode, rather than the cathode, and therefore forms the anode electrode. Similarly, the peripheral conductive track 31 IB is connected to the cathode, rather than the anode, and therefore forms the cathode electrode. A person skilled in the art would be able to adapt the connections described below for a protective device similar to the device 300 of Figures 3A and 3B.

[0108] Similar to [Fig. 1C], the LO 330A terminal includes a rear-facing connection pad 331A (ALUCAP), positioned opposite a rear-facing conductive track 314A at metallization level M4. The conductive track 314A is connected to the connection pad 331A by conductive vias 318 of the interconnect structure 310, similar to the front-facing vias 315 described previously. The LO 330A terminal includes a conductive via 333A passing through the substrate 101 between the upper face 101A and the lower face 101B, and connecting the conductive track 314A to a conductive track 31IC of the metallization level M1, which is isolated from the conductive track 31IB. The conductor via 333A is isolated from all or part of the substrate 101, at least from the enclosure 103', by an insulating trench 334A of the STI type. The conductive track 314A is also connected on its rear face to a conductive track 314A' which forms the anode connection for the DI diode of the protection device 300'.The conductive track 314A' is connected to the central conductive track 31 IA by the conductor via 318.

[0109] In [Fig. 3C], the rear face shows the metallization level M4, instead of the metallization level M2 shown in Figures 3A and 3B, the metallization level M2 being shown on the front face in [Fig. 3C]. Thus, reference 312A has been replaced by reference 314A'. The front face could be omitted, for example, with only the metallization level ML.

[0110] Thus the I / O terminal 330A, and its connection pad 331A, are connected to the anode of the DI diode of the protection device 300' via the conductive track 314A'.

[0111] The conductive track 31 IC is also connected to an N-type doped (N+) conductive region 326 of the photodiode 120 via another conductive track 311D of the metallization level Ml, allowing the photodiode 320 to be connected to the LO 330A terminal.

[0112] Another terminal LO 330B is shown on the other side of the photodiode 320 with respect to the terminal LO 330A. This terminal LO 330B is substantially similar to the terminal LO 330A, except that it connects to the metallization level M2.

[0113] The I / O terminal 330B includes another conductive track 314B of the metallization level M4, isolated from the conductive track 314A. The I / O terminal 330B includes another connection pad 33 IB (ALUCAP), isolated from the connection pad 331 A, positioned opposite the conductive track 314B and connected to it by other conductive vias 318 of the interconnection structure 310. The I / O terminal 330B further includes another conductive via 333B passing through the substrate 101 between the upper face 101A and the lower face 101B. The conductive via 333B is isolated from all or part of the substrate 101, in this case at least over a height corresponding to the depth of the box 103', by another insulating trench 334B of the STI type.The conductive via 333B connects the conductive track 314B to another conductive track 311F of the metallization level M1 isolated from the other conductive tracks of the metallization level M1, but connected to a conductive track 312D of the metallization level M2 by other vias 315. The conductive track 312D is connected to another conductive track 312C of the metallization level M2 which is connected to a P-type doped (GeP+) conductive region 325 of the photodiode 320 via another conductive track 311E of the metallization level M1 isolated from the other conductive tracks of the metallization level ML. Thus, the photodiode 320 is connected to the I / O terminal 330B. The conductive track 312C is connected via other vias 315 to the peripheral conductive track 31 IB which forms the cathode electrode. Thus, the I / O terminal 330B, and its connection pad 33IB, are connected to the cathode of the DI diode of the protection device 300.

[0114] It can be seen in [Fig.3C] by a representation of the current path 12 that the current arriving from terminal FO 330A can be diverted by the protection device 300 to reach terminal I / O 330B by the metallization level M2 to be evacuated, without passing through the photodiode 320, which can thus be protected.

[0115] Furthermore, it can be seen from [Fig. 3C] that the protective device 300' can be easily connected to the I / O terminal 330A, since the conductive track 314A' of the protective device 300' is on the rear face, like the connection pad 331A (ALUCAP) and the conductive track 314A of the FO terminal 330A, and is also at the same M4 metallization level as the conductive track 314A of the I / O terminal 330A. The protective device 300' can thus, for example, be placed as close as possible to the I / O terminal 330A, thereby optimizing protection.

[0116] One or more protection devices 300 can be associated with the I / O terminals of the integrated circuit 30. The FO terminals can be intended to receive and / or supply input-output signals, or even to receive high (VDD) and low (VSS) supply potentials.

[0117] Although the protection devices 300, 300' are diode-based, a protection device according to an embodiment may be based on several diodes, bipolar transistor(s) and / or MOSFET(s), thyristor(s), triac(s), or a a combination of several of these electronic components, in a manner known to a person skilled in the art. Two other types of protective devices will be illustrated below in relation to Figures 4A, 4B, 5A and 5B, although these examples are not exhaustive.

[0118] The interconnection structure 310 of Figures 4A, 4B, 5A, and 5B is similar to that of Figures 3A and 3B. It includes, in particular, conductive tracks 311 of the metallization level M1, as well as vias 315 and an insulating layer 316, on the front face. The interconnection structure 310 further includes conductive tracks 312 of the metallization level M2, as well as an insulating layer 317, on the rear face. Similar to what has been described in relation to Figures 3A and 3B, the conductive tracks 311 include a central conductive track 31IA and a peripheral conductive track 311B that surrounds the central conductive track 31IA in a substantially annular manner, and the conductive tracks 312 include two connected and perpendicular conductive tracks 312A and 312B. The conductive tracks 312 are shown in dotted lines and in transparency in figures 4B and 5B, being under the substrate 101.

[0119] Figure 4A is a cross-sectional view of a protective device 400 against electrostatic discharge according to another embodiment. Figure 4B is a top view of the protective device 400 of Figure 4A. Figure 4A is a view along section plane AA shown in Figure 4B.

[0120] The protective device 400 of Figures 4A and 4B includes elements common to the protective device 300 of Figures 3A and 3B. These common elements will not be described again below.

[0121] The protection device 400 of Figures 4A and 4B differs from the protection device 300 of Figures 3A and 3B in that it is of the thyristor type. For short, the protection device 400 may be referred to as a thyristor in the following description.

[0122] The protective device 400 of Figures 4A and 4B comprises: - a semiconductor enclosure 403 (PW), extending vertically through the thickness of the semiconductor substrate 101 from the upper face 101A of the substrate 101, and having a height less than the thickness of the substrate 101; and - a semiconductor box 404 (NW), extending vertically in the thickness of the semiconductor substrate 101 from the upper face 101A of the substrate 101, and having a height less than the thickness of the substrate 101.

[0123] The 403 box is of the first type of conductivity, in the example of type P. The 404 box is of the second type of conductivity, in the example of type N.

[0124] The 403 and 404 boxes have a higher level of doping than the semiconductor substrate 101. For example, the 403 box has a doping level substantially equal to that of the 404 box.

[0125] In the example of Figures 4A and 4B, the box 404 is annular around the conductor via 318 and the insulating trench 319, shown in dashed lines and in transparency in [Fig. 4A], being below the conductive track 31 IA. The box 403 is also annular and surrounds the box 404.

[0126] A semiconductor region 405 of the first type of conductivity, in the example of type P, and a semiconductor region 406 of the second type of conductivity, in the example of type N, are located in the box 403. The regions 405 and 406 extend vertically through the thickness of the semiconductor substrate 101 from the upper face 101A, their thicknesses being much less than those of the substrate 101 and the box 403. The semiconductor regions 405 and 406 have a higher level of doping than the semiconductor substrate 101 and the box 403.

[0127] A semiconductor region 407 of the first type of conductivity, in the example of type P, and a semiconductor region 408 of the second type of conductivity, in the example of type N, are located in the box 404. The regions 407 and 408 extend vertically through the thickness of the semiconductor substrate 101 from the upper face 101A, their thicknesses being much less than those of the substrate 101 and the box 404. The semiconductor regions 407 and 408 have a higher level of doping than the semiconductor substrate 101 and the box 404.

[0128] In the example shown in Figures 4A and 4B, the semiconductor regions 405, 406, 407, and 408 each have, in top view, an annular shape around the via conductor 318 and the insulating trench 319. The semiconductor region 408 is closest to the via conductor 318 and the insulating trench 319. The semiconductor region 407 is arranged around the semiconductor region 408. The semiconductor region 406 is arranged around the semiconductor region 407. The semiconductor region 405 is arranged around the semiconductor region 406.

[0129] The configuration shown in Figures 4A and 4B is not limiting, and for example, the P-type semiconductor region 407 could be closest to the via conductor 318 and the insulating trench 319, the N-type semiconductor region 408 could be around the P-type semiconductor region 407, the P-type semiconductor region 405 could be around the N-type semiconductor region 408, and the N-type semiconductor region 406 could be around the P-type semiconductor region 405. A thyristor structure with a central P-type box and a peripheral N-type box could also be considered. Those skilled in the art may consider any other configuration, provided it allows for the formation of a thyristor, more generally with a P+ region and an N+ region in a PW box, as well as an N+ region and a P+ region in an NW box.

[0130] The N-type semiconductor region 406 forms an NP-type heterojunction with the P-type box 403, and thus a first DI diode. The semiconductor region The P-type diode 407 forms a PN-type heterojunction with the N-type diode 404, thus creating a second diode D2, inverted with respect to the first diode D1. The thyristor 400 therefore comprises the first diode D1 and the second diode D2, inverted with respect to the first diode D1. Furthermore, the PN heterojunction between the diodes 403 and 404 forms a third diode D3.

[0131] The thyristor 400 can also be represented by two nested bipolar transistors: a first PNP transistor which includes the junctions formed by the P+ region 407, the NW box 404 and the PW box 403 (the N+ region 408 in the NW box 404 forming a control of this first transistor), and a second NPN transistor which includes the junctions formed by the N+ region 406, the PW box 403 and the NW box 404 (the P+ region 405 in the PW box 403 forming a control of this second transistor).

[0132] In the example illustrated in Figures 4A and 4B, the thyristor 400 comprises a first gate, or control electrode, corresponding to the P-type region 405 located in the P-type housing 403, and a second gate corresponding to the N-type region 408 located in the N-type housing 404. In this example, the first and second gates 405 and 408 are connected respectively to the peripheral conductive track 31 IB and the central conductive track 31 IA, which form the cathode and anode of the thyristor 400, respectively. In other words, the gate 405 and the cathode 31 IB of the thyristor 400 are short-circuited. Similarly, the gate 408 and the anode 31 IA of the thyristor 400 are short-circuited. The anode 31 IA of the thyristor 400 is connected to the conductive track 312 on the rear face by the conductive via 318.The thyristor 400 is in this case in blocked mode and is equivalent to a diode comprising a PN heterojunction whose doped region of the second type of conductivity (type N, in this example) is constituted by the semiconductor regions 407 and 408 and by the box 404, and whose doped region of the first type of conductivity (type P, in this example) is constituted by the regions 405 and 406 and by the box 403. The electrodes 311A ​​and 311B correspond respectively, for the diode to which the thyristor 400 is equivalent in blocked mode, to cathode and anode electrodes, while they correspond respectively to the anode and cathode of the thyristor 400. Current can flow between region 407 and region 406.

[0133] The trigger voltage of the thyristor, such as that shown in Figures 4A and 4B, is different from that of the diode-based protection device, such as that shown in Figures 3A and 3B.

[0134] This example of a thyristor is not limiting, and other thyristor structures may be considered by a person skilled in the art. For example, one or both gates may not be short-circuited with the anode or cathode of the thyristor. This allows control over the triggering of the protection and triggering it at lower voltages.

[0135] Fig. 5A is a cross-sectional view of a protective device 500 against electrostatic discharge according to another embodiment. Fig. 5B is a top view of the protective device 500 of Fig. 5A. In Fig. 5B, the metallization level M1 is not shown to better visualize the semiconductor regions and semiconductor enclosures. Fig. 5A is a view along the sectional plane AA shown in Fig. 5B, with the metallization level ML added.

[0136] The protective device 500 of Figures 5A and 5B comprises elements common with the protection device 300 of figures 3A and 3B. These common elements will not be described again below.

[0137] The protection device 500 of Figures 5A and 5B differs from the protection device 300 of Figures 3A and 3B in that it is of the triac type. For short, the protection device 500 may be referred to as a triac in the following description. A triac can be viewed as an elementary electronic component equivalent to the parallel connection of two thyristors, such as the thyristor 400 of Figures 4A and 4B, connected back-to-back (the anode of one is connected to the cathode of the other, the respective gates being controlled simultaneously).

[0138] The protective device 500 of Figures 5A and 5B comprises: - a semiconductor box 502 (NW1), extending vertically in the thickness of the semiconductor substrate 101 from the upper face 101A of the substrate 101, and having a height less than the thickness of the substrate 101; - a semiconductor enclosure 503 (PW), extending vertically through the thickness of the semiconductor substrate 101 from the upper face 101A of the substrate 101, and having a height less than the thickness of the substrate 101; and - a semiconductor box 504 (NW2), extending vertically in the thickness of the semiconductor substrate 101 from the upper face 101A of the substrate 101, and having a height less than the thickness of the substrate 101.

[0139] In the example of Figures 5A and 5B, the box 504 is annular around the conductor via 318 and the insulating trench 319, shown in dashed lines and in transparency in [Fig. 5B], being below the conductive track 31 IA. The box 503 is also annular and surrounds the box 504. The box 502 is also annular and surrounds the box 503.

[0140] The enclosure 502 is of the second type of conductivity, in the example of type N. The enclosure 503 is of the first type of conductivity, in the example of type P. The enclosure 504 is of the second type of conductivity, in the example of type N.

[0141] The cells 502, 503 and 504 have a higher level of doping than the semiconductor substrate 101. For example, cell 502 has a doping level substantially equal to that of cell 504. For example, cells 502 and 504 have a doping level substantially equal to that of cell 503.

[0142] In top view, the thyristor 500 can be seen to be arranged in four portions 500A, 500B, 500C, 500D of equal size. Portions 500A and 500C are symmetrical about the center and are similar. Portions 500B and 500D are symmetrical about the center and are similar.

[0143] In portions 500A and 500C, a semiconductor region 506 of the second type of conductivity, in the example of type N, is located in the cavity 502. In portions 500B and 500D, a semiconductor region 505 of the first type of conductivity, in the example of type P, is located in the cavity 502. Regions 505 and 506 extend vertically through the thickness of the semiconductor substrate 101 from the upper face 101A, their thicknesses being much less than those of the substrate 101 and the cavity 502. Semiconductor regions 505 and 506 have a higher level of doping than the semiconductor substrate 101 and the cavity 502. Regions 505 and 506 are connected to each other in the cavity 502 and form a continuous ring.

[0144] In portions 500B and 500D, a semiconductor region 508 of the second type of conductivity, in the example of type N, is located in the box 504. In portions 500A and 500C, a semiconductor region 507 of the first type of conductivity, in the example of type P, is located in the box 504. Regions 507 and 508 extend vertically through the thickness of the semiconductor substrate 101 from the upper face 101A, their thicknesses being much less than those of the substrate 101 and the box 504. Semiconductor regions 507 and 508 have a higher level of doping than the semiconductor substrate 101 and the box 504. Regions 507 and 508 are connected to each other in the box 504 and form a continuous ring.

[0145] In the four portions 500A, 500B, 500C, 500D, the P-type box 503 includes a semiconductor region 509 of the first type of conductivity, in the example of the P-type. The region 509 extends vertically through the thickness of the semiconductor substrate 101 from the upper face 101A, its thickness being much less than those of the substrate 101 and the box 503. The semiconductor region 509 has a higher level of doping than the semiconductor substrate 101 and the box 503. The region 509 is annular in shape.

[0146] In the example shown in figures 5A and 5B: - the semiconducting regions 507 and 508 connected together have, in top view, an annular shape around the conductor via 318 and the insulating trench 319; - the semiconductor region 509, viewed from above, has an annular shape around the semiconductor regions 507 and 508; and - the semiconductor regions 505 and 506 connected together have, in top view, an annular shape around the semiconductor region 509.

[0147] The P-type semiconductor region 505 forms a PN-type heterojunction with the N-type box 502, thus forming a first diode. The P-type semiconductor region 507 forms a PN-type heterojunction with the N-type box 504, thus forming a diode with the same polarity as the first diode. The heterojunctions between the PW box 503 and each of the NW boxes 502 and 504 form two diodes with opposite polarities.

[0148] In the example illustrated in figures 5A and 5B, the triac 500 includes a gate, or control electrode, corresponding to the P-type semiconductor region 509 located in the P-type housing 503.

[0149] In the example of Figures 5A and 5B, the gate 509 is connected to the central conductive track 31 IA, which forms the anode of the triac 500 and which is also connected to regions 507 and 508. In other words, the gate 509 and the anode 31 IA of the triac 500 are short-circuited. The anode 31 IA of the triac 500 is connected to the rear-panel conductive tracks 312 via conductor 318. Regions 505 and 506 are also connected to each other and to the peripheral conductive track 31 IB, which forms the cathode of the triac 500. Compared to diode or thyristor protection devices, such as those described previously, the triac provides a bidirectional structure, allowing current to flow from the anode to the cathode of the triac, and from the cathode to the anode of the triac.

[0150] This example of a triac is not limiting, and other triac structures can be considered by those skilled in the art. For example, one can consider having a P-type annular region and an N-type annular region in each of the N-type cells 502 and 504. The four portions 500A, 500B, 500C, 500D of the 500 triac would then be similar. One can also consider a triac structure with two P-type cells, each including an N-type annular region and a P-type annular region, and an N-type cell, including an N+ annular region, between these two P-type cells.

[0151] The embodiments described above can be used in many types of industrial markets, for example: - the personal electronics industry, for example in the field of mobile telephony and the Internet of Things (IoT), as well as in the field of broadband interfaces; - the communications equipment, computer and peripherals industry, for example in the field of infrastructure and data centers.

[0152] For example, the embodiments described above can be used in many applications implementing fiber communication.

[0153] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. In particular, although the case in which the first type of conductivity is P and the second type of conductivity is N has been detailed above, the embodiments and variants described are applicable to those skilled in the art in the case in which the first type of conductivity is N and the second type of conductivity is P.

[0154] Furthermore, although the semiconductor casings and semiconductor regions of the protection devices previously described in relation to Figures 2A, 2B, 3A, 3B, 4A and 4B each have an annular shape in top view, the semiconductor casings and semiconductor regions of the protection devices could, alternatively, each have a different shape. For example, the semiconductor casings and semiconductor regions of the protection devices could each have, in top view, the shape of a band extending laterally along a direction orthogonal to the cutting plane of Figures 2A, 3A, and 4A, or of an elongated "U" extending laterally along a direction orthogonal to the cutting plane of Figures 2A, 3A, and 4A, i.e., an open annular shape.

[0155] Furthermore, although Figures IC and 3C show a photodiode as the electronic component to be protected, it can be any electronic component that one wishes to protect from electrostatic discharges.

[0156] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional specifications given above. In particular, a person skilled in the art is able to predict the doping levels of the semiconductor substrate, the N-doped semiconductor boxes, the P-doped semiconductor boxes, as well as the N-doped semiconductor regions and the P-doped semiconductor regions.

Claims

Demands

1. An electronic device (300; 300'; 400; 500) adapted to protect an electronic component (320) against electrostatic discharges, the electronic device comprising semiconductor regions extending deep into a semiconductor substrate (101) from a first face (101A) of said semiconductor substrate, the semiconductor regions comprising: - a first semiconductor region (103; 306'; 403; 502) of a first type of conductivity; and - a second semiconductor region (306; 103'; 404; 503) of the second type of conductivity opposite to the first type of conductivity, forming a PN junction with the first semiconductor region; the first semiconductor region being connected to a first conductive track (311B) forming a first connection pin of the electronic device, the second semiconductor region being connected to a second conductive track (312A;314A') forming a second connection pin of the electronic device, the semiconductor substrate being between the first conductive track and the second conductive track.;

2. Electronic device (300; 300'; 400; 500) according to claim 1, wherein the semiconductor substrate (101) has a second face (101B) opposite the first face (101A), the electronic device comprising a conductive via (318) passing through the semiconductor substrate between the first face (101A) and the second face (101B), and connecting the second semiconductor region (306; 103'; 404; 503) to the second conductive track (312A; 314A').

3. Electronic device (300; 300'; 400; 500) according to claim 2, wherein the conductor via (318) is isolated from the semiconductor substrate (101) by an insulating trench (319).

4. Electronic device (300; 300'; 400; 500) according to any one of claims 1 to 3, wherein the semiconductor regions are annular, for example concentric around each other.

5. Electronic device (300; 300'; 400; 500) according to claim 4 in its dependence on claim 2 or 3, wherein the Semiconductor regions are annular around the via conductor (318).

6. Electronic device (300; 300') according to any one of claims 1 to 5, wherein the first semiconductor region (103) is a first semiconductor box and the second semiconductor region (306) is located in the first semiconductor box, or the second semiconductor region (103') is a first semiconductor box and the first semiconductor region (306') is located in the first semiconductor box.

7. Electronic device (400; 500) according to any one of claims 1 to 5, wherein the first semiconductor region (403; 502) is a first semiconductor box and the second semiconductor region (404; 503) is a second semiconductor box in contact with the first semiconductor box.

8. Electronic device (300; 300'; 400; 500) according to any one of claims 1 to 7, wherein the first and second conductive tracks are included in an interconnect structure (310) comprising several metallization levels, including at least a first metallization level (M1; M1, M2) on the side of the first face (101A) of the semiconductor substrate (101) and at least a second metallization level (M2; M4) on the side of the second face (101B) of the semiconductor substrate.

9. Electronic device (300; 300'; 400; 500) according to claim 8, wherein the first conductive track (31 IB) is included in the first level of metallization (M1), and the second conductive track (312A; 314A') is included in the second level of metallization (M2; M4).

10. Electronic device (300; 400) according to any one of claims 1 to 9, wherein the first type of conductivity is of type P, and the second type of conductivity is of type N.

11. Electronic device (300'; 500) according to any one of claims 1 to 9, wherein the first type of conductivity is of type N, and the second type of conductivity is of type P.

12. An electronic device according to any one of claims 1 to 11, the electronic device being an electrostatic discharge protection device comprising at least one component elementary electronic component including a diode, a bipolar transistor, a thyristor and a triac, said at least one elementary electronic component including the semiconductor regions, the first conductive track and the second semiconductor region.

13. Integrated circuit (30) comprising an electronic device according to any one of claims 1 to 12 and an electronic component (320) connected to said electronic device.

14. Integrated circuit (30) according to claim 13, further comprising a first terminal (330B) connected to the first connection pin (311B) of the electronic device and a second terminal (330A) connected to the second connection pin (314A') of the electronic device, at least one of the first and second terminals being connected to the electronic component (320).

15. Integrated circuit (30) according to claim 14, wherein the first and second terminals each comprise a connection pad (331B; 331A) on the side of a second face (101B) of the semiconductor substrate (101) opposite the first face (101A), the second connection pin (314A') of the electronic device also being on the side of the second face (101B).

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