SWITCHING POWER SUPPLY OF THE STEP-DOWN TYPE

Abstract

Step-down switching power supply This description relates to a step-down switching power supply (100) comprising: - a switching cell (101) including a first switch (102, 104) configured to be periodically switched on by a first control signal modulated by pulse-width modulation or pulse-frequency modulation; - an amplifier (114) configured to generate an error voltage representing a difference between a reference voltage and an output voltage of the power supply intended to be applied to the input of the amplifier (114); - a delay circuit (126) configured to apply a delay to the first control signal reducing a difference between the error voltage and the reference voltage;- a delay modulation circuit (130) configured to modulate the delay value according to a difference between the error voltage and the reference voltage. Figure for the abbreviation: Fig. 1;

Description

Title of the invention: SWITCHING POWER SUPPLY OF THE STEP-DOWN TYPE technical field

[0001] This description relates generally to the field of switched-mode power supplies (SMPS), in particular to DC-DC converters, and more particularly to step-down switching power supplies (also called Buck converters, or series choppers). Previous technique

[0002] A step-down switching power supply generally comprises a switching cell including a first transistor, referred to as the "high side," and a second transistor, referred to as the "low side," connected in series between an input electrical potential and ground. The first and second transistors, of complementary types (one n-type and the other p-type), are alternately switched on and off in a complementary manner (one is on while the other is off) by complementary first and second control signals applied to their gates. An LC low-pass filter is coupled to the connection node of this cell, that is, to the connection point to which the two transistors are coupled. The output voltage of the power supply is obtained across the filter capacitor.

[0003] The control signals applied to the transistors are modulated either by pulse width modulation (PWM) or by pulse frequency modulation (PFM). The level of the resulting output voltage depends on the duration of the transistors' on and off states during a period of the control signals. The modulation parameters of these control signals define the power supply conversion ratio.

[0004] When a large load is connected to the output of the power supply, a significant output current is required. In this case, the power supply operates with PWM-modulated control signals for the switching cell transistors, and the frequency of these control signals is fixed. The power supply includes a circuit that generates an error voltage whose value depends on the difference between the output voltage and a reference voltage corresponding to the target output voltage, and another circuit that generates a ramp voltage that increases from zero and, upon reaching the error voltage value, defines the duration of a first state of the control signals during which the switching cell charges the capacitor coupled to the connection node of the switching cell.

[0005] When a small load is coupled to the output of the power supply, a low output current is required. The power supply then operates with PFM-type modulated control signals for the switching cell transistors.

[0006] In such a switching power supply, the output voltage of the power supply fluctuates strongly during a change in the modulation of the control signals (switching between PWM and PFM modulations) if, at the time of this change, the error voltage and the reference voltage are not equal.

[0007] To avoid this problem, EP 3 644 486 A1 proposes introducing a delay that modifies the error voltage value to reduce the difference between the error voltage and the reference voltage. This delay is defined as equal to the comparator propagation time of the error voltage with the ramp voltage. This delay forces the power supply regulation loop to artificially increase the error voltage to obtain the same duty cycle, allowing the error voltage to approach the reference voltage and thus improving the transitions between PWM and PFM modulations.

[0008] One drawback of the solution proposed in the document mentioned above is that the maximum value of the duty cycle obtained for PWM modulation is limited by the introduction of this delay, which can lead to limited power supply performance. Summary of the invention

[0009] There is a need to propose a solution that does not present at least some of the disadvantages of existing solutions.

[0010] One embodiment overcomes all or part of the drawbacks of known solutions and proposes a step-down type switched-mode power supply comprising at least:

[0011] - a switching cell comprising at least a first switch configured to be periodically switched on by a first control signal modulated by pulse width modulation, PWM, or pulse frequency modulation, PFM;

[0012] - an amplifier configured to generate an error voltage representative of a difference between a reference voltage and a power supply output voltage intended to be applied to the amplifier input;

[0013] - a delay circuit configured to apply to the first control signal a delay reducing a difference between the error voltage and the reference voltage;

[0014] - a delay modulation circuit configured to modulate the delay value in function of a difference between the error voltage and the reference voltage.

[0015] According to a particular embodiment, the delay modulation circuit is configured to deliver at output a current or a voltage whose value is proportional to the difference between the error voltage and the reference voltage.

[0016] According to a particular embodiment, the delay modulation circuit is configured to reduce the delay value proportionally to the value of the difference between the error voltage and the reference voltage.

[0017] According to a particular embodiment, the delay modulation circuit includes at least one differential amplifier comprising a non-inverting input configured to receive the error voltage and an inverting input configured to receive the reference voltage.

[0018] According to a particular embodiment, the switching cell includes at least one second switch configured to be periodically put into the on state by a second control signal modulated by a PWM or PFM type modulation, in a manner complementary to the first switch.

[0019] According to a particular embodiment, the switching power supply further comprises at least one inductive element including a first electrode coupled to a connection node of the switching cell, and at least one capacitive element coupled to a second electrode of the inductive element and across whose terminals the output voltage of the power supply is intended to be obtained.

[0020] According to a particular embodiment, the switching power supply further comprises at least one comparator configured to receive as input the error voltage and a periodic increasing voltage ramp during a period of the first control signal.

[0021] According to a particular embodiment, the switching power supply further comprises at least one control signal generation circuit configured to generate at least the first control signal from the comparator output signal and an output signal from the delay circuit.

[0022] According to a particular embodiment, the switching power supply further comprises a voltage ramp generation circuit configured to generate the ramp voltage and whose output is coupled to a non-inverting input of the comparator.

[0023] According to a particular embodiment, the switching power supply further comprises a periodic signal generation circuit configured to deliver to the input of the delay circuit and the voltage ramp generation circuit a periodic signal with a frequency equal to a frequency of the first control signal.

[0024] According to a particular embodiment, the delay circuit comprises at least:

[0025] - a CMOS inverter configured to receive as input the periodic signal delivered by the periodic signal generation circuit;

[0026] - a capacitor coupled to an output terminal of the inverter;

[0027] - a Schmitt flip-flop comprising an input coupled to the output terminal of the inverter and one of whose outputs forms an output of the delay circuit;

[0028] - a MOS transistor configured to deliver an output current of maximum value lower than that of the inverter transistors, and coupled in series with one of the inverter transistors;

[0029] - a current source configured to draw power from a connection node between the MOS transistor and the inverter, the current whose value is proportional to the difference between the error voltage and the reference voltage.

[0030] A method for converting an input voltage into an output voltage whose value is lower than that of the input voltage is also proposed, comprising at least:

[0031] - control of at least one switching cell comprising at least one first switch periodically put into the on state by a first control signal modulated by a modulation of the type pulse width modulation, PWM, or pulse frequency modulation, PFM;

[0032] - generation of an error voltage representative of a difference between a voltage reference and output voltage of the power supply;

[0033] - generation of a delay reducing a difference between the error voltage and the voltage of reference ;

[0034] - modulation of the delay value as a function of a difference between the voltage error and reference voltage;

[0035] - application of the modulated delay on the first control signal.

[0036] According to a particular embodiment, the modulation of the delay value involves the generation of a current or a voltage whose value is proportional to the difference between the error voltage and the reference voltage. Brief description of the drawings

[0037] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0038] - Figure 1 schematically represents a switched-mode power supply of particular realization;

[0039] - Figure 2 schematically represents an example of the implementation of a circuit voltage ramp generation of a switched-mode power supply according to a particular embodiment;

[0040] - Figure 3 schematically represents an example of the implementation of a circuit delay of a switched-mode power supply according to a particular embodiment;

[0041] - Figure 4 schematically represents an example of the implementation of a circuit modulation of delay of a switched-mode power supply according to a particular embodiment;

[0042] - Figure 5 represents an example of the output current of a modulation circuit delay of a switched-mode power supply according to an embodiment;

[0043] - Fig. 6 shows examples of signals obtained in a power supply cutting according to a particular method of execution. Description of the implementation methods

[0044] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0045] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the implementation of the various elements and components of the switched-mode power supply is not detailed. A person skilled in the art will be able to implement these elements in detail from the description given here.

[0046] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the term "coupled" is used here to denote electrical coupling between several electrical and / or electronic elements (components, circuits, etc.).

[0047] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "in the order of" mean to the nearest 10%, preferably to the nearest 5%. Similarly, unless otherwise indicated, the ranges of values ​​shown include the bounds of those ranges.

[0048] A switched-mode power supply 100 according to a particular embodiment is described below with reference to [Fig. 1]. Only some of the elements, circuits and components of the power supply 100 are described below and shown in [Fig. 1], the power supply 100 being able to include other electrical or electronic elements, circuits and components.

[0049] The power supply 100 corresponds to a switching power supply of the step-down type, i.e. to a Buck converter.

[0050] In the example described in [Fig.1], the power supply 100 includes a switching cell 101 comprising a first power transistor 102 and a second power transistor 104. The two transistors 102, 104 are of opposite types, one of type n and the other of type p. In the example of [Fig.1], the first transistor 102 corresponds to a PMOS transistor and the second transistor 104 corresponds to an NMOS transistor.

[0051] Alternatively, the switching cell 101 may include switches other than MOS transistors (IGBT, bipolar transistor, etc.). In addition, one of the two switches of the switching cell 101 may be replaced by a diode.

[0052] Transistors 102 and 104 are coupled in series between an electrical input potential of the power supply 100 and ground, forming an input voltage V1N applied to the terminals of the switching cell 101.

[0053] In the described embodiment, first and second control signals are intended to be applied to the gates of transistors 102 and 104 (first control signal intended to be applied to the gate of the first transistor 102, and second control signal intended to be applied to the gate of the second transistor 104), thereby controlling the switching of cell 101. During operation of the power supply 100, transistors 102 and 104 are intended to be in complementary states (one of the two transistors 102 and 104 is conducting, the other of the two transistors 102 and 104 is blocked) when controlled by control signals modulated by PWM modulation. When using PFM modulation, both transistors 102 and 104 may be in the blocked state.

[0054] On the example of [Fig.1], the power supply 100 further comprises an inductive element 106, including for example an inductance, having a first electrode coupled to a connection node 108 of the switching cell 101 (node ​​to which the two transistors 102, 104 are coupled), and a second electrode coupled to an output terminal 110 of the power supply 100 on which an output current of the power supply 100 is intended to be obtained.

[0055] Following the example of [Fig. 1], the power supply 100 further comprises a capacitive element 112, including, for example, a capacitor, coupled between the output terminal 110 and ground, and across which an output voltage VOut is intended to be obtained. The capacitive element 112 forms, with the inductive element 106, a low-pass filter.

[0056] In the particular embodiment described, the power supply 100 also includes an amplifier 114 configured to generate an error voltage VERR representative of a difference between a reference voltage VRu and the output voltage VOut- In In this example, amplifier 114 includes an integrator with a correction function to stabilize the power supply regulation loop 100. In the example of [Fig. 1], the reference voltage VRu is intended to be applied to a non-inverting input of amplifier 114, and the output voltage VOut is intended to be applied to an inverting input of amplifier 114. The error voltage VERR obtained at the output of amplifier 114 corresponds to a DC voltage centered on the reference voltage, lower than the reference voltage VRu when the value of the reference voltage VRu is lower than that of the output voltage VOut, and higher than the reference voltage VREf when the value of the reference voltage VREE is greater than that of the output voltage VOut.

[0057] The value of the reference voltage VRu intended to be applied to the input of Amplifier 114 is chosen here to be equal to the target value of the output voltage VOut. For example, the input voltage Vin can be equal to 3 V, and the output voltage VOut (and therefore also the reference voltage Vj^f) can be equal to 1 V. In this example, the conversion ratio of power supply 100 is 1 / 3.

[0058] As shown in [Fig. 1], the power supply 100 also includes a comparator 116 comprising an inverting input coupled to the output of the amplifier 114, i.e., to which the error voltage VERR is intended to be applied, and a non-inverting input to which a periodic voltage ramp Vkamp, ​​obtained at the output of a voltage ramp generation circuit 118, is intended to be applied. The voltage obtained at the output of the comparator 116 corresponds to a square wave signal having a first value (corresponding to a low state in the example of [Fig. 1]) when the value of the periodic voltage ramp is less than the error voltage VERR, and a second value (corresponding to a high state in the example of [Fig. 1]) when the value of the periodic voltage ramp Vkamp becomes greater than the error voltage VERR.

[0059] The duration of the low state of the comparator 116 output signal therefore corresponds to the time during which the value of the periodic voltage ramp increases until it reaches the value of the error voltage VERR. However, since the error voltage VERR is generated as a function of the difference between the reference voltage VREE and the output voltage VOut, this duration of the low state of the comparator 116 output signal also depends on the difference in value between the reference voltage VRu and the output voltage VOut. The output signal of comparator 116 is therefore a periodic square wave whose duty cycle depends on the difference between the reference voltage VREE and the output voltage VOut.

[0060] An example of an embodiment of the periodic voltage ramp generation circuit 118 is described below in relation to [Fig.2].

[0061] In this example, circuit 118 includes a transistor 120 (an NMOS transistor in the example of [Fig. 2]). A ramp control signal VClk, corresponding here to a square wave signal, is applied to the gate of transistor 120. Circuit 118 also includes a current source 122 coupled between a supply voltage potential VCC and the drain of transistor 120 and configured to deliver a bias current Ip. Circuit 118 also includes a capacitor 124, intended to be charged by the bias current Ip and coupled between the drain of transistor 120 and ground. The periodic voltage ramp Vramp is intended to be obtained across capacitor 124.

[0062] In the example embodiment of circuit 118 shown in [Fig. 2], when the ramp control signal VClk is in a low state ("0"), putting transistor 120 in the off state, the bias current Ip delivered by the current source 122 charges capacitor 124, and the value of Vramp then increases linearly. When the ramp control signal goes into a high state ("1"), putting transistor 120 in the on state, the value of the periodic voltage ramp Vramp falls back to zero. The period of the ramp control signal is equal to the period of the control signals intended to be applied to the gates of transistors 102, 104.

[0063] Other embodiments of the voltage ramp generation circuit 118 are possible.

[0064] The power supply 100 also includes a delay circuit 126 configured to introduce, in the control signals intended to be applied to the gates of the transistors 102, 104 of the cell 101, a delay reducing a difference between the error voltage VERR and the reference voltage VreF, when these control signals are modulated by a PWM modulation to facilitate the transition from one to the other of the PWM and PFM modulations of the control signals.

[0065] As shown in [Fig. 1], a delayed clock signal is output from the delay circuit 126 and applied to the input of a control signal generation circuit 128. The circuit 128 is configured to generate, from the signal output from the comparator 116 and the delayed clock signal output from the delay circuit 126, the first and second control signals to be applied to the gates of transistors 102 and 104 in cell 101. For example, the first and second control signals are such that the first transistor 102 turns on and the second transistor 104 is off on the rising edge of the delayed clock signal. Then, when the delayed clock signal changes state and has a falling edge, the second transistor 104 turns on and the first transistor 102 is off.

[0066] The control circuit 128 includes, for example, a digital controller, for example of the finite state machine type ("Finite State Machine" in English, or FSM). Alternatively, when the switching cell 101 has only one switch, the circuit 128 can be configured to output only one control signal.

[0067] The power supply 100 also includes a delay modulation circuit 130 configured to modulate the value of the delay signal defined in the delayed clock signal delivered by the delay circuit 126 according to the difference between the error voltage VERR and the reference voltage VREE. In the embodiment shown in [Fig. 1], the delay modulation circuit 130 includes a differential amplifier comprising a non-inverting input to which the error voltage VERR is intended to be applied, and an inverting input to which the reference voltage VRu is intended to be applied. In this example, a current called ladd, the value of which is proportional to the difference between the value of the error voltage VERR and that of the reference voltage VRu, is obtained at the output of the delay modulation circuit 130.Alternatively, the delay modulation circuit 130 could output a voltage whose value is proportional to the difference between the value of the error voltage VERR and that of the reference voltage Vj^p. .

[0068] In the described embodiment, the power supply 100 further includes a periodic square wave generation circuit 132 configured to deliver at output a periodic square wave corresponding to the ramp control signal VClk- In the example of [Fig.1], the ramp control signal VClk is also applied at input of the delay circuit 126.

[0069] In the power supply 100, the different paths taken by the various signals and voltages result in a time lag between the error voltage VERR and the reference voltage VREE. In the described embodiment, this lag is due in particular to the comparator 116, which is composed of several transistors and generates a relatively long processing time compared to the period of the periodic square wave VClk-H. Therefore, there is a certain signal propagation time between the input and output of the comparator 116.

[0070] To overcome this drawback, the delay circuit 126 is configured to output a clock signal delayed by a delay whose value is between the signal propagation time in comparator 116 and zero, depending on the delay modulation applied by the delay modulation circuit 130. In the example described, the delay modulation circuit 130 is configured to reduce the delay value proportionally to the difference between the error voltage VERR and the reference voltage Vj^p, and such that the delay value is maximum when the error voltage VERR is less than the reference voltage Vj^p. reference voltage Vref. The delay value is reduced and tends towards zero when the error voltage value VERR is equal to the reference voltage VREE.

[0071] For example, the value of the signal propagation time in comparator 116 can be evaluated during a calibration phase of the power supply 100. The delay circuit 126 can then be configured so as to apply by default a delay equal to the value of the signal propagation time in comparator 116, and the delay modulation circuit 130 then applies to this delay a coefficient whose value can be between 0 and 1.

[0072] Fig. 3 schematically illustrates an example of an embodiment of the delay circuit 126.

[0073] In this example, the delay circuit 126 includes an inverter 134 formed here by a PMOS transistor and an NMOS transistor connected in series between the supply voltage VCC and ground. The gates of the transistors in the inverter 134 are coupled together to form an input terminal of the delay circuit 126 to which the ramp control signal VClk is applied. Furthermore, a node 136 to which the transistors of the inverter 134 are coupled forms an output terminal of the inverter 134.

[0074] As shown in [Fig. 3], the delay circuit 126 further includes a Schmitt trigger 138 whose input is coupled to node 136 and whose output forms the output of the delay circuit 126, to which the delayed clock signal is delivered. In addition, in this example, the delay circuit 126 includes a capacitor 140 coupled between node 136 and ground (GND).

[0075] The delay circuit 126 also includes a second transistor 141, here of the NMOS type, comprising an active region smaller than that of the inverter's NMOS transistor 134. In the example of [Fig. 3], this second transistor 141 is connected in series with the inverter's NMOS transistor 134. The delay circuit 126 also includes a current source 143 that draws the ladd current, the value of which is proportional to the difference between the error voltage VERR and the reference voltage VREE. This current source 143 corresponds, for example, to a transistor controlled to draw the ladd current. In this example, if VClk is high, the capacitor 140 discharges through the inverter's NMOS transistor 134 and the second transistor 141. Since the second transistor 141 is small, the discharge of the capacitor 140 is slow, which creates a delay.The ladd current is added to the current of transistor 141 to accelerate the discharge of capacitor 140 through the NMOS transistors of inverter 134. If the value of the error voltage VERR is equal to or close to that of the reference voltage VREE, the resulting delay is then maximal because Ldd is equal to or close to 0. If the value of the error voltage VERR is . much higher than that of the reference voltage VREF, the current Iadd is significant and the delay obtained is reduced given the acceleration of the discharge of the capacitance 140.

[0076] Other embodiments of the delay circuit 126 are possible. For example, the delay circuit 126 may have a structure similar to that of the comparator 116 so as to reproduce the propagation time of the signals in that comparator.

[0077] An example of the realization of a 130 delay modulation circuit is shown schematically in [Fig.4].

[0078] In [Fig. 4], the delay modulation circuit 130 includes a differential pair 142, formed here by two CMOS transistors, onto which the voltages VrEF and VERr are applied across the transistor gates. The delay modulation circuit 130 shown in [Fig. 4] further includes current mirrors 144, 146, and 148, also made of CMOS transistors. In this example, the higher the error voltage VERr is relative to the reference voltage VREf, the more current the PMOS transistor 146.2 of the current mirror 146 supplies and the less current the NMOS transistor 148.2 consumes. The delay modulation circuit 130 also includes another MOS transistor 150 coupled to the NMOS transistor 148.2 of the current mirror 148. The difference in current between that supplied by the PMOS transistor 146.2 and that consumed by the NMOS transistor 148.2 corresponds to the current Ldd flowing through transistor 150 and is the current used to modulate the delay value according to the difference between the error voltage and the reference voltage. Figure 5 schematically represents the current Iadd obtained with such a delay modulation circuit 130. In this example, the value of the current Iadd increases linearly proportionally to the value of the difference VErr - Vref.

[0079] Fig. 6 shows examples of signals obtained in the power supply 100 with a large load current (scheme b) and with a low or zero load current (scheme a).

[0080] In diagram a) of [Fig. 6], reference numeral 200 designates the voltage ramp VRAmp obtained at the output of circuit 118, reference numeral 202 designates the value of the error voltage VErr in the case of PWM modulation and that of the reference voltage Vref in the case of PFM modulation, and reference numeral 204 designates the current flowing through the inductive element 106. In diagram a), it is assumed that the power supply 100 provides very little current at the output or that the supply voltage VIX is high. Thus, a first delay 206 occurs between the moment when the voltage ramp Vramp exceeds the value of the error voltage VErr and the moment when the value of the current 204 stops increasing and begins to decrease, and a second delay 207 occurs between the clock signal going high, resetting the ramp The voltage Vramp drops to zero and the current value 204 stops decreasing and increases again. The first delay 206 is mainly due to the response time of comparator 116, and the second delay 207 is due to the delay introduced by the delay circuit 126.

[0081] In diagram b) of [Fig.6], the power supply 100 provides a significant output current or has a supply voltage Vin close to the output voltage VOut- The value of the error voltage VERR is therefore greater than that shown in diagram a). In this diagram b), the first delay 206 is found between the moment when the voltage ramp VRAMp exceeds the value of the error voltage VERR and the moment when the value of the current 204 stops increasing and starts decreasing, but the second delay 207 observed in diagram a) is not found.

[0082] In the particular embodiment described, the power supply 100 operates in closed loop and allows, if necessary, a significant duty cycle value of one or more control signals of the switch(es) of the switching cell so as to make the output voltage VOut equal to the reference voltage VREE, regardless of the value of the input voltage Vin.

[0083] Furthermore, in the described embodiment, the power supply 100 is configured to generate a voltage ramp Vkamp controlled by a periodic square wave signal. This voltage ramp VRAmp is compared with the error voltage VERR, and the control signal(s) sent to the switching cell 101 are generated from this comparison so as to make the output voltage VOut equal to the reference voltage VREE.

[0084] However, due to the intrinsic propagation delay of the signals, particularly within comparator 116, the duty cycle obtained at the output of comparator 116 is higher than that theoretically obtained, and corresponds to the rise time of the voltage ramp VRAmp from the error voltage VERR. The error voltage VERR tends to decrease so that the voltage ramp VRAMp reaches the value of the error voltage VERR sooner than in the ideal case of a power supply with no intrinsic propagation delay, in order to compensate for this delay.

[0085] Without correction induced by the generated delay, the power supply regulation loop 100 would tend to reduce the error voltage VERR to reach the value of the duty cycle necessary for the regulation of the output voltage VOut- H there is therefore a difference between the error voltage VERR and the reference voltage VREE depending in particular on the input voltage VIN.

[0086] Applying the delay to the control signal(s) of the switching cell 101 when the power supply 100 is applied advantageously allows the voltage ramp generation to start before the switch is turned on or one of the switches of cell 101 by the control signal(s) so as to compensate for said propagation delay intrinsic to the circuits of the power supply 100 and reduce the difference between the error voltage VERR and the reference voltage VRu> and a decrease or even elimination of the influence of the input voltage V1N on the quality of the transitions between the PWM and PFM modulations. These transitions between the PWM and PFM modulations become more stable and result in fewer oscillations on the output voltage VOut-

[0087] In the proposed power supply 100, the delay applied to the control signal(s) of the switching cell 101 decreases with the value of the difference between the error voltage VERR and the reference voltage V^f, which allows for a large duty cycle of the control signal(s) if needed, and thus leads to better performance of the power supply 100, without impacting the bandwidth of the power supply 100.

[0088] Power supply 100 can for example be intended for the automotive industry, in particular for electric vehicles.

[0089] The power supply 100 can, for example, be used in the industrial sector, for example for the development of green energy or for the electrification of infrastructure, for example for charging stations or for the integration of solar energy. The device can also be used in the field of the Internet of Things and smart homes. The device is, for example, intended to be implemented in the power and energy circuits of equipment.

[0090] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0091] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A step-down switching power supply (100) comprising at least: - a switching cell (101) comprising at least a first switch (102, 104) configured to be periodically switched on by a first control signal modulated by pulse-width modulation (PWM) or pulse-frequency modulation (PFM); - an amplifier (114) configured to generate an error voltage representative of a difference between a reference voltage and an output voltage of the power supply (100) intended to be applied to the input of the amplifier (114); - a delay circuit (126) configured to apply a delay to the first control signal reducing a difference between the error voltage and the reference voltage;- a delay modulation circuit (130) configured to modulate the delay value according to a difference between the error voltage and the reference voltage.;

2. Switching power supply (100) according to claim 1, wherein the delay modulation circuit (130) is configured to deliver at output a current or voltage whose value is proportional to the difference between the error voltage and the reference voltage.

3. Switching power supply (100) according to any one of the preceding claims, wherein the delay modulation circuit (130) is configured to reduce the delay value proportionally to the value of the difference between the error voltage and the reference voltage.

4. Switching power supply (100) according to any one of the preceding claims, wherein the delay modulation circuit (130) comprises at least one differential amplifier including a non-inverting input configured to receive the error voltage and an inverting input configured to receive the reference voltage.

5. Switching power supply (100) according to any one of the preceding claims, wherein the switching cell includes at least one second switch (102, 104) configured to be periodically switched on by a second control signal modulated by PWM or PFM type modulation, in a complementary manner to the first switch (102, 104).

6. Switching power supply (100) according to any one of the preceding claims, further comprising at least one inductive element (106) comprising a first electrode coupled to a connection node (108) of the switching cell (101), and at least one capacitive element (112) coupled to a second electrode of the inductive element (106) and across which the output voltage of the power supply (100) is intended to be obtained.

7. Switching power supply (100) according to any one of the preceding claims, further comprising at least one comparator (116) configured to receive as input the error voltage and a periodic increasing voltage ramp during a period of the first control signal.

8. Switching power supply (100) according to claim 7, further comprising at least one control signal generation circuit (128) configured to generate at least the first control signal from the output signal of the comparator (116) and an output signal of the delay circuit (126).

9. Switching power supply (100) according to claim 7 or 8, further comprising a voltage ramp generation circuit (118) configured to generate the ramp voltage and whose output is coupled to a non-inverting input of the comparator (116).

10. Switching power supply (100) according to any one of claims 7 to 9, further comprising a periodic signal generation circuit (132) configured to deliver to the input of the delay circuit (126) and the voltage ramp generation circuit (118) a periodic signal of frequency equal to a frequency of the first control signal.

11. Switching power supply (100) according to claims 2 and 10, wherein the delay circuit (126) comprises at least: - a CMOS inverter (134) configured to receive as input the periodic signal delivered by the periodic signal generation circuit (132);

12.

13. - a capacitor (140) coupled to an output terminal of the inverter (134); - a Schmitt flip-flop (138) comprising an input coupled to the output terminal of the inverter (134) and whose output forms an output of the delay circuit (126); - a MOS transistor (141) configured to deliver at output a maximum current value lower than that of the inverter transistors (134), and coupled in series with one of the inverter transistors (134); - a current source (143) configured to draw, from a connection node between the MOS transistor (141) and the inverter (134), the current whose value is proportional to the difference between the error voltage and the reference voltage. A method for converting an input voltage into an output voltage lower than the input voltage, comprising at least: - control of at least one switching cell (101) comprising at least one first switch (102, 104) periodically put into the conducting state by a first control signal modulated by a modulation of the type pulse width modulation, PWM, or pulse frequency modulation, PFM; - generation of an error voltage representative of a difference between a reference voltage and an output voltage of the power supply (100); - generation of a delay reducing a difference between the error voltage and the reference voltage; - modulation of the delay value as a function of a difference between the error voltage and the reference voltage; - application of the modulated delay on the first control signal. Conversion method according to claim 12, wherein the modulation of the delay value involves the generation of a current or voltage whose value is proportional to the difference between the error voltage and the reference voltage.

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