Manufacturing process for vertical GaN-based transistors

Abstract

Title: Method for manufacturing vertical GaN-based transistors. The invention relates to a method for manufacturing at least one vertical transistor (1a, 1b). First, a substrate (10) having a top face (11) is provided. Localized GaN epitaxy is performed on the substrate to form at least one island (100a, 100b). Then, at each island, at least one electrically conductive motif, called a gate (200), and at least one electrically conductive contact, called a source contact (300), are formed. The substrate (10) is removed, and then an electrically conductive layer (400) forming a drain (400) is formed against the bottom face (102a, 102b) of at least one island, thus forming at least one vertical transistor (1a, 1b). Figure for the abstract: Fig. 1F

Description

Title of the invention: Method for manufacturing vertical GaN-based transistors technical field

[0001] The present invention relates to the field of microelectronic devices, in particular GaN-based components. It finds, for example, a particularly advantageous application in the field of power electronics. STATE OF THE ART

[0002] There are many transistor architectures, including vertical transistors. The properties of these transistors are particularly exploited today in power electronics applications.

[0003] Vertical GaN-based transistors are typically fabricated by epitaxy from GaN substrates. However, commercially available GaN substrates are small in diameter. Current processes for manufacturing vertical GaN transistors on GaN substrates therefore do not allow for the simultaneous production of a quantity of transistors comparable to that achieved on larger diameter substrates (typically silicon substrates). These processes are also very expensive due to the high cost of GaN substrates.

[0004] One objective of the present invention is therefore to propose a method for manufacturing vertical GaN-based transistors that solves at least some of the problems mentioned above. SUMMARY

[0005] To achieve this objective, according to one embodiment, a manufacturing process for at least one vertical transistor is provided, comprising the following steps: - provide a substrate with a top surface, typically a silicon substrate, - to carry out localized epitaxy of gallium nitride (GaN) on the upper face of the substrate, so as to form at least one GaN-based island, each island comprising a first layer based on GaN doped with a first type taken from an n-type doping and a p-type doping, and a second layer based on GaN doped with the other type directly overlying the first layer, each island having a face, called the lower face, facing the upper face of the substrate, - at the level of each island, form at least one electrically conductive pattern called a grid in contact with the first layer and with the second layer, and at least one electrically conductive contact, called the source contact, in contact with the second layer, - to form an electrically conductive layer forming a drain, the drain being electrically connected to the underside of each island, thus forming at least one vertical transistor.

[0006] Thus, the process according to the invention makes it possible to initiate the formation of transistors on a large and inexpensive substrate, such as a silicon substrate. This avoids the need for a costly and small GaN substrate. The gate and source contact formation steps can be carried out while the islands are resting on the substrate, or after the substrate has been removed. Back-side drain formation simply requires prior removal of the substrate by grinding and / or CMP and / or etching, or by creating metallic interconnects within the substrate, which is perfectly reasonable in the case of a silicon substrate. This results in fully vertical GaN transistors without having to sacrifice a GaN substrate.

[0007] Local epitaxy of GaN can also allow the formation of islands up to 10 pm or even 20 pm in height. Thanks to this, the transistors formed by the process can withstand voltages as high as 1200V or even 2200V.

[0008] Furthermore, the process makes it possible to efficiently manufacture vertical transistors with a very high substrate coverage rate. For hexagonal islands, for example, the surface area lost due to gaps between islands is between 5 and 10% of the total surface area, which is very low.

[0009] Thus, the process according to the invention allows for efficient, large-scale, and inexpensive manufacturing of vertical GaN-based transistors. The manufactured transistors are also very compact and robust. BRIEF DESCRIPTION OF THE FIGURES

[0010] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0011] [Fig. 1 A] Figures 1A to 1F illustrate a first embodiment of the process according to the invention, in which the transistor gates are formed in the GaN islands.

[0012] [Fig.1B]

[0013] [Fig.1C]

[0014] [Fig.1D]

[0015] [Fig.1E] Figures 1E and 1F illustrate an example in which the substrate is removed and the drain is formed in direct contact with the islands.

[0016] [Fig.1F]

[0017] [Fig.1G] Figures IG and 1H illustrate an example in which metallic interconnections are formed in the substrate and the drain is formed at the contact of these interconnections.

[0018] [Fig.1H]

[0019] [Fig.2A] Figures 2A to 2F illustrate a second embodiment of the process according to the invention, in which the transistor gates are formed in the GaN islands.

[0020] [Fig.2B]

[0021] [Fig.2C]

[0022] [Fig.2D]

[0023] [Fig.2E]

[0024] [Fig.2F]

[0025] [Fig.3A] Figures 3A to 3D illustrate a third embodiment of the process according to the invention, in which the transistor gates are formed against the GaN islands.

[0026] [Fig.3B]

[0027] [Fig.3C]

[0028] [Fig.3D]

[0029] [Fig.4A] Figures 4A to 4C are scanning electron microscopy (SEM) images of GaN islands grown by localized epitaxy.

[0030] [Fig.4B] [Fig.4B] is an enlargement of [Fig.4A].

[0031] [Fig.4C] [Fig.4C] is an enlargement of [Fig.4B].

[0032] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0033] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0034] According to an advantageous example, the substrate is silicon-based. Silicon substrates are indeed inexpensive and are very well suited to localized GaN epitaxy.

[0035] According to a preferred example, each island has a height hiOo greater than or equal to 10 pm, preferably greater than or equal to 20 pm, hi00 being measured in a direction perpendicular to a plane in which the upper face of the substrate extends mainly.

[0036] According to one embodiment, the drain formation step comprises the following steps: - after forming at least one island, remove the substrate, then - form the drain against the underside of at least one island.

[0037] According to one embodiment, the drain formation step comprises the following steps: - for each island, form at least one metallic interconnection passing through the substrate and opening onto said island, - form the drain against an underside of the substrate opposite its upper side, the drain being in contact with at least one metallic interconnection.

[0038] According to an advantageous embodiment, the formation of at least one grid comprises the following steps: - to engrave at least one opening extending from the upper face of at least one island, the opening passing entirely through the second layer and at least partially through the first layer, - form at least one grid in at least one opening.

[0039] Due to the positioning of the gate (or gates) at the top face of the islands, this embodiment allows a high density of transistors.

[0040] According to an advantageous embodiment, the epitaxial step comprises the following step: epitaxially forming the first and second layers through a mask, so as to define at least one aperture extending from an upper face of at least one island, the aperture passing through the second layer and at least partially through the first layer, and at least one gate is formed in said at least one aperture. This embodiment does not require etching the GaN island(s) to form the gate(s), thus avoiding the introduction of charges into the islands. These charges are detrimental to the proper functioning of the transistors because they can cause hysteresis during switching. Furthermore, due to the positioning of the gate(s) at the upper face of the islands, this embodiment allows for a high transistor density.

[0041] According to a preferred example, a plurality of gates is formed at the contact of the first and second layers of the same island. The presence of a plurality of gates makes it possible to increase the power of the resulting transistor.

[0042] According to a preferred example, a plurality of source contacts is formed in contact with the second layer and, in projection into a plane in which the upper face of the substrate extends mainly, the grids and the source contacts are found alternately.

[0043] According to an advantageous embodiment, at least two islands and two transistors are formed, and the gate formed at the level of the first island and that formed at the level of the second island are in electrical continuity and form a common gate for the two transistors.

[0044] According to one example, the gate common to the two transistors extends between a lateral edge of the first island and a lateral edge of the second island. This embodiment does not require etching the GaN island(s) to form the gate(s), thus avoiding the introduction of charges into the islands. These charges are detrimental to the proper functioning of the transistors because they can cause hysteresis during switching.

[0045] According to one example, the drain is copper-based. The properties of copper make it possible to give the transistor(s) optimal thermal and electrical performance.

[0046] According to an advantageous example, the substrate removal step is performed before the formation of the gate and at least one source contact at each island, and possibly before the formation of the first and second layers. Removing the substrate at the beginning of the process reduces stress in the different layers, particularly in the GaN islands, during the process. This limits the number of structural defects in the stack and thus improves transistor performance.

[0047] According to an alternative example, the substrate removal step is carried out after the formation of the grid and at least one source contact at the level of each island.

[0048] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0049] A layer may also be composed of several sub-layers of the same material or of different materials.

[0050] A substrate, layer, or device "based" on a material M means a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example alloying elements, impurities, or dopant elements.

[0051] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio between the etching speed of material A to the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0052] Two elements are said to be "electrically connected" when they are each in contact with the same continuous electrical connection element having an electrical conductivity preferably greater than 107 S / m.

[0053] A coordinate system, preferably orthonormal, comprising the X, Y, Z axes is shown in [Fig. 1A]. This coordinate system is applicable by extension to the other figures. The Z direction may be designated as the "stacking direction".

[0054] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the longitudinal plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along Z when it extends mainly along the longitudinal plane XY, and a projecting element, for example an insulation trench, has a height along Z. The relative terms "on," "under," "above," "below," and "underlying" preferentially refer to positions measured along the Z direction.

[0055] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0056] A first embodiment of the process according to the invention will now be described with reference to figures IA to 1F. These figures illustrate the simultaneous formation of two transistors 1a, 1b, but it is understood that a larger number of transistors can be manufactured simultaneously by the process according to the invention.

[0057] Figure 1A illustrates the provision of a substrate 10. This substrate 10 is typically silicon-based. It has a top face 11 extending mainly in an XY plane, which can be designated the longitudinal XY plane. This plane is defined by a first direction X and a second direction Y. The substrate 10 further has a bottom face 12 opposite its top face 11.

[0058] Advantageously, buffer layers 15 are deposited on the upper face 11 of the substrate 10. These buffer layers 15 can, for example, each be based on one of the following materials: AIN, AlGaN, BN.

[0059] As illustrated in [Fig. 1B], GaN-based islands 100a, 100b are then locally grown by epitaxy on the upper face 11 of the substrate 10. Typically, these islands 100a, 100b are grown from buffer layers 15. [Fig. 4A] illustrates the experimental result of this step: it is a top view obtained by SEM of a set of islands grown by localized epitaxy on a silicon substrate. One can In particular, one can appreciate in this image that a large number of islets can be grown simultaneously by localized epitaxy.

[0060] The islands 100a, 100b are separated from each other. Thus, preferably, no continuous residual layer of GaN is found on the upper face 11 of the substrate 10 (with the exception of possible buffer layers which may include GaN).

[0061] The islands 100a, 100b each have a lower face 102a, 102b which is opposite the upper face 11 of the substrate 10, and typically in contact with the buffer layers 15. They also each have an upper face 101a, 101b opposite the lower face 102a, 102b.

[0062] The epitaxy step of the GaN islands 100a, 100b is advantageously configured to form GaN layers within each island 100a, 100b having different doping levels. According to an advantageous example, the islands 100a, 100b comprise the following layers, from the lower faces 102a, 102b of the islands 100a, 100b to their upper faces 101a, 101b: an n+ doped GaN layer, an n- doped GaN layer, which can be designated as the migration or drift layer 130a, 130b, a p doped GaN layer, called the first layer 110a, 110b, and an n+ doped GaN layer, called the second layer 120a, 120b. According to an alternative example, the layer dopings are reversed and the first layer 110a, 110b is n+ doped and the second layer 120a, 120b is p doped.

[0063] In a perfectly classical way, the dopant of the n-doped layers can be silicon (Si) and the dopant of the p-doped layers magnesium (Mg).

[0064] The islands 100a, 100b have a characteristic dimension in the XY plane, denoted 100a. In projection onto the XY plane, the islands 100a, 100b typically each have a hexagonal shape, as can be seen in [Fig. 4A]. In this case, the characteristic dimension 100a corresponds to the distance between two facing sides of the islands 100a, 100b. In [Fig. 4B], 100a is, for example, measured along the first X direction. 100a is preferably greater than 100 pm, and preferably less than or equal to 200 pm.

[0065] The lateral sides 103a, 103b of the islands 100a, 100b are typically inclined with respect to the stacking direction Z, as illustrated in the figures, l^o is then measured at the base of the islands 100a, 100b, at the level of their lower face 102a, 102b.

[0066] The islands 100a, 100b have a height h00 measured along the Z direction (also designated the stacking direction Z) perpendicular to the longitudinal plane XY. The height h is preferably greater than 10 pm or even 20 pm. Furthermore, the first layer 110a, 110b and the second layer 120a, 120b have a thickness en0 and a thickness e0 respectively along the stacking direction. Z. Typically, en0 is between 200 nm and 1500 nm. Typically, ei20 is between 20 nm and 300 nm.

[0067] In the longitudinal XY plane, the islands 100a, 100b are separated by a distance D (taken along the first X direction in Figures 1B, 4B, and 4C). D is measured at the base of the islands 100a, 100b, that is, at the height along Z at which the lower faces 102a, 102b of the islands 100a, 100b are located. The distance D is typically greater than 5 pm. Preferably, the distance D is less than 20 pm, or even less than 15 pm, or even 10 pm. D is typically between 10 and 15 pm. This allows for the fabrication of transistors with a higher density. For example, it is approximately equal to 8 pm.

[0068] The numerical values ​​given above are also valid for the second and third embodiments which will be described further.

[0069] As also illustrated in [Fig.1B], the lateral sides 103a, 103b of the islands 100a, 100b are advantageously covered with a passivation layer 150. The passivation layer 150 is for example based on alumina or SiN.

[0070] The spaces left empty between the islands 100a, 100b are preferably filled by a filler layer 160 based on a dielectric material, for example, based on silica or tetraethyl orthosilicate (TEOS). The filler layer 160 can be deposited by subatomic chemical vapor deposition (commonly referred to as SACVD). Advantageously, this deposition is carried out using a low-stress method.

[0071] The deposition of the filling layer 160 can be followed by a planarization step at the level of the upper face 101a, 101b of the islands 100a, 100b.

[0072] An etching step is then performed starting from the upper faces 101a, 101b of the islands 100a, 100b. This etching step is configured to form at least one aperture 20, and preferably a plurality of apertures 20, in each island 100a, 100b. Each aperture 20 passes completely through the second layer 120a, 120b and at least partially, preferably completely, through the first layer 110a, 110b. As will become apparent later, the dimensions of the apertures 20 determine those of the gates 200 of the transistors 1a, 1b. The apertures 20, for example, have a width l20 along the first X direction, with l20 ranging from 100 nm to 4000 nm. According to the second direction Y, the openings 20 can completely traverse the islands 100a, 100b. According to an alternative embodiment, the openings 20 have a hexagonal shape when projected onto the transverse plane XY. l20 then typically corresponds to one side of the hexagon.

[0073] In a perfectly conventional manner, this etching step can be carried out by dry etching through a masking layer.

[0074] In a step illustrated in [Fig. 1D], electrically conductive patterns 200 are formed in the openings 20. These electrically conductive patterns form the gates 200 of the transistors that will be formed at the end of the process. The width l200 of the gates 200 is substantially equal to the width l20 of the openings 20.

[0075] Furthermore, electrically conductive contacts called source contacts 300 are also formed on the second layer 120a, 120b.

[0076] As illustrated in [Fig. 1E], the substrate 10 and any buffer layers 15 are then removed. This removal is typically carried out by grinding and chemical-mechanical polishing (CMP). Advantageously, a major part of the removal is carried out by grinding and CMP, and then the removal is finalized by selective etching or time etching to stop precisely on the lower face 102a, 102b of the islands 100a, 100b.

[0077] Advantageously, the removal of the substrate 10 and the buffer layers 15 occurs after the islands 100a, 100b have been transferred onto a handle-substrate (not shown). This transfer takes place on the upper face 101a, 101b side of the islands 100a, 100b. The handle-substrate is removed after the formation of the drain 400 described above.

[0078] The removal of the substrate 10 and the buffer layers 15 can also occur earlier in the process. The substrate 10 can indeed be removed after the formation of the islands 100a, 100b (and the optional formation of the passivation layer 150 and the filling layer 160), and before the formation of the grids 200 and source contacts 300, between the steps illustrated in Figures IB and IC or IC and 1D. This makes it possible to reduce the mechanical stresses within the stack during the formation of the grids 200 and the source contacts 300.

[0079] After the formation of the gates 200 and the source contacts 300, an electrically conductive layer called the drain 400 is formed at the contact of the lower faces 102a, 102b of the islands 100a, 100b. This drain 400 extends continuously under the islands 100a, 100b. It is thus common to all the transistors 1a, 1b. The formation of the drain 400 is typically carried out by electrochemical metal deposition.

[0080] According to an alternative embodiment illustrated in Figures 1G and 1H, rather than removing the substrate 10 and the buffer layers 15, metallic interconnections are made. Thus, as illustrated in [Fig. 1G], it is possible to create through-holes 13 by etching, extending completely through the substrate 10 and optionally the buffer layers 15. The through-holes 13 thus extend, in particular, from the upper face 11 to the lower face 12 of the support. At least one through-hole 13 is formed opposite each island 100a, 100b. The through-holes 13 are typically formed by a photolithography and etching process. The through-holes 13 are then filled with an electrically conductive material, typically a metal, so as to form metallic interconnections 14. also passing through the substrate 10 and the buffer layers 15. The drain 400 is then formed against the lower face 12 of the substrate 10 ([Fig.1H]). The drain 400 is formed in contact with at least one metallic interconnection 14, preferably with all the metallic interconnections 14. The metallic interconnections 14 provide the electrical connection between the drain 400 and the islands 100a, 100b.

[0081] The process thus makes it possible to form at least one transistor la, 1b, each formed of the following elements: - Drain 400, or at least a portion of drain 400, - An island 100a, 100b, comprising layers of GaN with distinct doping levels including the first layer 110a, 110b and the second layer 120a, 120b, - At least one 200 grid placed in contact with the first layer 110a, 110b and the second layer 120a, 120b of the island 100a, 100b considered, - At least one 300 source contact deposited on the second 120 layer.

[0082] The various stages of the process (formation of the openings 20 in the islands 100a, 100b, formation of the gates 200, formation of the source contacts 300) are preferably such that, in projection onto the longitudinal XY plane, the gates 200 and the source contacts 300 are found alternately. Typically, each transistor 1a, 1b formed comprises one more source contact 300 than gates 200.

[0083] The presence of a plurality of gates 200 and source contacts 300 within each transistor la, 1b increases their power. Advantageously, each transistor la, 1b comprises at least 3 gates 200, preferably at least 5 gates 200.

[0084] A second embodiment will now be described with reference to figures 2A to 2F.

[0085] The second embodiment can for example start like the first embodiment described above with the provision of a substrate 10 and advantageously buffer layers 15, as illustrated in [Fig.1A].

[0086] Next, the epitaxy of the islands 100a, 100b begins above the upper face 11 of substrate 10, but it is interrupted before the formation of the first layer 110a, 110b and the second layer 120a, 120b, as illustrated in [Fig. 2B]. At this stage, the islands 100a, 100b each have an intermediate face 104a, 104b opposite their lower faces 102a, 102b.

[0087] A hard mask 170 is then formed on the intermediate faces 104a, 104b of the islands 100a, 100b. The hard mask 170 has at least one opening 171, and preferably a plurality of openings 171, partially revealing the intermediate faces 104a, 104b of the islands 100a, 100b. As will become apparent later, the dimensions of the pattern defined by mask 170 determine the dimensions of the gates 200 of transistors 1a, 1b. The mask 170 may, for example, include bands extending between the apertures 171. These mask strips 170 have a width li70 ​​along the first X direction, preferably with li70 ​​between 100 nm and 4000 nm. The mask 170 may also include apertures with a hexagonal shape. The characteristic dimension li70 ​​of these apertures then corresponds to the side length of the hexagon.

[0088] As illustrated in [Fig.2C], the first layer 110a, 110b and the second layer 120a, 120b are then formed by epitaxy from the intermediate face 104a, 104b, through the openings 171 of the mask 170.

[0089] Preferably, during this epitaxial stage, the formation of the first layer 110a, 110b is preceded by an n-GaN growth. This n-GaN layer preferably has a thickness at least equal to that of the gate dielectric.

[0090] According to an advantageous embodiment, the mask 170 is retained after the epitaxial step. This provides additional thickness at the base of the gate, which is beneficial for the gate's electric field strength when the component is blocked. In this case, advantageously, the thickness of the n-GaN layer is equal to the sum of the thickness of the gate dielectric and that of the mask 170.

[0091] In this embodiment, the first layer 110a, 110b and the second layer 120a, 120b are thus directly formed with openings 20, unlike the first embodiment where these are formed by etching in the first layer 110a, 110b and in the second layer 120a, 120b. The openings 20 are defined in this second embodiment by the mask 170.

[0092] Mask 170 is then removed, as illustrated by the transition from [Fig.2C] to [Fig.2D],

[0093] The grids 200 and source contacts 300 are then formed respectively in the openings 20 and on the second layer 120a, 120b as described previously in the first embodiment ([Fig.2D]).

[0094] The steps of removing the substrate 10 ([Fig. 2E]) and forming the drain 400 ([Fig. 2F]) are also carried out in a similar manner to that described with reference to the first embodiment. As in the first embodiment, it is also possible to create metallic interconnections in the substrate 10 and in the buffer layers 15 and to form the drain in contact with the lower face 12 of the substrate 10.

[0095] The process thus makes it possible to form at least one transistor la, 1b, each formed of the following elements: - Drain 400, or at least a portion of drain 400, - An island 100a, 100b, comprising layers of GaN with distinct doping levels including the first layer 110a, 110b and the second layer 120a, 120b, - At least one 200 grid placed in contact with the first layer 110a, 110b and the second layer 120a, 120b of the island 100a, 100b considered, - At least one 300 source contact deposited on the second 120 layer.

[0096] A third embodiment will now be described with reference to figures 3A to 3D.

[0097] Just like the first embodiment of the process, this embodiment can for example start with the supply of a substrate 10 and the formation by localized epitaxy of islands 100a, 100b ([Fig.1A] then IB corresponding to [Fig.3A]).

[0098] The spaces between islands 100a, 100b are also filled with a dielectric filling layer 160 ([Fig.3A]).

[0099] As illustrated in Figures 3A and 3B, the filling layer 160 can first be formed up to the height of the upper faces 101a, 101b of the islands 100a, 100b ([Fig.3A]) and then be engraved so that the filling layer 160 is set back in the Z direction relative to the first layer 110a, 110b and the second layer 120a, 120b ([Fig.3B]).

[0100] According to another example, the filling layer 160 is selectively etched so that it is set back along the Z direction relative to the first layer 110a, 110b and the second layer 120a, 120b ([Fig.3B]).

[0101] In both cases, as illustrated in [Fig.3B], the outer flanks 113a, 113b, 123a, 123b of the first 113a, 123a and second 113b, 123b layers are exposed.

[0102] An electrically conductive pattern or grid 200 is then deposited on the filling layer 160. The grid 200 extends from the outer edges 113a, 123a of the first and second layers 110a, 120a of an island 100a to the outer edges 113b, 123b of the first and second layers 110b, 120b of the neighboring island 100b. Thus, in this embodiment, the grid 200 is common to the two neighboring islands 100a, 100b.

[0103] Since the external sides of the islands 100a, 100b are inclined, the width of the grid 200 is typically variable along the Z direction. However, the inclination is relatively small, and the width of the grid 200 is actually of the same order of magnitude as the distance D separating the islands 100a, 100b.

[0104] For simplicity, the width l2Oo of the grid 200 is measured at its lower face, which is opposite or even in contact with the filling layer 160. The width l2oo is typically greater than 198 pm, for example 199 pm. The width l2Oo is preferably less than 200 pm or even 199 pm.

[0105] A source contact 300 is then formed on the second layer 120a, 120b of each island 100a, 100b. The source contacts 300 are specific to each island 100a, 100b.

[0106] This gives us the stacking illustrated in [Fig.3C].

[0107] The steps of removing the substrate 10 and forming the drain 400 ([Fig.3D]) are carried out in a similar way to what has been described with reference to the first embodiment.

[0108] The process thus makes it possible to form at least one transistor la, 1b, each formed of the following elements: - Drain 400, or at least a portion of drain 400, - An island 100a, 100b, comprising layers of GaN with distinct doping levels including the first layer 110a, 110b and the second layer 120a, 120b, - At least one grid 200 deposited in contact with the lateral sides 113a, 123a of the first layer 110a, 110b and the lateral sides 113b, 123b of the second layer 120a, 120b of the island 100a, 100b considered, - A 300 source contact deposited on the second layer 120.

[0109] The paragraphs below aim to detail the operation of the transistors 1a, 1b obtained by the process according to the invention. These explanations are valid for all embodiments. In particular, they apply to each gate 200 / source contact 300 in the case of multi-gate transistors as illustrated in the first and second embodiments.

[0110] When the grid(s) 200 are positively biased relative to the source contact(s) 300, an electron channel is formed through the first layer 110a, 110b and the second layer 120a, 120b, against the grid(s) 200. For example, in the case of the third embodiment, the electron channel is formed near or even at the outer edges 113a, 113b, 123a, 123b of these layers 110a, 110b, 120a, 120b. The electrons then pass into the drift layer 130a, 130b and then into the drain 400.

[0111] Conversely, when the grid(s) 200 are negatively biased relative to the source contact(s) 300, there is no longer an electron channel, the first layer 110a, 110b and the second layer 120a, 120b form a PN junction and the drift layer 130a, 130b is depleted.

[0112] Thus, in view of the different embodiments described above, the invention makes it possible to manufacture vertical GaN-based transistors without using a GaN substrate, which is expensive and often only available in small dimensions.

[0113] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Demands

1. A method for manufacturing at least one vertical transistor (1a, 1b) comprising the following steps: • providing a substrate (10) having a top face (H), • performing localized gallium nitride (GaN) epitaxy on the top face (11) of the substrate (10), so as to form at least one GaN-based island (100a, 100b), each island (100a, 100b) comprising a first layer (110a, 110b) based on GaN doped with a first type taken from n-type doping and p-type doping, and a second layer (120a, 120b) based on GaN doped with the other type directly overlying the first layer (110a, 110b), each island (100a, 100b) having a bottom face (102a, 102b), facing the upper face (11) of the substrate (10), • at the level of each island (100a, 100b), form at least one electrically conductive pattern called a grid (200) in contact with the first layer (110a, 110b) and with the second layer (120a, 120b),and at least one electrically conductive contact called the source contact (300) in contact with the second layer (120a, 120b), • forming an electrically conductive layer (400) forming a drain, the drain (400) being electrically connected to the lower face (102a, 102b) of each island (100a, 100b), thus forming at least one vertical transistor (1a, 1b).

2. A manufacturing method according to the preceding claim in which the substrate (10) is silicon-based.

3. A manufacturing method according to any one of the preceding claims wherein each island (100a, 100b) has a height hiOo greater than or equal to 10 pm, preferably greater than or equal to 20 pm, hioo being measured in a direction perpendicular to a plane (XY) in which the upper face (11) of the substrate (10) extends mainly.

4. A manufacturing method according to any one of the preceding claims, wherein the drain formation step (400) comprises the following steps: • after forming at least one island (100a, 100b), remove the substrate (10), then • form the drain (400) against the underside (102a, 102b) of at least one island (100a, 100b).

5. A manufacturing method according to any one of claims 1 to 3 wherein the drain (400) formation step comprises the following steps: • for each island (100a, 100b), forming at least one metallic interconnection through the substrate (10) and opening onto said island (100a, 100b), • forming the drain (400) against a lower face (12) of the substrate (10) opposite its upper face (11), the drain (400) being in contact with at least one metallic interconnection.

6. A manufacturing method according to any one of the preceding claims wherein the formation of at least one grid (200) comprises the following steps: • engraving at least one opening (20) extending from the upper face (101a, 101b) of at least one island (100a, 100b), the opening passing completely through the second layer (120a, 120b) and at least partially through the first layer (110a, 110b), • forming the at least one grid (200) in the at least one opening (20).

7. A manufacturing method according to any one of claims 1 to 5 wherein the epitaxial step comprises the following step: • forming by epitaxy the first layer (110a, 110b) and the second layer (120a, 120b) through a mask (170), so as to define at least one opening (20) extending from an upper face (101a, 101b) of at least one island (100a, 100b), the opening (20) passing through the second layer (120a, 120b) and at least partially through the first layer (110a, 110b), and wherein at least one grid (200) is formed in said at least one opening (20).

8. A manufacturing method according to any one of the preceding claims in which a plurality of grids (200) is formed in contact with the first layer (110a, 110b) and the second layer (120a, 120b) of the same island (100a, 100b).

9. A manufacturing method according to the preceding claim in which a plurality of source contacts (300) is formed in contact with the second layer (120a, 120b) and in which, in projection in a plane (XY) in which the upper face (11) of the substrate (10) extends mainly, the grids (200) and the source contacts (300) are found alternately.

10. A manufacturing method according to any one of claims 1 to 5 wherein at least two islands (100a, 100b) and two transistors (la, 1b) are formed, and wherein the gate (200) formed at the level of the first island (100a) and that formed at the level of the second island (100b) are in electrical continuity and form a gate (200) common to the two transistors (la, 1b).

11. A manufacturing method according to the preceding claim in which the gate (200) common to the two transistors (la, 1b) extends between a lateral flank (103 a) of the first island (100a) and a lateral flank (103b) of the second island (100b).

12. A manufacturing method according to any one of the preceding claims wherein the drain (400) is copper-based.

13. A manufacturing method according to claim 4 alone or in combination with any of claims 6 to 12 wherein the substrate removal step (10) is carried out before the formation of the grid (200) and at least one source contact (300) at each island (100a, 100b), and optionally before the formation of the first layer (110a, 110b) and the second layer (120a, 120b).

14. A manufacturing method according to claim 4 alone or in combination with any of claims 6 to 12 wherein the substrate removal step (10) is carried out after the formation of the grid (200) and at least one source contact (300) at each island (100a, 100b).

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