Gallium nitride IGBT devices with body diodes and their fabrication methods and chips

Abstract

This application belongs to the field of semiconductor technology and provides a gallium nitride IGBT device with a body diode, its fabrication method, and a chip. The gallium nitride IGBT device with a body diode includes: a P-type gallium nitride collector region, an N-type gallium nitride layer, a P-type gallium nitride layer, a gate dielectric layer, a gate, a first N-type emitter region, a Schottky metal region, an isolation region, a first emitter, a second emitter, and a collector. By disposing the Schottky metal region within the P-type and N-type gallium nitride layers, when the gallium nitride IGBT device is operating, the Schottky metal region can form the body diode of the gallium nitride IGBT device. When the gallium nitride IGBT device is turned off, the body diode formed by the Schottky metal region can dissipate the residual current of the gallium nitride IGBT device, i.e., cut off its tail current, thereby reducing the power consumption of the gallium nitride IGBT device during turn-off and improving the performance of the gallium nitride IGBT device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a gallium nitride IGBT device with a body diode, its fabrication method, and a chip. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the low on-resistance and high voltage withstand characteristics of both BJTs and MOSFETs, and also possesses many excellent characteristics such as voltage control, high input impedance, low drive power, low on-resistance, and low switching losses. It is widely used in medium and high power electronic systems.

[0003] IGBTs are commonly known as the "CPU" of power electronic devices. As one of the important high-power mainstream devices in power electronics, IGBTs have been widely used in home appliances, transportation, power engineering, renewable energy, and smart grids. In industrial applications, such as traffic control, power conversion, industrial motors, uninterruptible power supplies, wind and solar power equipment, and frequency converters for automatic control, existing IGBT power devices require a long time for current to disappear when turned off, resulting in excessive dynamic power consumption. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a gallium nitride IGBT device with a body diode, its fabrication method, and a chip, aiming to solve the problem that existing IGBT power devices require a long time for current to disappear during turn-off, resulting in excessive dynamic power consumption.

[0005] A first aspect of this application provides a gallium nitride IGBT device with a body diode, the gallium nitride IGBT device comprising:

[0006] P-type gallium nitride collector region;

[0007] An N-type gallium nitride layer is disposed on the front side of the P-type gallium nitride collector region;

[0008] A P-type gallium nitride layer is disposed on the N-type gallium nitride layer;

[0009] A gate dielectric layer is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer; wherein the gate dielectric layer has a concave structure, and the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride doped region and a second P-type gallium nitride doped region;

[0010] The gate is disposed within a groove in the gate dielectric layer;

[0011] The first N-type emitter region is located within the first P-type gallium nitride doped region and is in contact with the gate dielectric layer;

[0012] Schottky metal regions are disposed within the P-type gallium nitride layer and the N-type gallium nitride layer;

[0013] An isolation region is provided within the P-type gallium nitride layer and the N-type gallium nitride layer to isolate the Schottky metal region and the gate dielectric layer;

[0014] The first emitter is disposed on the first P-type gallium nitride doped region and the first N-type emitter region;

[0015] The second emitter is disposed on the Schottky metal region;

[0016] The collector electrode is located on the back side of the P-type gallium nitride collector region.

[0017] In one embodiment, the second P-type gallium nitride doped region is disposed between the isolation region and the gate dielectric layer, and the second emitter is connected to the first emitter.

[0018] In one embodiment, the gallium nitride IGBT device with a body diode further includes:

[0019] The second N-type emitter region is disposed within the second P-type gallium nitride doped region and is located between the gate dielectric layer and the isolation region;

[0020] The second emitter is disposed on the second N-type emitter region, the isolation region, and the Schottky metal region.

[0021] In one embodiment, the isolation region is in contact with the gate dielectric layer, and the second emitter is connected to the first emitter.

[0022] In one embodiment, the thickness of the isolation region is the same as the thickness of the Schottky metal region.

[0023] In one embodiment, the thickness of the gate dielectric layer is greater than the thickness of the P-type gallium nitride layer, but less than the sum of the thicknesses of the P-type gallium nitride layer and the N-type gallium nitride layer.

[0024] In one embodiment, the gallium nitride IGBT device with a body diode further includes:

[0025] The first buffer doped region and the second buffer doped region are disposed on the back side of the P-type gallium nitride collector region; wherein the first buffer doped region and the second buffer doped region are respectively disposed on both sides of the collector electrode and do not contact the collector electrode.

[0026] The first substrate doped region and the second substrate doped region are respectively disposed on the back side of the first buffer doped region and the second buffer doped region.

[0027] A second aspect of this application provides a method for fabricating a gallium nitride IGBT device with a body diode, comprising:

[0028] A buffer layer is formed on the front side of a semiconductor substrate, and an N-type gallium nitride layer is formed on the buffer layer;

[0029] A P-type gallium nitride layer is formed on the N-type gallium nitride layer;

[0030] A gate dielectric layer and an isolation region are formed, wherein the gate dielectric layer is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer; wherein the gate dielectric layer has a concave structure, and the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride doped region and a second P-type gallium nitride doped region, and the isolation region is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer;

[0031] A first N-type emitter region is formed within the first P-type gallium nitride doped region; wherein the first N-type emitter region is in contact with the gate dielectric layer;

[0032] A gate and a Schottky metal region are formed within the groove of the gate dielectric layer; wherein the Schottky metal region is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer, contacting the isolation region;

[0033] A first emitter is formed on the first P-type gallium nitride doped region and the first N-type emitter region; a second emitter is formed on the Schottky metal region.

[0034] Etching is performed on the back side of the semiconductor substrate, and P-type dopant ions are implanted into the N-type gallium nitride layer under a first preset condition to form a P-type gallium nitride collector region on the back side of the N-type gallium nitride layer.

[0035] A collector electrode is formed on the back side of the P-type gallium nitride collector region.

[0036] In one embodiment, the implantation of P-type dopant ions into the N-type gallium nitride layer under a first preset condition includes:

[0037] A P-type doped ion implantation process is performed under a pressure range of 300MPa-500MPa and a temperature range of 1200℃-1300℃ to form a P-type gallium nitride collector region on the back side of the N-type gallium nitride layer; wherein the time of the P-type doped ion implantation process is 10-20 minutes.

[0038] A third aspect of this application provides a chip comprising: a gallium nitride IGBT device having a body diode as described in any of the preceding claims.

[0039] The beneficial effects of this application embodiment compared with the prior art are as follows: By disposing the Schottky metal region within the P-type gallium nitride layer and the N-type gallium nitride layer, the Schottky metal region contacts both the P-type and N-type gallium nitride layers respectively. When the gallium nitride IGBT device is operating, the Schottky metal region can form the body diode of the gallium nitride IGBT device. Furthermore, because the Schottky metal region is connected to the N-type emitter region, when the gallium nitride IGBT device is turned off, the body diode formed by the Schottky metal region can dissipate the residual current of the gallium nitride IGBT device, i.e., cut off its tail current, thereby reducing the power consumption of the gallium nitride IGBT device during turn-off and improving the performance of the gallium nitride IGBT device. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a gallium nitride IGBT device with a body diode provided in one embodiment of this application. Figure 1 ;

[0041] Figure 2 This is a schematic diagram of the structure of a gallium nitride IGBT device with a body diode provided in one embodiment of this application. Figure 2 ;

[0042] Figure 3 This is a schematic diagram of the structure of a gallium nitride IGBT device with a body diode provided in one embodiment of this application. Figure 3 ;

[0043] Figure 4 This is a schematic diagram of the structure of a gallium nitride IGBT device with a body diode provided in one embodiment of this application. Figure 4 ;

[0044] Figure 5 This is a schematic diagram of the fabrication steps of a gallium nitride IGBT device with a body diode provided in one embodiment of this application;

[0045] Figure 6 This is a schematic diagram of a buffer layer, an N-type gallium nitride layer, and a P-type gallium nitride layer sequentially formed according to an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of the formation of the gate dielectric layer and the isolation region according to an embodiment of this application;

[0047] Figure 8 This is a schematic diagram of the formation of the first N-type emission region provided in one embodiment of this application;

[0048] Figure 9This is a schematic diagram of the bottom right side of the isolation region 80 after dry etching, provided in one embodiment of this application.

[0049] Figure 10 This is a schematic diagram of the formation of the gate and Schottky metal region according to an embodiment of this application;

[0050] Figure 11 This is a schematic diagram of the formation of the first emitter and the second emitter according to an embodiment of this application;

[0051] Figure 12 This is a schematic diagram of the formation of a P-type gallium nitride collector region provided in one embodiment of this application;

[0052] Figure 13 This is a schematic diagram of the current collector formed according to an embodiment of this application. Detailed Implementation

[0053] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0054] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0057] In this specification, references to "one embodiment," "some embodiments," or simply "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," and "in a particular application," appearing in various parts of this specification, do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0058] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the low on-resistance and high voltage withstand characteristics of both BJTs and MOSFETs, and also possesses many excellent characteristics such as voltage control, high input impedance, low drive power, low on-resistance, and low switching losses. It is widely used in medium and high power electronic systems.

[0059] IGBTs are commonly known as the "CPU" of power electronic devices. As one of the important high-power mainstream devices in power electronics, IGBTs have been widely used in home appliances, transportation, power engineering, renewable energy, and smart grids. In industrial applications, such as traffic control, power conversion, industrial motors, uninterruptible power supplies, wind and solar power equipment, and frequency converters for automatic control, existing IGBT power devices require a long time for current to disappear when turned off, resulting in excessive dynamic power consumption.

[0060] To address the technical problem of the inability to balance breakdown voltage and on-resistance in LDMOS devices, embodiments of this application provide a gallium nitride IGBT device with a body diode, as referenced. Figure 1 As shown, a gallium nitride IGBT device with a body diode includes: a P-type gallium nitride collector region 10, an N-type gallium nitride layer 20, a P-type gallium nitride layer 30, a gate dielectric layer 40, a gate 50, a first N-type emitter region 60, a Schottky metal region 70, an isolation region 80, a first emitter 90, a second emitter 100, and a collector 110.

[0061] Specifically, an N-type gallium nitride (GaN) layer 20 is disposed on the front side of the P-type GaN collector region 10. A P-type GaN layer 30 is disposed on the N-type GaN layer 20. A gate dielectric layer 40 is disposed within the P-type GaN layer 30 and extends into the N-type GaN layer 20; wherein, the gate dielectric layer 40 has a concave structure, dividing the P-type GaN layer 30 into a first P-type GaN doped region 31 and a second P-type GaN doped region 32. A gate 50 is disposed within the recess of the gate dielectric layer 40. A first N-type emitter region 60 is disposed within the first P-type GaN doped region 31 and is in contact with the gate dielectric layer 40. A Schottky metal region 70 is disposed within the P-type GaN layer 30 and the N-type GaN layer 20. An isolation region 80 is disposed within the P-type gallium nitride layer 30 and the N-type gallium nitride layer 20, and is used to isolate the Schottky metal region 70 and the gate dielectric layer 40. A first emitter 90 is disposed on the first P-type gallium nitride doped region 31 and the first N-type emitter region 60. A second emitter 100 is disposed on the Schottky metal region 70. A collector 110 is disposed on the back side of the P-type gallium nitride collector region 10.

[0062] In this embodiment, the gate dielectric layer 40 is disposed within the P-type gallium nitride layer 30 and extends into the N-type gallium nitride layer 20. The gate dielectric layer 40 has a concave structure, dividing the P-type gallium nitride layer 30 into a first P-type gallium nitride doped region 31 and a second P-type gallium nitride doped region 32. It is understood that after forming the N-type gallium nitride layer 20 and the P-type gallium nitride layer 30, a groove extending into the N-type gallium nitride layer 20 is formed in a predetermined region of the P-type gallium nitride layer by etching. Then, gate dielectric material 50 is deposited on the inner wall of the groove to form the gate dielectric layer 40. The gate dielectric layer 40 separates the P-type gallium nitride layer 30 in the middle, dividing it into the first P-type gallium nitride doped region 31 and the second P-type gallium nitride doped region 32, which are not in contact with each other.

[0063] In this embodiment, the gate 50 is disposed in the groove of the gate dielectric layer 40. The gate dielectric layer 40 is mainly used to isolate the gate 50 from the N-type gallium nitride layer 20 and the gate 50 from the P-type gallium nitride layer 30, so as to isolate the gate 50 from the N-type gallium nitride layer 20 and the P-type gallium nitride layer 30.

[0064] In this embodiment, the Schottky metal region 70 is disposed within the P-type gallium nitride layer 30 and the N-type gallium nitride layer 20, and the Schottky metal region 70 is in contact with the P-type gallium nitride layer 30 and the N-type gallium nitride layer 20, respectively. When the gallium nitride IGBT device is operating, the Schottky metal region 70 can form the body diode of the gallium nitride IGBT device. Since the Schottky metal region 70 is connected to the N-type emitter region, when the gallium nitride IGBT device is turned off, the body diode formed by the Schottky metal region 70 can dissipate the residual current of the gallium nitride IGBT device, that is, cut off its tail current, thereby reducing the power consumption of the gallium nitride IGBT device when it is turned off and improving the performance of the gallium nitride IGBT device.

[0065] In this embodiment, the positions of the isolation region 80 and the Schottky metal region 70 can be etched when etching the gate dielectric layer 40 region, thus saving the lamp cover.

[0066] In this embodiment, the P-type gallium nitride collector region 10 is disposed on the back side of the N-type gallium nitride layer 20, the collector electrode 110 is disposed on the back side of the P-type gallium nitride collector region 10, and the ion doping concentration of the P-type gallium nitride collector region 10 is 2.3 to 2.5 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type collector region. 19 cm -3 This results in a high defect density and a large resistance, which in turn leads to a large on-resistance of the IGBT device and affects its performance. The embodiments of this application set a high concentration of P-type collector regions. The high concentration of P-type collector regions can enable the IGBT device to have a low on-resistance during operation, thereby improving the application scenarios of the IGBT device.

[0067] In one embodiment, the Schottky metal region 70 is a metallic material.

[0068] In one specific embodiment, the Schottky metal region 70 is any one of gold, silver, aluminum, platinum, etc.

[0069] In one embodiment, reference Figure 1 As shown, the second P-type gallium nitride doped region 32 is disposed between the isolation region 80 and the gate dielectric layer 40, and the second emitter 100 is connected to the first emitter 90.

[0070] In this embodiment, by positioning the second P-type gallium nitride doped region 32 between the isolation region 80 and the gate dielectric layer 40, the influence of the body diode (Schottky diode) formed by the Schottky metal region 70 on the gallium nitride IGBT device during operation can be avoided, thus improving the stability of the gallium nitride IGBT device. In this embodiment, the second emitter 100 and the first emitter 90 are connected, for example, they can be connected by a metal wire. By connecting the second emitter 100 and the first emitter 90, and because the second emitter 100 is connected to the Schottky metal region 70, when the gallium nitride IGBT device stops working (i.e., is powered off), the Schottky diode can dissipate the residual current of the gallium nitride IGBT device, thereby reducing the power consumption of the gallium nitride IGBT device during turn-off and improving the performance of the gallium nitride IGBT device.

[0071] In one embodiment, reference Figure 2 As shown, the gallium nitride IGBT device with a body diode also includes a second N-type emitter region 120.

[0072] Specifically, the second N-type emitter region 120 is disposed within the second P-type gallium nitride doped region 32, and the second N-type emitter region 120 is located between the gate dielectric layer 40 and the isolation region 80. The second emitter 100 is disposed on the second N-type emitter region 120, the isolation region 80, and the Schottky metal region 70.

[0073] In this embodiment, the first N-type emitter region 60 and the second N-type emitter region 120 are respectively disposed on both sides of the gate dielectric layer 40, and the second N-type emitter region 120 is connected to the Schottky metal region 70 through the second emitter 100. It can be understood that the second emitter 100 is a metallic material. (Reference) Figure 2 As shown, by connecting the second N-type emitter region 120 to the Schottky metal region 70 via the second emitter 100, the first emitter 90 does not need to be connected to the second emitter 100 via a wire. Using the second emitter 100 to the Schottky metal region 70 makes the Schottky diode's performance in interrupting the gallium nitride IGBT device's tail current more stable. Furthermore, wire connections can cause electromagnetic interference to the gallium nitride IGBT device during operation, affecting its performance. This application, by connecting the second N-type emitter region 120 to the Schottky metal region 70 via the second emitter 100, can more stably dissipate the residual current of the gallium nitride IGBT device after it stops working (i.e., power is turned off), reducing the power consumption of the gallium nitride IGBT device during turn-off.

[0074] In one specific embodiment, both the isolation region 80 and the gate dielectric layer 40 are made of silicon oxide.

[0075] In one embodiment, reference Figure 3 As shown, the isolation region 80 is in contact with the gate dielectric layer 40, and the second emitter 100 is connected to the first emitter 90.

[0076] In this embodiment, reference Figure 3 As shown, isolation region 80 is in contact with gate dielectric layer 40, and Schottky metal region 70 is in contact with isolation region 80. Schottky metal region 70 is isolated from gate dielectric layer 40 and gate 50 through isolation region 80, avoiding mutual interference between gate 50 and Schottky metal region 70. Furthermore, the second emitter 100 and the first emitter 90 are connected by a metal wire. When the gallium nitride IGBT device stops working (i.e., is powered off), the Schottky diode can dissipate the residual current of the gallium nitride IGBT device, thereby reducing the power consumption of the gallium nitride IGBT device during turn-off and improving the performance of the gallium nitride IGBT device.

[0077] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 3 As shown, the thickness of the isolation region 80 is the same as the thickness of the Schottky metal region 70. In this embodiment, by setting the thickness of the isolation region 80 to be the same as the thickness of the Schottky metal region 70, the Schottky metal region 70 can be completely isolated from the gate 50 and the gate dielectric layer 40 of the gallium nitride IGBT device, avoiding mutual interference and improving the stability of the gallium nitride IGBT device with a body diode.

[0078] In one embodiment, reference Figure 1 , Figure 2 as well as Figure 3 As shown, the thickness of the gate dielectric layer 40 is greater than the thickness of the P-type gallium nitride layer 30, but less than the sum of the thicknesses of the P-type gallium nitride layer 30 and the N-type gallium nitride layer 20.

[0079] In this embodiment, the thickness of the gate dielectric layer 40 refers to the maximum thickness of the gate dielectric layer 40. That is, the gate dielectric layer 40 has a concave structure, including concave walls and concave bottoms. The maximum thickness of the gate dielectric layer 40 is the sum of the thicknesses of the concave walls and concave bottoms. In this embodiment, the gate dielectric layer 40 is mainly used to isolate the gate 50 from the N-type gallium nitride layer 20 and the P-type gallium nitride layer 30. The groove depth of the gate dielectric layer 40 is greater than the thickness of the P-type gallium nitride layer 30. This makes the thickness of the gate 50 greater than the thickness of the P-type gallium nitride layer 30. When the gallium nitride IGBT device is working, the gate 50 can form an electron channel along the gate dielectric layer 40 in the N-type gallium nitride layer 20 and the P-type gallium nitride layer 30, so that the gallium nitride IGBT device can work normally.

[0080] In one embodiment, reference Figure 4As shown, the gallium nitride IGBT device with a body diode also includes: a first buffer doped region 131, a second buffer doped region 132, a first substrate doped region 141, and a second substrate doped region 142.

[0081] Specifically, the first buffer doped region 131 and the second buffer doped region 132 are disposed on the back side of the P-type gallium nitride collector region 10; wherein, the first buffer doped region 131 and the second buffer doped region 132 are respectively disposed on both sides of the collector 110, and the first buffer doped region 131 and the second buffer doped region 132 are not in contact with the collector 110. The first substrate doped region 141 and the second substrate doped region 142 are respectively disposed on the back side of the first buffer doped region 131 and the second buffer doped region 132.

[0082] In this embodiment, when forming the collector 110, reference is used. Figure 1 As shown, the bottom semiconductor substrate and buffer layer need to be etched to expose the P-type gallium nitride collector region 10, and then the collector electrode 110 is formed on the back side of the P-type gallium nitride collector region 10. Alternatively, only part of the semiconductor substrate and buffer layer can be etched to improve the stability of the IGBT device, see reference [reference needed]. Figure 4 As shown.

[0083] In one specific embodiment, the material of the N-type gallium nitride layer 20 is N-type GaN.

[0084] In one specific embodiment, the material of the P-type gallium nitride layer 30 is P-type GaN.

[0085] In one embodiment, gallium nitride material can be deposited first on the N-type gallium nitride layer 20, and then a P-type doped ion implantation process can be performed on the gallium nitride material to form the P-type gallium nitride layer 30.

[0086] In one specific embodiment, the concentration of N-type doped ions in the N-type gallium nitride layer 20 is 10. 19 cm -3 .

[0087] In one specific embodiment, the first N-type emission region 60 and the first N-type emission region 60.

[0088] In one specific embodiment, the first emitter 90 and the second emitter 100 are made of metallic materials.

[0089] In one specific embodiment, the doping concentration of N-type ions in the first N-type emitter region 60 and the second N-type emitter region 120 can be 10. 20 cm -3 The concentration of P-type doped ions within the P-type gallium nitride layer 30 is 10. 19 cm -3It is understandable that the first N-type emitter region 60 and the second N-type emitter region 120 are heavily doped, while the P-type gallium nitride layer 30 is lightly doped.

[0090] In one specific embodiment, the thickness of the first emitter 90 and the second emitter 100 is 200-500 angstroms.

[0091] In one specific embodiment, the gate 50 material can be polysilicon.

[0092] In one specific embodiment, the gate 50 material can be a metallic material.

[0093] In one specific embodiment, the gate dielectric layer 40 is made of silicon oxide.

[0094] In one specific embodiment, the concentration of the P-type gallium nitride collector region 10 reaches 2.3–2.5 × 10⁻⁶. 19 cm -3 ,

[0095] This application also provides a method for fabricating a gallium nitride IGBT device with a body diode, see reference. Figure 5 As shown, it includes steps S10 to S70.

[0096] Step S10 includes: referencing Figure 6 As shown, a buffer layer 130 is formed on the front side of the semiconductor substrate 140, an N-type gallium nitride layer 20 is formed on the buffer layer 130, and a P-type gallium nitride layer 30 is formed on the N-type gallium nitride layer 20.

[0097] In this embodiment, the buffer layer 130 is formed on the front side of the semiconductor substrate 140 by an epitaxial process, the N-type gallium nitride layer 20 is formed on the front side of the buffer layer 130 by an epitaxial process, and the P-type gallium nitride layer 30 is formed on the front side of the N-type gallium nitride layer 20 by an epitaxial process. Furthermore, the thickness of the N-type gallium nitride layer 20 is greater than the thickness of the buffer layer 130, wherein the N-type gallium nitride layer 20 can be obtained by doping gallium nitride material with N-type dopant ions.

[0098] In one specific embodiment, the semiconductor substrate 140 is a silicon substrate or a silicon carbide substrate.

[0099] In one specific embodiment, the material of the buffer layer 130 may be aluminum nitride.

[0100] In one specific embodiment, the thickness of the P-type gallium nitride layer 30 is the same as the thickness of the N-type gallium nitride layer 20.

[0101] In one embodiment, in-situ doping can be used during the deposition of the N-type gallium nitride layer 20, that is, N-type impurities can be introduced during the deposition process. Alternatively, after the N-type gallium nitride layer 20 is deposited, N-type impurities can be introduced into the N-type gallium nitride layer 20 through steps such as impurity implantation and propulsion, or steps such as pre-deposition and propulsion.

[0102] Step S20 includes: referencing Figure 7 As shown, a gate dielectric layer 40 and an isolation region 80 are formed. The gate dielectric layer 40 is disposed within the P-type gallium nitride layer 30 and extends into the N-type gallium nitride layer 20. The gate dielectric layer 40 has a concave structure and divides the P-type gallium nitride layer 30 into a first P-type gallium nitride doped region 31 and a second P-type gallium nitride doped region 32. The isolation region 80 is disposed within the P-type gallium nitride layer 30 and extends into the N-type gallium nitride layer 20.

[0103] In this embodiment, the P-type gallium nitride layer 30 can be dry-etched to form a trench extending into the N-type gallium nitride layer 20 in a first predetermined region. Then, a gate dielectric material 50 is deposited on the inner wall of the trench to form a gate dielectric layer 40. Similarly, the P-type gallium nitride layer 30 can be dry-etched to form a trench extending into the N-type gallium nitride layer 20 in a second predetermined region. Then, a gate dielectric material 50 is deposited on the inner wall of the trench to form a gate dielectric layer 40.

[0104] In one embodiment, the gate dielectric layer 40 and the isolation region 80 have the same thickness.

[0105] In one embodiment, both the gate dielectric layer 40 and the isolation region 80 are made of silicon oxide.

[0106] Step S30 includes: referencing Figure 8 As shown, a first N-type emitter region 60 is formed within the first P-type gallium nitride doped region 31; wherein the first N-type emitter region 60 is in contact with the gate dielectric layer 40.

[0107] In this embodiment, under the cover of a mask, a first N-type emitter region 60 is formed in a predetermined portion of the first P-type gallium nitride doped region 31 by N-type ion implantation. The first N-type emitter region 60 is located on the top right side of the first P-type gallium nitride doped region 31.

[0108] In one embodiment, ion implantation can be performed at high temperatures, wherein the temperature range is 1000°C to 1200°C.

[0109] In one embodiment, the N-type dopant ion can be phosphorus, and a high-temperature annealing process is performed to allow the phosphorus ion to enter the first P-type gallium nitride doped region 31 to form the first N-type emitter region 60.

[0110] Step S40 includes: referencing Figure 9 , Figure 10 As shown, a gate 50 and a Schottky metal region 70 are formed in the groove of the gate dielectric layer 40; wherein, the Schottky metal region 70 is disposed in the P-type gallium nitride layer 30 and extends into the N-type gallium nitride layer 20, and contacts the isolation region 80 of the Schottky metal region 70.

[0111] Specifically, in this embodiment, a corresponding metal material is deposited within the groove of the gate dielectric layer 40 to form the gate 50, and dry etching is performed on the bottom right side of the isolation region 80 to form a groove extending into the N-type gallium nitride layer 20 on the bottom right side of the isolation region 80. (Refer to...) Figure 9 As shown, a corresponding Schottky metal material is then deposited on the right side of the isolation region 80 to form the Schottky metal region 70, as referenced. Figure 10 As shown.

[0112] In one specific embodiment, the gate 50 material can be polysilicon.

[0113] In one specific embodiment, the gate 50 material can be a metallic material.

[0114] In one specific embodiment, the material of the Schottky metal region 70 is any one of gold, silver, aluminum, platinum, etc.

[0115] Step S50 includes: referencing Figure 11 As shown, a first emitter 90 is formed on the first P-type gallium nitride doped region 31 and the first N-type emitter region 60; a second emitter 100 is formed on the Schottky metal region 70.

[0116] In this embodiment, reference Figure 11 As shown, corresponding metal materials are deposited on the first P-type gallium nitride doped region 31 and the first N-type emitter region 60 and etched to form the first emitter 90, and corresponding metal materials are deposited on the Schottky metal region 70 and etched to form the second emitter 100, wherein the first emitter 90 and the second emitter 100 have the same thickness.

[0117] In one specific embodiment, the first emitter 90 and the second emitter 100 are made of metallic materials.

[0118] In one specific embodiment, the thickness of the first emitter 90 and the second emitter 100 is 200-500 angstroms.

[0119] Step S60 includes: referencing Figure 12 As shown, etching is performed on the back side of the semiconductor substrate 140, and P-type doped ions are implanted into the N-type gallium nitride layer 20 under a first preset condition to form a P-type gallium nitride collector region 10 on the back side of the N-type gallium nitride layer 20.

[0120] In this embodiment, photoresist can be used as a mask to cover the back side of the semiconductor substrate 140. Then, photolithography is performed on the back side of the semiconductor substrate 140 to expose the N-type gallium nitride layer 20, and excess photoresist is removed. Under a first preset condition, P-type dopant ions are implanted into the N-type gallium nitride layer 20 to form a P-type collector region on the back side of the N-type gallium nitride layer 20. The first preset condition is a high-temperature, high-pressure condition. In this embodiment, by using a high-temperature, high-pressure method to implant P-type dopant ions into the N-type gallium nitride layer 20, the concentration of the P-type collector region can reach 2.3–2.5 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type collector region. 19 cm -3 This results in a high defect density and a large resistance, which in turn leads to a large on-resistance of the IGBT device and affects its performance. The embodiments of this application can form a high-concentration P-type collector region. The high concentration of the P-type collector region can enable the IGBT device to have a low on-resistance during operation, thus improving the application scenarios of the IGBT device.

[0121] In one embodiment, etching on the back side of the semiconductor substrate 140 may only etch a portion of the semiconductor substrate 140 and the buffer layer 130, such that the semiconductor substrate 140 is divided into a first substrate doped region 141 and a second substrate doped region 142, and the buffer layer 130 is divided into a first buffer doped region 131 and a second buffer doped region 132.

[0122] In one embodiment, etching on the back side of the semiconductor substrate 140 can etch the entire semiconductor substrate 140 and the buffer layer 130.

[0123] Step S70 includes: referencing Figure 13 As shown, a collector 110 is formed on the back side of the P-type gallium nitride collector region 10.

[0124] In this embodiment, under the cover of a mask, a metal material is deposited on the back side of the P-type collector region and etched to form a collector electrode 110, wherein the width of the collector electrode 110 is smaller than the width of the P-type collector region.

[0125] In one embodiment, implanting P-type doped ions into the N-type gallium nitride layer 20 under first preset conditions includes: performing a P-type doped ion implantation process under a pressure range of 300MPa-500MPa and a temperature range of 1200℃-1300℃ to form a P-type gallium nitride collector region 10 on the back side of the N-type gallium nitride layer 20; wherein the P-type doped ion implantation process takes 10-20 minutes.

[0126] In this embodiment, injecting P-type doped ions into the N-type gallium nitride layer 20 under the first preset condition can result in a higher ion concentration in the P-type collector region. It is understood that the P-type collector region is located at the bottom of the N-type gallium nitride layer 20, the gate dielectric layer 40 is located at the top of the N-type gallium nitride layer 20, and the gate dielectric layer 40 and the P-type collector region in the N-type gallium nitride layer 20 do not contact each other.

[0127] In one embodiment, when a P-type doped ion implantation process is performed at a pressure of 500 MPa and a temperature of 1300 °C for 20 minutes, the concentration of the resulting P-type collector region is 2.5 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type collector region. 19 cm -3 This results in a high defect density and significant resistance, leading to a large on-resistance in the IGBT device and negatively impacting its performance. In this embodiment, the defect density is set to 2.5*10⁻⁶. 19 cm -3 The P-type collector region enables IGBT devices to have lower on-resistance during operation, thus expanding the application scenarios of IGBT devices.

[0128] In one embodiment, when a P-type doped ion implantation process is performed at a pressure of 300 MPa and a temperature of 1200 °C for 20 minutes, the concentration of the resulting P-type collector region is 2.3 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type collector region. 19 cm -3 This results in a high defect density and high resistance, leading to a large on-resistance in the IGBT device and affecting its performance. In this embodiment, the defect density is set to 2.4*10⁻⁶. 19 cm -3 The P-type collector region allows the IGBT device to have a lower on-resistance during operation, expanding the application scenarios of the IGBT device. This application also provides a chip, including: a gallium nitride IGBT device with a body diode as described in any of the above embodiments.

[0129] This application provides a gallium nitride IGBT device with a body diode, its fabrication method, and a chip. A Schottky metal region 70 is disposed within a P-type gallium nitride layer 30 and an N-type gallium nitride layer 20, with the Schottky metal region 70 in contact with both layers. When the gallium nitride IGBT device is operating, the Schottky metal region 70 forms the body diode. Since the Schottky metal region 70 is connected to the N-type emitter region, when the gallium nitride IGBT device is turned off, the body diode formed by the Schottky metal region 70 can dissipate the residual current in the gallium nitride IGBT device, effectively cutting off its tail current. This reduces the power consumption of the gallium nitride IGBT device during turn-off and improves its performance.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0131] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gallium nitride IGBT device with a body diode, characterized in that, The gallium nitride IGBT device includes: P-type gallium nitride collector region; An N-type gallium nitride layer is disposed on the front side of the P-type gallium nitride collector region; A P-type gallium nitride layer is disposed on the N-type gallium nitride layer; A gate dielectric layer is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer; wherein the gate dielectric layer has a concave structure, and the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride doped region and a second P-type gallium nitride doped region; The gate is disposed within a groove in the gate dielectric layer; The first N-type emitter region is located within the first P-type gallium nitride doped region and is in contact with the gate dielectric layer; Schottky metal regions are disposed within the P-type gallium nitride layer and the N-type gallium nitride layer, and are in contact with the P-type gallium nitride layer and the N-type gallium nitride layer, respectively; An isolation region is provided within the P-type gallium nitride layer and the N-type gallium nitride layer to isolate the Schottky metal region and the gate dielectric layer; The first emitter is disposed on the first P-type gallium nitride doped region and the first N-type emitter region; The second emitter is disposed on the Schottky metal region; The collector electrode is located on the back side of the P-type gallium nitride collector region.

2. The gallium nitride IGBT device with a body diode as described in claim 1, characterized in that, The second P-type gallium nitride doped region is disposed between the isolation region and the gate dielectric layer, and the second emitter is connected to the first emitter.

3. The gallium nitride IGBT device with a body diode as described in claim 1, characterized in that, The gallium nitride IGBT device with a body diode further includes: The second N-type emitter region is disposed within the second P-type gallium nitride doped region and is located between the gate dielectric layer and the isolation region; The second emitter is disposed on the second N-type emitter region, the isolation region, and the Schottky metal region.

4. The gallium nitride IGBT device with a body diode as described in claim 1, characterized in that, The isolation region is in contact with the gate dielectric layer, and the second emitter is connected to the first emitter.

5. The gallium nitride IGBT device with a body diode as described in claim 1, characterized in that, The thickness of the isolation region is the same as the thickness of the Schottky metal region.

6. The gallium nitride IGBT device with a body diode as described in any one of claims 1-5, characterized in that, The thickness of the gate dielectric layer is greater than the thickness of the P-type gallium nitride layer, but less than the sum of the thicknesses of the P-type gallium nitride layer and the N-type gallium nitride layer.

7. The gallium nitride IGBT device with a body diode as described in any one of claims 1-5, characterized in that, The gallium nitride IGBT device with a body diode further includes: The first buffer doped region and the second buffer doped region are disposed on the back side of the P-type gallium nitride collector region; wherein the first buffer doped region and the second buffer doped region are respectively disposed on both sides of the collector electrode and do not contact the collector electrode. The first substrate doped region and the second substrate doped region are respectively disposed on the back side of the first buffer doped region and the second buffer doped region.

8. A method for fabricating a gallium nitride IGBT device with a body diode, characterized in that, include: A buffer layer is formed on the front side of a semiconductor substrate, and an N-type gallium nitride layer is formed on the buffer layer; A P-type gallium nitride layer is formed on the N-type gallium nitride layer; A gate dielectric layer and an isolation region are formed, wherein the gate dielectric layer is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer; wherein the gate dielectric layer has a concave structure, and the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride doped region and a second P-type gallium nitride doped region, and the isolation region is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer; A first N-type emitter region is formed within the first P-type gallium nitride doped region; wherein the first N-type emitter region is in contact with the gate dielectric layer; A gate and a Schottky metal region are formed within the recess of the gate dielectric layer; wherein the Schottky metal region is disposed within the P-type gallium nitride layer and extends into the N-type gallium nitride layer, contacting the isolation region, and the Schottky metal region contacts both the P-type gallium nitride layer and the N-type gallium nitride layer; A first emitter is formed on the first P-type gallium nitride doped region and the first N-type emitter region; a second emitter is formed on the Schottky metal region. Etching is performed on the back side of the semiconductor substrate, and P-type dopant ions are implanted into the N-type gallium nitride layer under a first preset condition to form a P-type gallium nitride collector region on the back side of the N-type gallium nitride layer. A collector electrode is formed on the back side of the P-type gallium nitride collector region.

9. The preparation method according to claim 8, characterized in that, The implantation of P-type doped ions into the N-type gallium nitride layer under the first preset condition includes: A P-type doped ion implantation process is performed under a pressure range of 300MPa-500MPa and a temperature range of 1200℃-1300℃ to form a P-type gallium nitride collector region on the back side of the N-type gallium nitride layer; wherein the P-type doped ion implantation process takes 10-20 minutes.

10. A chip, characterized in that, include: The gallium nitride IGBT device with a body diode as described in any one of claims 1-7.

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