Silicon substrate texturing process

Abstract

Process for Texturing Silicon Substrates This description relates to a process for texturing silicon substrates comprising the following steps: a) providing: - a first silicon substrate (100), comprising a first face (101), covered by an oxide layer (110), and a second face (102), and - a second silicon substrate (200) comprising a first face (201), covered by an oxide layer (210), and a second face (202), b) joining the first substrate (100) and the second substrate (200) by direct hydrophilic bonding, by bringing the oxide layers (110, 210) of the substrates (100, 200) into contact, c) contacting the second face (102) of the first substrate (100) and the second face (202) of the second substrate (200) with a basic solution, thereby bonding the second face (102) of the first substrate (100) and the second face (202) of the second substrate (200) are textured, d) separate the substrates (100,200). Figure for the abstract: Fig.1D.

Description

Title of the invention: Method for texturizing silicon substrates technical field

[0001] The present description relates generally to the field of silicon substrates, in particular silicon substrates and, in particular, crystalline silicon substrates used for the manufacture of photovoltaic cells, in particular tandem photovoltaic cells, in particular perovskite tandem cells on silicon, using a variable structure subcell (heterojunction, TopCon) or single junction photovoltaic cells such as heterojunction or TopCon type photovoltaic cells. Previous technique

[0002] Tandem photovoltaic cells comprise two sub-cells: a lower sub-cell (or 'Bottom Cell') and an upper sub-cell ('Top Cell').

[0003] Heterojunction subcells, for example silicon heterojunction subcells, typically comprise a crystalline silicon substrate, covered on both sides by an intrinsic amorphous silicon layer serving as a passivation layer and then by, on one side, an n-doped amorphous silicon layer, and on the other side by a p-doped amorphous silicon layer.

[0004] The lower sub-cell generally has a textured face on the front side, exposed to light, and a polished face on the rear side.

[0005] The polished rear face has minimal roughness to allow the liquid deposition of the layers forming the upper subcell. The polishing can be chemical mechanical polishing (CMP).

[0006] The textured face allows for the recovery of a maximum of photons and thus increases current, the current being directly related to the conversion efficiency.

[0007] Texturing is generally carried out by chemical attack.

[0008] To maintain a polished and smooth surface during texturing, it is generally covered with a protective layer. Such a process is, for example, described in document WO 2012 / 083944 AL. The process comprises the following steps: polishing the front and back faces of a silicon substrate, depositing a protective layer, for example, a silicon nitride layer and / or a silicon oxide layer, onto the front face of the silicon substrate, and texturing the back face of the silicon substrate using a basic solution. The protective layer is generally deposited by PECVD. It is removed at the end of the process, for example, using an HF solution.

[0009] The process has several drawbacks: - Applying the barrier layer is time-consuming and expensive, - The barrier layer must be perfectly homogeneous and sufficient to prevent localized etching. - PECVD deposition is generally carried out at 450°C, a temperature at which defects can be generated in the silicon substrate (for example, in Fz ('Float Zone') substrates, so-called dead zones can form, - it can be a source of metallic contamination.

[0010] Such a process requires removing the barrier layer after the single-sided texturing step, which increases the number of steps required and the cost. Furthermore, this barrier layer must be perfectly etched because the presence of residue would cause malfunctions in the future tandem cell. Summary of the invention

[0011] There is a need for a manufacturing process that allows for a silicon substrate having a polished face and a textured face, and which at least partially remedies the disadvantages of the prior art.

[0012] This goal is achieved by a silicon substrate texturing process, the process comprising the following steps: a) providing: - a first silicon substrate, comprising a first polished face, covered by an oxide layer, and a second face, and - a second silicon substrate comprising a first polished face, covered by an oxide layer, and a second face, b) assemble the first substrate and the second substrate by direct hydrophilic bonding, by bringing the oxide layers of the first substrate and the second substrate into contact, c) bring the second face of the first substrate and the second face of the second substrate into contact with a basic solution, preferably a solution of KOH, NaOH or TMAH, thereby textured the second face of the first substrate and the second face of the second substrate, d) separate the first substrate from the second substrate.

[0013] According to a particular embodiment, the oxide layers are chemical oxide layers, preferably having a thickness between 0.8 nm and 1.8 nm, and preferably between 1.2 nm and 1.6 nm.

[0014] According to a particular embodiment, the oxide layers are thermal oxide layers.

[0015] According to a particular embodiment, the thermal oxide is formed by carrying out a heat treatment at a temperature below 400°C, for example at a temperature between 150°C and 300°C.

[0016] According to a particular embodiment, the oxide layers are native oxide layers, having for example a thickness of 1 nm.

[0017] According to a particular embodiment, during step c), retaining elements, for example clips or rings, preferably made of polymer, are used to hold the first substrate and the second substrate against each other.

[0018] According to a particular embodiment, the second face of the first substrate and the second face of the second substrate are textured in the form of pyramids having a height between 300 nm and 3 pm, preferably between 1 and 2 pm.

[0019] According to a particular embodiment, the first substrate and the second substrate are obtained by cutting a silicon ingot using a diamond element, for example a diamond wire, defects, resulting from the cutting step, present on the second face of the first substrate and on the second face of the second substrate, being able to be removed by polishing in a KOH solution having, preferably, a concentration greater than 30% by mass.

[0020] This goal is also achieved by a method of manufacturing a photovoltaic cell, for example a tandem cell or a single junction cell, comprising a step in which a silicon substrate is textured by implementing the process as described above. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1A], [Fig.1B], [Fig.1C] and [Fig.1D] schematically represent different stages of a single-sided texturing process of a substrate, according to a particular embodiment of the invention;

[0023] [Fig.2] is a photographic image of the polished face of a substrate, which was protected by gluing during the texturing step, according to a particular embodiment of the invention;

[0024] [Fig.3] is a photographic image of two substrates assembled by molecular bonding and held together by a retaining element (rings), according to another particular embodiment of the invention;

[0025] [Fig.4A] is a photographic image of the polished face of a substrate, which was protected by gluing during the texturing step, according to another particular embodiment of the invention;

[0026] [Fig.4B] is a photographic image of the textured face of a substrate at the end of the texturing process according to another particular embodiment of the invention;

[0027] [Fig.5] is a graph representing the ratio between the lifetime of the charge carriers and the resistivity of the material (tau / rho ratio) of different textured substrates;

[0028] [Fig.6] is a graph representing the open circuit voltage (Voc) of different textured substrates;

[0029] [Fig.7] is a graph representing the intensity of photoluminescence (PL signal) in number of hits of different textured substrates;

[0030] Fig. 8 represents several photographs obtained by photoluminescence of different textured substrates.

[0031] In figures 5, 6, 7 and 8: - A) and B) correspond to two substrates whose polished faces were protected by a layer of SiN during the texturing step (examples given for comparison purposes) - C) and D) correspond to two substrates whose polished faces, coated with a chemical oxide, were protected by bonding during the texturing step, according to another particular embodiment of the invention, - E) and F) correspond to two substrates whose polished faces covered with a native oxide were protected by bonding during the texturing step, the substrates having also been held together by means of retaining elements (PTFE rings), during the texturing step, according to another particular embodiment of the invention.

[0032] The different elements are not necessarily represented at a uniform scale to make the figures more legible. Description of the implementation methods

[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0035] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean at 10%, preferably at 5%.

[0038] By transparency, it is understood that the structure or element in question has a transmittance greater than or equal to 70%, preferably greater than or equal to 80%, and even more preferably greater than or equal to 90%. Transmittance represents the intensity of light passing through the element or structure across the visible spectrum. It can be measured by UV-Vis-IR spectrometry. The transmittance of the visible spectrum corresponds to the transmittance for wavelengths between 350 and 800 nm.

[0039] By polished face or smooth face, we mean a face having an arithmetic mean roughness Ra of less than 2.5 nm, preferably less than 1 nm, and even more preferably less than 0.6 nm.

[0040] The roughness Ra can be determined by measuring Rdiffu or RD using a spectrophotometer. For this purpose, an incident beam illuminates the surface of the sample. The diffuse reflectivity RD is equal to the ratio of the intensity of the scattered light to the intensity of the incident beam. The respective intensities of the incident beam and the scattered light can be measured by one or more photoelectric detectors. Diffuse reflectivity is a strictly increasing function of the roughness of the sample. It is possible to establish a correlation law or a nomogram giving the roughness of the sample as a function of its diffuse reflectivity.

[0041] By textured face, we mean a structured face covered by texturing elements, for example pyramids 1 to 2 pm high. Preferably, this is a sub-micrometer or micrometer scale structure. The texturing elements preferably have a height between 300 nm and 3 pm.

[0042] By between X and Y, we mean that the bounds X and Y are included.

[0043] We will now describe in more detail the simple texturing process facing a silicon substrate with reference to Figures IA to 1D. The process includes the following steps: a) provide: - a first silicon substrate 100, comprising a first face 101 and a second face 102, the first face 101 of the first substrate 100 being covered by a layer of oxide 110, and - a second silicon substrate 200 comprising a first face 201 and a second face 202, the first face 201 of the second substrate 200 being covered by an oxide layer 210, b) assemble the first substrate 100 and the second substrate 200 by direct hydrophilic bonding, by bringing the oxide layers 110, 210 of the first substrate 100 and the second substrate 200 into contact, c) bring the second faces 102, 202 of the first substrate 100 and the second substrate 200 into contact with a basic solution, preferably a solution of potassium hydroxide (KOH), sodium hydroxide (NaOH) or tetramethylammonium hydroxide (TMAH), to texture them, d) separate the first substrate 100 from the second substrate 200.

[0044] The process is a selective texturing process. It allows simultaneous texturing of one face 102, 202 of each of the substrates 100, 200. The other face 101, 201 of the substrates 100, 200 is protected by molecular bonding.

[0045] The process makes it possible to do away with the masking step (by means of a protective layer of SiNx or SiOx deposited by PEVCD) commonly used in prior art processes.

[0046] The first substrate 100 comprises a first face 101 and a second face 102.

[0047] The second substrate 200 comprises a first face 201 and a second face 202.

[0048] The first faces 101, 201 of the substrates 100, 200 are polished. They are smooth: they have almost zero roughness. The substrates 100, 200 are polished, for example, by CMP (mirror polishing).

[0049] The substrates 100, 200 provided in step a) are silicon-based substrates. Preferably, they are silicon substrates. More particularly, they are crystalline silicon substrates, preferably monocrystalline silicon.

[0050] The substrates are, for example, Fz silicon substrates ('Float Zone').

[0051] According to one embodiment, the substrates are silicon substrates obtained by a Cz (Czochralski) process using silicon ingots that are sawn, for example, with diamond wires. Such substrates are less expensive than substrates obtained by a Cz process. Sawing the ingot leads to damage on the surface of the cut substrate. It is possible, prior to step b) of molecular bonding, to etch the work-hardened area of ​​the substrate to remove the saw damage (a step known as SDR or 'Saw Damage Removal') and obtain a very low roughness for texturing. The etching is carried out, for example, using a highly concentrated KOH solution (typically with a concentration greater than 30 wt., for a duration of, for example, at least 10 minutes). This produces surfaces with low roughness, which improves molecular bonding.

[0052] Silicon substrates 100, 200 can be p-doped or n-doped, depending on the application sought.

[0053] The first face 101 of the first substrate 100 and the first face 201 of the second substrate 200 are each covered by a layer of oxide 110, 210.

[0054] The oxides can be native oxides. A native oxide has a thickness, for example, of 10 Å.

[0055] Oxides can be chemical oxides. A chemical oxide has a thickness, for example, of 12 to 16 Å. A chemical oxide can be formed by bringing the surface to be oxidized into contact with an acidic solution. For example, this could be a solution of DIO3, HF / HC1 / DIO3, H2O2 / HC1, or H2SO4 / H2O2 (with DIO3 being a mixture of deionized water and ozone).

[0056] The oxides can be thermal oxides. A thermal oxide has a thickness, for example, of 10 to 900 nm. A thermal oxide can be formed in an oxidation furnace. Preferably, it is formed at a temperature below 400°C. Thermal oxides allow for strong bonding between the surfaces to be bonded. By using thermal oxides instead of native oxides, the bonding interface is stronger, which limits the risk of etching solution seeping between the substrates 100, 200, and thus reduces the percentage of defective surface on the first faces 101, 201 (i.e., the percentage of textured surface when the surface should remain polished).

[0057] A chemical oxide layer or a thermal oxide layer differs from a native oxide layer both in its thickness (the native oxide layer is much thinner than the thermal oxide layer) and in its stoichiometry.

[0058] It is also possible to use a first substrate 100 with a native oxide and a second substrate 200 with a chemical oxide or a thermal oxide (or vice versa), or a first substrate 100 with a thermal oxide and a second substrate 200 with a chemical oxide (or vice versa).

[0059] In step b), the substrates 100, 200 are then assembled in pairs. The assembly is achieved by molecular bonding by bringing the two oxide layers 110, 210 into contact. The attractive forces between the two surfaces are thus high enough to cause molecular adhesion. Molecular bonding is initially induced by the sum of the attractive forces (Van der Waals forces) of electronic interaction between atoms or molecules of the two surfaces to be bonded. The bonding here is a hydrophilic surface bonding. Hydrogen bonding interactions (stronger than Van der Waals interactions) are also involved because the surfaces contain electronegative atoms (therefore exhibiting an affinity for electrons) bonded to hydrogen atoms.

[0060] It is possible to carry out a heat treatment step and / or to carry out vacuum bonding to improve the bonding.

[0061] The first face 101 of the first substrate 100 and the first face 201 of the second substrate 200 are thus arranged within the assembly and protected during step c).

[0062] In step c), the second face 102 of the first substrate 100 and the second face 202 of the second substrate 200 are brought into contact with an etching solution in order to texture them. Since the etching is anisotropic, it leads to the formation of patterns on the surface of the second faces 102, 202 of the substrates 100, 200.

[0063] The patterns 120, 220 of the texturing have a height, preferably, between 300 nm and 3 pm, for example between 1 and 2 pm.

[0064] Preferably, the engraving will lead to the formation of pyramids on the "free" faces (i.e. the first faces) of the substrates 100, 200.

[0065] Since the glued faces 101, 201 are not in contact with the etching solution, they will not be textured and will remain smooth.

[0066] The etching solution is a basic solution. Preferably, it is a solution containing a hydroxide derivative. For example, a solution of KOH, TMAH, or NaOH may be chosen. Preferably, a KOH solution is used. It may have a concentration between 0.5 and 4% by mass. The solution may also contain surfactants. The surfactant concentration is, for example, between 0.25 and 5% by mass. Surfactants modify the surface tension and thus facilitate the removal of hydrogen bubbles generated by the etching of silicon in a basic medium. Since the hydrogen bubbles no longer obscure the surface, there will be a maximum number of nucleation sites and therefore a homogeneous surface. Texturing (in particular the generation of pyramids) will be easier and more homogeneous.

[0067] During step c) of texturing, and possibly during step b), retaining elements can be used to mechanically hold the substrates against each other. This can prevent etching solution from seeping through the edges of the substrates 100, 200 at the bonding interface.

[0068] The retaining elements can be clips or rings.

[0069] The retaining elements are made of a material inert to the solution of They are not designed to cause engraving and do not generate contamination (particularly metallic contamination). For example, they are made of polymers, especially fluorinated polymers such as polytetrafluoroethylene (PTFE) or perfluoroalkoxy (PFA).

[0070] In step d), the first substrate 100 and the second substrate 200 are separated. This step can be carried out with tweezers or with a jet of inert gas, for example, a nitrogen jet. The means used will depend, for example, on the nature of the bonded oxides.

[0071] A step of removing the oxide layer can be implemented.

[0072] Silicon substrates 100, 200 thus textured can be used to manufacture tandem photovoltaic cells (e.g., Silicon / perovskite) or, more generally, multi-junction solar cells (e.g., Si / PK / PK).

[0073] By way of example, the solar cell may be a pin-type silicon-perovskite tandem cell comprising an upper subcell, for example made of perovskite, and a lower silicon heterojunction subcell. Illumination of a Si / PK tandem device is achieved from the perovskite-based subcell.

[0074] The two sub-cells can be separated by an electronically conductive or semiconducting intermediate layer, preferably transparent to electromagnetic radiation, for example in a TCO (transparent conductive oxides) in particular in ITO (indium tin oxide).

[0075] The silicon heterojunction subcell comprises, for example, from the intermediate layer or from the perovskite-based subcell: - an n-doped amorphous silicon layer, - preferably a layer based on intrinsic amorphous silicon serving as a passivation layer, - the n-doped crystalline silicon 100 substrate, textured according to the process described above, - preferably, a layer based on intrinsic amorphous silicon serving as a passivation layer, - a layer of p-doped amorphous silicon, - a transparent layer, for example in ITO, and a metallization, for example in silver, copper or Ag / Cu.

[0076] The second textured face 102 of the silicon substrate 100 is opposite the p-doped amorphous silicon layer and the first polished face 101 of the silicon substrate 100 is opposite the n-doped amorphous silicon layer.

[0077] Tandem cells can be manufactured according to the following steps: - texture a 6-inch (15.24 cm) n-type silicon 100 substrate, according to the process described above, - deposit by PECVD intrinsic and doped a-Si:H layers (n or p depending on the face) on both sides of the silicon substrate, - deposit 1TTO on the back (i.e., on the first textured face) and possibly recombination TITO on the front face (i.e., on the second polished face), for example by PVD, - deposit the Ag electrode on the back face, for example by thermal evaporation under vacuum. - to form the upper subcell in perovskite on the front face.

[0078] The textured silicon substrate can also be used to manufacture photovoltaic cells with TopCon or PERC technology or for CARLAH structures ('Conductive Anti-Reflective LAyer for High temperature heterojunction') with passivated contacts. Illustrative and non-exhaustive examples

[0079] Initially, 6-inch (15.24 cm) silicon substrates ('wafers') were polished by CMP on the front and back faces. An oxide layer is formed on their surface.

[0080] In the case of native oxide, the substrates are left in the open air in a clean environment.

[0081] In the case of the chemical oxide, they are soaked in a bath of deionized water containing ozone DLO3 (20 to 40 ppm of O3) for a few minutes (2 to 4 minutes) to allow the formation of this oxide.

[0082] The oxide layer formed on the substrates is extremely thin (10 to 16 Å).

[0083] The substrates are then joined in pairs by molecular bonding. To do this, they are placed one on top of the other and then brought into physical contact. Local pressure on the edges of the upper substrate using tweezers maximizes the bond. This step can be carried out under vacuum to improve the bond. Heat treatment can also be applied.

[0084] Once assembled, the substrates are textured: they are placed in a chemical basket and then soaked in a basic solution. The solution contains KOH (concentration greater than 1% by mass) and additives (concentration greater than 0.2% by mass). The temperature of the solution is above 70°C and below 95°C. The substrates are then rinsed and cleaned using an acidic process.

[0085] After the texturing step, tweezers are used to separate the substrates.

[0086] After separation of the substrates, it was observed that the "free" faces which were in contact with the KOH solution were textured while the glued faces were not textured and remained smooth.

[0087] For substrates with the native oxide, only a few areas on the surfaces in contact with each other were slightly damaged due to slight penetration of the etching chemistry (see circled areas in [Fig. 2]). The substrate exhibits less than 5% defect rate.

[0088] By using retaining elements to mechanically hold the two substrates together and close the bonding interface, the percentage of defective surface (i.e., textured when the surface should remain polished) is reduced.

[0089] By way of illustration, [Fig. 3] represents two substrates, the first face of which is coated with native oxide, bonded to each other by molecular bonding and held together to the other by retaining elements (PTFE rings). Figure 4A shows, after separation of the substrates, one of the faces that was bonded. However, these rings can locally hinder texturing and slightly modify the local fluidic properties (Figure 4B).

[0090] Comparative tests were carried out by performing the texturing step on two substrates positioned against each other, not glued together, and held together only by Teflon rings. Physical support alone (via the Teflon rings) does not allow for single-sided texturing: the chemistry is incorporated on the inner faces, and both faces of each substrate are textured at the end of the process.

[0091] By using thermal oxides instead of native oxides, the percentage of defective surface is reduced, even without using retaining elements.

[0092] Following this single-sided texturing process (with implementation of molecular bonding), the detached substrates were passivated by PECVD (with nanometric layers of doped amorphous silicon).

[0093] Various properties of the textured substrates were then measured and compared to the properties of single-sided textured substrates using the conventional method with a silicon nitride barrier layer. In particular, lifetimes were measured by IC-PCD (Inductively Coupled Photo-Conductance Decay) at the center of the substrates. The results are shown in Figures 5, 6, and 7. Photoluminescence images were also obtained, highlighting the homogeneity of the minority carrier lifetimes across the entire surface of the bonded substrates ([Fig. 8]).

[0094] These results highlight the advantages of this single-sided texturing process. In addition to offering numerous implementation benefits, the process produces devices with excellent passivation levels. These passivation levels are similar to those obtained with the reference barrier layer process.

[0095] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0096] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for texturing silicon substrates, the method comprising the following steps: a) providing: - a first silicon substrate (100), comprising a first polished face (101) covered by an oxide layer (110), and a second face (102), and - a second silicon substrate (200) comprising a first polished face (201) covered by an oxide layer (210), and a second face (202), b) joining the first substrate (100) and the second substrate (200) by direct hydrophilic bonding, by bringing the oxide layers (110, 210) of the first substrate (100) and the second substrate (200) into contact, c) bringing the second face (102) of the first substrate (100) into contact with a basic solution, preferably a solution of KOH, NaOH, or TMAH, thereby causing the second face (102) of the first substrate (100) and the second face (202) of the second substrate (200) are textured,d) separate the first substrate (100) from the second substrate (200).

2. A method according to claim 1, wherein the oxide layers (110, 210) are chemical oxide layers, preferably having a thickness between 0.8 nm and 1.8 nm, and preferably between 1.2 nm and 1.6 nm.

3. A method according to claim 1, wherein the oxide layers (110, 210) are thermal oxide layers.

4. A process according to the preceding claim, wherein the thermal oxide is formed by carrying out a heat treatment at a temperature below 400°C, for example at a temperature between 150°C and 300°C.

5. A method according to claim 1, wherein the oxide layers (110, 210) are native oxide layers, having, for example, a thickness of 1 nm.

6. A method according to any one of the preceding claims, wherein, in step c), retaining elements, for example, clips or rings, preferably made of polymer, are used to retain the first substrate (100) and the second substrate (200) against each other.

7. A method according to any one of the preceding claims, wherein the second face (102) of the first substrate (100) and the second face (202) of the second substrate (200) are textured in the form of pyramids (120, 220).

8. Method according to claim 7, wherein the pyramids (120, 220) have a height between 300 nm and 3 pm, preferably between 1 and 2 pm.

9. A method according to any one of the preceding claims, wherein the first substrate (100) and the second substrate (200) are obtained by cutting a silicon ingot using a diamond element, for example a diamond wire, defects, resulting from the cutting step, present on the second face (102) of the first substrate (100) and on the second face (202) of the second substrate (200), being able to be removed by polishing in a KOH solution having, preferably, a concentration greater than 30% by mass.

10. A method for manufacturing a photovoltaic cell, for example a tandem cell, comprising a step in which a silicon substrate (100) is textured by implementing the method according to any one of claims 1 to 9.

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