Epitaxial process from a nucleation layer

Abstract

Title: Epitaxial Process from a Nucleation Layer The invention relates to an epitaxial process from a nucleation layer. A stack (1) is provided, comprising, stacked along a direction called the stacking direction (Z), a support (10), preferably made of silicon, an insulating layer (20), and a semiconductor-based layer, called the nucleation layer (30). The insulating layer (20) has a portion not covered by the nucleation layer (30), called the exposed portion (25). At least a portion of the exposed portion (25) of the insulating layer, called the roughened portion (26), is then roughened, and then epitaxial growth is performed from the nucleation layer (30). Figure for the abstract: Fig. 6C

Description

Title of the invention: Epitaxy process from a nucleation layer. Technical field

[0001] The present invention relates to the fields of microelectronics and optoelectronics. It relates to an epitaxial process using a thin film deposited on a substrate, for example, a thin film of indium phosphide (InP) on a silicon (Si) substrate. The present invention can be used, in particular, for the manufacture of microelectronic or optoelectronic components. Its particularly advantageous applications include high-frequency devices, photonics (3D detection, health monitoring, etc.), and short-wave infrared (SWIR) image sensors. STATE OF THE ART

[0002] Components based on III V materials, and in particular indium phosphide (InP), are increasingly used in microelectronics and optoelectronics. They can be produced using various processes.

[0003] The current commercial solution consists of manufacturing the components directly on a bulk InP substrate, then packaging them into chips. In some technology sectors, these chips are then transferred onto a silicon substrate.

[0004] A more economically and environmentally friendly approach is to deposit a thin InP layer onto a Si wafer, thus forming an InPOSi substrate, and then grow the components directly on this thin layer. This approach offers numerous advantages. For example, the laser systems fabricated in this way exhibit low-loss evanescent optical coupling with the photonic Si of the circuits. They can also be manufactured using dense integration to improve chip performance and reduce manufacturing costs. More generally, when this approach is implemented using Smart Cut™ technology, it reduces manufacturing costs. Indeed, the bulk InP portion from which the InP thin layer is derived can be recycled after bonding and separation.Since InP is an expensive material (approximately €700 per 100 mm diameter wafer), material recycling is a significant advantage. Furthermore, by using InPOSi paved structures, it is possible to consider large substrates, which is not the case with a solid InP substrate, as these substrates currently have a maximum diameter of 150 mm. mm.

[0005] InPOSi substrates can thus be divided into two categories: • InPOSi substrates obtained by full-plate InP transfer (only applicable to small InP bulk substrates, i.e., those with a diameter of 150 mm or less). The substrate thus obtained is illustrated in Figures IA (top view) and IB (cross-sectional view). • InPOSi substrates obtained by discontinuous transfer of InP chips from a pseudo-donor substrate. The InP chips typically form a tiling on the Si substrate, as illustrated in Figures 2A and 2B.

[0006] In both configurations, the InP film does not generally extend to the very edge of the Si wafer. This is due to the presence of bevels at the periphery of the substrates and is characteristic of layer transfer techniques based on the molecular bonding of substrates (wafer bonding), of which Smart Cut™ technology is a part. As illustrated in Figures IA, IB, 2A, and 2B, a dielectric ring 25 with a width on the order of a few millimeters (usually 3 mm) thus extends at the periphery. Furthermore, in the case of an InPOSi substrate with InP tiling, the dielectric is also visible between the InP chips.

[0007] During the epitaxial step performed using the InPOSi substrate, the presence of these inactive areas at the periphery and possibly between the InP chips can generate a SAG (selective area growth) effect, i.e., selective growth of the epitaxial material. This is particularly the case with chemical vapor deposition (CVD) techniques using metal-organic precursors of the MOCVD (Metal-Organic Chemical Vapor Deposition) type. Indeed, two precursor diffusion regimes contribute to the variation in the deposition rate: gas-phase diffusion and surface diffusion, represented by arrows labeled 2 and 3 respectively in [Fig. 3]. These diffusion phenomena cause a variation in the growth rate because both diffusions are dependent on the precursor concentration.As a result, the deposited thicknesses are greater near the dielectric zone, thus resulting in an excess thickness 45 in the vicinity of this zone (see [Fig.3]).

[0008] It is also noted that vapor-phase diffusion 2 has a diffusion length much greater than surface diffusion 3 (several hundred microns versus a few micrometers). These diffusion lengths depend on the epitaxial conditions (epitaxial temperature, gas flow rate, pressure, etc.), the desired epitaxial stacking (nature of the materials, layer thickness, total stacking thickness, etc.), and also on the size of the dielectric mask. Thus, although both phenomena are present, they operate at different scales: the Surface diffusion 3 dominates in the immediate vicinity of the mask, while vapor phase diffusion 2 becomes predominant as one moves away from the mask.

[0009] In the intended applications, the SAG effect is a drawback. It induces overgrowth of epitaxial growth at the InP edge, and even variations in composition. The use of these areas for manufacturing functional components is not possible, which significantly reduces the wafer's usable surface area. This is exacerbated for tiled structures such as those illustrated in Figures 2A and 2B, where the SAG effect occurs even between the InP chips.

[0010] Moreover, for strong epitaxies, the SAG effect will be amplified and may lead to delaminations, crystalline defects, cracks and / or variations in composition, prohibiting the use of the InPOSi substrate.

[0011] The object of the invention is thus to minimize or even eliminate the SAG effect during epitaxy. SUMMARY

[0012] To achieve this objective, a first aspect of the invention relates to an epitaxial process from a nucleation layer comprising the following steps: • provide a stack comprising, stacked according to a so-called stacking direction: • a support, preferably made of silicon, • a layer based on a first electrically insulating material, called the insulating layer, and • a layer based on a semiconductor, called the nucleation layer, the insulating layer having a portion not covered by the nucleation layer, called the exposed portion.

[0013] The process preferably includes the following steps: • to roughen at least part of the exposed portion of the insulating layer, known as the roughened portion, • perform an epitaxy from the nucleation layer.

[0014] The roughened part is located at the level of the crown, at the edge of the wafer, and possibly, in the case of a stack obtained by transferring semiconductor chips, between these chips.

[0015] Roughening the roughened area allows for greater nucleation in this zone. By promoting this nucleation, growth is homogenized during the epitaxial stage, both in terms of thickness and composition of the epitaxial layer. The layer formed by epitaxy thus exhibits a less pronounced overthickness than in prior art, or even a virtually constant thickness. Furthermore, the composition of the epitaxial layer shows less variation. The SAG effect is therefore reduced.

[0016] Thanks to the process according to the invention, the unusable areas for the production of devices are thus reduced or even eliminated.

[0017] A second aspect of the invention relates to a stack comprising, stacked according to a so-called stacking direction: • a support, preferably made of silicon, • a layer based on a first electrically insulating material, called the insulating layer, the insulating layer having a portion, called the roughened part, having an RMS roughness greater than or equal to 0.30 nm, preferably greater than or equal to 0.40 nm • a semiconductor-based layer, called the nucleation layer, preferably based on a III-V material, • a layer based on an epitaxial semiconductor, called the epitaxial layer, extending above the nucleation layer and the roughened portion.

[0018] The advantages described with reference to the method according to the first aspect of the invention apply mutatis mutandis to the stacking according to the second aspect of the invention. BRIEF DESCRIPTION OF THE FIGURES

[0019] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0020] [Fig.1A] [Fig.1B] Figures IA and IB represent a substrate obtained by full-plate transfer of a semiconductor thin film onto a support.

[0021] [Fig.2A] [Fig.2B] Figures 2A and 2B represent a substrate obtained by transferring a thin semiconductor film in the form of a plurality of chips onto a support.

[0022] [Fig.3] Fig.3 illustrates the SAG effect occurring during the epitaxy of a thin film near a dielectric layer.

[0023] [Fig.4A] [Fig.4B] [Fig.4C] [Fig.4D] [Fig.4E] Figures 4A to 4E illustrate a first embodiment of the present invention in which the final epitaxy is carried out from a continuous nucleation layer.

[0024] [Fig.5A] [Fig.5B] [Fig.5C] [Fig.5D] [Fig.5E] Figures 5A to 5E illustrate a second embodiment of the present invention in which the final epitaxy is carried out from a plurality of nucleation chips disjoint from each other.

[0025] [Fig.6A][Fig.6B][Fig.6C] Figures 6A to 6C illustrate an example of achieving the roughening of the oxide layer by depositing a rough layer on the insulating layer.

[0026] [Fig.7A] [Fig.7B] Figures 7A and 7B illustrate the increase in roughness through the deposition of a rough layer on the insulating layer.

[0027] [Fig.8A] [Fig.8B] Figures 8A and 8B illustrate the reduction of the excess thickness of the epitaxial layer near the insulating layer thanks to the prior deposition of a rough layer on the insulating layer.

[0028] [Fig.9A] [Fig.9B] Figures 9A and 9B illustrate an example of carrying out the roughening of the oxide layer by creating grooves in the latter.

[0029] [Fig.10A][Fig.10B] Figures 10A and 10B are explanatory diagrams illustrating the increase in nucleation at the level of inactive areas and thus the reduction of the SAG effect thanks to the present invention.

[0030] [Fig.llA][Fig.llB][Fig.llC] Figures 11A to 11C illustrate the roughening of the support and the transfer of roughness to the insulating layer formed on the support.

[0031] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0032] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0033] Advantageously, the roughening step is configured to impart to the roughened part an RMS roughness greater than or equal to 0.30 nm, and preferably greater than or equal to 0.40 nm. Preferably, the roughening step is configured to impart to the roughened part an RMS roughness greater than or equal to 0.50 nm, preferably 60 nm, preferably 80 nm, or even 1 µm. When the roughening step is implemented by certain methods such as saw structuring, the roughening step can be configured to impart to the roughened part an even greater RMS roughness, for example, greater than or equal to 2 µm, or for example, equal to 3 µm.

[0034] Preferably, in a transverse plane substantially perpendicular to the stacking direction, the roughened part extends from the nucleation layer.

[0035] Advantageously, the roughened portion extends from the nucleation layer over a dimension L26, with L26 > 30 pm, preferably L26 > 40 pm, preferably L26 > 100 pm, for example L26 = 200 pm. L26 may typically be equal to L25, the dimension of the exposed portion.

[0036] Advantageously, the roughened part surrounds the nucleation layer, preferably entirely.

[0037] According to an advantageous example, the nucleation layer is based on a III-V material, for example InP, GaAs or GaN.

[0038] According to one embodiment, the roughening step includes the formation, in contact with the insulating layer, of a so-called roughening layer based on a second electrically insulating material, preferably identical to the first electrically insulating material.

[0039] According to one example, the formation of the roughening layer comprises the following steps: • Apply the roughening layer to the stack, • Remove, selectively with respect to the nucleation layer, the roughening layer in areas where it covers the nucleation layer, leaving it in place in areas where it directly covers the insulating layer.

[0040] According to an alternative example, the formation of the roughening layer is carried out using a photolithography process, after masking the nucleation layer.

[0041] According to another embodiment, the formation of the roughening layer is configured so that the roughening layer extends at least partially over the nucleation layer. The roughening layer is then deposited on an area of ​​the nucleation layer extending from the exposed part of the insulating layer. This allows for better anchoring of the nucleation layer and thus further limits the risk of delamination during subsequent steps, particularly during the epitaxy step.

[0042] According to one example, the roughening step further includes the removal of the roughening layer. During the removal of the roughening layer, its roughness is transferred to the exposed portion of the underlying insulating layer. This forms the roughened portion of the insulating layer.

[0043] According to one example, the second electrically insulating material is SiO2.

[0044] According to one embodiment, the roughening step includes a surface roughening treatment applied to at least a part of the exposed portion of the insulating layer.

[0045] According to one embodiment, the roughening step comprises, in the stack supply step, the following steps: • provide support, • perform a surface roughening treatment applied to the substrate, then • deposit the insulating layer and the nucleation layer onto the support.

[0046] According to one example, the roughening treatment includes subjecting the patient to laser radiation.

[0047] According to one example, the roughening treatment includes an ion bombardment step.

[0048] According to one example, the roughening treatment includes at least one of the following treatments: saw structuring, water jet structuring, milling, chemical etching, plasma etching.

[0049] According to one example, the support is silicon-based.

[0050] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. The selectivity is the ratio between the etching speed of material A and the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0051] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0052] A layer may also be composed of several sub-layers of the same material or of different materials.

[0053] The term "IILV material" refers to a semiconductor composed of one or more elements from columns III and V of the Mendeleev periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus. The term "ILVI material" refers to a semiconductor composed of one or more elements from columns II and VI of the Mendeleev periodic table, while the term "IV-IV material" refers to a semiconductor composed of at least two elements from column IV of the Mendeleev periodic table.

[0054] A substrate, layer, or device "based on" a material M is understood to mean a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example, alloying elements, impurities, or dopant elements. Thus, a material based on a material IIIN may comprise a material IIIN with added dopants.

[0055] A material is said to be "electrically conductive" when it has an electrical conductivity preferably greater than 108 S / m.

[0056] A material is said to be "electrically insulating" when it has a conductivity preferably less than 10⁸ S / m or a resistivity greater than 10⁸ Ωm

[0057] A coordinate system, preferably orthonormal, comprising the X, Y, and Z axes is shown in [Fig. 6A]. This coordinate system is applicable by extension to the other figures. The direction along the Z axis is typically designated the Z stacking direction.

[0058] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the transverse plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along Z when it extends mainly along the transverse plane XY, and a projecting element, for example a trench, has a height along Z. The relative terms "on," "under," and "below" preferentially refer to positions measured along the Z direction.

[0059] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0060] RMS roughness corresponds to the root mean square of the microscopic peaks and troughs measured on a surface. It is classically measured using an atomic force microscope (AFM) over a 1 pm x 1 pm field.

[0061] The method according to the invention will now be described in more detail.

[0062] A first embodiment is illustrated in Figures 4A to 4E. This first embodiment of The process employs a substrate obtained by full-plate transfer of a semiconductor layer onto a support.

[0063] A first phase of the process consists of forming a thin semiconductor film on a support. This first phase can notably be carried out using a Smart Cut™ process, as illustrated in Figures 4A to 4E and described in detail below.

[0064] A donor substrate 100 having a top face 101 is first provided ([Fig. 4A]). The donor substrate 100 is based on a semiconductor material, for example, ILVI, III-V (typically InP, GaN, or GaAs), or IV-IV. A coating 20' based on an electrically insulating material (for example, SiO2), called the dielectric coating 20', can then be deposited on the top face 101 of the donor substrate 100 ([Fig. 4B]). Ion implantation, for example of hydrogen ions H+ and / or helium ions, is then carried out in the donor substrate 100 ([Fig. 4C]). As illustrated in [Fig. 4D], a receiving substrate, also referred to as support 10, is then provided. This is typically a silicon substrate that has undergone thermal oxidation and thus has an oxide coating 20”. The donor substrate 100 is then bonded to the support 10 via the dielectric coating 20' and the oxide coating 20”.This . The assembly is, for example, achieved by hydrophilic bonding. It is possible to introduce other bonding layers between the dielectric coating 20' and the oxide coating 20”. It is also possible that there is no intermediate bonding coating or only one of the dielectric coating 20' and the oxide coating 20”, in which case the bonding is achieved respectively between the donor substrate 100 and the oxide coating 20” or between the dielectric coating 20' and the support 10.

[0065] As illustrated by the transition from [Fig. 4D] to [Fig. 4E], the donor substrate 100 then undergoes annealing, allowing its fracture at the previously performed ion implantation. This fracture leaves only a thin film of semiconductor on the support 10. The remainder of the donor substrate 100 can be retained for a further iteration of the process according to the invention.

[0066] This gives us the stacking 1 illustrated in [Fig.4E] comprising: • Support 10, typically silicon-based, • An insulating layer 20 extending between the support 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20', • A nucleation layer 30, corresponding to the thin film left on the support after fracture of the donor substrate 100.

[0067] The nucleation layer 30 has a thickness e30 measured along the stacking direction Z. e30 is typically less than or equal to 5 pm.

[0068] Alternatively, stack 1 can be obtained by a conventional disassembly technique (not illustrated). In this variant, the donor substrate 100 is not implanted and then fractured. After bonding to the support 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 100 undergoes, for example, mechanical thinning by milling (grinding) and / or a CMP (chemical-mechanical polishing) step to thin it to the desired thickness e30. Stack 1 is then obtained.

[0069] Regardless of the method used to obtain the stack 1, in a completely conventional manner, the nucleation layer 30 has lateral dimensions smaller than those of the insulating layer 20 and the support 10. Thus, in the transverse plane XY, the insulating layer 20 extends beyond the nucleation layer 30. In other words, the insulating layer 20 has a portion 25 not covered by the nucleation layer 30. This portion is called the exposed portion 25. It extends over a dimension L25 from the nucleation layer 30. In the conventional case where the insulating layer 20 and the nucleation layer 30 each have a substantially circular shape in the transverse plane XY, the exposed portion 25 extends radially around the nucleation layer 30 and completely surrounds it. The dimension L25 is then measured radially around the nucleation layer 30. L25 is, for example, greater than or equal to 500 pm, for example greater than or equal to 1 mm or even 5 mm.

[0070] At this stage, various treatments may be carried out as appropriate (cleaning, heat treatment, CMP, ...) in order to prepare the nucleation layer 30 for epitaxy.

[0071] In the case of the Smart Cut™ process, a CMP step can be performed to remove the fracture zone, i.e. the area at which the ions had been implanted and the fracture of the donor substrate 100 took place.

[0072] The invention provides at this stage for roughening at least part of the exposed portion 25, referred to as the roughened portion 26. The roughening step will be described further.

[0073] A second embodiment is illustrated in Figures 5A to 5E. This second embodiment uses a substrate obtained by transferring a semiconductor layer in the form of a plurality of chips onto a support.

[0074] This second embodiment is particularly advantageous in that it is compatible with supports 10 with a diameter of 200 mm as well as 300 mm.

[0075] First, a so-called pseudo-donor substrate is provided, comprising a support 1000 surmounted by a discontinuous donor substrate 100, forming a plurality of donor chips 150 ([Fig. 5A]). The discontinuous donor substrate 100, and therefore the donor chips 150, are based on a semiconductor material, for example, ILVI, III-V (typically InP), or IV-IV.

[0076] A coating 20' based on an electrically insulating material (for example SiO2), called a dielectric coating 20', can then be deposited on the donor chips 150 ([Fig.5B]). This coating is optional.

[0077] In the case of a Smart Cut™ process, ion implantation, for example of hydrogen ions H+ and / or helium ions, is then carried out in the donor substrate 100 ([Fig. 5C]). As illustrated in [Fig. 5D], a receiving substrate, also referred to as support 10, is then provided. As in the first embodiment, this is typically a silicon substrate, optionally coated with an oxide layer 20”. The donor chips 150 are then bonded to the support 1000 via the dielectric layer 20' and the oxide layer 20”. This assembly is, for example, achieved by hydrophilic bonding. It is possible to introduce other bonding layers, for example between the dielectric layer 20' and the oxide layer 20”.

[0078] As illustrated by the transition from [Fig. 5D] to [Fig. 5E], the donor chips 150 then undergo thermal annealing, allowing them to fracture at the previously performed ion implantation. This fracture makes it possible to retain a discontinuous, semiconducting thin film is deposited on the support 10, thus forming a plurality of semiconductor chips. The remaining donor chips 150 can be retained for a further iteration of the process according to the invention.

[0079] This gives us the stacking 1 illustrated in [Fig.5E] comprising: • Support 10, typically silicon-based, • An insulating layer 20 extending between the support 10 and the nucleation layer 30 and formed from a portion of the oxide coating 20” and the dielectric coating 20', • A nucleation layer 30, corresponding to the discontinuous thin film left on the substrate after fracture of the donor chips 150. The nucleation layer 30 is thus formed from a plurality of semiconductor chips 35.

[0080] The semiconductor chips 35 have a dimension l30. In the case of square-shaped chips in the transverse XY plane, l30 corresponds to their side. l30 is typically greater than or equal to 0.3 cm, for example, approximately equal to 1 cm.

[0081] The semiconductor chips 35 are also spaced apart by an inter-chip distance dinter- dinter is typically greater than or equal to 100 pm, for example substantially equal to 250 pm.

[0082] As in the first embodiment, alternatively, the stacking Stack 1 can be obtained by a conventional disassembly technique (not illustrated). In this variant, the donor chips 150 are not implanted and then fractured. After bonding to the support 10 via the dielectric coating 20' and optionally the oxide coating 20", the donor substrate 100 undergoes mechanical thinning, for example by milling and / or a CMP (chemical-mechanical polishing) step to reduce it to the desired thickness e30. This results in stack 1.

[0083] As in the first embodiment, before carrying out an epitaxial step to form an epitaxial layer 40 from the nucleation layer 30, the invention provides for carrying out a roughening to limit or even eliminate the SAG effect.

[0084] Several roughening techniques that can be used within the framework of the present invention will now be described with reference to Figures 6A to 1 IC.

[0085] The objective of these different roughening techniques is to form the roughened portion 26 of the insulating layer 30. This roughened portion 26 extends over a dimension L26 from the nucleation layer 30. In the classical case where the insulating layer 20 and the nucleation layer 30 each have a substantially circular shape in the transverse plane XY, the roughened portion 26 extends radially around the nucleation layer 30 and completely surrounds it. The dimension L26 is then measured radially around the nucleation layer 30.

[0086] According to a first example illustrated by Figures 6A to 6C, roughening is achieved by depositing a layer with advantageous roughness, designated the roughening layer 27, onto the exposed portion 25. Figure 6A is an enlargement of Figure 4E or Figure 5E at the level of the exposed portion 25 of the insulating layer 20. Figures 6B and 6C illustrate the formation of the roughening layer 27 on the exposed portion 25. In the figures, the roughening layer 27 is deposited over the entire width of the exposed portion 25, and the roughened portion 26 therefore corresponds to the entire exposed portion 25 (L26 is then equal to L25), but it is understood that the roughening layer can be deposited on only a portion of the exposed portion 25. The roughened portion 26 corresponds in all cases to the portion of the exposed portion 25 covered by the roughening layer 27.

[0087] Furthermore, in the case of a discontinuous nucleation layer 30, the roughening layer 27 can be deposited at the level of the portions of the insulating layer 20 apparent between the semiconductor chips 35.

[0088] The roughening layer 27 is based on a second electrically insulating material, typically a dielectric material such as SiO2.

[0089] The roughening layer 27 is advantageously formed by plasma-enhanced chemical vapor deposition (PECVD). The roughening layer 27 can initially be deposited directly onto the exposed portion 25 and onto the nucleation layer 30 ([Fig. 6B]). The portion of the roughening layer 27 covering the nucleation layer 30 can then be removed by an HF deoxidation step ([Fig. 6C]). Since the selectivity of the SiO2 removal chemistry relative to InP is very high, it is advantageous to opt for a SiO2-based roughening layer 27 when the nucleation layer 30 is InP-based. Good selectivity between the material of the roughening layer 27 and that of the nucleation layer 30 allows the roughening layer 27 to be deposited in a full plate manner and to avoid certain photolithography and etching steps.This reduces the number of steps required, and therefore the complexity and cost of the process.

[0090] However, it is also possible to deposit the nucleation layer through a lithography mask so as to deposit it only on the exposed part 25 (transition from [Fig.6A] to [Fig.6C] directly).

[0091] The roughening layer 27 has a thickness e27 measured along the stacking direction Z. When the roughening layer 27 extends only over the exposed portion 25, e27 is typically configured so that the rough area of ​​the layer rugosification layer 27 is found to be substantially level with the upper face 31 of the nucleation layer 30.

[0092] It is also possible to retain a portion of the roughening layer 27 deposited on the nucleation layer 30. Typically, the roughening layer 27 then overlaps the nucleation layer 30 over a width of 10 to 30 pm from the exposed portion 25 of the insulating layer 20 (width typically measured radially in the transverse XY plane). Depositing and retaining the roughening layer 27 on a portion of the nucleation layer 30 creates an additional anchoring effect for the nucleation layer 30, which helps to limit or even prevent delamination during subsequent steps, particularly during the epitaxy step. In this particular example, preferably, the roughening layer 27 is continuous. Thus, the portion of the roughening layer 27 overlapping the insulating layer 20 and the portion overlapping the nucleation layer 27 are continuous. This allows for better anchoring of the nucleation layer 30.

[0093] The roughening layer 27 thus deposited has a much higher roughness than the exposed portion 25, which has generally undergone a CMP step. The roughening layer 27 therefore roughens the exposed portion 25, thereby facilitating nucleation during epitaxy.

[0094] Figures 7A and 7B are reproductions of images obtained by atomic force microscopy (AFM) illustrating the increase in roughness due to the PECVD deposition of SiO2 on the exposed area 25. Figure 7A shows the surface of the exposed area 25 before deposition of the roughening layer 27. The exposed area 25 underwent a CMP step and thus exhibits a very low RMS roughness of 0.15 nm. Figure 7B is centered on the same area, this time after deposition of the roughening layer 27 and deoxidation. It can be seen that the RMS roughness has more than doubled and increased to 0.41 nm.

[0095] Epitaxy was then performed on these same samples. Figures 8A and 8B, illustrating the results obtained, are images obtained by optical microscopy. It was observed that when epitaxy is performed on a sample without a roughening layer 27 ([Fig. 8A]), the thickness in the vicinity of the insulating layer (14.38 pm) is significantly greater than that observed when a roughening layer 27 is deposited (8.56 pm, [Fig. 8B]). These experimental results demonstrate the reduction of the SAG effect by roughening the exposed area 25.

[0096] According to another example, the roughening layer 27 deposited on the exposed part 25 is removed after its deposition by non-selective etching with respect to the insulating layer 20. The removal etching then makes it possible to transfer the roughness of the roughening layer 27 to the exposed part 25, thus forming the roughened part 26 directly on the insulating layer 20.

[0097] This embodiment allows, for example, the full-plate deposition and subsequent removal of the roughening layer 27, which, provided that materials with adequate selectivity are selected, eliminates the need for any photolithography step. This reduces the number of steps required and therefore the complexity and cost of the process.

[0098] According to another example, the roughening layer 27 does not have the advantageous roughness when it is deposited but undergoes a surface treatment enabling its roughening after its deposition on the exposed part 25. This surface treatment can be taken from those described below with reference to a direct roughening of the exposed part 25.

[0099] It is possible to roughen the exposed part 25 in other ways. For example, it is possible to carry out a surface treatment allowing the roughening of at least part of the exposed part 25, thus forming the roughened part 26.

[0100] Several surface treatments are possible for this purpose.

[0101] According to an illustrated example, laser treatment is carried out on the exposed part 25. In this example, the laser locally melts the first electrically insulating material (typically SiO2), enabling the roughening of the exposed area 25. The laser radiation is applied to the exposed area 25 according to a predetermined map, allowing for the desired roughening. Advantageously, the laser used is a nanosecond laser.

[0102] According to another example, the surface treatment is ion bombardment, for example using localized ion beams. During bombardment, the nucleation layer 30 can be protected by a resin or a hard mask (for example a layer of SiO2 or SiN) produced by prior photolithography steps.

[0103] According to another example, the exposed portion is roughened by a mechanical surface treatment. Possible treatments include sawing, waterjet cutting, and milling. In each of these cases, a series of grooves is formed in the exposed portion 25, typically to a depth of a few tens of micrometers. Figures 9A and 9B are photographs showing the result of roughening an insulating layer 20 by creating grooves 10 µm deep. The grooves may, if necessary, extend through the entire thickness of the insulating layer 20 or even cut into part of the underlying layer. Figure 9B, in particular, illustrates the area at the edge of the plate, where the substrate 10, the insulating layer 20, and the nucleation layer 30 are visible.

[0104] The exposed part can also be roughened by implementing an engraving process, possibly combined with one or more masking steps. For example, networks of dots or lines, or even grids, can be created. surface of the exposed part. This may include chemical etching or plasma etching.

[0105] Advantageously, the nucleation layer 30 is protected during any surface treatment, for example by a resin or a hard mask (for example a layer of SiO2 or SiN).

[0106] The possible mask used to protect the nucleation layer is then removed by an HF process.

[0107] It is then possible to carry out a CMP or chemical cleaning step to reduce the defect induced by the roughening step by mechanical treatment.

[0108] Samples were roughened by saw structuring, and then epitaxy was performed from the nucleation layer. The wafer edges were then analyzed, and the following results were obtained: thanks to saw roughening, the thickness of the epitaxial layer 40 near the insulating layer was reduced from 12 pm to 8.5 pm. A reduction in the SAG effect is therefore observed.

[0109] Figures 10A and 10B are diagrams explaining more precisely the increase in nucleation at the level of the insulating layer due to its roughening.

[0110] Figure 10A illustrates the stacking obtained after epitaxy on a stack of art Previously, it was observed that the insulating layer 20 was particularly smooth and therefore only allowed a very low density of crystals to grow. These two factors resulted in a high concentration of growth at the edge of the nucleation layer 30.

[0111] Figure 10B illustrates the stacking obtained after epitaxy on a The stack according to the present invention has undergone roughening at the level of the insulating layer 20. This roughening allows for better adhesion and therefore better crystal growth during epitaxy. Furthermore, the roughening typically has the effect of making the lateral edge of the nucleation layer 30 more abrupt. These two characteristics help to homogenize the thickness of the epitaxial layer.

[0112] The various surface treatments presented above for roughening the exposed part 25 of the insulating layer 20 can be used alone or in combination.

[0113] According to an alternative embodiment, the roughening surface treatment is applied to the substrate 10 rather than to the insulating layer 20. Indeed, during the formation of the insulating layer 20 on the substrate 10, the roughness of the substrate 10 will then be transferred to the insulating layer 20. Figures 11A to 11C illustrate the transfer of roughness: [Fig. 11A] shows the supply of the substrate 10 alone, [Fig. 11B] the roughening of its upper face 11, and finally [Fig. 11C] the formation of the insulating layer 20, for example by oxidation. It can be observed that the upper face 21 of the insulating layer 20 opposite the upper face 11 of the support 10 is roughened at the level of the portions surmounting the portions of the support 10 which are themselves roughened.

[0114] Thus, surface treatment can, for example, be carried out: • in the case of a full plate nucleation layer 30: i. before the support provision step 10 illustrated in Figure 6D, or ii. just before the epitaxial stage, • in the case of a nucleation layer 30 in the form of a plurality of nucleation chips 150 i. before the support provision step 10 illustrated in Figure 7D, or ii. just before the epitaxy stage.

[0115] When the roughening of the insulating layer 20 is performed by laser, it is particularly advantageous to carry out this step before the transfer of the semiconductor layer. This increases the safety level of the process. Furthermore, it has been shown that the topology produced by laser structuring is very well transferred from the support 10 to the insulating layer 20 during oxidation. Good results have, for example, been obtained by structuring the support 10 with a laser with a power of 1.9 J / cm².

[0116] It appears from the various embodiments described above that the present invention offers an effective solution for reducing the SAG effect. It thus allows the fabrication of high-quality stacks over a larger area, which can be used to manufacture microelectronic and optoelectronic components.

[0117] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Demands

1. Epitaxial process from a nucleation layer comprising the following steps: • provide a stack (1) comprising, stacked in a direction called stacking (Z): i. a support (10), preferably of silicon, ii. a layer based on a first electrically insulating material, called insulating layer (20), and iii. a layer based on a semiconductor, called nucleation layer (30), preferably based on a III-V material, the insulating layer (20) having a portion not covered by the nucleation layer (30), called exposed portion (25), • perform a roughening of at least a part of the exposed portion (25) of the insulating layer, called the roughened portion (26), • perform an epitaxial process from the nucleation layer (30).

2. A method according to the preceding claim wherein the roughening step is configured to impart to the roughened part an RMS roughness greater than or equal to 0.40 nm.

3. A method according to any one of the preceding claims wherein, in a transverse plane (XY) substantially perpendicular to the stacking direction (Z), the roughened part (26) extends from the nucleation layer (30).

4. A method according to the preceding claim in which the roughened part (26) extends from the nucleation layer (30) over a dimension L26, with L26 > 30 pm, preferably L26 > 40 pm, preferably L26 > 100 pm, for example L26 = 200 pm.

5. A method according to any one of the preceding claims wherein the roughened portion (26) surrounds the nucleation layer (30), preferably entirely.

6. A method according to any one of the preceding claims wherein the nucleation layer is InP-based.

7. A method according to any one of the preceding claims wherein the roughening step comprises the formation, in contact with the insulating layer, of a so-called roughening layer (27) based on a second electrically insulating material, preferably identical to the first electrically insulating material.

8. A method according to the preceding claim in which the formation of the roughening layer (27) is configured so that the roughening layer (27) extends at least partially over the nucleation layer (30).

9. A method according to any one of claims 7 and 8 wherein the second electrically insulating material is SiO2.

10. A method according to any one of claims 7 to 9 wherein the roughening step further comprises the removal of the roughening layer (27).

11. A method according to any one of claims 1 to 6 wherein the roughening step comprises a surface roughening treatment applied to at least a part of the exposed portion of the insulating layer.

12. A method according to any one of claims 1 to 6 wherein the roughening step comprises, in the stack supply step, the following steps: • supplying the support, • performing a surface roughening treatment applied to the support, and then • depositing the insulating layer and the nucleation layer on the support.

13. A method according to any one of claims 11 and 12 wherein the roughening treatment comprises subjecting to laser radiation.

14. A method according to any one of claims 11 to 13 wherein the roughening treatment comprises an ion bombardment step.

15. A method according to any one of claims 11 to 14 wherein the roughening treatment comprises at least one of the following treatments: saw structuring, water jet structuring, milling, chemical etching, plasma etching.

16.

17. A method according to any one of the preceding claims, wherein the support is silicon-based. Stacking (1) comprising, stacked along a so-called stacking direction (Z): • a support (10), preferably made of silicon, • a layer based on a first electrically insulating material, called the insulating layer (20), the insulating layer (20) having a portion, called the roughened part (26), having an RMS roughness greater than or equal to 0.40 nm, • a layer based on a semiconductor, preferably a III-V material, called the nucleation layer (30), • a layer based on an epitaxial semiconductor, called the epitaxial layer (40), extending above the nucleation layer (30) and the rugosified part (26).