III-Nitride power semiconductor based heterojunction device comprising a bootstrap device

Abstract

A III-nitride power semiconductor based heterojunction device includes a first active heterojunction transistor 20, e.g. a Gallium Nitride (GaN) transistor, a first voltage supply node VDDL, a second

Description

HI-NITRIDE POWER SEMICONDUCTOR BASED HETEROJUNCTION DEVICE COMPRISING ABOOTSTRAP DEVICE Field of the Disclosure The present disclosure relates to a lll-nitride power semiconductor based heterojunction device comprising a bootstrap device. Background of the Disclosure Gallium Nitride (GaN) is a wide band gap material suitable for power and RF semiconductor devices. GaN technology allows the design of transistors with high electron mobility and a high saturation velocity, both of which are, generally, useful traits in the field of power and Radio-Frequency (RF) electronics. The use of GaN material has additional advantages in power devices. For example, the wide band gap of the material (Eq=3.39eV) results in high critical electric field (E.=3.3MV / cm), which can allow the design of devices with a shorter drift region (and therefore a lower on- state resistance) compared to silicon-based devices with the same breakdown voltage. The use of an Aluminium Galium Nitride (AIGaN) / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high carrier mobility values (e.g. u=2000cm?(Vs)). In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure can result in a high electron density in the 2DEG layer (e.g. 1 x 10™ cm). These properties allow the development of High Electron Mobility Transistors (HEMTs) with very competitive performance parameters. An extensive amount of research has focused on the development of power devices using AlGaN / GaN heterostructures, resulting in several technologies that enable normally on (Schottky gate based technology) and normally off (insulated gate and p-GaN gate technology) HEMT devices. It will be understood that normally off devices may also be referred to as enhancement mode devices, while normally on devices may also be referred to as depletion mode devices. Power devices (including GaN power devices) are often used in a half bridge circuit configuration as illustrated in Figure 1. A half bridge is a common building block of power electronic circuits and in specific topologies may find use in various applications, for example DC-DC conversion, power factor correction, motor drives etc. The half bridge comprises a low side transistor 20 and a high side transistor 21 in series. One challenge in a half bridge circuit is to provide a supply voltage for the gate driving circuit of the high side. In prior art, a bootstrap diode may be commonly used as illustrated in Figure 2. In this circuit, the high side voltage supply will be lower than the low side voltage supply by the forward voltage drop of the diode used. As such it may be important for the diode to have a small forward voltage drop. This diode may be monolithically integrated with the low side power transistor in a single package. In the case of GaN power devices, a lateral GaN diode may be monolithically integrated with the main power GaN device to provide this function. Different types of GaN diodes and rectifiers have been reported in prior art. Lateral GaN-on-Si HEMT based diodes / rectifiers are attractive due to low cost of manufacturing and the option of monolithic integration with the GaN power device and other components. In general, they offer high switching speed and low form factor (low size dimensions) mainly due to their compact drift region, where most of the blocking voltage is supported. A GaN HEMT diode could be built by using a HEMT device with its gate connected to the source and forming the anode terminal of the diode and the drain forming the cathode terminal of the diode. The HEMT could use a p-GaN gate. A GaN HEMT diode as described, commonly has a forward voltage drop of around 1.5V which can be considered too large. Alternatively, a lateral GaN Schottky diode may be used which can offer a reduced forward voltage drop but likely at the cost of increased off-state leakage as a trade-off. Summary The invention disclosed describes a Ill-nitride power semiconductor based heterojunction device (such as a GaN Chip) with a bootstrap device which may be monolithically integrated with an active heterojunction transistor (e.g. a GaN power transistor). The bootstrap device can provide a high side supply voltage in a half bridge configuration, with a negligible (i.e. close to zero) voltage drop between the low side voltage supply (first voltage supply) and high side voltage supply (second voltage supply). To eliminate the voltage drop between the low side voltage supply and the high side voltage supply, a bootstrap device connected (e.g. in series) between the low side voltage supply and the high side voltage supply may be actively driven under certain conditions. The decision to actively drive the bootstrap device may be dependent on the drain-to-source voltage of the low side (first) transistor in a half bridge configuration. The drain-to-source voltage of the low side transistor may be inferred from the gate driving signal of the low side transistor, that is when the gate driving signal is high it may be assumed that the drain-to-source voltage of the low side transistor is low (e.g. <5V). Nevertheless, some time delay may be present between the gate driving signal of the low side transistor going high and drain-to-source voltage of the low side transistor going low. This delay may lead to the bootstrap circuit being actively driven even though the drain-to-source voltage of the low side transistor is still high, leading to a discharge (or partial discharge) of the high side supply. A more accurate indication of the drain-to-source voltage across the low side (first) transistor may be provided by sensing the voltage directly by including a sense circuit (also referred to as a sensing circuit) configured to sense the drain-to-source voltage of the low side transistor. Described herein is lll-nitride power semiconductor based heterojunction device comprising: a first active heterojunction transistor, the first active heterojunction comprising a first active heterojunction transistor source terminal and a first active heterojunction drain terminal; a first voltage supply node; a second voltage supply node; a sense circuit connected between the first active heterojunction transistor source terminal and the first active heterojunction transistor drain terminal, the sense circuit being configured to sense a voltage between the first active heterojunction transistor drain terminal and the first active heterojunction transistor source terminal; a bootstrap device connected between the first voltage supply node and the second voltage supply node, the bootstrap device comprising a bootstrap transistor; wherein the sense circuit is configured to modulate the bootstrap device such that: when the voltage between the first active heterojunction transistor drain terminal and the first active heterojunction source terminal is below a threshold value, the bootstrap transistor is in an on state operation; and when the voltage between the first active heterojunction transistor drain terminal and the first active heterojunction source terminal is greater than or equal to the threshold value, the bootstrap transistor is in an off state operation. Advantageously, the sense circuit can provide a more accurate indication of the voltage between the first active heterojunction transistor drain terminal and the first active heterojunction transistor source terminal in comparison to an inference of said voltage based on a gate driving signal of the first active heterojunction transistor. The first active heterojunction transistor may comprise: a first active heterojunction transistor source terminal, a first active heterojunction transistor drain terminal, and a first active heterojunction transistor gate terminal. The bootstrap transistor may be a heterojunction transistor. The bootstrap transistor may comprise a bootstrap transistor source terminal, a bootstrap transistor drain terminal, and a bootstrap transistor gate terminal. The sense circuit may be connected in parallel between the first active heterojunction transistor source terminal and the first active heterojunction transistor drain terminal. The lll-nitride power semiconductor based heterojunction device described herein may further comprise a second active heterojunction transistor. The first active heterojunction transistor and the second active heterojunction transistor may be arranged in a half bridge configuration. The second active heterojunction transistor may comprise: a second active heterojunction transistor source terminal, a second active heterojunction transistor drain terminal, and a second active heterojunction transistor gate terminal. The first voltage supply node may be a low side voltage supply node. The first voltage supply node may be connected to a first voltage supply, which may be a low side voltage supply (e.g. in a half bridge configuration). The second voltage supply node may be a high side voltage supply node. The second voltage supply node may be connected to a second voltage supply, which may be a high side voltage supply (e.g. in a half bridge configuration). For example, the first (low) voltage supply may be a voltage supply that powers a gate driver, gate controller, or power IC on a low side of a half bridge configuration (e.g. to control a gate of the first active heterojunction transistor). A capacitor may be connected between the first voltage supply node and the first active heterojunction transistor source terminal. For example, the second (high) voltage supply may be a voltage supply that powers a gate driver, gate controller, or power IC on a high side of a half bridge configuration (e.g. to control a gate of the second active heterojunction transistor). A capacitor may be connected between the second voltage supply node and the second active heterojunction transistor source terminal. Merely as an example, the threshold value may be approximately 5 V. It will be appreciated that the first active heterojunction transistor also be referred to as a main power transistor. In an example, the first active heterojunction transistor may comprise a power high- electron-mobility transistor (HEMT), such as a pGaN gate HEMT. The first active heterojunction transistor may comprise an AlGaN layer and a GaN layer forming a heterojunction where a two dimensional electron gas (2DEG) is present. The 2DEG may act as a conduction path during the on-state operation of the transistor. The HEMT may further comprise a transition layer, a silicon substrate, a substrate terminal, passivation layers, a source terminal, a drain terminal, a gate terminal, and a highly p- doped GaN layer. In some example implementations, the first active heterojunction transistor may be a lateral three-terminal device with an AlGaN / GaN heterostructure grown epitaxially on a standard silicon (Si) wafer. The transition layer may facilitate the growth of a high quality GaN layer despite the significant lattice mismatch between the GaN and Si layers. Carbon p-type doping is often added in the GaN layer. Finally, a thin and patterned GaN layer may be provided to form a gate with a Magnesium (Mg) p-type doping density greater than 1x10'%cm=. An example pGaN gate device with this construction may have a threshold voltage of ~1.5 - 2V and maximum allowable gate bias voltage of < 8V. The first active heterojunction transistor may comprise a first active heterojunction transistor gate terminal. The second active heterojunction transistor may comprise a second active heterojunction transistor gate terminal. The lll-nitride semiconductor based heterojunction device may further comprise a first gate driver connected to the first active heterojunction transistor gate terminal, the first gate driver being further connected to the first voltage supply node. The lll-nitride semiconductor based heterojunction device may further comprise a second gate driver connected to the second active heterojunction transistor gate terminal, the second gate driver being further connected to the second voltage supply node. It will be appreciated that the first gate driver may be referred to as a low side gate driver, and that the second gate driver may be referred to as a high side gate driver. The first and second gate drivers may be configured to drive (i.e. control) the gate terminals of the first and second active heterojunction transistors, respectively. The sense circuit may comprise a sense transistor. The sense transistor may comprise a sense transistor source terminal, a sense transistor drain terminal, and a sense transistor gate terminal. For example, the sense transistor may comprise a heterojunction transistor. The sense circuit may further comprise a sense load. The sense transistor source terminal may be connected to the sense load. The sense transistor drain terminal may be connected to the first active heterojunction transistor drain terminal. In some examples, the sense transistor may have a similar architecture to the first active heterojunction transistor. For example, the sense transistor and first active heterojunction transistor may have substantially identical structures. However, the sense transistor may be scaled to a different area or gate perimeter than the main power transistor by a given scale factor X. The scale factor X being larger than 1 means that the sense transistor is smaller than the main power transistor by that factor. For example, a scale factor of 2 would mean that the area or gate perimeter of the main heterojunction is twice the size of the sense transistor. Conversely, a scale factor less than 1 would mean that the sense transistor is larger than the main power transistor. In some examples, X is at least 20. In some examples, X is at least 50. The sense transistor gate terminal may be connected to a fixed voltage, for example a regulated fixed voltage rail. The regulated fixed voltage rail may be provided externally or using an on-chip voltage regulator. In some examples, the sense transistor gate terminal may be connected to a switching voltage. The switching voltage may be the gate drive signal of the first active heterojunction transistor, or may be a level-shifted version of a gate drive signal (e.g. from the first gate driver). In some examples, the sense transistor gate terminal may be connected to an analog voltage signal or a variable voltage signal. The sense load may comprise a resistor. The resistor may comprise any suitable structure, such as a 2DEG, metal, or other material or layers (e.g. SiCr). The sense circuit may be configured to modulate the bootstrap device via a signal. For example, the sense circuit may generate a signal, and transmit the signal to the bootstrap device. The lll-nitride power semiconductor based heterojunction device may further comprise a signal conditioning circuit. The sense circuit may be configured to modulate the bootstrap device via a signal transmitted through the signal conditioning circuit. The signal conditioning circuit may comprise an inverter. In some examples, the inverter comprises an enhancement mode transistor and a current source. In some examples, the inverter is configured to be powered via the first voltage supply node. In some examples, the inverter is configured to be powered by a voltage supply, which voltage supply exceeds a voltage supplied to the first voltage supply node by at least an amount equal to a threshold voltage of the enhancement mode transistor. In some examples, the signal conditioning circuit comprises a level-shifting inverter. In some examples, the level-shifting inverter comprises an enhancement mode transistor, a current source, and a level-shifting inverter transistor connected to the current source. It will be appreciated that the term “level-shifting inverter transistor” is merely a designation to differentiate said transistor from the other transistors described in the present disclosure. The level-shifting inverter transistor may comprise a level-shifting inverter transistor source terminal, a level-shifting inverter transistor drain terminal, and a level-shifting inverter transistor gate terminal. The level-shifting inverter transistor may be an enhancement mode transistor. In some examples, the level-shifting inverter transistor comprises an enhancement mode HEMT. The level-shifting inverter transistor may be a source-gate connected transistor, or a gate-source connected transistor. The level-shifting inverter transistor may be connected in parallel to the current source. The level-shifting inverter transistor may be configured to raise a low voltage output of the level-shifting inverter to a potential above a source potential of the enhancement mode transistor. The level-shifting inverter may comprise an additional transistor, the additional transistor being configured to control a current dissipation of the level-shifting inverter. The additional transistor may be a heterojunction transistor. The additional transistor may comprise an additional transistor source terminal, an additional transistor drain terminal, and an additional transistor gate terminal. The additional transistor gate terminal may be connected to an additional fixed potential or voltage. In some examples, the additional transistor gate terminal is connected to the same fixed voltage as the sense transistor gate terminal. The additional transistor may reduce the power consumption of the level-shifting inverter. In some examples, the signal conditioning circuit comprises a low pass filter. The sense transistor and the sense load may form a potential divider circuit. In operation, when the first active heterojunction transistor is in different modes of operation (e.g. on-state, off-state), the potential at the mid-point of the potential divider circuit (i.e. the source of the sense transistor) can vary, as the drain to source voltage of the first active heterojunction transistor varies. This mid-point potential may therefore be configured to serve as an indicator of the mode of operation of the first active heterojunction transistor. In an example (e.g. where the signal conditioning circuit comprises an inverter), the mid-point potential is connected to an inverter circuit. The input of the inverter circuit may comprise the gate terminal of an enhancement mode HEMT. If the midpoint potential of the potential divider is below a threshold value then the input to the inverter is considered low and the output will be high. If the midpoint potential of the potential divider is greater than or equal to the threshold value, then the input to the inverter is considered high and the output will be low. In the on-state of the active heterojunction transistor, a small potential (e.g. <5V) is present across the drain and source terminals of the active heterojunction transistor. In this mode of operation, the sense circuit and inverter may be configured such that the input to the inverter is considered low and the output of the inverter will be high. In the off-state of the active heterojunction transistor, a large potential (e.g. >5V or >50V) is present across the drain and source terminals of the active heterojunction transistor. In this mode of operation, the sense circuit and inverter may be configured such that the input to the inverter is considered high and the output of the inverter will be low. The output of the inverter can be configured to modulate (directly or indirectly) a bootstrap transistor such that: when the drain to source potential of the active heterojunction transistor is small (e.g. <5V), the bootstrap transistor is also in the on-state, when the drain to source potential of the active heterojunction transistor is large (e.g. >5V), the bootstrap transistor is also in the off-state. For example, a high inverter output may be a potential, VDD. VDD may be a regulated voltage generated on chip or applied externally. For example, when the device is used on the low side of a half bridge circuit, VDD may be the low side supply voltage or VDD may be generated from the low side supply voltage. The inverter pull-up may comprise a current source or a resistor rather than p-channel device. Therefore the high inverter output may be lower than potential, VDD. A low inverter output may be the source potential of the active heterojunction transistor. In other examples, a level shifting inverter circuit may be used. In this example, the high output of the inverter circuit may be configured to be lower than VDD, and the low output of the inverter circuit may be configured to be higher than the source potential. The sense circuit may comprise additional signal conditioning components or circuits. In some examples the output of the signal conditioning circuit (and therefore the signal modulating the bootstrap device) may be a differential signal. Where the bootstrap transistor described herein is connected between the low-side voltage supply and high-side voltage supply in a half bridge circuit, the bootstrap transistor is preferably configured as a high voltage transistor. In some examples, the source terminal of the bootstrap transistor is connected to the low-side voltage supply (i.e. connected to the first voltage supply node), the gate terminal of the bootstrap transistor is connected to the output of the inverter and the drain terminal of the bootstrap transistor is connected to the high-side supply (i.e. connected to the second voltage supply node). In some examples, the bootstrap transistor may a depletion mode transistor. Several approaches are possible to design a depletion mode AlGaN / GaN heterojunction transistor such as a Schottky gate or an insulated gate transistor. In some examples, the bootstrap transistor comprises a depletion mode llI-nitride semiconductor based heterojunction transistor comprising: a substrate; a lll-nitride semiconductor region formed over the substrate, wherein the lll-nitride semiconductor region comprises a heterojunction comprising a two-dimensional carrier gas of a second conductivity type; a bootstrap transistor first terminal operatively connected to the Ill-nitride semiconductor region; a bootstrap transistor second terminal laterally spaced from the bootstrap transistor first terminal in a first dimension and operatively connected to the lll-nitride semiconductor region; a plurality of highly doped semiconductor regions of a first conductivity type formed over the lll-nitride semiconductor region, the plurality of highly doped semiconductor regions being formed between the bootstrap transistor first terminal and the bootstrap transistor second terminal; and an active gate region formed over the plurality of highly doped semiconductor regions; wherein the highly doped semiconductor regions are spaced from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension. The bootstrap transistor first terminal may correspond to a bootstrap transistor source terminal, or a bootstrap transistor drain terminal. Similarly, the bootstrap transistor second terminal may correspond to a bootstrap transistor drain terminal, or a bootstrap transistor source terminal. The active gate region may be operatively connected to a bootstrap transistor gate terminal. The depletion mode llI-nitride semiconductor based heterojunction transistor comprising the plurality of highly doped semiconductor regions may enable the threshold voltage of the bootstrap transistor to be controlled by configuring the layout of the highly doped semiconductor regions. The highly doped semiconductor regions may correspond to a plurality of discontinuous regions of the first conductivity type. For example, the depletion mode transistor may comprise a gate structure based on a discontinuous p-GaN layer (or discontinuous regions of a first conductivity type) containing islands within stripes or closed shapes around the cells that act to modulate the conductive path, given by the 2D electron gas (or a 2D carrier gas of a second conductivity type) between the high voltage terminal and low voltage terminal (bootstrap first terminal and bootstrap second terminal, respectively), when a gate voltage is provided. All such islands may be connected to a same gate electrode. It will be appreciated that by discontinuous islands it is meant that between adjacent islands there is no p-GaN layer present, and as such, there is a direct, unobstructed conductive path between the source and the drain terminals, provided by the 2D electron gas. However, adjacent islands are placed close together across (orthogonal to) the current path such that the potential applied to the p-GaN gate islands modulate the conductive region between the islands and thus modulate the direct path between the source and the drain. The p-GaN layers in the continuous and discontinuous gate structures may be fabricated in a same process step and a difference between continuous and discontinuous may be realized by a layout change of a same mask. In some examples, the bootstrap device comprises two bootstrap transistors arranged in a cascode configuration. For example, the bootstrap transistor described hereinabove may be a first bootstrap transistor, and the bootstrap device may further comprise a second bootstrap transistor. The first bootstrap transistor and the second bootstrap transistor may be arranged in a cascode configuration. The first bootstrap transistor and the second bootstrap transistor may be arranged in series. In a cascode configuration, a drain terminal of the first bootstrap transistor may be referred to as a first bootstrap transistor drain terminal, and a source terminal of the second bootstrap transistor may be referred to as a second bootstrap transistor source terminal. The first bootstrap transistor drain terminal may be connected to the second voltage supply node. The second bootstrap transistor source terminal may be connected to the first voltage supply node. As described above, the first active heterojunction transistor gate terminal may be driven by a gate driver. The gate driver may be powered by the low side voltage supply if the first active heterojunction transistor is arranged on the low side of a half bridge, or by the high side voltage supply if placed on the high side of a half bridge. In some examples, the lll-nitride power semiconductor heterojunction device further comprises a first auxiliary gate circuit, and / or a first Miller clamp circuit, configured to be powered via the first voltage supply node. The first auxiliary gate circuit and / or Miller clamp circuit may be configured to control the voltage and / or current levels supplied to the first active heterojunction transistor (i.e. the first auxiliary gate circuit and / or Miller clamp circuit is connected to the first active heterojunction transistor gate terminal). The first auxiliary gate circuit and / or Miller clamp circuit may be monolithically integrated with the first active heterojunction transistor. In some examples, the lll-nitride power semiconductor heterojunction device further comprises a second auxiliary gate circuit, and / or a second Miller clamp circuit, configured to be powered via the second voltage supply node. The second auxiliary gate circuit and / or Miller clamp circuit may be configured to control the voltage and / or current levels supplied to the second active heterojunction transistor (i.e. the second auxiliary gate circuit and / or Miller clamp circuit is connected to the second active heterojunction transistor gate terminal). The second auxiliary gate circuit and / or Miller clamp circuit may be monolithically integrated with the second active heterojunction transistor. In some examples, the bootstrap device and the first active heterojunction transistor are monolithically integrated. In some examples, the bootstrap device, the sense circuit, and the first active heterojunction transistor are monolithically integrated. Brief Description of the Drawings Figure 1 illustrates a schematic diagram of a half bridge circuit; Figure 2 illustrates a schematic diagram of a half bridge circuit comprising a bootstrap diode; Figure 3 illustrates a schematic diagram of a device comprising a sense circuit and a bootstrap device according to the present disclosure; Figure 4 illustrates a schematic diagram of a device comprising a sense circuit, a bootstrap device, and a signal conditioning circuit according to the present disclosure; Figure 5 illustrates a schematic diagram of a device comprising a bootstrap transistor according to the present disclosure; Figure 6 illustrates a schematic diagram of a device comprising a bootstrap device comprising two transistors arranged in a cascode configuration according to the present disclosure; Figure 7 illustrates an example of a depletion mode transistor; Figure 8 illustrates a schematic diagram of a device comprising a level shifting inverter according to the present disclosure; Figure 9 illustrates a schematic diagram of a further device comprising a level shifting inverter according to the present disclosure; Figure 10 illustrates a schematic diagram of a device comprising a bootstrap device, the bootstrap device comprising an enhancement mode transistor, according to the present disclosure; Figure 11 illustrates a schematic diagram of a device comprising an auxiliary gate circuit according to the present disclosure; and Figure 12 illustrates an example of a device comprising an auxiliary gate. Detailed Description Figure 1 illustrates a schematic diagram of a half bridge circuit which comprises a low- side transistor 20 and a high-side transistor 21. Figure 2 illustrates a schematic diagram of a half bridge circuit which comprises a low- side transistor 20 and a high-side transistor 21. The low-side transistor is driven by a low-side gate driver 22. The low-side gate driver is powered by a low side supply VDDL. The high-side transistor is driven by a high-side gate driver 23. The high side gate driver is powered by a high-side supply VDDH. In the example illustrated in Figure 2, the high side supply is charged through the bootstrap diode 26. Figure 3 illustrates a schematic diagram of an example of a GaN chip 30 with a monolithically integrated bootstrap transistor as described herein. The two sections 30 may be monolithically integrated but are illustrated in Figure 3 as separate to simplify the illustration. The GaN chip comprises an active heterojunction transistor 20, a sense circuit 27 and a bootstrap device 28. The active heterojunction transistor 20 can act as the low-side transistor in a half bridge circuit. The sense circuit 27 is connected in parallel to the active heterojunction transistor and is configured to sense whether the drain to source voltage across transistor 20 is above or below a certain threshold value and generate a signal SCO accordingly. This, to an extent, may also indicate whether transistor 20 is in the on-state mode of operation or off-state of operation. The generated signal from the sense circuit SCO is configured to modulate a bootstrap transistor in the bootstrap device 28, such that the high side supply VDDH can be charged from the low side supply VDDL when the drain to source voltage across the active heterojunction transistor 20 is below the selected threshold voltage value. When the drain to source potential across the active heterojunction transistor is above the selected threshold value, the bootstrap transistor in the bootstrap device 28 is modulated to block any current from the high side supply VDDH to the low side supply VDDL (beyond any leakage current in the bootstrap transistor). In some examples, the sense circuit output signal may be a differential signal. Figure 4 illustrates a schematic diagram of an example of a GaN chip 30 with a monolithically integrated bootstrap device as described herein. This example is similar to the example illustrated in Figure 3 but an additional circuit block in the sense circuit is illustrated. The additional circuit block in this example is a signal conditioning circuit 275. The signal conditioning circuit may comprise an inverter, a level shifting inverter, a low pass filter, a circuit generating a differential signal etc. Figure 5 illustrates a schematic diagram of an example of a GaN chip with a monolithically integrated bootstrap transistor as described herein. Components / circuit blocks 20, 270, 271 and 281 may be monolithically integrated. The schematic in Figure 5 illustrates some examples of the blocks illustrated in Figure 3. For example, sense circuit 27 may comprise the sense circuit 270 and an inverter 271. Sense circuit 270 comprises a sense transistor and a sense load. The bootstrap device 28 in Figure 3 may comprise a depletion mode transistor 281 as illustrated in Figure 5. The gate-source potential of transistor 281 for different outputs of the inverter will be: if inverter output is low, Vgs = -VDDL if inverter output is high, Vgs = 0V Therefore, if depletion mode transistor 281 threshold voltage, Vth is less negative than -VDDL, transistor 281 will be in the off-state when the inverter output is low and in the on-state when the inverter output is high. Figure 6 illustrates a schematic diagram of an additional example of a GaN chip with a monolithically integrated bootstrap transistor. In this example the sense circuit may be the same as the sense circuit in the example of Figure 5. However, in this example the bootstrap device 282 may comprise two transistors connected in a cascode configuration where transistor 2821 is a high voltage depletion mode transistor and transistor 2822 is a low voltage depletion mode transistor. Transistor 2821 in this example is modulated by changing the potential on its source terminal. The gate terminal of transistor 2821 is connected to the source of the active heterojunction transistor which in use on the low side of a half bridge circuit would be connected to a fixed ground potential. When the output of inverter 271 is low, the gate of transistor is biased close to OV bias and therefore 2822 is in the off-state as it has a negative gate-source bias. When the output of inverter 271 is high, the gate of transistor 2822 will be biased close to VDDL and therefore 2822 is in the on-state as it has a gate-source bias close to OV. The gate-source potential of transistor 2821 for different outputs of the inverter will be: if inverter output is low, Vgs = -(VDDL + Vds(2822)) if inverter output is high, Vgs = -VDDL Therefore, if depletion mode transistor 2821 threshold voltage, Vth is: —(VDDL + Vds(2822)) < Vth < —VDDL Transistor 2821 will be in the off-state when the inverter output is low and in the on- state when the inverter output is high. The example in Figure 6 therefore allows the control of a high voltage depletion mode transistor with a Vth which is more negative than -VDDL. As illustrated with the bootstrap device examples of Figure 5 and Figure 6, it may be desirable for flexible design to use a depletion mode transistor whose threshold voltage can be easily adjusted such that it can be optimized to correspond to the VDDL level used. In various depletion mode transistor technologies the threshold voltage of the device is controlled by a process change (e.g. adjusting doping levels, thicknesses of layers, metal used in gate contact etc.). Changes can therefore be costly and time consuming. Control over the threshold voltage through layout may therefore be very useful when designing the circuits described. An example of a depletion mode transistor where the threshold voltage may be controlled by layout is illustrated in Figure 7 and is described in US 2021 / 0335781 A1, the contents of which are hereby incorporated by reference. As illustrated in Figure 7, a depletion mode transistor may comprise a substrate 4 (e.g. a silicon substrate), and lll-nitride semiconductor region grown epitaxially on the substrate 4. In the example illustrated in Figure 7, the lll-nitride semiconductor region comprises a transition layer 4 which allows a high quality GaN layer 2 to be grown despite the significant lattice mismatch between GaN and silicon. The llI-nitride semiconductor region may further comprise an AlGaN layer 1 grown on the GaN layer 2. The depletion mode transistor further comprises a low voltage source terminal 8, high voltage drain terminal 9, and a plurality of p-GaN islands 11 arranged between the source terminal 8 and the drain terminal 9. The p-GaN islands are operatively connected through a contact layer 10 to a common gate terminal. A threshold voltage for the transistor may be controlled by varying the pitch (distance) between the p-GaN islands 11 The depletion mode transistor of Figure 7 may be used as the high voltage transistor 281 or 2821 in a bootstrap device. The depletion mode transistor of Figure 7 may be used as the low voltage transistor 2822 in a bootstrap device. In the examples illustrated in Figure 5 and Figure 6 the gate of the transistor connected to the output of the inverter may be subject to a potential of Vgs = -VDDL magnitude when the output of the inverter is low. Depending on the design of the transistor and the VDDL requirement for the GaN chip, this potential may be too high and may damage the gate of the transistor. A level shifting inverter may be desirable in this scenario. An example is illustrated in Figure 8 where level-shifting inverter 272 is illustrated in a similar circuit to the circuit illustrated in Figure 6. The level shifting inverter comprises an enhancement mode HEMT 2721, a current source 2722 and two source-gate (or drain-gate) connected transistors 2723 2724 in series. In operation, the low voltage output of the inverter will be approximately: VDDL- 2 =Vth Therefore the maximum absolute Vgs for depletion mode transistor 2822 will be 2*Vth. Vth is the threshold voltage of the source-gate connected transistors. Fewer or more source-gate transistors may be used according to the design requirements. Figure 9 illustrates an additional example of a level shifting inverter 273. This example is similar to the example illustrated in Figure 8 but it contains an additional transistor 2735. Transistor 2735 may control the current dissipation of inverter 273 in order to minimise the power consumption of the circuit. Figure 10 illustrates a schematic diagram of an additional example of a GaN chip with a monolithically integrated bootstrap transistor. This example is similar to the example illustrated in Figure 5, however in this example the bootstrap transistor is an enhancement mode transistor 283. In this example, for the enhancement mode transistor to turn-on the gate-source potential of the transistor need to be above a threshold voltage, Vth. Therefore, a high output of the inverter 274 needs to be at least greater than VDDL + Vth in order to turn-on transistor 283. Therefore VDDL4 which powers the inverter in this example needs to be greater than the low side supply voltage, VDDL. The low output of the inverter can be at source potential or at a level-shifted potential as described in previous examples. Figure 11 illustrates a schematic diagram of an additional example of a GaN chip 30 with a monolithically integrated bootstrap transistor as described herein. This example is similar to the example shown in Figure 3 but it includes an additional auxiliary gate circuit 291 connected between the gate driver 22 and the active heterojunction transistor 20 (taking the half-bridge low side as an example although a similar connection is illustrated on the high-side). An example of an auxiliary gate circuit is described in WO 2020 / 225362 A1, the contents of which are hereby incorporated by reference. The auxiliary gate circuit 291 may be monolithically integrated with the other circuit blocks on the GaN chip 30. In Figure 12, a Gallium Nitride (GaN) chip 1000 is shown according to some examples. The GaN chip 1000 may comprise at least three terminals. These at least three terminals may include one or more of a high voltage terminal, a low voltage terminal and a control terminal. The chip 1000 may further comprise one or more heterojunction transistors 500 with an internal gate. According to some examples, the heterojunction transistor 500 of Figure 12 corresponds to the first active heterojunction transistor described herein. The source and drain terminals of the transistor 500 may be connected to the low voltage and high voltage terminals of the GaN chip 1000 respectively. The GaN chip 1000 may further comprise a current control circuit 530, a pull-down circuit 520 and / or an auxiliary gate circuit 510. The auxiliary gate circuit 510 may contain at least one low-voltage heterojunction transistor (also referred to as an auxiliary transistor) with an internal gate. The auxiliary gate circuit 510 may be operatively connected to at least the internal gate of the heterojunction transistor 500 by a first connection, and may further comprise a second connection to operatively connect the auxiliary gate 510 to the control terminal. A third connection of the auxiliary gate circuit 510 may operatively connect the internal gate of the low-voltage heterojunction transistor of auxiliary gate circuit 510 to the pull down circuit 520. In addition to the at least one connection to the auxiliary gate circuit, pull-down circuit 520 may comprise at least one connection to the current control circuit and at least one connection to the source terminal of the transistor 500. Current control circuit 530 may comprise at least one connection to each of the control terminal, auxiliary gate circuit 510 and pull down circuit 520. The auxiliary gate 510 may partly control the voltage and the current levels into the internal gate of the transistor 500. The current control circuit 530 may control the current level into pull down circuit 520 and in conjunction with the pull down circuit may further determine the voltage level applied to the internal gate of the low-voltage heterojunction transistor of auxiliary gate 510. The pull-down circuit in turn may actively pull down the gate voltage of the low-voltage heterojunction transistor in order to clamp the voltage of the internal gate of the transistor 500. A similar circuit to that illustrated in Figure 12 may be employed in relation to the second active heterojunction described herein, where the heterojunction transistor 500 of Figure 12 may correspond to the second active heterojunction transistor. In an alternative example, the gate of an active heterojunction transistor described herein may be controlled via a Miller clamp circuit. For example, an active Miller clamp circuit may be implemented, composed of an enhancement mode transistor operating as a Miller clamp. The enhancement mode transistor may be driven by associated circuitry, for example an inverter. The inverter may be powered by the low side power supply if the active heterojunction transistor is used as a low side device in a half bridge circuit. The inverter may be powered by the high side power supply if the active heterojunction transistor is used as a high side device in a half bridge circuit. Additionally, the transistor operating as a Miller clamp may be a depletion mode transistor rather than an enhancement mode transistor. The depletion transistor may be a pGaN island transistor as described herein. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:

1. A lll-nitride power semiconductor based heterojunction device comprising: a first active heterojunction transistor, the first active heterojunction comprising a first active heterojunction transistor source terminal and a first active heterojunction transistor drain terminal; a first voltage supply node; a second voltage supply node; a sense circuit connected between the first active heterojunction transistor source terminal and the first active heterojunction transistor drain terminal, the sense circuit being configured to sense a voltage between the first active heterojunction transistor drain terminal and the first active heterojunction transistor source terminal; a bootstrap device connected between the first voltage supply node and the second voltage supply node, the bootstrap device comprising a bootstrap transistor; wherein the sense circuit is configured to modulate the bootstrap device such that: when the voltage between the first active heterojunction transistor drain terminal and the first active heterojunction source terminal is below a threshold value, the bootstrap transistor is in an on state operation; and when the voltage between the first active heterojunction transistor drain terminal and the first active heterojunction source terminal is greater than or equal to the threshold value, the bootstrap transistor is in an off state operation.

2. A lll-nitride power semiconductor based heterojunction device according to claim 1, further comprising a second active heterojunction transistor, wherein the first active heterojunction transistor and the second active heterojunction transistor are arranged in a half bridge configuration.

3. A lll-nitride power semiconductor based heterojunction device according to claim 2, wherein the first active heterojunction transistor comprises a first active heterojunction transistor gate terminal, and where the second active heterojunction transistor comprises a second active heterojunction transistor gate terminal; and wherein the llI-nitride semiconductor based heterojunction device further comprises: a first gate driver connected to the first active heterojunction transistor gate terminal, the first gate driver being further connected to the first voltage supply node; and a second gate driver connected to the second active heterojunction transistor gate terminal, the second gate driver being further connected to the second voltage supply node.

4. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, wherein the sense circuit comprises: a sense transistor, the sense transistor comprising a sense transistor source terminal, a sense transistor drain terminal, and a sense transistor gate terminal; and a sense load; wherein the sense transistor source terminal is connected to the sense load; and wherein the sense transistor drain terminal is connected to the first active heterojunction transistor drain terminal.

5. A lll-nitride power semiconductor based heterojunction device according to claim 4, wherein the sense transistor gate terminal is connected to a fixed voltage.

6. A lll-nitride power semiconductor based heterojunction device according to claim 4 or 5, further comprising a signal conditioning circuit, wherein the sense circuit is configured to modulate the bootstrap device via a signal transmitted through the signal conditioning circuit.

7. A lll-nitride power semiconductor based heterojunction device according to claim 6, wherein the signal conditioning circuit comprises an inverter.

8. A lll-nitride power semiconductor based heterojunction device according to claim 6, wherein the inverter comprises an enhancement mode transistor and a current source.

9. A lll-nitride power semiconductor based heterojunction device according to claim 7 or 8, wherein the inverter is configured to be powered via the first voltage supply node.

10. A lll-nitride power semiconductor based heterojunction device according to claim 8, wherein the inverter is configured to be powered by a voltage supply, which voltage supply exceeds a voltage supplied to the first voltage supply node by at least an amount equal to a threshold voltage of the enhancement mode transistor.

1. A lll-nitride power semiconductor based heterojunction device according to claim 6 or 7, wherein the signal conditioning circuit comprises a level-shifting inverter.

12. A lll-nitride power semiconductor based heterojunction device according to claim 11, wherein the level-shifting inverter comprises an enhancement mode transistor, a current source, and a level-shifting inverter transistor connected to the current source; wherein the level-shifting inverter transistor is configured to raise a low voltage output of the level-shifting inverter to a potential above a source potential of the enhancement mode transistor.

13. A lll-nitride power semiconductor based heterojunction device according to claim 12, wherein the level-shifting inverter comprises an additional transistor, the additional transistor being configured to control a current dissipation of the |level-shifting inverter.

14. A lll-nitride power semiconductor based heterojunction device according to any one of claims 6 to 13, wherein the signal conditioning circuit comprises a low pass filter.

15. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, wherein the bootstrap transistor comprises depletion mode llI-nitride semiconductor based heterojunction transistor comprising: a substrate; a lll-nitride semiconductor region formed over the substrate, wherein the Ill-nitride semiconductor region comprises a heterojunction comprising a two- dimensional carrier gas of a second conductivity type; a first bootstrap transistor terminal operatively connected to the llI-nitride semiconductor region; a second bootstrap transistor terminal laterally spaced from the bootstrap transistor source terminal in a first dimension and operatively connected to the llI-nitride semiconductor region; a plurality of highly doped semiconductor regions of a first conductivity type formed over the lll-nitride semiconductor region, the plurality of highly doped semiconductor regions being formed between the first bootstrap transistor terminal and the second bootstrap transistor terminal; and an active gate region formed over the plurality of highly doped semiconductor regions; wherein the plurality of highly doped semiconductor regions are spaced from each other in a second dimension, and wherein the second dimension is perpendicular to the first dimension.

16. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, wherein the bootstrap transistor is a first bootstrap transistor, and wherein the bootstrap device further comprises a second bootstrap transistor, wherein the first bootstrap transistor and the second bootstrap transistor are arranged in a cascode configuration.

17. A llI-nitride power semiconductor based heterojunction device according to claim 16, wherein the first bootstrap transistor comprises a first bootstrap transistor drain terminal; and wherein the second bootstrap transistor comprises a second bootstrap transistor source terminal; wherein the first bootstrap transistor drain terminal is connected to the second voltage supply node; and wherein the second bootstrap transistor source terminal is connected to the first voltage supply node.

18. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, further comprising a first auxiliary gate circuit configured to be powered via the first voltage supply node, the first auxiliary gate circuit being monolithically integrated with the first active heterojunction transistor.

19. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, further comprising a first Miller clamp circuit configured to be powered via the first voltage supply node, the first Miller clamp circuit being monolithically integrated with the first active heterojunction transistor.

20. A lll-nitride power semiconductor based heterojunction device according to any one of clams 2 to 19, further comprising a second auxiliary gate circuit configured to be powered via the second voltage supply node, the second auxiliary gate circuit being monolithically integrated with the second active heterojunction transistor.

21. A lll-nitride power semiconductor based heterojunction device according to any one of claims 2 to 20, further comprising a second Miller clamp circuit configured to be powered via the second voltage supply node, the second Miller clamp gate circuit being monolithically integrated with the second active heterojunction transistor.

22. A lll-nitride power semiconductor based heterojunction device according to any one of the preceding claims, wherein the bootstrap device, the sense circuit, and the first active heterojunction transistor are monolithically integrated.

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