A method of performing qubit operations

Abstract

A method of performing logical qubit operations 27,29,31,33 on an ensemble of logical qubits 1a-d, each logical qubit having a plurality of physical qubits. The method comprising: performing one or mo

Description

The present invention relates to a method of performing qubit operations, and a quantum processing system on which qubit operations are performed. In quantum computers, various different operations can be performed on qubits. Examples of qubit operations include the manipulation of the state of a qubit or the measurement of the state. Error correction is necessary to protect quantum information held on qubits from decoherent noise and other forms of noise that may randomly flip the state of qubits and cause other errors. In common error correction schemes, physical qubits (a single two state quantum system) are grouped together to form logical qubits. The physical qubits making a logical qubit are generally divided into data qubits and auxiliary qubits. The data qubits and auxiliary qubits play different roles in error correction, to preserve the state of qubits. In operating a quantum computer, logical qubits are manipulated individually by single qubit logical operations / single qubit logical gates and are entangled by multi-qubit logical operations / multi-qubit logical gates. A logical operation on a logical qubit or set of logical qubits is performed by carrying out a set of physical operations on the individual physical qubits making up the logical qubit(s). Single logical qubit operations include, but are not limited to: logical identity / idle operations (e.g. quantum memory, or QMEM operations such as syndrome extraction); logical H-gate; logical Pauli X / Y / Z gates; logical S gate; logical T gate rotation gates. Multi-qubit logical operations include, but are not limited to: CNOT gate, CPHASE, CZ gate; SWAP gate; Toffoli gate; Fredkin gate. Typically, to maintain fidelity and provide error correction, logical operations are performed on logical qubits in rounds or cycles. For example, when two logical qubits are entangled in a multi-qubit logical operation, each individual logical qubit first has a number of rounds single qubit logical operations performed on it. Operations are performed on physical qubits using electrical or optical pulses generated by a control system. The pulses need to be calibrated to determine the correct duration and shape of a pulse to achieve a desired outcome. Due to manufacturing tolerances, there may be variation in the quantum processing units, ion / atoms traps, lasers and other elements of the system, This means that the shape and duration of pulses are adjusted for each individual physical qubit or qubit site to maximise the fidelity of the physical operation. Thus the pulses corresponding to the same physical qubit operation are individually tuned and slightly different for each physical qubit. This is exacerbated when considering operations on logical qubits, which involve manipulating a number of physical qubits. When a multi-qubit logical operation is performed on two or more logical qubits, it is desirable to keep the logical qubits in a fault tolerant regime until all the logical qubits involved in the operation are in the correct state to carry out the logical operation. In a fault tolerant regime it is unlikely that decoherence or other quantum noise will randomly alter the state of the logical qubit. The different pulse times for different logical qubits mean that, even when the same single qubit logical operation is performed on two logical qubits for the same number of cycles, the time taken to complete the cycles before performing a multi-qubit logical operation is different for the two logical qubits. This can lead to scheduling issues when attempting to perform multi-qubit logical operations between logical qubits. There is, therefore, a desire to operate the logical qubits in a way avoids scheduling issues that arise from calibration differences between logical qubits. According to a first aspect of the invention, there is provided a method of performing logical qubit operations on an ensemble of logical qubits, each logical qubit having a plurality of physical qubits, the method comprising: performing one or more rounds of single qubit logical operations on each of a set of the logical qubits; and performing a multi-qubit logical operation using at least two of the set of logical qubits, wherein the logical qubits involved in the multi-qubit logical operation are synchronised prior to the multi-qubit logical operation by one or more of: providing periods of physical idle time between rounds of single qubit logical operations performed on one or more of the logical qubits involved in the multi-qubit logical operation; and performing different numbers of rounds of single qubit logical operations on the logical qubits involved in the multi-qubit logical operation in a fixed period of time. The fixed period of time may be the time immediately preceding a logical qubit operation. This may be the time from initialisation of the logical qubit up to the multiqubit logical operation or the period between a logical qubit being involved in a first multi-qubit logical operation and a second multi-qubit logical operation. The logical qubits involved in the multi-qubit logical operation may be synchronised prior to the multi-qubit logical operation by one or more of: providing periods of physical idle time between rounds of single qubit logical operations; and performing more rounds of single qubit logical operations in a fixed period of time, on a first logical qubit of the logical qubits involved in the multi-qubit logical operation, the first logical qubit having a shorter duration for rounds of single qubit logical operations than a second logical qubit involved in the multi-qubit logical operation. Rounds of single qubit logical operations on the second logical qubit may be of longer duration than rounds of single qubit logical operations on the first logical qubit. More rounds of single qubit logical operations may be performed on the first logical qubit than on the second logical qubit. The method may include providing one or more periods of physical idle time on the second logical qubit. The method may include providing periods of physical idle time between rounds of single qubit logical operations on the second logical qubit. The periods of physical idle time on the second logical qubit may be after each round of single qubit logical operations and / or may be of equal duration. The method may include performing a single period of physical idle time on the first logical qubit. The single period of physical idle time may be after the last round of single qubit logical operations before the multi-qubit logical operation. The same number of rounds of single qubit logical operations may be performed on the first and second logical qubits. The start of each round of single qubit logical operations on the first logical qubit may be synchronised to the start of a corresponding round of single qubit logical operations on the second logical qubit. Periods of physical idle time may be provided after each round of single qubit logical operation on the first logical qubit. The periods of physical idle time provided after each round of single qubit logical operations on the first logical qubit may be the same duration. Any period of physical idle time may be less than the median energy relaxation time and dephasing time of the physical qubits making up the logical qubits. Any period of physical idle time may be at least an order of magnitude less than the median energy relaxation time and dephasing time of the physical qubits making up the logical qubits. Any period of physical idle time may be less than 500ns. At least some of the rounds of single qubit logical operations may include syndrome extraction rounds. When there are more rounds of single qubit logical operations on a logical qubit, any additional rounds of single qubit logical operations may be syndrome extraction rounds. The syndrome extraction rounds may be QMEM operations. The same single qubit logical operation may be performed on different logical qubits. A plurality of multi-qubit logical operations may be performed at the same time with non-overlapping groups of two or more logical qubits. A plurality of multi-qubit logical operations may be performed in time series with overlapping or non-overlapping groups of two or more logical qubits. Non-overlapping groups of logical qubits involved in multi-qubit logical operations may be synchronised in parallel. When multi-qubit logical operations are performed on overlapping groups, synchronisation may be performed for a group associated with a later multi-qubit logical operation after all logical qubits in the group have completed the corresponding earlier multi-qubit logical operations they are involved in as part of different groups. When multi-qubit logical operations are performed on overlapping groups, synchronisation may be at least in part performed for a group associated with a later multi-qubit logical operation when at least one of the logical qubits in the group has completed its earlier multi-qubit logical operations but before other logical qubits in the group have completed their earlier multi-qubit logical operations. The method may include performing single logical qubit operations on the at least one logical qubit after it has completed its previous multi-qubit logical operation. The method may include performing different numbers of rounds of single qubit logical operations on the logical qubits in the group associated with the later multi-qubit logical operation in the period between the at least one logical qubit completing its previous multi-qubit logical operation and the rest of the logical qubits in the group associated with the later multi-qubit logical operation have completed their previous multi-qubit logical operations. The method may include: calibrating the ensemble of logical qubits to generate first calibration data specifying the time taken for single and multi-qubit logical operations; generating a schedule of a first part of the plurality of multi-qubit logical operations, including the synchronisation, based on the first calibration data; performing the first part of the plurality of multi-qubit logical operations; recalibrating the ensemble of logical qubits to generate second calibration data specifying the time taken for single and multi-qubit logical operations; generating a schedule of a second part of the plurality of multi-qubit logical operations, including the synchronisation, based on the second calibration data; and performing the second part of the plurality of multi-qubit logical operations. According to a second aspect of the invention, there is provided a method of determining a pulse schedule for performing at least part of a quantum circuit on an ensemble of logical qubits, each logical qubit having a plurality of physical qubits, the method comprising: obtaining calibration data of the ensemble of logical qubits, the calibration data specifying the time taken to perform single and multi-qubit logical operations in the quantum circuit; and generating a schedule for pulses to be generated to cause the ensemble of logical qubits to perform the quantum circuit, wherein, in order to synchronise the logical qubits involved in a multi-qubit logical operation are prior to the multi-qubit logical operation, the pulse schedule includes one or more of: periods of physical idle time between rounds of single qubit logical operations on one or more of the qubits involved in a multi-qubit logical operation; and different numbers of rounds of single qubit logical operations on the logical qubits involved in a multi-qubit logical operation in a fixed period of time. According to a third aspect of the invention, there is provided a non-transitory computer readable medium comprising instructions which, when executed by a processor, cause the processor to perform the steps of the first or second aspect. According to a fourth aspect of the invention, there is provided a system comprising: a quantum processing unit having an ensemble of physical qubits arranged to form a plurality of logical qubits; for each physical qubit, one or more pulse generators arranged to drive and read out the physical qubits to perform single and multi-qubit logical operations on the logical qubits; and a scheduler comprising one or more processors, the one or more processors arranged to cause the pulse generators to: perform one or more rounds of single qubit logical operations on each of a set of the logical qubits, perform a multi-qubit logical operation, using at least two of the set of the logical qubits, wherein the logical qubits involved in a multi-qubit logical operation are synchronised prior to the multi-qubit logical operation by one or more of: providing periods of physical idle time between rounds of single qubit logical operations on one or more of the logical qubits involved in the multi-qubit logical operation; and performing different numbers of rounds of single qubit logical operations on the logical qubits involved in the multi-qubit logical operation in a fixed period of time. There may be a significant time difference between two different logical qubits completing rounds of single qubit logical operations and thus being in the correct states to carry out a multi-qubit logical operation. By providing physical idle time between rounds of single qubit logical operations and / or adding in additional rounds of single qubit logical operations on some but not all of the logical qubits, the duration of any single period of physical idle time on the physical qubits can be reduced to below the energy relaxation and dephasing times for a physical qubit, ensuring the logical qubit remains in the fault tolerant regime. This may be accomplished in a number of different ways. For example, this may be achieved by spreading the physical idle time between the rounds of single qubit logical operations on the logical qubit which takes has a shorter duration for single qubit logical operations, as in option (i). Alternatively, an additional cycle / round of a single qubit logical operation may be added on the logical qubit which has a shorter duration for single qubit logical operations as in option (ii). Even when taken in a single block, the physical idle time may be reduced to below the energy relaxation and dephasing times for a physical qubit, ensuring the logical qubit remains in the fault tolerant regime. Alternatively, the reduced physical idle time may be spread between the rounds of single qubit logical operations, combining options (i) and (ii) and further reducing the duration of any single period of physical idle time thus further reducing the chances of errors occurring. In yet another example, a short period of physical idle time may be added to a logical qubit which takes more time to complete single qubit logical operations. This may, for example, increase the overall time difference taken to complete the full set of single qubit logical operations such that an additional single qubit logical operation can be performed on the logical qubit which takes less time to complete the single qubit logical operations. These schemes can be expanded out to larger quantum circuits where logical qubits may be involved in multi-qubit logical operations with different logical qubits at different times. Even over the performance of a single quantum circuit, the time taken to perform operations may change. Recalibrating the physical qubits, and only generating the schedule for the circuit in portions allow the changes in calibration data to be accommodated. It will be appreciated that features discussed in relation to a particular aspect of the invention may be applied mutatis mutandis to any other aspect. Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates the operation of a single round of syndrome extraction on a logical qubit; Figures 2A-C schematically illustrate different schemes for synchronising two logical qubits before a multi-qubit logical operation; Figure 3 illustrates a control system for operating logical qubits using the schemes shown in Figures 2A-C; Figure 4 shows a method of generating a pulse schedule for synchronising two or more logical qubits; Figure 5A illustrates a first example of a pulse schedule for a four logical qubit system with three multi-qubit logical operations; Figure 5B illustrates a second example of a pulse schedule for a four logical qubit system with three multi-qubit logical operations; and Figure 6 shows a schematic for the operation of a quantum circuit. Figure 1 schematically illustrates a round of syndrome extraction on a first logical qubit la. The logical qubit la is made of a set of seven physical qubits 3a-g, each represented by a separate horizontal line. The set of physical qubits is divided into four data qubits 3d, 3e, 3f, 3g (used to encode the logical quantum state of the logical qubit) and three auxiliary qubits 3a, 3b, 3c used for error correction stabiliser measurements. Syndrome extraction is a logical operation performed on logical qubits by performing check operations (such as stabiliser measurement operations) on the physical qubits that make up the logical qubits. Logical operations (or gates) are quantum operations that act upon logical quantum states encoded in logical qubits la. Physical operations (or gates) are quantum operations that act directly upon physical qubits 3a-g. Logical quantum operations are generally formed of multiple physical operations acting upon the physical qubits 3a-g that make up the logical qubit(s) la involved in the quantum operation. As one skilled in the art will appreciate, syndrome extraction is used in quantum error correction to obtain check values that provide a syndrome representative of an error state of physical qubits 3a-g that make up logical qubits la. Syndrome extraction is generally repeated numerous times. In the absence of any other logical operations, repeated syndrome extraction with quantum error correction will preserve the logical states of logical qubits la; rounds of syndrome extraction may therefore be referred to as quantum memory (QMEM) operations. The round of syndrome extraction is implemented by a number of physical gates or physical qubit operations. The operations performed on each physical qubit 3a-g are shown on the lines representing the qubit 3a-g in time order from left to right. The operations are driven by pulsed signals sent to the physical qubits 3a-g. The timing of the different operations is controlled by the timing of transmission of the pulsed signals. Squares on a horizontal line represent different single qubit gates or operations 5a-c on the corresponding physical qubits 3a-g. Vertical lines terminated by circles at either end and extending between two horizontal lines represent two qubit operations 7. The two qubit operations 7 are carried out on physical qubits 3a-g joined by the ends of the lines (the terminating circles being on the lines of the qubits involved in the operation 7). In this case, each of the two qubit operations 7 are CNOT gates (also referred to as a controlled-X or CX gates). The CX gate applies a bit flip to the target qubit when the control qubit is in a specified state. It will be appreciated that multiple operations can be performed at the same time. For example, single qubit operations can be performed at the same time, two qubit operations can be performed on different pairs of qubits 3a-g at the same time. A period where multiple operations are carried out at the same time is referred to as a layer. The round of syndrome extraction includes an entanglement portion Ila followed by a detection portion 11b. In the entanglement portion Ila, H-gate operations are performed on two of the auxiliary qubits 3a, 3c in a single layer, followed by a number of CNOT gate operations 7. Each CNOT gate operation 7 is between an auxiliary qubit and 3a,b,c and a data qubit 3d,e,f,g. The CNOT gates are carried out in a number of layers. The H-gates are then repeated in a single layer. In Figure 1, operations being performed at the same time (in the same layer) are indicated by operations being at the same position along the lines, or by square brackets above and below the lines representing the qubits 3a-g. In the example shown in Figure 1, the first auxiiary qubit 3a which has an H-gate is involved with CNOT gate operations 7 with two of the data qubits 3d, 3e and the other auxiliary qubit 3c which has an H-gate is involved in CNOT gate operations 7 with the other two data qubits 3f, 3g. The remaining auxiliary qubit 3b is involved in CNOT gate operations with all four data qubits 3d, 3e, 3f, 3g. In the detection portion 11b, each of the auxiliary qubits 3a, 3b, 3c are measured. The phases lla,b shown in Figure 1 and discussed above represent a syndrome extraction (e.g. a QMEM operation). This may be repeated a number of times. Figure 1 represents an example of a single logical qubit operation round for a single logical qubit la. When two logical qubits la, lb are involved in a multi-qubit operation (for example entanglement of the two logical qubits la,lb), each logical qubit la, lb may perform a number of rounds of single qubit logical operations (e.g. the round of syndrome extraction as in Figure 1) before a multi-qubit logical operation is performed (such as a logical CNOT gate). The syndrome extraction provides the logical qubits la, lb in the correct state, and maintains them in that state. As with the single qubit logical operation, multiple qubit logical operations are implemented by series of pulses sent to the physical qubits forming the two logical qubits la, lb, and the timing of the operations is controlled by the timing of the pulses. Ideally, the single qubit logical operations on each logical qubit la, lb will take the same amount of time, such that both logical qubits la, lb are ready to perform the multiqubit logical operation at the same time. This ensures neither logical qubit la, lb is ever idle. However, in practice, the individual operations on the two logical qubits la, lb will not take the same amount of time, even when the same operations are performed. By way of example, consider two logical qubits that run ten rounds of syndrome extraction (i.e. QMEM operations) as shown in Figure 1, prior to performing a logical CNOT gate. A round of syndrome extraction may include physical qubit H gates, CNOT gates and measurement gates. Due to manufacturing and material variations, the exact time for each of these physical qubit operations can vary from physical qubit to physical qubit. In an exemplary superconducting qubit system; Physical H gate operations can take anywhere from 40 to 60ns Physical CNOT gates can take anywhere from 68 to 104ns Physical measurement can take o 500ns for readout o Ring down time of 144 to 300ns In a round of syndrome extraction, physical H gates may be performed before and after the physical CNOT gates. To minimise the time taken, at least some of the physical CNOT gates may be performed simultaneously in a layer. However, there may be several layers of physical CNOT gates as a result of the different pairs used to perform CNOT operations. In the example discussed above, there are four layers of physical CNOT gates. This may lead to a variation of up to 340ns for a single round of syndrome extraction (QMEM operation) between two logical qubits la, lb. Over the course of ten rounds of QMEM, this leads to a total difference of 3.40us. Therefore, if ten rounds of syndrome extraction are completed in series, a first logical qubit la may sit idle for up to 3.40ps without being driven or measured by pulses, whilst waiting for the other logical qubit lb. In another example, consider a first logical qubit la that performs a logical H gate on the logical qubit la prior to a logical CNOT gate with a second logical qubit lb. A logical H-gate operation on a logical qubit la requires 3d+4 rounds of physical measurement (where d is code size). Typically, the same number of rounds of syndrome extraction would be performed on the second logical qubit lb. However, the logical H gate operation includes a different number of physical gates to syndrome extraction, and thus the logical qubits la, lb will take different amounts of time, again resulting in one of the logical qubits la,b being idle without being driven or measured by pulses, whilst waiting for the other logical qubit la,b. When a logical qubit la,b or physical qubit 3a-g is described as physically idle (i.e. during periods of physical idle time), there no operation performed on it and no pulses are generated to drive or measure that qubit la,b, 3a-g. In the below, reference to idle qubits and idle time will be taken as a reference to physically idle qubits and physical idle time. In an exemplary system, the median energy relaxation time of the physical qubits may be 14.8ps and the dephasing time may be 8.5ps. The idle times in the examples above are comparable to the relaxation and dephasing times. Physical idle time incurs a substantial penalty that negatively impacts later operations involving the logical qubit la by introducing errors and possibly offsets any previous error correction. With such a long idle time, the logical qubit la may be considered to have moved outside the fault tolerant regime. Figures 2A, 2B and 2C schematically illustrate control schemes that mitigate the idle time and ensure there is no single instance of idle time having duration comparable to the relaxation and dephasing times prior to a logical multi-qubit logical operation. This ensures the logical qubits la, lb both remain in the fault tolerant regime. Figures 2A, 2B and 2C show rounds of single logical qubit operations on a first logical qubit la in the upper row and a second logical qubit lb in the lower row, in time series from left to right. By way of example only, both logical qubits la, lb perform a number of rounds of syndrome extraction. However, it will be appreciated that this is by way of example only, and any single qubit logical operations may be performed. Figures 2A, 2B and 2C only show the single qubit logical operations. The multi logical qubit logical operation is not illustrated. For illustrative purposes only, it is considered that the syndrome extraction operations 17a-k on the first logical qubit la take 1725 ns and the syndrome extraction operations 19a-j on the second logical qubit lb take 1925. Therefore, the second logical qubit lb takes 2us longer to complete the ten rounds of syndrome extraction. In the first control scheme, shown in Figure 2A, each logical qubit la, lb completes ten rounds of syndrome extraction 17a-j, 19a-j. In this example, the total idle time for the first logical qubit la is split across the different single qubit logical operations 17a-j. Therefore, the first logical qubit la is held idle for a period 2la-j of 200ns after each round of syndrome extraction 17a-j. This means that the start of each syndrome extraction operation 17a-j on the first logical qubit la is synchronised to the start of a syndrome extraction operation 19a-j on the second logical qubit lb. Each logical qubit la, lb is able to complete ten rounds of syndrome extraction 17a-j, 19a-j and reach a point 23 for the logical CNOT operation to start whilst in the error tolerant regime, since no single period of idle time 2 la-j is comparable in length to the relaxation and dephasing times of the physical qubits la, lb. In the schemes of Figure 2B and 2C, the first logical qubit la performs eleven rounds of syndrome extraction 17a-k, whilst the second logical qubit lb performs ten rounds of syndrome extraction 19a-j. Even with an additional round of syndrome extraction 17k, the first logical qubit la takes 275ns less than the second logical qubit lb to complete the single logical qubit logical operations. In the scheme of Figure 2B, the first logical qubit la is held idle for a period 21a after completing all eleven syndrome extraction operations. The duration of this idle period 21a is 275ns. In the scheme of Figure 2C, the period of idle time is split, in a similar manner to the scheme of Figure 2A. In this example, the first logical qubit la is held for an idle period 21a-k after each syndrome extraction operation. The duration of each idle period 21a-k is (275 / 11) = 25ns. The inset of Figure 2C shows the first few rounds of syndrome extraction in more detail. In the schemes of Figure 2B and 2C, the start of rounds of syndrome extraction 17a-k, 19a-j are only synchronised for the first operation 17a, 19a. As with the scheme of Figure 2A, each logical qubit la, lb is able to complete the specified number of rounds of syndrome extraction 17a-j, 19a-j and reach a point 23 for the logical CNOT operation to start whilst in the error tolerant regime, since no single period of idle time 21a-k is comparable in length to the relaxation and dephasing times of the physical qubits in the logical qubits la, lb. Figure 3 illustrates a control system 100 for operating logical qubits la, lb using the schemes discussed above. The control system 100 includes at least a memory 102, a processor 104 such as a digital signal processor (DSP), an interface or input / output unit 106 and one or more pulse generators 108 for generating the pulses used to drive qubit operations. The interface unit 106 allows for user input or connection to the control unit 100. It may include input and output devices such as a keyboard, a monitor, a touchscreen and the like to allow for direct input to and monitoring of the control unit 100. Instead of or as well as the input and output devices, the interface unit 106 may provide a wired and / or wireless connection to allow for remote access, for example over Wi-Fi, 3G, 4G, 5G, the internet, Bluetooth, Local Area Networks, Wide area Networks and the like. The memory 102, DSP 104, input / output unit 106 and pulse generators 108 are all in communication with each other over a suitable communication bus 110 or other wired or wireless connection. The memory 102 has a programme storage portion 112 and a data storage portion 114. The programme storage portion 112 includes various software modules 116, 118, 120, 126 which contain instructions that, when performed on the DSP 104 cause the control system 100 to perform various functions. The modules in the programme storage portion 112 include drivers 116 for controlling operation of the pulse generators 108 and other aspects of the system. The programme storage portion 112 also includes a calibration module 118 for calibrating the pulses for different qubits and the times of various single and multi-qubit operations (on both physical and logical qubits). Calibration data 118a generated by the calibration module can be stored in the data storage portion 114 of the memory 102. The programme storage portion 112 also includes instructions for providing a software application 120 that allows input of quantum circuits, operations and routines to be performed on a quantum processing unit 122 driven by pulses transmitted from the pulse generators 108. The quantum circuits, operations and routines may be specified by the user or may be selected from prestored operations 124 stored in the data storage portion 104 of the memory 102. The input of the quantum circuits, operations and routines may be by a user, either directly through the input / output unit 106 or remotely through another system or may be a higher level controller or control system. The programme storage portion 112 further includes a scheduler (or compiler / scheduler) module 126 that creates the schedule of pulses to be generated, including any idle time, based on the schemes discussed above and the calibration data 118a stored in the memory 102. The scheduler 126 or another module of the controller 100 then initiates the pulses according to the schedule. Further modules (not shown) may be provided to allow for control and readout of qubit operations. The different modules 116, 118, 120, 126 may call other modules where necessary and may retrieve data stored in the data storage portion 114 of the memory 102. For example, the scheduler 126 and calibration module (or any other modules that control operation of the quantum processing unit 122 may call the drivers 116. Figure 4 shows a method 200 of generating a pulse schedule for two or more logical qubits la, lb, and then performing the operation using the determined pulse schedule and the pulse generators 108. While the examples discussed above relate only to two logical qubits performing a single multi-qubit logical operation, it will be appreciated the same schemes can be applied to more complex quantum circuits. A quantum circuit is considered to a series of operations that provide an outcome to a user. The quantum circuit includes at least some operations to be performed on single logical qubits la, lb, and at least some multiqubit operations to be performed on multiple logical qubits la, lb. In a first step 202, the scheduler 126 receives a request to ran a quantum circuit. In a second step 204, calibration data 118a is retrieved from the memory 102. If no calibration data 118a is present or if it is present but out-of-date, a calibration process may be performed to measure calibration data 118a. In a third step 206, a schedule for the pulses required to enact the quantum circuit is generated. The schedule is developed to include periods of idle time that are not comparable with the relaxation and dephasing times of the physical qubits in the logical qubits la, lb, which are also determined during calibration. This may be based on any of the schemes discussed above. The schedule may be generated based on a number of principles. As discussed above, no period of idle time should be comparable to the length of the relaxation and dephasing times of the physical qubits, to ensure the logical qubits remain in the fault tolerant regime. In one example, the schedule is optimised to minimise the total idle time across all the logical qubits la, lb, whilst maintaining the logic of the overall circuit. In order to achieve this, the following guidelines may be used, in the following order of priority: 1. If the difference between the times taken for the logical qubits to complete the same number of rounds of single qubit logical operations is sufficient that one of the qubits can perform one or more additional operations, the additional operations are included in the schedule. Sufficient operations should be added such that the time difference is less than the length of one single qubit logical operation. 2. If adding one round of a single qubit logical operation to the qubit which takes less time to perform single qubit logical operations reduces the overall idle time (across all qubits), this should be added, and the remaining idle time split between the single qubit logical operations on the other qubit. 3. Any remaining idle time is split between single qubit logical operations on the qubit that takes less time to perform single qubit logical operations. These guidelines are given by way of example only. In other situations, there may be additional or different considerations other than minimising total idle time and different guidelines and / or priorities may be considered. As discussed above, the schemes ensure that there is no period of idle time comparable to the length of the relaxation and dephasing times of the physical qubits, to ensure the logical qubits remain in the fault tolerant regime. In some examples, this may simply mean that the periods of idle time are shorter than the relaxation and dephasing times. In other examples, the maximum idle time is at least an order of magnitude less than the relaxation and dephasing times. The maximum idle times may be more than an order of magnitude less than the relaxation and dephasing times. In some cases, the periods of idle time may be less than 500ns. In a final step 208 the scheduler 126 runs the quantum circuit based on the determined schedule, using the pulse generators 108. In the examples shown in Figures 2A to 2C, two logical qubits la, lb are shown, and the only multi-qubit logical operation is performed between the two logical qubits la, lb. However, it will be appreciated that the schemes discussed in relation to Figures 2A to 2C and the method shown in Figure 4 may be scaled up to any number of logical qubits la, lb. Furthermore, where a quantum circuit includes a number of multi-qubit logical operations, any given logical qubit la, lb may be involved with different logical qubits for different logical operations and logical qubits la, lb may be involved in different multi-qubit logical operations with different logical qubits. By way of example, Figure 5A illustrates a set of four logical qubits la, lb, 1c, Id. A first multi-qubit logical operation 25a (for example a logical CNOT gate) is performed on the third and fourth logical qubits 1c, Id, a second multi-qubit logical operation 25b is then performed on the first and second logical qubits la, lb and a third multi-qubit logical operation 25c is finally performed on the second and third logical qubits lb, 1c. Each logical qubit la-d performs a number of single qubit logical operations 27a-g, 29a-g, 3 1 a-i. 33a-d (for example syndrome extraction or QMEM) prior to any multi-qubit logical operation. After the first logical qubit operation 25a, the fourth logical qubit Id is no longer considered, since it is no longer involved in further operations. Likewise, after the second qubit logical operation 25b, the first logical qubit la is no longer considered. When developing the schedule for the operations discussed above: The third and fourth logical qubits 1c, Id are kept in the fault tolerant regime prior before the first multi-qubit logical operation 25a by providing periods of idle time 35a-d after each round of syndrome extraction 3 la-d on the third logical qubit 1c. This is in line with the scheme shown in Figure 2A. The first and second logical qubits la, lb are kept in the fault tolerant regime prior before the second multi-qubit logical operation 25b by completing one more rounds of syndrome extraction 27g on the first logical qubit la than the second logical qubit lb in this period. In addition, periods of idle time 37a-g are provided after each round of syndrome extraction 27a-g on the first qubit la. This is in line with the scheme shown in Figure 2C. After the first multi-qubit logical operation, the third logical qubit 1c is kept in the fault tolerant regime by continuing to cycle rounds of syndrome measurement 3 le-i. After the second multi-qubit logical operation 25b a further round of syndrome extraction 29g is performed on the second logical qubit lb. The end of the final rounds of syndrome extraction 29g, 3 li on the second and third logical qubits lb, 1c are synchronised such that the third multi-qubit logical operation can be performed without any logical qubit la-d falling out of the fault tolerant regime. Figure 5B illustrates a second example of a set of four logical qubits la, lb, 1c, Id performing a number of single qubit logical operations 27a-g, 29a-g, 3 la-j, 33a-d and multi-qubit logical operations 25a-c. In the example shown in Figure 5A, the multiqubit logical operations 25a-c include only a single round of operation. In the example shown in Figure 5B, at least some of the multi-qubit logical operations 25a-c include multiple rounds. In the example shown in Figure 5B, a first multi-qubit logical operation 25a (for example a logical CNOT gate) is performed on the third and fourth logical qubits 1c, Id. The first multi-qubit operation involves only a single round of operations across the third and fourth qubits 1c, Id. A second multi-qubit logical operation 25b is then performed on the first and second logical qubits la, lb, involving three rounds of operations 25bi, 25b2, 25bs. Finally, a third multi-qubit logical operation 25c is performed on the second and third logical qubits lb, 1c, involving two rounds of operation 25ci, 25c2. Multiple rounds of multi-qubit logical operations may be required in scenarios such as lattice surgery. In the schedule shown in Figure 5B the logical qubits la-d are generally synchronised in a similar manner to the schedule shown in Figure 5A. However, since the two multiqubit logical operation 25b takes longer to complete, additional single qubit logical operations are required on the third logical qubit 1c. The schemes shown in Figures 2A to 2C are given by way of example only. The schemes are used to synchronise two (or more) logical qubits so that both are available for multiqubit logical operations at the same time, and no single period of idle time is comparable in length to the relaxation and dephasing times of the physical qubits, and the logical qubits la,b,c,d stay in the fault tolerant regime. It will be appreciated that there are various ways of splitting (and adding) idle time and / or using additional single qubit logical operations to synchronise a set of logical qubits la, lb, 1c, Id, so that they are in the correct state at the correct time for a multiqubit logical operation. Where the same number of operations are performed on different logical qubits la, lb, 1c, Id, the periods of idle time and single qubit logical operations may be arranged such that the starts of the single qubit logical operations are synchronised, such as in Figure 2A. However, this need not be the case, and the single qubit logical operations on different logical qubits la, lb, 1c, Id need not be synchronised, even when the same number of logical operations are performed on both logical qubits la, lb, 1c, Id. In the above examples, the periods of idle time and / or additional single qubit logical operations are provided on the logical qubit la, lb, 1c, Id which has a shorter time to complete the single qubit logical operations. However, this need not be the case. In some cases, it may be that either one or both of the logical qubits la, lb has one or more periods of idle time and / or additional rounds of single qubit logical operations to synchronise the logical qubits for a multiple qubit logical operation. For example, it may be that where the time difference for the time to complete the single qubit logical operations on two logical qubits la, lb is less than the duration of a single qubit logical operation on whichever of the logical qubits la, lb takes less time to complete the single qubit logical operations, then one or more periods of idle time may be added to the logical qubit la, lb that takes longer, to allow an extra round of single qubit logical operations to be performed in the logical qubit la, lb that takes less time. In the examples discussed above, periods of idle time have the same duration when multiple periods of idle time are introduced on a single logical qubit la, lb. This need not be the case, and the idle time need not be split equally between single qubit logical operations. For example, different periods of idle time may have different durations and / or a number of single qubit logical operations may be performed without any idle period. In the above examples, the multi-qubit logical operations are pair-wise operations. However, this need not be the case, and it will be appreciated that the schemes discussed above may be applied to three or more logical qubits. In the examples discussed above, the same single qubit logical operation (syndrome extraction) is used on the logical qubits involved in a multi-qubit logical operation. It will be appreciated that this need not be the case. Different single qubit logical operations may be performed on different logical qubits la, lb, 1c, Id. Furthermore, even on a single logical qubit la, lb, 1c, Id, multiple different single qubit logical operations can be performed rather than repeating the same logical operation. It will be appreciated that the above techniques may be implemented with any suitable single and multiple qubit logical operations. Syndrome extraction, QMEM and H gates are given as examples of single logical qubit operations, and CNOT is an example of a multi-qubit logical operation, but any other type of single and multiple qubit logical operations may be used. Single logical qubit operations include, but are not limited to: syndrome extraction; QMEM; logical H-gate; logical Pauli X / Y / Z gates; logical S gate; logical T gate; logical rotation gates. Multi-qubit logical operations include, but are not limited to: logical CNOT (CX) gate; logical CPHASE (CZ) gate; logical SWAP gate; logical Toffoli gate; logical Fredkin gate. Where additional rounds of single qubit logical operations are provided, they may comprise a logical identity operation that does not change the state of the qubit (or a pair of logical operations comprise a state change and its inverse, so there is no overall state change). Different numbers of rounds of single-qubit logical operations may also be performed by changing the order of logical operations and / or propagating single-qubit logical operations through multi-qubit logical operations. For example, the order of commuting logical operations (e.g. a multi-qubit logical gate and a single qubit logical gate acting on one of the logical qubits involved in the multi-qubit logical gate) may be swapped such that an additional single-qubit logical operation is performed in the fixed period of time before a multi-qubit gate rather than simply performing additional rounds of logical identity operations. Changing the order of logical gates in this way advantageously allows the overall runtime of the quantum computation to be reduced by utilising logical qubits that would otherwise be idle. The gate ordering may be determined by a compilation system or similar ahead of runtime. The control system 100 discussed above is given by way of example only. Any suitable control system may be used to generate a pulse schedule and implement the pulse schedule on a quantum processor 122. In the examples discussed above, the control system 100 generates the pulse schedule for an entire quantum circuit prior to the operation being performed. However, it will be appreciated that in some cases, the scheduler 126 may only generate the schedule for an initial portion of the circuit before the quantum circuit begins. The pulse schedule for later portions may be generated after at least part of the first portion has been completed. By generating the pulse schedule in portions, it allows for any updates to recalibration to also be taken into account, if they occur. Figure 6 illustrates the schematic of the operation of a quantum circuit in which the pulse schedule is prepared in portions or parts. In this example, time is on the vertical axis. As in the method discussed in relation to Figure 4, the process 300 starts when the application 120 initiates 302 the quantum circuit. In a next step 304, the calibration data is retrieved from the memory 102 by the scheduler 126, and a schedule for the first portion of the quantum circuit is determined in further step 306. The first portion of the quantum circuit is then run at step 308. At regular intervals, the calibration data is updated in the memory 102, in a repeating step 310. At step 312, the scheduler 126 determines that the pulse schedule should be updated using new calibration data. This may be when the quantum circuit is approaching the end of the first portion, or if a change above a predetermined threshold is detected in the calibration data. At next step 314, the updated calibration data is retrieved, and the pulse schedule for the second portion is determined at step 316. The second portion of the quantum circuit is then implemented at step 318. In this example, the quantum circuit only includes two portions. Therefore, the quantum processing unit 122 returns a complete message 320 to the scheduler 126, and the scheduler 126 provides the outcome 322 of the circuit to the application 120. It will be appreciated that a quantum circuit may include any number of portions. The portions may be scheduled so that there is a simultaneous break in activity on all logical qubits between each portion, allowing for the schedule to be updated. Where a first portion is being implemented, the schedule for the next portion may be being determined in parallel, to allow the second portion to be implemented immediately after the first. In some cases, the schedule for multiple portions may be generated at once. These schedules may only be updated if a significant change in the calibration data is detected, Figures 2A, 2B and 2C and Figures 5A, 5B and 6 are given by way of example only. The Figures are not to scale along the time axes, and the Figures are for illustrative purposes only. Values, durations and the like are also given by way of example only. 5

Claims

1. A method of performing logical qubit operations on an ensemble of logical qubits, each logical qubit having a plurality of physical qubits, the method comprising:performing one or more rounds of single qubit logical operations on each of a set of the logical qubits; andperforming a multi-qubit logical operation using at least two of the set of logical qubits,wherein the logical qubits involved in the multi-qubit logical operation are synchronised prior to the multi-qubit logical operation by one or more of:i. providing periods of physical idle time between rounds of single qubit logical operations performed on one or more of the logical qubits involved in the multi-qubit logical operation; andii. performing different numbers of rounds of single qubit logical operations on the logical qubits involved in the multi-qubit logical operation in a fixed period of time.

2. The method of claim 1, wherein the logical qubits involved in the multi-qubit logical operation are synchronised prior to the multi-qubit logical operation by one or more of:i. providing periods of physical idle time between rounds of single qubit logical operations; andii. performing more rounds of single qubit logical operations in a fixed period of time,on a first logical qubit of the logical qubits involved in the multi-qubit logical operation, the first logical qubit having a shorter duration for rounds of single qubit logical operations than a second logical qubit involved in the multi-qubit logical operation.

3. The method of claim 2 in which more rounds of single qubit logical operations are performed on the first logical qubit than on the second logical qubit, roundsof single qubit logical operations on the second logical qubit being of longer duration than rounds of single qubit logical operations on the first logical qubit.

4. The method of claim 3 including:providing one or more periods of physical idle time on the second logical qubit.

5. The method of claim 4, including providing periods of physical idle time between rounds of single qubit logical operations on the second logical qubit, optionally wherein the periods of physical idle time on the second logical qubit are after each round of single qubit logical operations and / or of equal duration.

6. The method of any of claims 3 to 5, including performing a single period of physical idle time on the first logical qubit, optionally wherein the single period of physical idle time is after the last round of single qubit logical operations before the multi-qubit logical operation.

7. The method of claim 2, wherein the same number of rounds of single qubit logical operations are performed on the first and second logical qubits.

8. The method of claim 7, wherein the start of each round of single qubit logical operations on the first logical qubit is synchronised to the start of a corresponding round of single qubit logical operations on the second logical qubit.

9. The method of any of claims 2 to 5 or 7 to 8, in which periods of physical idle time are provided after each round of single qubit logical operation on the first logical qubit.

10. The method of claim 9, wherein the periods of physical idle time provided after each round of single qubit logical operations on the first logical qubit are the same duration.

11. The method of any preceding claim, wherein any period of physical idle time is less than the median energy relaxation time and dephasing time of the physical qubits making up the logical qubits.

12. The method of claim 11, wherein any period of physical idle time is at least an order of magnitude less than the median energy relaxation time and dephasing time of the physical qubits making up the logical qubits.

13. The method of claim 11 or claim 12, wherein any period of physical idle time is less than 500ns.

14. The method of any preceding claim, wherein at least some of the rounds of single qubit logical operations include syndrome extraction rounds.

15. The method of claim 14 wherein, when there are more rounds of single qubit logical operations on a logical qubit, any additional rounds of single qubit logical operations are syndrome extraction rounds.

16. The method of claim 14 or claim 15, wherein the syndrome extraction rounds are QMEM operations.

17. The method of any preceding claim wherein the same single qubit logical operation is performed on different logical qubits.

18. The method of any preceding claim, wherein a plurality of multi-qubit logical operations are performed:at the same time with non-overlapping groups of two or more logical qubits; and / orin time series with overlapping or non-overlapping groups of two or more logical qubits, optionally wherein non-overlapping groups of logical qubits involved in multi-qubit logical operations are synchronised in parallel.

19. The method of claim 18, wherein when multi-qubit logical operations are performed on overlapping groups, synchronisation is performed for a groupassociated with a later multi-qubit logical operation after all logical qubits in the group have completed the corresponding earlier multi-qubit logical operations they are involved in as part of different groups.

20. The method of claim 18 or claim 19, wherein when multi-qubit logical operations are performed on overlapping groups, synchronisation is at least in part performed for a group associated with a later multi-qubit logical operation when at least one of the logical qubits in the group has completed its earlier multi-qubit logical operations but before other logical qubits in the group have completed their earlier multi-qubit logical operations.

21. The method of claim 20, including at least one of:performing single logical qubit operations on the at least one logical qubit after it has completed its previous multi-qubit logical operation; andperforming different numbers of rounds of single qubit logical operations on the logical qubits in the group associated with the later multi-qubit logical operation in the period between the at least one logical qubit completing its previous multi-qubit logical operation and the rest of the logical qubits in the group associated with the later multi-qubit logical operation have completed their previous multi-qubit logical operations.

22. The method of any of claims 18 to 21, comprising:calibrating the ensemble of logical qubits to generate first calibration data specifying the time taken for single and multi-qubit logical operations;generating a schedule of a first part of the plurality of multi-qubit logical operations, including the synchronisation, based on the first calibration data;performing the first part of the plurality of multi-qubit logical operations; recalibrating the ensemble of logical qubits to generate second calibration data specifying the time taken for single and multi-qubit logical operations;generating a schedule of a second part of the plurality of multi-qubit logical operations, including the synchronisation, based on the second calibration data; andperforming the second part of the plurality of multi-qubit logical operations.

23. A method of determining a pulse schedule for performing at least part of a quantum circuit on an ensemble of logical qubits, each logical qubit having a plurality of physical qubits, the method comprising:obtaining calibration data of the ensemble of logical qubits, the calibration data specifying the time taken to perform single and multiqubit logical operations in the quantum circuit; andgenerating a schedule for pulses to be generated to cause the ensemble of logical qubits to perform the quantum circuit, wherein, in order to synchronise the logical qubits involved in a multi-qubit logical operation are prior to the multi-qubit logical operation, the pulse schedule includes one or more of:i. periods of physical idle time between rounds of single qubit logical operations on one or more of the qubits involved in a multi-qubit logical operation; andii. different numbers of rounds of single qubit logical operations on the logical qubits involved in a multi-qubit logical operation in a fixed period of time.

24. A non-transitory computer readable medium comprising instructions which, when executed by a processor, cause the processor to perform the steps of any preceding claim.

25. A system comprising:a quantum processing unit having an ensemble of physical qubits arranged to form a plurality of logical qubits;for each physical qubit, one or more pulse generators arranged to drive and read out the physical qubits to perform single and multi-qubit logical operations on the logical qubits; anda scheduler comprising one or more processors, the one or more processors arranged to cause the pulse generators to:perform one or more rounds of single qubit logical operations on each of a set of the logical qubits,5 perform a multi-qubit logical operation, using at least two of theset of the logical qubits,wherein the logical qubits involved in a multi-qubit logical operation are synchronised prior to the multi-qubit logical operation by one or more of:10 i. providing periods of physical idle time between rounds ofsingle qubit logical operations on one or more of the logical qubits involved in the multi-qubit logical operation; andii. performing different numbers of rounds of single qubit15 logical operations on the logical qubits involved in themulti-qubit logical operation in a fixed period of time.

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