A comparator circuitry

Abstract

A comparator 300 comprising: a logic circuitry configured to receive two binary inputs A and B, and identify if the binary inputs are same or different, where the logic circuitry comprises a plurality

Description

TECHNICAL FIELD

[0001] The application relates to systems for detecting faults in the operation of circuits. The application is particularly related to comparator detecting faults in the operation of circuits while detecting any fault within itself. BACKGROUND

[0002] Safety-critical systems are typically those systems whose failure would cause a significant increase in the risk to the safety of people or the environment. In safety-critical systems, at least some of the components of a system must meet safety goals sufficient to enable the system as a whole to meet a level of safety deemed necessary forthat system.

[0003] Safety-critical systems can be implemented either as dedicated hardware or as processors for running safety-critical software. For example, fly-by-wire systems for aircraft, driver assistance systems, railway signalling systems and control systems for medical devices would typically all be safety-critical software running on processors. Where processors / processing systems form an integral part of a safety-critical system it is necessary for the processing system itself to satisfy safety goals such that the system as a whole can meet the appropriate safety level. In the automotive industry, the safety level is normally an Automotive Safety Integrity Level (ASIL) as defined in the functional safety standard ISO 26262.

[0004] For various hardware elements of a processing system, such as its processing unit(s), safety goals may be expressed as a set of metrics, such as: a maximum number of failures in a given period of time (often expressed as Failures in Time, or FIT); and the effectiveness of mechanisms for detecting single point failures (e.g. Single Point Fault Metric, or SPFM) and latent failures (e.g. Latent Fault Metric, or LFM). It is possible for the hardware elements of a processing system to develop permanent faults. It may not be possible forthose hardware elements to recover from (e.g. return to normal operation after developing) a permanent fault. It is also possible for the hardware elements of a processing system to develop transient faults. For example, transient faults can be introduced into hardware by transient events (e.g. due to ionizing radiation, voltage spikes, or electromagnetic pulses). In binary systems, these types of transient events can cause random bitflipping in memories and along the data paths of a processor. It may be possible for the hardware elements of a processing system to recover from (e.g. return to normal operation after developing) a transient fault. For example, this could be achieved by returning those hardware elements to a known state - e.g. by performing a “reset” of those hardware elements.

[0005] In general, transient, or permanent faults in memory or data paths that move data without transforming it can be protected against and / or corrected for by error correcting code (ECC) and / or parity bit check error detection mechanisms. There may be various methods to make the system more reliable such as modular redundancy. Modular redundancy is a technique used in software and hardware systems to ensure reliability. It involves duplicating components of a system, so that if one component fails, another can replace it. There are various types of modular redundancy techniques, such as N Modular Redundancy, Dual Modular Redundancy (DMR), and Triple Modular Redundancy (TMR).

[0006] The safety-critical systems may use processing systems that are required to meet the ASIL B or ASIL D standards of ISO 26262. In order to be certified as meeting the ASIL B or ASIL D standards of ISO 26262, it may need to be demonstrated that a range of different faults that might occur at a processing system can be detected within a predetermined time period of those faults occurring. As such, it is desirable to provide a processing system that is configured in such a way that faults occurring at that processing system can be detected.

[0007] It is also to be understood that processing systems can be used in other applications, other than the automotive applications. For example, processing systems can be used in super-computing I data centre applications. In said other applications, it can also be desirable to provide a processing system that is configured in such a way that one or more faults occurring at that processing system can be detected - e.g. such that appropriate action(s) can be timely taken to recover from those faults, and / or such that faulty or defective parts can be identified and replaced - whether or not those other applications are subject to safety standards. SUMMARY

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0009] A comparator comprising a logic circuitry configured to receive two binary inputs A and B, and identify if the binary inputs are same or different is provided. The logic circuitry comprises a plurality of logic gates configured to: perform bitwise operations logically equivalent to AND operations A • B, A • B, A • B and A ■ B; and generate a binary codeword [Z, ~Z\ indicative of whether the binary inputs are the same or different based on the outputs of the bitwise operations, wherein one binary codeword is predefined as a legal codeword to indicate that the binary inputs are the same.

[0010] According to a first aspect, there is provided a comparator comprising a logic circuitry configured to receive two binary inputs A and B, and identify if the binary inputs are same or different. The logic circuitry comprises a plurality of logic gates configured to: perform bitwise operations logically equivalent to AND operations A ■ B, A ■ B, A ■ B and A • B; and generate a binary codeword [Z, ~Z\ indicative of whether the binary inputs are the same or different based on the outputs of the bitwise operations, wherein one binary codeword is predefined as a legal codeword to indicate that the binary inputs are the same.

[0011] Optionally, the comparator provides the generated binary codeword as output of the comparator.

[0012] Optionally, the comparator is configured to generate a binary codeword otherthan the legal codeword when the inputs A and B are different.

[0013] Optionally, the comparator is configured to receive each binary input A and B from different systems and perform the comparison to indicate if the systems are producing the same output.

[0014] Optionally, the comparator is configured to operate as a fault avoidance architecture by masking faults in the working of the comparator that do not affect the output of the comparator when the generated codeword is from a first subset of possible binary codewords. The first subset of possible binary codewords are the correct outputs of the comparator (i.e. codewords [1,0] and [0,1] which are the outputs generated when the comparator is working correctly). Optionally, the comparator is configured to mask single stuck-at faults within the logic circuitry of the comparator that do not affect the correct working of the comparator. When a stuck-at fault occurs in any of the gates in the comparator, and when the other gates are functioning correctly, then the comparator either still provides an output indicating the correct comparison result or provides an output indicating the fault is present. When the single stuck-at fault in the comparator does not affect the correct working of the comparator, the comparator may mask such faults and generate an output indicating the correct comparison result.

[0015] Optionally, the comparator is configured such that codewords from a second subset of possible binary codewords indicate that there is a fault in the working of the comparator. The second subset of possible binary codewords are incorrect output of the comparator (i.e. codewords [0,0] and [1,1] which are generated when the comparator is not working correctly). Optionally, the comparator is configured to identify single stuck-at faults within the logic circuitry of the comparator that affect the correct working of the comparator.

[0016] Optionally, the logical operations are performed by a plurality of AND gates.

[0017] Optionally, the logic circuitry generates the binary codeword [Z, ~Z\ by: generating Zby performing a bitwise operation logically equivalent to an OR operation between A.Sand A.B;and generating ~Zby performing a bitwise operation logically equivalent to an OR operation between A.B and A.B.

[0018] Optionally, the logic circuitry comprises two OR gates for generating the binary codeword [Z, ~Z|.

[0019] Optionally, the logic circuitry comprises NOT gates for generating invented inputs A and B.

[0020] Optionally, the legal codeword is [1,0],

[0021] Optionally, the binary codeword other than the legal codeword includes [0,0], [0, 1] and [1,1],

[0022] According to a second aspect, there is provided a method of identifying if two binary inputs A and B received by a comparator are same or different. The method comprises: performing bitwise operations logically equivalent to AND operations A- B, A-B, A-B and A-B; and generating a binary codeword [Z, ~Z\ indicative of whether the binary inputs are the same or different based on the outputs of the bitwise operations, wherein one binary codeword is predefined as a legal codeword to indicate that the binary inputs are the same.

[0023] Optionally, the method further comprises providing the generated binary codeword as the output of the comparator.

[0024] Optionally, the method comprises generating a binary codeword other than the legal codeword when the binary input A and B a re different.

[0025] Optionally, the method comprises receiving each binary input A and B from different systems and performing the comparison to indicate if the systems are producing the same output.

[0026] Optionally, the method comprises masking the faults in the working of the comparator that do not affect the output of the comparator when the generated codeword is from a first subset of possible binary codewords.

[0027] Optionally, the method comprises indicating that there is a fault in the working of the comparator when the generated codeword is from a second subset of possible binary codeword.

[0028] Optionally, the method comprises generating the binary codeword [Z, ~Z\ by: generating Z by performing an OR operation between two logical AND operations A ■ B and A ■ B; and generating -Z by performing an OR operation between the other two logical AND operations A ■ B and A ■ B.

[0029] According to a third aspect, there is provided a method of manufacturing, using an integrated circuit manufacturing system, a comparator according to the first aspect.

[0030] According to a fourth aspect, there is provided computer readable code configured to cause the method according to the second aspect to be performed when the code is run.

[0031] According to a fifth aspect, there is provided computer readable storage medium having encoded thereon the computer readable code according to the fourth aspect.

[0032] According to a sixth aspect, there is provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a comparator according to the first aspect.

[0033] According to a seventh aspect, there is provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a comparator according to the first aspect that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the comparator.

[0034] According to an eighth aspect, there is provided a comparator, wherein the comparator comprising: a logic circuitry configured to receive inputs A and B, wherein the logic circuitry comprises a plurality of logic gates configured to: for each input [A, B[ perform an AND operation between all four combinations of A B, A and B; generate a first output by performing an OR operation between output of two AND operations A ■ B and A-B; generate a second output by performing an OR operation between output of two AND operations A ■ B and A • B, and wherein one combination [1, 0] of the first and second output indicates that the inputs A and Fare same and any other combination of the first and second output indicates that the input A and Fare different or there is a fault in the comparator.

[0035] According to a ninth aspect, there is provided a logic circuit of a comparator configured to compare two inputs A and F, wherein the logic circuit comprises: a first AND gate configured to perform AND operation between A and B, a second AND gate configured to perform AND operation between NOT A and NOT B, a third AND gate configured to perform AND operation between A and NOT B, a fourth AND gate configured to perform AND operation between NOT A and B, a first OR gate configured to perform OR operation between outputs of the first and the second AND gates to generate a first output; a second OR gate configured to perform OR operation between outputs of the third and the fourth AND gates to generate a second output; and wherein a combination [1,0] of the first and second output indicates that the inputs A and B are same and any other combination of the first and second output indicates that the input A and B are different or there is a fault in the comparator.

[0036] The comparator may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, a comparator. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture a comparator. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of a comparator that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a comparator.

[0037] There may be provided an integrated circuit manufacturing system comprising: a non-transitory computer readable storage medium having stored thereon a computer readable description of the comparator; a layout processing system configured to process the computer readable description so as to generate a circuit layout description of an integrated circuit embodying the comparator; and an integrated circuit generation system configured to manufacture the comparator according to the circuit layout description.

[0038] There may be provided computer program code for performing any of the methods described herein. There may be provided non-transitory computer readable storage medium having stored thereon computer readable instructions that, when executed at a computer system, cause the computer system to perform any of the methods described herein.

[0039] The above features may be combined as appropriate, as would be apparent to a skilled person, and may be combined with any of the aspects of the examples described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Examples will now be described in detail with reference to the accompanying drawings in which:

[0041] FIG. 1 shows a fault detecting system according to the prior art;

[0042] FIG. 2 illustrates a fault detection system;

[0043] FIG.3 shows a comparator according to the present invention;

[0044] FIG.4 shows an example implementation of the comparator according to the present invention;

[0045] FIG. 5 is a flowchart illustrating the working of the comparator in accordance with the present invention;

[0046] FIG. 6 shows a computer system in which the comparator is implemented; and

[0047] FIG. 7 shows an integrated circuit manufacturing system for generating an integrated circuit embodying a comparator.

[0048] The accompanying drawings illustrate various examples. The skilled person will appreciate that the illustrated element boundaries (e.g., boxes, groups of boxes, or other shapes) in the drawings represent one example of the boundaries. It may be that in some examples, one element may be designed as multiple elements or that multiple elements may be designed as one element. Common reference numerals are used throughout the figures, where appropriate, to indicate similar features. DETAILED DESCRIPTION

[0049] The following description is presented by way of example to enable a person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein and various modifications to the disclosed embodiments will be apparent to those skilled in the art.

[0050] Embodiments will now be described by way of example only.

[0051] FIG. 1 shows a fault detecting system 100. The system 100 uses a fault tolerant / detection technique such as triple modular redundancy (TMR) sometimes known as triple-mode redundancy. As discussed above TMR is a modular redundancy technique used in software and hardware systems to ensure reliability. It involves replicating a system as three systems so that even if one system fails, there are still two remaining systems whose outputs can be crosschecked. The overall system 100 comprises three identical circuits (or systems, or sub-systems) such as a first circuit 102, a second circuit 104 and a third circuit 106. The second and third circuits would be a replication of the first circuit 102. Therefore, the three circuits would be identical to each other. The three circuits are connected to a majority voting gate 108.

[0052] The three circuits 102,104 and 106 may compute the same specified Boolean function for the same input. Each circuit produces an output for the input provided to it. The first circuit 102 produces an output A, the second circuit 104 produces an output B and the third circuit 106 produces an output C for the provided input. Ideally the output A, B and C should be the same as all three circuits perform the same specified Boolean function for the same input. However, any of the outputs A, B or C may differ if there is any fault within the corresponding circuit producing the result.

[0053] The outputs A, B and C from these circuits are then compared using the majority voting gate 108. The majority voting gate 108 produces the final output after comparing the outputs A, B and C. If there are no circuit failures i.e. no fault within any of the three circuits 102,104 and 106, the outputs of A, B and C will be identical (e.g. bit 1) and the majority voting gate 108 produces the same output A, B and C as the three circuits. If any one of the three circuits fails, i.e. generate a wrong / different output (e.g. bit 0), the majority voting gate 108 outputs the result of the other two circuits which are correct / same, (e.g. bit 1) and mask the fault within the circuit that failed. However, if more than one circuit (majority of the circuit) produce wrong results (e.g. bit 0) and one circuit produces the correct result (e.g. bit 1), then the output of the majority voting gate 108 would be 0 as it outputs the majority. The output Q would thus be erroneous causing a failure. The majority voting gate for a TMR can be represented by the following Boolean equation: Q=A-B + B-C + A-C where + represents a logical OR operation, and e.g. ‘A ■ B' represents a logical AND operation between inputs A and B.

[0054] The truth table for the 3-input majority voting gate is: Table 1 Input Output A B C Q 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

[0055] As shown in the above truth table, when any two inputs to the majority voting gate 108, i.e. outputs A, B or C, are 0, then the majority voting gate produces output Q=0 and when any two inputs to the majority voting gate 108, i.e. outputs A, B or C are 1, then the majority gate produces output Q=1. Thus, if two circuits produce the wrong result then the majority gate outputs the wrong result. Therefore, although having three identical systems and a further majority voting gate to enhance fault tolerance and reliability, there may be chances of failure. Also, the need for three identical circuits will increase the area in the silicon on chip.

[0056] FIG. 2 illustrates a fault detection system. The fault detection system 200 is a comparator circuit comparing input received from two logic circuits. The fault detection system 200 comprises a comparator 206 receiving input from a first logic circuit 202 and a second logic circuit 204. The first logic circuit is replicated to generate the second logic circuit. The first logic circuit 202 produces an output A and the second logic circuit 204 produces an output B. Ideally the output A and B would be the same as one logic circuit is a replication of the other. A simple comparator compares two inputs and provides an output Z indicating whetherthe inputs are the same or different. A simple comparator for comparing two inputs signals (A and B) can be implemented using a basic XNOR gate. The XNOR gate produces the below truth table: Table 2 A 8 Z 0 0 1 0 1 0 1 0 0 1 1 1

[0057] The XNOR gates compares two inputs (or binary digits) and produces an output 1 only if both inputs are the same and produces an output ‘0’ only when the inputs are different. Hence when there is no fault within the circuits 202 and 204, the comparator produces an output ‘Z=1’ and when there is a fault within the circuits 202 and 204 and they produce different outputs, the comparator produces an output ‘Z=0’. However, when there is a fault within the comparator circuit itself, the comparator may produce faulty output indicating that there is no error in the circuits when there is actually an error, which could lead to failure. A fault within the comparator circuit itself could also produce faulty output indicating that there is an error in the circuits when in fact there is no error -this would be a ‘false positive’ in terms of detecting an error and, whilst systems would ideally ‘fail safe’ in these situations, it would nonetheless be an unnecessary failure when considering the correctness of the outputs from the logic circuits supplying the signals to the comparator.

[0058] When implementing a comparator as a fault detecting system, the comparator requires only two inputs and hence only two replicated circuits / system unlike the triple modular redundancy circuit, hence the area required for implementing a fault detection system using a comparator is less compared to the triple modular redundancy system.

[0059] The inventor devised that instead of a simple XNOR gate the circuitry of the comparator could be designed such that the comparator can compare two inputs and provide an output indicating whether the inputs are the same or different whilst also self-checking for any fault within the comparator itself. The comparator circuitry is therefore capable of eliminating single-point failure by self-checking for any fault within the comparator. That is, the comparator copes with single stuck-at faults within the comparator logic. When a stuck-at fault occurs in any of the gates in the comparator, and when the other gates are functioning correctly, then (depending on which gate develops which type of stuck-at fault for which combination of inputs to the comparator) the comparator either still provides an output indicating the correct comparison result or provides an output indicating the fault is present.

[0060] As described earlier, safety goals may be expressed as a set of metrics, such as a maximum number of failures in a given period of time, and the effectiveness of mechanisms for detecting single point failures etc. The comparator circuitry meets the requirements as the comparator provides 100 percent detection of single stuck-at faults within its own circuity, thus eliminating single point failure. Whilst the comparator circuitry is immune to single stuck-at fault failures, it is not immune to multiple stuck-at fault failures. However, the probability of having a double fault in the comparator is extremely low especially in comparison to the number of gates that may be present in the circuits being compared - e.g. systems like CPUs, and GPUs have millions of gates. When implementing the comparator circuitry in such systems, multiple instances of these comparators can be used depending on the ASIL target. The probability of having exactly the same double faults that mask an error in the input signals in multiple comparators would be extremely low. Also, when considering transient faults, introduced by transient events (e.g. due to ionizing radiation, voltage spikes, or electromagnetic pulses), there are more chances for the occurrence of a single stuck at fault. The chances of having a double fault is extremely low when there is a transient event. The comparator circuitry enables protection against single point failure by indicating that there is a single fault in the comparator, so that the system can take possible action within the Fault Tolerance Time Interval (FTTI) and hence satisfies the requirement of ISO standards (such as ISO 26262 ASILs). The self-checking comparator circuitry can be implemented in the fault detection circuit 200 instead of the XNOR comparator receiving inputs from the first logic circuit 202 and the second logic circuit 204.

[0061] FIG. 3 illustrates a design of a self-checking comparator according to the present invention. The comparator 300 receives two inputs A and B (or binary digits) from two logic circuits / systems as explained in FIG. 2, and produces a binary codeword [Z~Z] as output unlike the single output Z produced by a conventional XNOR comparator. A first logic circuit produces an output A, and a second logic circuit produces an output B. The logic circuits may be for performing a fixed function in hardware. In one example, the first and second logic circuits may be replaced with a first processing system and a second processing system producing a binary signal for comparison (e.g. that could be compared bit by bit). Examples of the processing systems may include but are not limited to two CPU’s or two GPU’s or even a CPU and a GPU or an accelerator etc. As explained with respect to FIG. 2, the second circuit / system would be a replication of the first circuit / system. The two circuits / systems would be performing the same Boolean operations (or same function), thereby ideally producing the same outputs A and B. However, any error in the circuits / systems may lead to the circuits / systems producing different outputs A and B. The comparator 300 compares inputs and produces an output indicating that the inputs are the same or different while checking if there is any fault within the comparator. That is the comparator is capable of self-checking and potentially providing an indication that there is a fault within the comparator such as a single stuck-at fault. The single stuck-at faults may be generated due to bit flipping or voltage spikes etc.

[0062] The comparator 300 is configured to receives two inputs [A,B] and perform a plurality of logical operations to produce a binary codeword [Z~Z], The comparator 300 may comprise a plurality of logic circuits / gates configured to perform the plurality of logical operations. The comparator 300 is configured to invert the two inputs A and B to generate inverted inputs A and B using a first set of logical gates. The comparator 300 performs a first NOT / invert operation 302 for inverting the input A and a second NOT / invert operation 304 for inverting the input B.

[0063] The input signals A, B, and the inverted inputs A and B are provided to a second set of logic gates for performing logical AND operations. The comparator is configured to perform logical AND operations between all four possible combinations of 4 B, A and B. The four possible combinations are [AB], [A, B], [AB] and [AB], Thus, the comparator is configured to perform a first AND operation 306 between inputs A and B, a second AND operation 308 between the two inverted inputs A and B,a third AND operation 310 between input signal A and the inverted input signals, and a fourth AND operation 312 between the inverted input signal A and input signal B.

[0064] Further outputs obtained after performing the four logical AND operations A • B, A • B, A ■ B and A ■ B are provided to a third set of logical gates to perform two logical OR operations. The comparator is configured to perform OR operations between a combination of the outputs from the AND operations to generate an output code word \Z~Z], The comparator 300 performs a first OR operation 314 between the outputs of the first AND operation 306 and the second AND operation 308 to generate an output Z. The comparator 300 further performs a second OR operation 316 between the outputs of the third AND operation 310 and the fourth AND operation 312 to generate an output ~Z. The comparator provides the binary codeword [Z,~Z] as the output of the comparator. The various combinations of the binary code word [Z,~Z] indicate whether the inputs are the same or different or if there is a fault within the comparator circuit. The comparator 300 may be implemented using any combination of logic gates performing logically equivalent operations of the NOT, AND, and OR operations explained above. The more detailed explanation of comparator 300 is provided in the following paragraphs.

[0065] FIG. 4 illustrates the logic circuit implementation of the comparator 300. The logic circuit 400 comprises two NOT gates 402 and 404, four AND gates 406, 408, 410 and 412 and two OR gates 414 and 416. However, it is understood for a person skilled in the art that different other implementations of the logic circuits performing the equivalent logical operations can be used in the circuit 400. For example, one or more AND gates may be replaced by NAND gate followed by NOT gate. Similarly, an OR gate may be implemented by a NOR gate followed by a NOT gate. Also, it is understood by a person skilled in the art that the comparator may also be implemented using any combination of logic gates providing logically equivalent output that communicates the same information (i.e. that permits the same analytical deductions). For example, a NOT operation can be performed at each of the outputs of the illustrated comparator to get inverted outputs (compared to the illustrated comparator) that would communicate the same information as the outputs from the illustrated comparator, but with different specific code words - i.e. inverting the output for all combinations of inputs would permit the same conclusions to be drawn as discussed below (just based on different specific code words).

[0066] The two NOT gates 402 and 404 receive inputs A and Band perform two NOT operations or inverter operations inverting inputs A and B. The first NOT gate (G1) 402 produces the output A. The second NOT gate (G2) 404 produces the output B. Further, the comparator is configured to perform the AND operations between all four possible combinations of the inputs A, B, A and B. The first AND gate (G3) 406 is configured to receive the inputs A and Band perform AND operation A ■ B. The second AND gate (G4) 408 is configured to receive the two inverted inputs from the first and second NOT gates 402 and 404 and performs an AND operation A ■ B. The third AND gate (G5) 410 is configured to receive the input signal A as a first input and an invented input signal B from the second NOT gate 404 to perform a third AND operation A ■ ~B. The fourth AND gate (G6) 412 is configured to receive the inverted input A from the first NOT gate 402 and the input signal B and perform a fourth AND operation A -B. Further the comparator 400 comprises a first OR gate (G7) 414 configured to receive inputs from the first AND gate 406 and the second AND gate 408 and perform OR operation to generate an output Z. The comparator 400 comprises a second OR gate (G8) 416 configured to receive inputs from the third AND gate 410 and the fourth AND gate 412 and perform an OR operation to generate an output ~Z.

[0067] Therefore, the comparator 300 / 400 receives the two inputs A and B and generates an output code word [Z, ~Z\. The Boolean expressions for each element of the output code word [Z,~Z ] are: Z = A • B + A ■ B ~Z = A- B+ A- B

[0068] Consider an example when the input signal [A, B\ is [0, 0], The output generated by each logic gate in the logic circuit 400 and the codeword thus generated (assuming the comparator is working correctly) is shown in Table 3. The comparator produces an output codeword [Z, ~Z| as [1, 0] for an input combination [0,0]. Similarly, the comparator produces an output codeword [Z, as [1,0] for an input combination [1,1], The comparator produces an output codeword [Z,~Z] as [0, 1] for an input combination [0,1] and for the input combination [1,0], Therefore, it can be inferred that for the same inputs A and B, i.e. [0,0] and [1,1], the codeword generated by the logic circuitry is [1,0] and for different inputs A and B i.e., [0,1] and [1,0], the codeword generated by the logic circuitry is [0,1], Thus, when the comparator is working correctly it will only generate correct output codeword [1,0] for the same inputs A and B and correct output codeword [0,1] for different inputs. Any other output codewords i.e. [0,0] or [1,1] are incorrect output codewords - i.e. outputs that cannot be produced when the comparator is working correctly. As a result, the occurrence of any such output codewords indicates that the comparator is not working correctly. Table 3 A B G1=A G2=B G3=4 ■ B G4=A ■ B G5=4 ■ B G6=A■B Z=G3 +G4 ~Z =G5+G6 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0

[0069] Thus, the truth table forthe comparator with no fault within the logic gates in the comparator would be as follows: Table 4 A B z -z 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0

[0070] As explained above, the comparator produces the code word [Z, as [1,0] when both inputs A and / / are the same and there is no fault within the comparator. Thus, the codeword [Z,~Z] as [1,0] is pre-defined as a legal codeword which when generated indicates that the inputs are the same. All other combinations of the codewords such as [0,1] [0, 0] and [1, 1] are defined as illegal codewords which indicate that either the inputs are different or there is a fault with the comparator. The comparator 300 / 400 can also be capable of identifying if there is a fault with any of the gates in the logic circuit or, in other words, perform a self-check by producing an incorrect code word, in the sense of a code word that cannot be produced by the correctly functioning comparator. The comparator produces an illegal codeword when there is a fault within the comparator and / or when the inputs are different. Also, in some cases when the fault in the comparator does not affect the correct operation of the comparator, the comparator may mask such faults. In other words, the comparator in some scenarios may act as a fault isolation or fault avoidance architecture by masking a fault within the comparator such as a single stuck-at fault within the comparator and generating outputs that correctly indicate if the inputs are same or different. That is, in some scenarios, despite a stuck at fault error at a gate within the comparator’s own circuitry, the comparator will output the correct code word for the particular combination of inputs it receives. However, whatever the single stuck at fault scenario, the comparator will not output a code word that represents the wrong comparison result for the particular inputs (i.e. it will not output a ’correct’ code word, in the sense of a code word that can be output by the correctly operating comparator, that actually represents the wrong comparison result).

[0071] The fact that the design of the comparator is capable of self-checking its own faults can be understood by simulating individual errors (or a single stuck at fault) at the output of each of the gates as explained below. When an error is considered at the output of each gate as explained below, the remaining gates in the comparator circuit are considered to be working correctly without any error.

[0072] As explained earlier, the first NOT gate (G1) 402 and the second NOT gate (G2) 404 receive inputs A and ^and perform two NOT operations or inverter operations inverting inputs A and B respectively. G1 402 receives input A and produces the output A. G2 404 receives input B and produces the output B. Consider that a stuck at 0 error is present at the first NOT gate (G1) 402 in the logic gate circuit 400. The output of the comparator for all combination of inputs A and 8, for the stuck at 0 error at the first NOT gate (G1) 402 is provided in Table 5 below. When a stuck at 0 fault in the output of G1 402 occurs, on receiving the input ^4=0, there is a failure within the comparator itself as the output of the G1 402 would be stuck ‘O’, and the correct output would be ‘1 Thus, the comparator produces illegal codewords when the input A=0, i.e. for input combinations [0,0] and [0, 1] indicating that there is a fault within the comparator. However, despite the stuck at 0 fault, for 74=1 the output of G1 402 would be correct and hence the failure within the comparator is masked. Hence for input combination with ,4=1, the comparator produces the correct output for the comparison.

[0073] Similarly, a stuck at 1 fault could occur at the first NOT gate (G1) 402 and stuck at 0 and stuck at 1 faults could occur at the second NOT gate (G2) 404 in the logic gate circuit 400. The output of the comparator for all combination of inputs A and B, for each of the stuck at 0 and stuck at 1 faults occurring at the first NOT gate (G1) 402 and the second NOT gate (G2) 404 are explained in detail below and are provided in Table 5.

[0074] In Table 5, fora stuck at 0 fault in the output of G1 402, it is shown that for input combination [A B\ = [0,0] an illegal codeword output [0, 0] is generated instead of the legal codeword [1,0], Since [0,0] is not a correct output of the comparator (i.e. it is not an output generated by the comparator when working correctly), the illegal codeword output [0, 0] generated indicates that the comparator has a failure within itself (N.B Table 5 doesn’t distinguish between faults that can be attributed to a comparator failure and faults attributed to the inputs not being the same). For input combination [A, B\ = [1,1], the stuck at 0 fault for G1 does not affect the actual operation of the comparator since for t4=1, output of G1 is supposed to be 0, therefore the legal codeword [1,0] is generated as [Z, ~Z] indicating that inputs A and B are the same and thus masking the failure within the comparator (i.e. failure of G1 402) and acting as a fault avoidance architecture. In other words, the primary purpose of the comparator is to corroborate that the inputs are the same (when the system is working normally / correctly). As such, a ‘false positive’ output that does not provide that corroboration, due to a problem within the comparator, is undesirable if in fact the inputs to the comparator are indeed the same. The illustrated comparator avoids that undesirable outcome in this scenario. For input combination [0,1], illegal codeword [0,0] is generated as the output [Z, ~Z\ of the comparison. The output [0, 0] is also not a correct output of the comparator (i.e. not an output generated by the comparator when working correctly), and hence would also indicate that there is a fault within the comparator. For input combination [1,0], illegal codeword [0,1] is generated as [Z, ~2| thus correctly indicating the output of the comparison (which is to indicate a fault in one of the circuits supplying signals yland B).

[0075] Similarly, when a stuck at 1 fault in the output of G1 402 occurs, on receiving the input A=0, the output of G1 402 would be correct and hence the failure within the comparator (i.e. with G1 402) is masked. However, for A=1, the output of G1 402 would be stuck at ‘1’, instead of providing the correct output of ‘O’. For input combination [A, B\ = [0,0] the stuck at 1 fault does not affect the actual operation of the comparator since for ^4=0, output of G1 is supposed to be 1, therefore the legal codeword [1,0] is generated as [Z, ~Z\ masking the failure within the comparator and thereby acting as a fault avoidance architecture. For input combination [A, = [1,1], the stuck at 1 fault for G1 produces an illegal codeword [1,1] as [Z, ~Z\ instead of the legal codeword [1,0] which is supposed to be generated as output for the same inputs A and B. Since [1,1] is not a correct output of the comparator (i.e. not an output generated by the comparator when working correctly), the illegal codeword output [1,1] generated indicates that the comparator has a failure within itself. For input combinations [1,0] and [0, 1], illegal codewords [1,1] and [0,1] are generated as outputs. The output [1,1] for input [1,0] is not a correct output of the comparator (i.e. not an output generated by the comparator when working correctly) and hence indicates that there is a fault within the comparator. For input combination [0,1], illegal codeword [0,1] as [Z, is generated thus correctly indicating the output of the comparison (which is to indicate that the inputs A and / / a re different and hence a fault in one of the circuits supplying signals A and B).

[0076] In the same way, when a stuck at 0 fault in the output of G2 404 occurs, on receiving the input ^=0, the output of the G2 404 would be stuck at ‘0’ instead of generating the correct output ‘1’. However, for ^=1 the output of G2 404 stuck at 0 would be the correct output of G2 404. For input combination [A, = [0,0] an illegal codeword output [0, 0] is generated instead of the legal codeword [1,0] as [Z, which is supposed to be generated as output for the same inputs A and B. Since [0,0] is not a correct output of the comparator (i.e. not an output generated by the comparator when working correctly), the illegal codeword output [0,0] generated indicates that the comparator has a failure within itself. For input combination [A, B\ = [1,1], the stuck at 0 fault for G2 does not affect the actual operation of the comparator since for ^1, output of G2 is supposed to be 0, therefore the legal codeword [1,0] is generated as [Z, ~2| masking the failure within the comparator and thereby acting as a fault avoidance architecture. For input combinations [1,0] and [0, 1], illegal codewords [0,0] and [0,1] are generated as output [Z, ~Z\. The output [0, 0] is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence indicates that there is a fault within the comparator. For input combination [0,1], illegal codeword [0,1] is generated thus correctly indicating the output of the comparison (which is to indicate that the inputs A and 7? are different and hence there is a fault in one of the circuits supplying signals A and B).

[0077] Similarly, when a stuck at 1 fault in the output of G2 404 occurs, on receiving the input B=0, the output of G2 404 would be correct and hence the failure within the comparator is masked. However, for S=1, the output of the G2 404 would be stuck ‘1 ’ instead of generating the correct output of ‘O’. For input combination [A, B[ = [0,0] the stuck at 1 fault does not affect the actual operation of the comparator since for Zt=O, output of G2 is supposed to be 1, therefore the legal codeword [1,0] is generated as [Z, ~2\ indicating that inputs A and ^are the same and thus masking the failure within the comparator and acting as a fault avoidance architecture. For input combination [A, B\ = [1,1], the stuck at 1 for G2 404 produces an illegal codeword [1,1] as [Z, -2] instead of the legal codeword [1,0] which is supposed to be generated for the same inputs A and S. Since [1,1] is not a correct output of the comparator (i.e. not an output generated by the comparator when working correctly), the illegal codeword output [1,1] generated indicates that the comparator has a failure within itself. For input combinations [1,0] and [0, 1], illegal codewords [0,1] and [1,1] are generated as output [Z, ~Zf. The output [1,1] is not a correct output of the comparator (i.e. it is not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. For input combination [1,0], illegal codeword [0,1] is generated thus correctly indicating the output of the comparison (which is to indicate that the inputs A and B are different and hence there is a fault in one of the circuits supplying signals A and B).

[0078] Thus, from Table 5 it is clearthat for various input combinations, even when there is a stuck at 0 or stuck at 1 fault occurring at G1 402 and G2 404, the comparator would provide output correctly indicating that the inputs are the same when the output generated is a legal codeword [1, 0] or correctly indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], In other words, for a single point failure within the comparator, the outputs of the comparator can be relied on to know there is definitely a match or mismatch between the inputs if either the [1,0] code word or the [0, 1] code word is returned, even though that code masks the failure in the comparator. So, this is a ‘fail safe’ scenario in the sense that the failure still results in the correct output. In the case of the comparator returning either the [1, 1] code word or the [0, 0] code word, the fault in the comparator is explicitly identified, which is also a ‘fail safe’ scenario. In 5 this scenario, this output could be used to instigate some action to correct the error / failure within the comparator (e.g. perhaps to initiate a hard reset, or perhaps to re-perform the comparison to rule out a transient error). Table 5 A B z ~z Outcome Scenario: Stuck-at 0 fault in output of G1 0 0 0 0 Fault discovered: Illegal codeword generated 0 1 0 0 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output of G1 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 1 1 Fault discovered: Illegal codeword generated 1 1 1 1 Fault discovered: Illegal codeword generated Scenario: Stuck-at 0 fault in output of G2 0 0 0 0 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 0 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output of G2 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 1 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 1 Fault discovered: Illegal codeword generated 10

[0079] Although the preceding analysis has focussed on the first two gates, G1 402 and G2 404, the same benefits as explained above are enjoyed if a fault develops at any one of the other gates. For completeness, a consideration of the possible faults at each remaining gate follows below.

[0080] Next, consider how the comparator operates when simulating each of a stuck at 0 and stuck at 1 fault at the first AND gate (G3) 406 in the logic gate circuit 400. The first AND gate (G3) 15 406 is configured to receive the inputs A and B and perform AND operation A ■ B. The output of the comparator for all combinations of inputs A and 8, for the stuck at 0 and stuck at 1 faults occurring at the first AND gate (G3) 406 is shown in Table 6 provided below.

[0081] When a stuck at 0 fault occurs in the output of G3 406, on receiving either or both of the inputs A=0 or 8=0, the output of the G3 406 would be stuck at ‘0’ which is the expected output for those inputs. In other words, for input combination [4 B[ = [0,0], the stuck at 0 for G3 406 does not affect the actual operation of the comparator since for [4 B\ = [0,0], output of G3 406 (i.e. A • B) is supposed to be 0, therefore the legal codeword [1,0] is generated as [Z, ~Z\ indicating that inputs A and B are the same and thus masking the failure within the comparator and acting as a fault avoidance architecture. Similarly for input combinations [0, 1] and [1,0] the stuck at 0 for G3 406 does not affect the actual operation of the comparator since the output of G3 406 is supposed to be 0 if any of the inputs A or 8 is 0. Therefore, the illegal codeword [0,1] is generated as [Z, -Z^ indicating that the inputs are different (i.e. to indicate thatthere is a fault in one of the circuits supplying signals A and 8). However, for inputs [A, 8] = [1,1], the output of G3 406 would be stuck at 0 instead of generating the expected output 1 when both inputs A and 8 are 1, therefore the illegal codeword [0,0] is generated as [Z, ~Z\. The output [0, 0] is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly), and hence it indicates that there is a fault within the comparator.

[0082] When stuck at 1 fault occurs in the output of G3 406, on receiving the input combination [4 = [1,1], the output of G3 406 would be correct, as the output of G3 406 is supposed to be 1 when both inputs are 1, therefore the legal codeword [1,0] is generated which is the correct output of the comparator indicating that inputs A and £are the same and hence the failure within the comparator is masked. For input combinations [1,0] and [0, 1] the output of G3 406 would be stuck at 1 instead of producing an output 0 when one or more inputs are 0. This would generate an illegal codeword [1,1] as [Z, ~Z / which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. For input combination [4 = [0,0], the output of G3 406 would be stuck at 1 instead of producing an output 0 when one or more inputs are 0. However, this does not affect the actual operation of the comparator since the error is not propagated to the output codeword. In other words, for [4 = [0,0], output of G3 406 is supposed to be 0, however the output 1 at G3 406 is provided as an input to the first OR gate (G7) 414. The output of G7 414 is 1 when at least one input is 1, and in this case the input from G4 408 is 1 (being the result of an AND operation between NOT A and NOT B)\ therefore the legal codeword [1,0] is generated as [Z, ~Z\ indicating that inputs A and B a re the same, thus masking the failure within the comparator and acting as a fault avoidance architecture.

[0083] Thus, from Table 6 it is clearthat for various input combinations, even when there is a stuck at 0 or stuck at 1 fault occurring at G3 406, the comparator would provide output correctly indicating that the inputs are same when the output generated is a legal codeword [1,0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], This output could be used to instigate some action to correct the error / failure within the comparator. Table 6 A B Z ~z Outcome Scenario: Stuck-at 0 fault in output of G3 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 0 0 Fault discovered: Illegal codeword generated Scenario: Stuck-at 1 fault in output of G3 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 1 1 Fault discovered: Illegal codeword generated 1 0 1 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done

[0084] The stuck at 0 and stuck at 1 faults occurring at the second AND gate (G4) 408 in the logic gate circuit 400 are explained below. The output of G1 402 is provided as a first input to G4 408 and the output of G2 404 is provided as second input to G4 408. The second AND gate (G4) 408 is therefore configured, in normal operation, to perform an AND operation A -B.Thus for an input combination \A,B^ the inverted inputs [A,B] are provided as input to G4 4O8.The output of the comparator for all combinations of inputs A and B, for the stuck at 0 and stuck at 1 faults at the second AND gate (G4) 408 is shown in Table 7 provided below.

[0085] When a stuck at 0 fault occurs in the output of G4 408, on receiving the input combination [A, B\ = [1,1] as input to the comparator, the inputs to G4 408 will be [0,0] (i.e. [A ,B]) and the output of G4 408 (i.e. A • B) would be stuck at ‘0’ which is the expected output. In other words, for input combination [A, 8] = [1,1], the stuck at 0 fault for G4 408 does not affect the actual operation of the comparator since for A=1, 8=1, the input to G4 408 would be A=0, B=0, therefore the output of G4 408 which is an AND gate is supposed to be 0. The legal codeword [1,0] is thus generated as [Z, ~2| indicating that the inputs A and 7? are the same, thus masking the failure within the comparator and thereby acting as a fault avoidance architecture. Similarly for input combinations [0, 1] and [1,0] received as inputs to the comparator, the stuck at 0 for G4 408 does not affect the actual operation of the comparator since the output of G4 408 (i.e. A -B) is supposed to be 0. Therefore, the illegal codeword [0,1] is generated as [Z, ~Z\ indicating that the inputs are different (i.e. to indicate that there is a fault in one of the circuits supplying signals A and B). However, for input combination [A, B\ = [0,0] received as input to the comparator, the output of G4 408 (i.e. A ■ B) would be stuck at 0 instead of generating the expected output 1. Therefore, the illegal codeword [0,0] is generated by the comparator as [Z, -2],The output [0, 0] is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly). The output codeword [1,1] would therefore indicate that there is a fault within the comparator.

[0086] Wien a stuck at 1 fault occurs in the output of G4 408, on receiving the input combination [A B\ = [0,0] received as input to the comparator, the output of G4 408 (i.e. A ■ B) would be correct, as the output of G4 408 is supposed to be 1, therefore the legal codeword [1,0] is generated as [Z, ~Z\ indicating that the inputs A and B are same and hence the failure within the comparator is masked. For input combination [A, = [1,0] and [A, B] = [0,1] received as input to the comparator, the output of G4 408 would be stuck at 1 when the output of G4 408 is supposed to be 0. Therefore, the illegal codeword [1,1] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. For input [A, B\ = [1,1] received as input to the comparator, the output of G4 408 is stuck at ‘1’ instead of generating the correct output ‘O’. But this does not affect the operation of the comparator since the error is not propagated to the output codeword. In other words, for [A = [1, 1] the output stuck at 1 at G4 408 is provided as an input to the first OR gate (G7) 414. The other input to G7 414 comes from G3 406. For the same inputs [1,1] the output of G3 406 would be A ■ B = 1. The output of G3 406 and G4 408 are provided to G7 414. The output of G7 414 (output of G3 OR output of G4) would be 1 when at least one of the inputs is 1. Since the output of G4 408 is stuck at 1, G7 would produce 1 irrespective of what the output of G3 406 is and in this case the input from G3 406 is 1 (being the result of an AND operation between A = 1 and B = 1); therefore the legal codeword [1,0] is generated as [Z, -Z[ indicating that the inputs A and B are same thus masking the failure within the comparator and acting as a fault avoidance architecture.

[0087] Thus, from Table 7 it is clear that for various input combinations, even when stuck at 0 or stuck at 1 faults occur at G3 406, the comparator would provide output correctly indicating that the inputs are same when the output generated is a legal codeword [1, 0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], This output could be used to instigate some action to correct the error / failure within the comparator. Table 7 A B z ~z Outcome Scenario: Stuck-at 0 fault in output ofG4 0 0 0 0 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output ofG4 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 1 1 Fault discovered: Illegal codeword generated 1 0 1 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done

[0088] The stuck, at 0 and stuck at 1 faults occurring at the third AND gate (G5) 410 in the logic gate circuit 400 are explained below. The third AND gate (G5) 410 receives input A as a first input and the output of G2 402 (i.e. B) as the second input. The third AND gate (G5) 410 is configured to perform a third AND operation A ■ B. Thus for an input combination [A,BJ provided to the comparator, G5 410 receives [A, B] as its input. The output of the comparator for all combination of inputs A and B, for the stuck at 0 and stuck at 1 fault occurring at the third AND gate (G5) 410 is shown in Table 8 provided below.

[0089] When a stuck at 0 fault occurs in the output of G5 410, on receiving the input combination [A, B\ = [0,0] as input to the comparator, the output of the G5 410 (which is A ■ B) would be stuck ‘0’ which is the expected output when at least one input is 0. In other words, for inputs [A,B\ = [0,0], the stuck at 0 fault forG5 410 does not affect the actual operation of the comparator since for A=0, 8=0, the input to G5 410 would be A=0, B=1, therefore the output A ■ B of G5 410 is supposed to be 0. The legal codeword [1,0] is thus generated indicating that the inputs A and Bare the same thus masking the failure within the comparator and enabling it to act as a fault avoidance architecture. Similarly for input combination [A, 8] = [1,1] received as input to the comparator, the output of G5 410 would be stuck ‘0’ which is the expected output. Therefore, the illegal codeword [1,0] is generated as [Z, ~Z\ indicating that the inputs A and B are the same thus masking the failure within the comparator and enabling it to act as a fault avoidance architecture. For input combination [0, 1] received as input to the comparator, the stuck at 0 for G5 410 does not affect the actual operation of the comparator since for A=0 and 8=1, input to G5 410 would be A=0, B=0. The output ‘0’ of G5 410 (which is A ■ B) is correct and therefore the illegal codeword [0,1] is generated as [Z, ~2| indicating that the inputs are different (i.e. indicating that there is a fault in one of the circuits supplying signals A and B). For input combination [1,0] received as input to the comparator, the output for G5 410 would be stuck ‘0’ instead of generating an output 1 that would be expected for these inputs. Thus, an illegal codeword [0,0] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator

[0090] Wien a stuck at 1 fault occurs in the output of G5 410, on receiving the input combination [4 B| = [0,0] as input to the comparator, the output of the G5 410 (which is A ■ B) would be stuck at 1 when the output of G5 410 is supposed to be 0. Therefore, the illegal codeword [1,1] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. Similarly for input combination [4B| = [1,1] received as input to the comparator, the output ofG5 410 would be stuck at 1 when the output of G5 410 (which is A ■ B) is supposed to be 0. Therefore, the illegal codeword [1,1] is generated as [Z, which indicates that there is a fault within the comparator. For input combination [4 = [0,1] received as input to the comparator, the output of G5 410 would be stuck at 1 when the output of G5 410 (which is A ■ B) is supposed to be 0. However, this does not affect the actual operation of the comparator since the different output from G5 410 does not affect the functioning of the second OR gate G8 416. G8 416 takes inputs from G5 410 and G6 412. G6 412 performs an AND operation on NOT A and B. So, in the case of comparator inputs [A, 8] = [0,1], G6 412 outputs 1. This means that G8 416 receives a 1 from G6 412 and so, being an OR gate, should output 1 irrespective of the input it receives from G5 410. Therefore, the illegal codeword [0,1] is generated as [Z, thus correctly indicating that the inputs are different (i.e. to indicate that there is a fault in one of the circuits supplying signals A and 8), and masking the fault in the comparator. For input combination [A, 8] = [1,0] received as input to the comparator, the output of G5 410 would be stuck at 1 which is the correct output of G5 410 (which is A ■ B) for these inputs. In other words, for inputs [A, B\ = [1,0], the stuck at 1 fault for G5 410 does not affect the actual operation of the comparator since for A=1,8=0, the input to G5 410 would be A=1,5=1, therefore the output A • B of G5 410 is supposed to be 1. The illegal codeword [0,1] is thus generated indicating that the inputs A and B are different, thus masking the failure within the comparator and enabling it to act as a fault avoidance architecture.

[0091] Thus, from Table 8 it is clear that for various input combinations, even when a stuck at 0 or stuck at 1 fault occurs at G3 406, the comparator would provide output correctly indicating that the inputs are the same when the output generated is a legal codeword [1,0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], This output could be used to instigate action to correct the error / failure within the comparator. Table 8 A B z ~z Outcome Scenario: Stuck-at 0 fault in output of G5 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 0 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output of G5 0 0 1 1 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 1 Fault discovered: Illegal codeword generated

[0092] The stuck at 0 and stuck at 1 faults occurring at the fourth AND gate (G6) 412 in the logic gate circuit 400 are explained below. The fourth AND gate (G6) 412 receives a first input from the output of NOT gate G1 402 and the second input as B. The fourth AND gate (G6) 412 is configured to perform a fourth AND operation A -B Thus, for an input combination [A, B\ provided to the comparator, G6 412 receives [A , B\ as its input. The output of the comparator for all combinations of inputs A and 8, for the stuck at 0 and stuck at 1 faults occurring at the fourth AND gate (G6) 412 is shown in Table 9 provided below.

[0093] When a stuck at 0 fault occurs in the output of G6 412, on receiving the input combination [A, 8] = [0,0] as input to the comparator, the output of the G6 412 (which is A ■ B) would be stuck ‘0’ which is the expected output of G6 412. In other words, for input combination [A, = [0,0], the stuck at 0 fault for G6 412 does not affect the actual operation of the comparator since for A=0, 8=0, the input to G6 412 would be A=1, B=0, therefore the output of G6 412 is supposed to be 0. The legal codeword [1,0] is thus generated as [Z, ~Z\ indicating that the inputs A and ^are the same thus masking the failure within the comparator and acting as a fault avoidance architecture. Similarly for input combination [A, B\ = [1,1] received as input to the comparator, the output of G5 410 would be stuck at ‘0’ which is the expected output and hence the failure within the comparator is masked. Therefore, the legal codeword [1,0] is generated as [Z, ~Z\ by the comparator to indicate that inputs A and ^are the same thus masking the failure within the comparator and acting as a fault avoidance architecture.

[0094] For input combination [0,1] received as input to the comparator, the stuck at 0 for G6 412 would affect the actual operation of the comparator since for A=0 and ^1, input to G6 412 would be A=1, 8=1. For these inputs, therefore, the output of G6 412 is stuck at 0 instead of generating a correct output 1 and therefore the illegal codeword [0,0] is generated as [Z, -Z[ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. For input combination [1,0] received as input to the comparator, the output for G6 412 would be stuck ‘0’ which is the expected output and hence the failure within the comparator is masked. Thus, the illegal codeword [0,1] is generated as [Z, ~Z\ indicating that the inputs are different (i.e. indicating that there is a fault in one of the circuits supplying signals A and 8).

[0095] When a stuck at 1 fault occurs in the output of G6 412, on receiving the input combination [A, 8] = [0,0] as input to the comparator, the output of the G6 412 (which is A ■ B) would be stuck at 1 instead of generating an expected output 0. Therefore, the illegal codeword [1,1] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. Similarly for input combination [A,B\ = [1,1] received as input to the comparator, the output ofG6 412 would be stuck at 1 instead of generating an expected output 0. Therefore, the illegal codeword [1,1] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. For input combination [A, B\ = [0,1] received as input to the comparator, the output of G6 412 would be stuck at 1 which is the correct output of G6 412 (which is A ■ B) for these inputs. In other words, for inputs [A, = [0,1], the stuck at 1 fault for G6 412 does not affect the actual operation of the comparator since for A=0, 8=1, the input to G6 412 would be A = 1,B = 1 therefore the output A • B of G6 412 is supposed to be 1. The illegal codeword [0,1] is thus generated indicating that the inputs A and 8 are different, thus masking the failure within the comparator and enabling it to act as a fault avoidance architecture. For input combination [A, = [1,0] received as input to the comparator, the output of G6 412 would be stuck at 1 when the output of G5 410 (which is A- B) is supposed to be 0. However, this does not affect the actual operation of the comparator since the different output from G6 412 does not affect the functioning of the second OR gate G8 416. G8 416 takes inputs from G5 410 and G6 412. G5 410 (as discussed above) performs an AND operation on A and NOT B. So, in the case of comparator inputs [A, = [1,0], G5 410 outputs 1. This means that G8 416 receives a 1 from G5 410 and so, being an OR gate, should output 1 irrespective of the input it receives from G6 412. Therefore, the illegal codeword [0,1] is generated as [Z, ~Z\ thus correctly indicating that the inputs are different (i.e. to indicate that there is a fault in one of the circuits supplying signals A and B), and masking the fault in the comparator.

[0096] Thus, from Table 9 it is clearthat for various input combinations, even when a stuck at 0 or stuck at 1 fault occurs at G3 406 the comparator would provide output correctly indicating that the inputs are the same when the output generated is a legal codeword [1,0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], This output could be used to instigate action to correct the error / failure within the comparator. Table 9 A B z ~z Outcome Scenario: Stuck-at 0 fault in output ofG6 0 O 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 0 0 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output ofG6 0 0 1 1 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 1 Fault discovered: Illegal codeword generated

[0097] The stuck at 0 and stuck at 1 faults occurring at the first OR gate (G7) 414 in the logic gate circuit 400 are explained below. The first OR gate (G7) 414 receives a first input from the first AND gate G3 406 and the second input from the second AND gate G4 408. The first OR gate (G7) 414 configured to perform OR operation between the output of G3 406 and G4 408 to generate an output Z. For input combination [A, B\ provided to the comparator, G7 414 receives A ■ B and A -B as its inputs. The output of the comparator for all combinations of inputs A and S, for the stuck at 0 and stuck at 1 scenario at the first OR gate (G7) 414 is shown in Table 10 provided below.

[0098] When a stuck at 0 fault occurs in the output of G7 414, on receiving the input combination [A, B\ = [0,0] as input to the comparator, the output of the G7 414 (which is A ■ B + A ■ B) would be stuck at 0 instead of generating the expected output 1. Therefore, the illegal codeword [0,0] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicate that there is a fault within the comparator. Similarly for input combination [A, = [1,1] received as input to the comparator, the output of G7 414 would be stuck at 0 when the expected output of G7 414 is 1. Therefore, the illegal codeword [0,0] is generated as [Z, which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicating that there is a fault within the comparator. For input combination [A, = [1,0] and [A, B\ = [0,1] received as inputs to the comparator, the stuck at 0 for G7 414 would not affect the actual operation of the comparator since the expected outputs would both be 0. Therefore, the illegal codeword [0,1] is generated as [Z, ~Zf in each case, indicating that the inputs are different (i.e. indicating that there is a fault in one of the circuits supplying signals A and S).

[0099] When a stuck at 1 fault occurs in the output of G7 414, on receiving the input combination [A, B\ = [0,0], the output of the G7 414 (which is A ■ B + A ■ B) would be stuck ‘1 ’ which is the expected output. The legal codeword [1,0] is generated as [Z, ~Z\ indicating that the inputs A and B are the same thus masking the failure within the comparator and acting as a fault avoidance architecture. Similarly for input combination [A, = [1,1], the output of G7 414 would be stuck T which is the expected output. Therefore, the legal codeword [1,0] is generated as [Z, by the comparator indicating that the inputs A and B are the same and thus masking the failure within the comparator and acting as a fault avoidance architecture. For input combinations [A, £| = [1,0] and [A, B] = [0,1] received as input to the comparator, the stuck at 1 fault for G7 414 would affect the actual operation of the comparator since for both these input combinations, the expected output of G7 414 would be 0. In these cases, when the output of G7 414 is stuck at 1 instead of generating the expected output 0, then the illegal codeword [1,1] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicating that there is a fault within the comparator..

[0100] Thus, from Table 10 it is clear that for various input combinations, even when a stuck at 0 or stuck at 1 fault occurs at G3 406, the comparator would provide output correctly indicating that the inputs are same when the output generated is a legal codeword [1, 0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1]. This output could be used to instigate action to correct the error / failure within the comparator. Table 10 A B z ~z Outcome Scenario: Stuck-at 0 fault in output ofG7 0 0 0 0 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 0 0 Fault discovered: Illegal codeword generated Scenario: Stuck-at 1 fault in output ofG7 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 1 1 Fault discovered: Illegal codeword generated 1 0 1 1 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done

[0101] The stuck, at 0 and stuck at 1 faults occurring at the second OR gate (G8) 416 in the logic gate circuit 400 are explained below. The second OR gate (G8) 416 receives a first input from the third AND gate G5 410 and a second input from the fourth AND gate G6 412. The second OR gate (G8) 416 is configured to perform an OR operation between the output of G5 410 and G6 412 to generate an output ~Z. For an input combination [A, B] provided to the comparator, G8 416 would receive A- B and A • B as its inputs. The output of the comparator for all combinations of inputs A and B, for the stuck at 0 and stuck at 1 faults occurring at the second OR gate (G8) 416 is shown in Table 10 provided below.

[0102] When a stuck at 0 fault occurs in the output of G8 416, on receiving the input combinations [A, B\ = [0,0], the output of the G8 416 (which is A ■ B + A ■ B) would be stuck ‘0’ which is the expected output. The legal codeword [1,0] is thus generated indicating that the inputs A and B are the same thus masking the failure within the comparator and acting as a fault avoidance architecture. Similarly for input combination [A, B\ = [1,1], the output of G8 416 would be stuck ‘0’ which is the expected output. Therefore, the illegal codeword [1,0] is generated by the comparator indicating that the inputs A and B are the same thus masking the failure within the comparator and acting as a fault avoidance architecture. For input combinations [A, = [1,0] and [A, B] = [0,1], the stuck at 0 fault for G8 416 would affect the actual operation of the comparator as the expected output for both these input combinations would be 1. In these cases, when the output of G8 416 is stuck at 0 instead of generating the expected output 1, then the illegal codeword [0,0] is generated as [Z, ~Z\ which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence would indicating that there is a fault within the comparator.

[0103] When a stuck at 1 fault occurs in the output of G8 416, on receiving the input combination [4 = [0,0] the output of the G8 416 (which is A ■ B + A ■ B) would be stuck at 1 when the expected output of G8 416 is 0. Therefore, the illegal codeword [1,1] is generated which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence indicates that there is a fault within the comparator. Similarly for input combination [A, B\ = [1,1], the output of G8 416 would be stuck, at 1 when the expected output of G8 416 is 0. Therefore, the illegal codeword [0,0] is generated as [Z, ~2| which is not a correct output of the comparator (i.e. not an output that is generated when the comparator is working correctly) and hence indicating that there is a fault within the comparator. For input combinations [A, = [1,0] and [Zl, B] = [0,1] the stuck at 1 for G8 416 would not affect the actual operation of the comparator since the expected output for both of these input combinations is 1. Therefore, the illegal codeword [0,1] is generated as [Z, ~Z\ indicating that the inputs are different (i.e. indicating that there is a fault in one of the circuits supplying signals A and B) and masking the error in the comparator 400.

[0104] Thus, from Table 11 it is clear that for various input combinations, even when a stuck at 0 or stuck at 1 fault occurs at G3 406, the comparator would provide output correctly indicating that the inputs are same when the output generated is a legal codeword [1, 0] or indicating that the inputs are different when the output generated is an illegal codeword [0,1] or indicating that there is a fault within the comparator when the output generated is one of the illegal codewords [0,0], [1 1], This output could be used to instigate action to correct the error / failure within the comparator. Table 11 4 B z ~z Outcome Scenario: Stuck-at 0 fault in output of G8 0 0 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done 0 1 0 0 Fault discovered: Illegal codeword generated 1 0 0 0 Fault discovered: Illegal codeword generated 1 1 1 0 Fault masked: Comparator does not report the fault, as the fault is mimicking the actual circuit and no damage done Scenario: Stuck-at 1 fault in output of G8 0 0 1 1 Fault discovered: Illegal codeword generated 0 1 0 1 Fault discovered: Illegal codeword generated 1 0 0 1 Fault discovered: Illegal codeword generated 1 1 1 1 Fault discovered: Illegal codeword generated

[0105] Thus, from the truth Tables 5-11 provided above (and assuming that, at most, a single stuck at fault is present), it can be understood that when the comparator produces a legal codeword i.e. [1,0] as the output then that indicates that there is definitely a match between inputs, and that there may or may not be a single stuck-at fault in the comparator that has been masked. Similarly, when the comparator produces an illegal codeword [0,1] as output then that indicates that there is definitely a mismatch between inputs, and that there may or may not be a single stuck-at fault in the comparator that has been masked. Further when there is a fault in the comparator and the fault is not masked, the comparator produces the output [1,1] or [0,0] which are not correct outputs of the comparator (i.e. not an output that is generated when the comparator is working correctly) and therefore indicate that the comparator is not functioning correctly. That is, from the above truth Tables 5-11, it is clear that wherever the comparator produces the output [1,1] / [0,0], there is definitely a fault in the comparator, and we don't know if there is a match or a mismatch between the inputs. In this case the output is reported to an error correction circuit to fix the error in the system. Hence the comparator is capable of performing a self-check on whether there is a fault in the comparator thus eliminating a potential point of failure. Also, in some cases, the comparator 300 / 400 may act as a fault isolation or fault avoidance architecture thus masking the faults that does not affect the correct operation of the comparator, and thereby avoiding unnecessarily interrupting the functioning of the wider system. The comparator in some cases may produce an output [1,0], indicating that there is definitely a match between inputs even if there is a fault in the comparator. The comparator may in some other cases, produce an output [0,1], indicating that there is definitely a mismatch between inputs even if there is a fault in the comparator.

[0106] It would be evident to a person skilled in the art that though the one or more logic gates in circuit 400 are replaced by different logic gates or logic gate performing logically equivalent operations then the comparator would be capable of producing the correct results while self-checking for the fault in the comparator. As discussed above, it will be understood that logically equivalent circuits encompass those that communicate the same information (i.e. that permits the same analytical deductions), and need not communicate that information with identical codewords. For example, a NOT operation can be performed at each of the outputs of the illustrated comparator to get inverted outputs (compared to the illustrated comparator) that would communicate the same information as the outputs from the illustrated comparator, but with different specific code words and would thus be logically equivalent.

[0107] FIG. 5 is a flowchart illustrating the working of the comparator. The method comprises at step 502, receiving two binary inputs A and B from two systems. The different system may be any logic circuits or CPUs, GPUs, NNA, or any other system producing binary output. The two systems are identical system performing the same Boolean operations and thus ideally generating the same output. But due to various faults that can occur in the system such as transient faults and permanent faults the output A and B may be different in some cases.

[0108] The method comprises, at step 504, performing Boolean operations which are logically equivalent to AND operation between all possible combinations of binary inputs A, B, A and B. The maximum possible number of combinations in this case is four. The binary inputs A and 7? are received directly from the two systems. The inverted binary inputs such as A and B may be obtained by performing an inverting operation or a NOT operation of each of the two binary inputs A and B received as input to the comparator. The AND operations A ■ B, A • B, A ■ B and A ■ B or operations logically equivalent to these AND operations are performed by a plurality of logic gates. These operations can be performed by four AND gates. A first AND gate receives two binary inputs A and B and performs a logical AND operation A ■ B. A second AND gate receives two binary inputs A and B and performs a logical AND operation A ■ B. A third AND gate receives two binary inputs A and B and performs a logical AND operation A • B. A fourth AND gate receives two binary inputs A and B and performs a logical AND operation A • B. It is known to a person skilled in the art that different other logical gates can be used to perform the operations logically equivalent to these AND operations. In one example a NAND gate followed by a NOT gate can be used.

[0109] Once all the four AND operations are performed, the method, at step 506, generates a binary codeword [Z, ~Zf. The generated binary codeword is provided as the output of the comparator. The binary codeword indicates whether the binary inputs are same or different based on the outputs of the bitwise operations. A binary codeword is predefined as a legal codeword to indicate that the binary inputs are same. In the embodiment illustrated above, the predefined legal codeword is [1,0], There method may also generate other binary codewords such as illegal codewords [0, 1], [0,0], [1,1] in the embodiment illustrated above. The method of generating the binary codeword [Z, ~Z\ comprises generating Z by performing an OR operation between two logical AND operations (A.B) and (A.B) and generating ~Z by performing an OR operation between the other two logical AND operations {AS) and (AS). The OR operations maybe performed by OR gates or any logic circuit (or combination of circuits) performing a logically equivalent operation.

[0110] The method further comprises checking, at step 508, if the binary codeword generated is a legal codeword. If yes, at step 510, it is determined that the binary inputs received are same. Generation of legal codeword [1,0] as [Z, ~Z\ indicates that there is definitely a match between the inputs or in other words the inputs are same. It can be observed, from the instances in the above tables when there is a single stuck-at failure within the comparator i.e. a fault within any one of the logic gates, that in some cases for the same inputs the legal codeword [1,0] is generated. For example, even when there is a stuck at 0 fault at G1 402, for the same input [1,1] the output is a legal codeword [1,0], In this case, the method masks the fault that does not affect the working of the comparator. Thus, the comparator acts as a fault isolation or fault avoidance architecture i.e. it is capable of masking the fault that does not affect the correct operation of the comparator.

[0111] If the result of step 508 is ‘no’ then, at step 512, it is determined that the binary inputs are different and / or there is a fault within the comparator. If the binary codeword generated is the illegal codeword [0,1], then there is definitely a mismatch between the inputs whether or not there is a fault within the comparator. Thus, when the illegal codeword [0, 1] is generated then it is determined that the binary inputs are different. In some cases, even when there is a single stuck-at faults in any of the logic gates of the comparator, the illegal codeword [0, 1] is generated as the binary codeword thus masking the fault within the comparator. This is because the fault does not affect the working of the comparator and hence the comparator behaves as a fault avoidance architecture. In these circumstances, the system can determine how to handle the mismatch between inputs. For example, a workload may be reissued to the circuits producing signals A and 8 and if no mismatch occurs for the reissued workload it may be that the original mismatch was due to a transient error, and no further action is needed. Alternatively, if the same illegal codeword is produced for the reissued workload, this may indicate that a more permanent fault has developed which, for example, may requiring further investigation and / or disabling of the circuits producing the input signals A and 8.

[0112] It is thus apparent that the method can mask the fault within the comparator when the output generated is a first subset of the possible binary codewords. The first subset of possible binary codeword include the legal codeword [1,0] and the illegal codeword [0,1] as discussed above. In other words, the comparator act as a fault avoidance architecture for the working of the comparator.

[0113] Now when the binary codeword is a second subset of the possible binary codewords i.e. [0, 0] or [1,1] it is determined that the there is definitely a fault within the comparator. In this case the input may be the same or different. Thus, when the binary codeword generated is [0, 0] or [1,1] the output determined may be communicated to an error correcting circuit to indicate that the comparator itself is experiencing a fault. Hence the comparator act as a self-checking circuitry when the binary codewords i.e. [0, 0] or [1,1] is generated. Thus, the comparator copes with single stuck-at faults. In other words, in some cases when a stuck-at fault occurs in any of the gates in the comparator, and when the other gates are functioning correctly, then the comparator still provide an output indicating the correct comparison result or provides an output indicating that a fault is present in the comparator itself. The comparator may also provide a correct comparison result or indicate a fault within the comparator when there is a double-stuck at fault or multiple stuck-at fault but not in all cases. However, it provides 100 percent reliable output in all cases of single stuck-at fault.

[0114] FIG.6 shows a computer system in which processing systems described herein may be implemented. The computer system comprises a CPU 602, a GPU 604, a memory 606, a neural network accelerator (NNA) 608 and other devices 614, such as a display 616, speakers 618 and a camera 622. The computer system may comprise two or more CPUs. The system may also further comprise two or more GPUs or NNA within the system. Output of any two CPUs, GPUs or NNA may be provided to the comparator to identify that the provided outputs are same or different. The components of the computer system can communicate with each other via a communications bus 620. A store 612 is implemented as part of the memory 606.

[0115] The comparator 300 / 400 of FIG. 3-4 are shown as comprising a number of functional blocks. This is schematic only and is not intended to define a strict division between different logic elements of such entities. Each functional block may be provided in any suitable manner. It is to be understood that intermediate values described herein as being formed by a system need not be physically generated by the comparator 300 / 400 at any point and may merely represent logical values which conveniently describe the processing performed by the comparator 300 / 400 between its input and output.

[0116] The comparator 300 / 400 described herein may be embodied in hardware on an integrated circuit. The comparator 300 / 400 described herein may be configured to perform any of the methods described herein. Generally, any of the functions, methods, techniques, or components described above can be implemented in software, firmware, hardware (e.g., fixed logic circuitry), or any combination thereof. The terms “module,” “functionality,” “component,” “element”, “unit”, “block” and “logic” may be used herein to generally represent software, firmware, hardware, or any combination thereof. In the case of a software implementation, the module, functionality, component, element, unit, block, or logic represents program code that performs the specified tasks when executed on a processor. The algorithms and methods described herein could be performed by one or more processors executing code that causes the processors) to perform the algorithms / methods. Examples of a computer-readable storage medium include a random-access memory (RAM), read only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices that may use magnetic, optical, and other techniques to store instructions or other data and that can be accessed by a machine.

[0117] The terms computer program code and computer readable instructions as used herein refer to any kind of executable code for processors, including code expressed in a machine language, an interpreted language, or a scripting language. Executable code includes binary code, machine code, bytecode, code defining an integrated circuit (such as a hardware description language or netlist), and code expressed in a programming language code such as C, Java, or OpenCL. Executable code may be, for example, any kind of software, firmware, script, module or library which, when suitably executed, processed, interpreted, compiled, executed at a virtual machine or other software environment, cause a processor of the computer system at which the executable code is supported to perform the tasks specified by the code.

[0118] A processor, computer, or computer system may be any kind of device, machine or dedicated circuit, or collection or portion thereof, with processing capability such that it can execute instructions. A processor may be or comprise any kind of general purpose or dedicated processor, such as a CPU, GPU, NNA, System-on-chip, state machine, media processor, an application-specific integrated circuit (ASIC), a programmable logic array, a field-programmable gate array (FPGA), or the like. A computer or computer system may comprise one or more processors.

[0119] It is also intended to encompass software which defines a configuration of hardware as described herein, such as HDL (hardware description language) software, as is used for designing integrated circuits, or for configuring programmable chips, to carry out desired functions. That is, there may be provided a computer readable storage medium having encoded thereon computer readable program code in the form of an integrated circuit definition dataset that when processed (i.e. run) in an integrated circuit manufacturing system configures the system to manufacture a system configured to perform any of the methods described herein, or to manufacture a comparator 300 / 400 comprising any apparatus described herein. An integrated circuit definition dataset may be, for example, an integrated circuit description.

[0120] Therefore, there may be provided a method of manufacturing, at an integrated circuit manufacturing system, a comparator 300 / 400 as described herein. Furthermore, there may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the method of manufacturing a comparator 300 / 400 to be performed.

[0121] An integrated circuit definition dataset may be in the form of computer code, for example as a netlist, code for configuring a programmable chip, as a hardware description language defining hardware suitable for manufacture in an integrated circuit at any level, including as register transfer level (RTL) code, as high-level circuit representations such as Verilog or VHDL, and as low-level circuit representations such as OASIS (RTM) and GDSII. Higher level representations which logically define hardware suitable for manufacture in an integrated circuit (such as RTL) may be processed ata computer system configured for generating a manufacturing definition of an integrated circuit in the context of a software environment comprising definitions of circuit elements and rules for combining those elements in orderto generate the manufacturing definition of an integrated circuit so defined by the representation. As is typically the case with software executing at a computer system so as to define a machine, one or more intermediate user steps (e.g. providing commands, variables etc.) may be required in order for a computer system configured for generating a manufacturing definition of an integrated circuit to execute code defining an integrated circuit so as to generate the manufacturing definition of that integrated circuit.

[0122] An example of processing an integrated circuit definition dataset at an integrated circuit manufacturing system so as to configure the system to manufacture a will now be described with respect to FIG. 7.

[0123] FIG. 7 shows an example of an integrated circuit (IC) manufacturing system 702 which is configured to manufacture a comparator 300 / 400 as described in any of the examples herein. In particular, the IC manufacturing system 702 comprises a layout processing system 704 and an integrated circuit generation system 706. The IC manufacturing system 702 is configured to receive an IC definition dataset (e.g. defining a comparator 300 / 400 as described in any of the examples herein), process the IC definition dataset, and generate an IC according to the IC definition dataset (e.g. which embodies a comparator 300 / 400 as described in any of the examples herein). The processing of the IC definition dataset configures the IC manufacturing system 702 to manufacture an integrated circuit embodying a comparator 300 / 400 as described in any of the examples herein.

[0124] The layout processing system 704 is configured to receive and process the IC definition dataset to determine a circuit layout. Methods of determining a circuit layout from an IC definition dataset are known in the art, and for example may involve synthesising RTL code to determine a gate level representation of a circuit to be generated, e.g. in terms of logical components (e.g. NAND, NOR, AND, OR MUX and FLIP-FLOP components). A circuit layout can be determined from the gate level representation of the circuit by determining positional information for the logical components. This may be done automatically or with user involvement in order to optimise the circuit layout. When the layout processing system 704 has determined the circuit layout it may output a circuit layout definition to the IC generation system 706. A circuit layout definition may be, for example, a circuit layout description.

[0125] The IC generation system 706 generates an IC according to the circuit layout definition, as is known in the art. For example, the IC generation system 706 may implement a semiconductor device fabrication process to generate the IC, which may involve a multiple-step sequence of photo lithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconducting material. The circuit layout definition may be in the form of a mask which can be used in a lithographic process for generating an IC according to the circuit definition. Alternatively, the circuit layout definition provided to the IC generation system 906 may be in the form of computer-readable code which the IC generation system 706 can use to form a suitable mask for use in generating an IC.

[0126] The different processes performed by the IC manufacturing system 702 may be implemented all in one location, e.g. by one party. Alternatively, the IC manufacturing system 702 may be a distributed system such that some of the processes may be performed at different locations, and may be performed by different parties. For example, some of the stages of: (i) synthesising RTL code representing the IC definition dataset to form a gate level representation of a circuit to be generated, (ii) generating a circuit layout based on the gate level representation, (iii) forming a mask in accordance with the circuit layout, and (iv) fabricating an integrated circuit using the mask, may be performed in different locations and / or by different parties.

[0127] In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture a comparator 300 / 400 without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA).

[0128] In some embodiments, an integrated circuit manufacturing definition dataset, when processed in an integrated circuit manufacturing system, may cause an integrated circuit manufacturing system to generate a device as described herein. For example, the configuration of an integrated circuit manufacturing system in the manner described above with respect to FIG. 7 by an integrated circuit manufacturing definition dataset may cause a device as described herein to be manufactured.

[0129] In some examples, an integrated circuit definition dataset could include software which runs on hardware defined at the dataset or in combination with hardware defined at the dataset. In the example shown in FIG. 7, the IC generation system may further be configured by an integrated circuit definition dataset to, on manufacturing an integrated circuit, load firmware onto that integrated circuit in accordance with program code defined at the integrated circuit definition dataset or otherwise provide program code with the integrated circuit for use with the integrated circuit.

[0130] The implementation of concepts set forth in this application in devices, apparatus, modules, and / or systems (as well as in methods implemented herein) may give rise to performance improvements when compared with known implementations. The performance improvements may include one or more of increased computational performance, reduced latency, increased throughput, and / or reduced power consumption. During manufacture of such devices, apparatus, modules, and systems (e.g. in integrated circuits) performance improvements can be traded-off against the physical implementation, thereby improving the method of manufacture. For example, a performance improvement may be traded against layout area, thereby matching the performance of a known implementation but using less silicon. This may be done, for example, by reusing functional blocks in a serialised fashion or sharing functional blocks between elements of the devices, apparatus, modules and / or systems. Conversely, concepts set forth in this application that give rise to improvements in the physical implementation of the devices, apparatus, modules, and systems (such as reduced silicon area) may be traded for improved performance. This may be done, for example, by manufacturing multiple instances of a module within a predefined area budget.

[0131] The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A comparator comprising:a logic circuitry configured to receive two binary inputs A and B, and identify if the binary inputs are same or different, wherein the logic circuitry comprises a plurality of logic gates configured to:perform bitwise operations logically equivalent to AND operations A ■ B, A ■ B, A ■ B and A -B; andgenerate a binary codeword [Z, ~Z\ indicative of whether the binary inputs are the same or different based on the outputs of the bitwise operations, wherein one binary codeword is predefined as a legal codeword to indicate that the binary inputs are the same.

2. The comparator as claimed in claim 1, wherein the comparator provides the generated binary codeword as output of the comparator.

3. The comparator as claimed in claim 1 or 2, wherein the comparator is configured to generate a binary codeword other than the legal codeword when the inputs A and B are different.

4. The comparator as claimed in claims 1 to 3, wherein the comparator is configured to receive each binary input A and Bfrom different systems and perform the comparison to indicate if the systems are producing the same output.

5. The comparator as claimed in claim 1 to 4, wherein the comparator is configured to operate as a fault avoidance architecture by masking faults in the working of the comparator that do not affect the output of the comparator when the generated codeword is from a first subset of possible binary codewords.

6. The comparator as claimed in claim 1 to 5, wherein the comparator is configured such that codewords from a second subset of possible binary codewords indicate that there is a fault in the working of the comparator.

7. The comparator as claimed in claim 1 to 6, wherein the logical operations are performed by a plurality of AND gates.

8. The comparator as claimed in claim 1-7, wherein the logic circuitry generates the binary codeword [Z, ~Z\ by:generating Zby performing a bitwise operation logically equivalent to an OR operation between A. B and AB;andgenerating -Zby performing a bitwise operation logically equivalent to an OR operation between AB and AB.

9. The comparator as claimed in claim 1 to 8, wherein the logic circuitry comprises two OR gates for generating the binary codeword {Z, ~Z\.

10. The comparator as claimed in claim 1 to 9, wherein the logic circuitry comprises NOT gates for generating invented inputs A and B.

11. The comparator as claimed in claim 1 to 10, wherein the legal codeword is [1,0],12. The comparator as claimed in claim 1 to 11, wherein the binary codeword other than thelegal codeword includes [0,0], [0,1] and [1,1].

13. A method of identifying if two binary inputs A and B received by a comparator are same or different, the method comprises:performing bitwise operations logically equivalent to AND operations A ■ B, A ■ B, A ■ B and A -B; andgenerating a binary codeword [Z, ~2\ indicative of whether the binary inputs are the same or different based on the outputs of the bitwise operations, wherein one binary codeword is predefined as a legal codeword to indicate that the binary inputs are the same.

14. The method as claimed in claim 13, the method further comprises providing the generated binary codeword as the output of the comparator.

15. The method as claimed in claim 13-14, wherein the method comprises generating a binary codeword other than the legal codeword when the binary input A and 2? are different.

16. The method as claimed in claim 13-15, wherein the method comprises receiving each binary input A and B from different systems and performing the comparison to indicate if the systems are producing the same output.

17. The method as claimed in claim 13-16, wherein the method comprises masking the faults in the working of the comparator that do not affect the output of the comparator when the generated codeword is from a first subset of possible binary codewords.

18. The method as claimed in claim 13-17, wherein the method comprises indicating that there is a fault in the working of the comparator when the generated codeword is from a second subset of possible binary codeword.

19. The method as claimed in claim 13-18, wherein generating the binary codeword [Z, ~Z\ comprises:generating Zby performing an OR operation between two logical AND operations A ■ B and A ■ B; andgenerating -Z by performing an OR operation between the other two logical AND operations A ■ B and A ■ B.

20. The method as claimed in claims 13-19, wherein the legal codeword is [1,0],21. A method of manufacturing, using an integrated circuit manufacturing system, a comparator as claimed in any of claims 1 to 12.

22. Computer readable code configured to cause the method of any of claims 13 to 20 to be performed when the code is run.

23. A computer readable storage medium having encoded thereon the computer readable code of claim 22.

24. An integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a comparator as claimed in any of claims 1 to 12.

25. A non-transitory computer readable storage medium having stored thereon a computer readable description of a comparator as claimed in any of claims 1 to 12 that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the comparator.36

Images