Task delegation

Abstract

An apparatus, a method or a computer program, comprising a plurality of registers (2) configured to store data. The plurality of registers comprising at least one array register (3) . The data process

Description

The present invention relates to data processing. More particularly, the present invention relates to an apparatus, a method, and a computer program. An apparatus may be provided with data processing circuitry for processing a sequence of instructions and a plurality of registers configured to store data. According to a first aspect of the present techniques there is provided an apparatus comprising: a plurality of registers configured to store data, the plurality of registers comprising at least one array register; data processing circuitry for processing a sequence of instructions, wherein the data processing circuitry comprises decoder circuitry responsive to receipt of one or more instructions of the sequence of instructions specifying the at least one array register to control the data processing circuitry to perform array processing operations in relation to the at least one array register; and extension processing circuitry associated with the data processing circuitry and responsive to identification, by the data processing circuitry, of a delegated task to perform the delegated task asynchronously to the data processing circuitry, wherein the decoder circuitry is responsive to a delegation instruction to trigger the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations. According to a second aspect of the present techniques there is provided a method of operating an apparatus comprising a plurality of registers configured to store data, the plurality of registers comprising at least one array register, the method comprising: with decoder circuitry, receiving a sequence of instructions, and in response to receipt of one or more instructions of the sequence of instructions specifying the at least one array register, performing array processing operations in relation to the at least one array register; and in response to identification of a delegated task by the data processing circuitry, causing extension processing circuitry associated with the data processing circuitry to perform the delegated task asynchronously to the data processing circuitry; and in response to a delegation instruction, triggering the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations. According to a third aspect of the present techniques there is provided a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: a plurality of data structures configured to store data, the plurality of data structures comprising at least one array data structure; data processing program logic for processing a sequence of instructions, wherein the data processing program logic comprises decoder program logic responsive to receipt of one or more instructions of the sequence of instructions specifying the at least one array data structure to perform array processing operations in relation to the at least one array data structure; and extension processing program logic associated with the data processing program logic and responsive to identification, by the data processing program logic, of a delegated task to perform the delegated task asynchronously to the data processing program logic, wherein the decoder program logic is responsive to a delegation instruction to trigger the extension processing program logic to perform, as the delegated task, one or more operations associated with one of the array processing operations. According to a further aspect of the present techniques, there is provided a storage medium configured to store the computer program according to the third aspects. In some configurations the storage medium is a non-transitory storage medium. The present techniques will be described further, by way of example only, with reference to configurations thereof as illustrated in the accompanying drawings, in which: Figure 1 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 2 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 3 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 4 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 5 schematically illustrates an array register according to some configurations of the present techniques; Figure 6 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 7 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 8 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 9 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 10 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 11 schematically illustrates an apparatus according to some configurations of the present techniques; Figure 12 schematically illustrates a sequence of steps according to some configurations of the present techniques; Figure 13 schematically illustrates a sequence of steps according to some configurations of the present techniques; Figure 14 schematically illustrates some example operations according to some configurations of the present techniques; Figure 15 schematically illustrates a sequence of steps according to some configurations of the present techniques; and Figure 16 schematically illustrates a simulator implementation according to some configurations of the present techniques. According to some configurations of the present techniques there is provided an apparatus comprising a plurality of registers configured to store data, the plurality of registers comprising at least one array register. The apparatus comprises data processing circuitry for processing a sequence of instructions. The data processing circuitry comprises decoder circuitry responsive to receipt of one or more instructions of the sequence of instructions specifying the at least one array register to control the data processing circuitry to perform array processing operations in relation to the at least one array register. The apparatus comprises extension processing circuitry associated with the data processing circuitry and responsive to identification, by the data processing circuitry, of a delegated task to perform the delegated task asynchronously to the data processing circuitry. The decoder circuitry is responsive to a delegation instruction to trigger the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations. Registers are provided as part of the apparatus (e.g., a data processing apparatus) to store data that is to be used in processing operations that are carried out in response to instructions executed by the apparatus, or that are used to store results generated by the instructions. The registers may include scalar registers configured to store scalar operands and / or vector registers configured to store vector operands. The registers include at least one array register. The array register stores a two dimensional array of elements where each element of the array register may be accessed based on a selection of a row and a column corresponding to the row and column of the array register in which that element is located. The array register may be addressable in a plurality of different access patterns depending on micro-operation register access pattern information specified by a micro-operation which references the array register. For example, the array register may be accessible as slices in either a horizontal dimension or vertical dimension of a two-dimensional array of elements, or can be accessible as “tiles” formed of a number of portions of elements selected from different portions of the array register storage at intervals of a certain stride offset. The apparatus is provided with data processing circuitry to process instructions from a sequence of instructions. The sequence of instructions comprise instructions of an instruction set architecture (ISA) which is a complete set of instructions that a programmer or compiler can use to control the data processing circuitry. The instructions of the ISA are interpreted by decoder circuitry which is comprised in the data processing circuitry. The decoder circuitry therefore acts to receive and interpret instructions of the instruction set architecture and, in response to these instructions, to control the data processing circuitry to perform the operations specified in those instructions. The data processing circuitry may be responsive to a wide range of different instructions, for example, arithmetic instructions, logical instructions and / or instructions to access a memory hierarchy containing data and / or further instructions to be loaded for utilisation by the data processing circuitry. The data processing circuitry is responsive to at least one instruction (i.e., one or more instructions) that specifies the at least one array register to perform an array processing operation. The at least one instruction may specify the array register as an input operand to be used in the instruction or as a location in which to store an output of an instruction. The at least one instruction may specify other registers in addition to the array register, for example, to identify additional inputs or as a location to store the output. In addition to the data processing circuitry, the apparatus is also provided with extension processing circuitry that is associated with the data processing circuitry. The extension processing circuitry is configured to perform such a function (a delegated task) in response to an identification of that deleted task by the data processing circuitry. For example, the data processing circuitry may issue a delegation signal to trigger the extension processing circuitry to perform the delegated task. Such extension processing circuitry may also be referred to as a threadlet extension (TE) herein, or as a CPU Accelerated Function Extension (CAFE). The one or more operations carried out by the extension processing circuitry, and that form the delegated task, may also be referred to as a threadlet herein. The extension processing circuitry, although closely associated (tightly coupled) with the data processing circuitry, is configured to perform the delegated task asynchronously to the array processing operations performed by data processing circuitry. Threadlets are functions or collections of operations that, once triggered, can be executed asynchronously relative to other processing activities performed by the data processing circuitry. The asynchronous operation of the extension processing circuitry with respect to the data processing circuitry is possible because, unlike some prior art techniques, the extension processing circuitry receives a directive or command from the thread currently executing on the data processing circuitry and performs the required operations independently, that is without requiring a stream of instructions from the data processing circuitry to directly control or influence its internal operation. The data processing circuitry is therefore free to continue executing other code and potentially reduce overall runtime by overlapping the execution of the sequence of instructions, after the directive or command is sent to the extension processing circuitry, with the operation of the extension processing circuitry. The directive or command sent to the extension processing circuitry to initiate the delegated task is generated in response to a delegation instruction defined purpose in the instruction set architecture of the data processing circuitry. The decoder circuitry is responsive to the delegation instruction to issue the delegation signal to the extension processing circuitry to delegate the delegated task to the extension processing circuitry. Because of the tight integration of the extension processing circuitry with the data processing circuitry, the extension processing circuitry can be launched rapidly and its state can be checked in a short amount of time (e.g. of the order of a few ns) relative to some prior art techniques, which would require a great many clock cycles for launching commands or performing synchronisation operations. The inventors have recognised that the use of an array register by the data processing circuitry requires both operations to move data to or from the array register, and operations to manipulate (or perform calculations on) the data within the array register. As the array register is relatively large, for example, compared to a scalar register, the time taken to move data can, in some example use cases, take up significant time that could otherwise be used for performing operations to manipulate data, e.g., arithmetic or logical instructions. The decoder circuitry is therefore responsive to the delegation instruction to trigger the extension processing circuitry to perform a delegated task in which one or more operations associated with the array processing operations are performed. Because the one or more operations are performed by the extension processing circuitry, they are performed asynchronously to the array processing operations performed by the data processing circuitry. Making use of the asynchronous nature of the extension processing circuitry therefore allows some of the array processing operations to be overlapped with other processing operations resulting in a greater utilisation of the data processing circuitry and a greater overall throughput. The particular operations that are performed by the extension processing circuitry can vary. In some configurations the extension processing circuitry is configured to perform, as one of the one or more operations, one or more pre-processing operations to prepare one or more data elements for one of the array processing operations. The pre-processing operations may directly target the array register itself, for example, by loading data into the array register and / or by manipulating data within the array processing register into a different form (e.g., by duplicating data values, moving data values, and / or rearranging data values). Alternatively, or in addition, the one or more operations may target registers other than the array register. For example, the one or more operations may comprise moving data into scalar registers or vector registers to be subsequently utilised by the data processing circuitry in one of the array processing operations. In some configurations the one or more pre-processing operations comprise loading data from a memory system into at least one target register of the plurality of registers. The one or more pre-processing operations may comprise one or more load operations. The one or more load operations may specify an address or a sequence of addresses in the memory system. Alternatively, or in addition, in some configurations the extension processing circuitry is configured to perform, as one of the one or more operations, a postprocessing operation to offload data generated by one of the array processing operations. For example, the post-processing operation may be a store operation to store data to the memory system. The data being stored may be stored from the array register, for example, in a use case in which the array register is used as an output registers for the array processing operations. The data may also, or instead, be stored from a scalar register or a vector register, for example, where the array register is used as an input to the array processing operations and the scalar register or the vector register is used as an output for those array processing operations. In some configurations the one or more post-processing operations comprise storing data from at least one target register of the plurality of registers to a memory system. For example, the one or more post-processing operations may comprise a store operation carried out in response to a store instruction specifying the target register and a location in memory to which the data is to be stored. Alternatively, or in addition, the one or more post-processing operations may comprise load operations carried out in response to load instructions specifying the target register and a location in memory from which the data is to be loaded. In some configurations the target register is the array register. However, as discussed, in some alternative use cases the target register may be a register, other than the array register, that is used (e.g., is accessed) in the array processing operations. In some configurations the target register is a register provided as part of an array processing unit and that is arranged to be accessed as part of the array processing operations. In some configurations the delegation instruction specifies one or more specified registers of the plurality of registers, and the decoder circuitry is responsive to the array processing instruction to indicate the one or more specified registers to the extension processing circuitry. The extension processing circuitry may therefore receive an indication of the delegated task along with an indication of specified registers that are to be used, e.g., as the target register, in the delegated task. Alternatively, one or more default registers may be used as the target register. The one or more specified registers may be any of the registers accessible by the array processing instructions, e.g., vector registers or scalar registers. In some configurations the one or more specified registers comprises the array register. The specification of the one or more specified registers may specify the whole of the array register or a portion of the array register, e.g., one or more tiles of the array register. In some configurations the one or more specified registers may comprise multiple portions of the array register. The multiple portions of the array register may be contiguous portions of the array register or non-contiguous portions dependent, for example, on the particular use case. In addition to being responsive to the delegation instruction, in some configurations the decoder circuitry is responsive to an extension synchronisation instruction to determine whether the extension processing circuitry has completed the delegated task. For example, in some use cases, the data processing circuitry may be able to proceed with one or more array processing operations whilst the extension processing circuitry is performing the delegated task. However, the inventors have recognised that there are some use cases where the data processing circuitry may not be able to continue processing until the delegated task is completed. For example, if the delegated task relates to particular regions of the array register, or to other registers in the plurality of registers, the data processing circuitry may not be able to access or write to those registers until the extension processing circuitry has completed the delegated task. Because the extension processing circuitry operates asynchronously to the data processing circuitry, the data processing circuitry does not know how long the extension processing circuitry will take to perform the delegated task. The provision of the extension synchronisation instruction therefore enables the data processing circuitry to determine whether or not the extension processing circuitry has finished the delegated task. The provision of this instruction allows a programmer or compiler to determine whether the delegated task is finished and can use the result of this determination to influence further processing activities performed by the data processing circuitry. In some configurations the decoder circuitry is responsive to the extension synchronisation instruction to control the extension processing circuitry to pass at least one result data value to at least one result register of the plurality of registers when the extension processing circuitry has completed the delegated task. The result data value may be a binary indication that the extension processing circuity has finished and / or a result associated with the one or more operations performed by the extension processing circuitry. The at least one result register may be a default result register or a register specified by the data processing circuitry in response to the delegation instruction. The result value may be used by the data processing circuitry, for example to cause the data processing circuitry to branch dependent on whether the extension processing circuitry has completed the delegated task. In some configurations the data processing circuitry is responsive to a determination that the extension processing circuitry has not completed the delegated task to set at least one incomplete condition flag in a condition register of the set of registers. The incomplete condition flag may be a special flag defined for the purpose of interaction between the data processing circuitry and the extension processing circuitry. Alternatively, the incomplete condition flag may be an existing general purpose flag used to control the outcome of a branch condition. In some configurations the data processing circuitry is responsive to the at least one incomplete condition flag being set to divert from the received sequence of instructions to retrieve an alternative set of instructions and to perform a further set of data processing operations in dependence on the alternative set of instructions. As discussed, the diversion may be performed by one or more branch instructions which branches, i.e., jumps to a non-consecutive instruction, if the incomplete condition flag is set and that does not branch if the incomplete condition flag is not set. This approach allows a programmer or compiler to design a program such that it will proceed to perform an alternative sequence of operations in the event that the extension processing circuitry takes longer than anticipated to perform the delegated task and allows the programmer or compiler to take advantage of available processing resources to increase the overall throughput in this way. The data processing circuitry may be arranged as a single processing unit configured to operate as a processing pipeline that is capable of scalar processing, vector processing, and array processing. However, in some configurations the data processing circuitry comprises a data processing pipeline and matrix processing circuitry, wherein the matrix processing circuitry is configured to perform the array processing operations in relation to the at least one array register. The matrix processing circuitry may be configured to perform specific matrix operations, e.g., matrix multiply operations, matrix multiply accumulate operations, matrix addition operations, and / or matrix rearrangement operations, etc. The matrix processing circuitry performs the specific matrix operations using data arranged in the array register, e.g., laid out in a two dimensional array having data addressable in two or more rows and two or more columns. The data processing pipeline and the matrix processing circuitry may each access a different set of registers. For example, the matrix processing circuitry may be provided with a set of vector registers (in addition to the array register), that are different to vector registers accessible to the data processing pipeline. As discussed, the extension processing circuitry performs, as the delegated task, one or more operations associated with one of the array processing operations where the array processing operations are those ones of the processing operations that access the registers (either the array register, the vector registers, or one or more scalar registers) that are accessible to the matrix processing circuitry. Hence, whilst the extension processing circuitry may not itself directly access the array register, it accesses registers that are accessible and can be utilised by the matrix processing circuitry when performing the array operations. In some configurations the data processing pipeline is one of a plurality of data processing pipelines configured to interact with the matrix processing circuitry; and the extension processing circuitry is one of a plurality of instances of extension processing circuitry, each instance of the extension processing circuitry coupled to a corresponding one of the data processing pipelines and configured to receive the identification of the delegated task to be performed by that instance of the extension processing circuitry from the corresponding one of the data processing pipelines. In other words, the relationship between the data processing pipelines and the matrix processing circuitry may be a many to one relation, and the relationship between the data processing pipelines and the extension processing circuitry may be a one to one relationship. This is not always the case though and in some configurations multiple sets of extension processing circuitry may be provided to a single data processing pipeline. Alternatively, multiple data processing pipelines may share a smaller number of sets of extension processing circuitry. For example, a single set of extension processing circuitry may be provided and shared between a plurality of data processing pipelines. In some configurations the extension processing circuitry is configured to perform, as one of the one or more operations, a matrix processing operation accessing the at least one array register. The matrix processing operation may be a load operation to load data into the array register from memory, an arithmetic operation to generate elements to be stored in the array register from elements stored either in the array register or in one or more vector registers associated with the array register, an arithmetic operation to generate elements to be stored in a vector or scalar register from data stored in the array register, or a store operation to store data from the array register to memory. In some configurations the matrix processing operation comprises reading data from the at least one array register. In some configurations the matrix processing operation comprises writing result data to the at least one array register. In some configurations the at least one matrix processing operation comprises reading data from the array register and writing to data to the array register. In such configurations, the data read from the array register and the data written to the array register may target either a same portion of the array register or different portions of the array register. In some configurations the array register is a two dimensional array register storing data elements identified by coordinates in a first array direction and a second array direction. The two dimensional array register comprises at least two rows and at least two columns. The two dimensional array register is two dimensional in terms of how it is accessed. The two dimensional nature of the array register does not necessarily correspond to how it is laid out when fabricated. For example, the two dimensional array register may be accessible as an N by M array having N rows and M columns. However, the array may be fabricated so that the physical storage elements are arranged in a linear fashion, randomly distributed around a chip, or arranged in an array having P rows and Q columns where, in some configurations P is equal to N and Q is equal to M, whilst in other configurations P is not equal to N and Q is not equal to M. In some configurations the extension processing circuitry is capable of performing the one or more operations in parallel with the data processing circuitry performing the array processing operations. By performing the one or more operations in parallel with the array processing operations performed by the data processing circuitry, the rate at which operations are processed can be increased and the overall throughput of the apparatus can be improved. In some configurations the apparatus comprises a plurality of physical array registers; and array register renaming circuitry configured to map the at least one array register to one of the plurality of physical array registers, wherein the extension processing circuitry is configured to interact with one of the plurality of physical array registers other than the one of the plurality of physical array registers currently mapped to the at least one array register. Register renaming is a technique in which a different number of physical registers are provided than the number of architectural registers specified in an instruction set architecture. Typically, a greater number of physical registers are provided than there are architectural registers. The register renaming circuitry can then map different physical registers to the architectural registers for different instructions allowing instructions to be performed out of program counter order, e.g., by mapping two different uses of a same architectural register to two different physical registers, thereby avoiding the need for one use of that architectural register to be complete before the other use of that architectural register can begin. The inventors have recognised that this approach can also be used to provide improved independence of the extension processing circuitry and the data processing circuitry by having a plurality of physical array registers with a different one of the array registers being utilised by each of the extension processing circuitry and the data processing circuitry. For example, whilst there may only be a single architecturally defined array register the data processing pipeline could be arranged to write data to a particular region of the single architectural register whilst the extension processing circuitry offloads data from the same region of the single architecturally defined array register by having the architecturally defined array register mapped to one of the physical array registers for the extension processing circuitry and to another of the physical array registers for the data processing circuitry. Subsequent to the completion of the offloading, these registers could be swapped by the array register renaming circuitry and without the explicit instruction or knowledge of a programmer or compiler preparing code to be implemented on the apparatus. In some configurations the apparatus comprises one or more data transfer channels coupled between the extension processing circuitry and the data processing circuitry configured to transfer data between the extension processing circuitry and the data processing circuitry when performing the delegated task. For example, each element of the array register may be provided with access to a data transfer channel to transfer data between an element of the array register as accessible to the data processing circuitry and the element of the array register as accessible to the extension processing circuitry. In other words, in addition to providing an input / output port from the array register to be used by the data processing circuitry, an additional input / output port may be provided from the array register to the extension processing circuitry. Whilst in some configurations the extension processing circuitry may be task specific circuitry configured to perform a single delegated task, in some configurations the extension processing circuitry is configured to perform a plurality of different delegated tasks, and the decoder circuitry is configured to specify the delegated task to be performed from amongst the plurality of different delegated tasks. For example, the extension processing circuitry may be configured to perform loading tasks, data manipulation tasks and offloading tasks as specified by the data processing circuitry. Alternatively, or in addition, the extension processing circuitry may be configured to perform one or more arithmetic matrix operations utilising the array register as selected by the data processing circuitry. The provision of extension processing circuitry that is capable of performing multiple different tasks as specified by the data processing circuitry introduces improved flexibility. In some configurations the delegated task is specified in the delegation instruction. The delegated task may be specified as an immediate operand in the delegation instruction or as a specific parameter, e.g., as specified in one of the plurality of registers. In some configurations the data processing circuitry may be responsive to a plurality of different encodings of the delegation instruction with a different encoding being provided for each task that could potentially be performed by the extension processing circuitry. In some configurations the delegation instruction may be one of a plurality of different delegation instructions recognised by the decoder circuitry and may cause the data processing circuitry to issue the delegation signal indicating which one of the delegation instructions caused the data processing circuitry to issue the delegation signal. Some configurations of the present techniques will now be described with reference to the accompanying figures. Figure 1 schematically illustrates an apparatus 1 according to some configurations of the present techniques. The apparatus 1 is provided with a plurality of registers 2, data processing circuitry 6, and extension processing circuitry 8. The plurality of registers 2 includes scalar registers 5, vector registers 4, and an array register 3. The plurality of registers 2 is accessible by the data processing circuitry 6 and the extension processing circuitry 8. The data processing circuitry 6 comprises decoder circuitry 7 which is configured to receive a sequence of instructions. The decoder circuitry 7 decodes the received instructions and controls the processing circuitry 6 to perform the operations set out in the instructions using data values stored in the plurality of registers 2. In particular, the data processing circuitry 6 is arranged to perform array operations that utilise data stored in the array register 3. The data processing circuitry 6 is also coupled to the extension processing circuitry 8. The decoder circuitry 7 is responsive to a delegation instruction to trigger the extension processing circuitry 8 to perform a delegated task. The extension processing circuitry 8 is responsive to the trigger received from the data processing circuitry 6 to perform the delegated task asynchronously to the data processing circuitry 6 and without further input from the data processing circuitry 6. The delegated task performed by the extension processing circuitry 8 is associated with the array processing operations that are performed by the data processing circuitry 6 and includes accessing at least one of the plurality of registers 2 that is accessible to the data processing circuitry 6 and that is utilised by the data processing circuitry 6 when performing one of the array operations. Figure 2 schematically illustrates further examples of an apparatus 10 according to some configurations of the present techniques. The data processing apparatus 10 is schematically shown to have a pipelined configuration, which for the purposes of brevity and clarity is shown in a conceptual representation here. The illustrated pipeline stages comprise an instruction cache 11, a fetch stage 12, a decode stage 13, a micro-op cache 14, an issue stage 15, and a plurality of registers 24. A sequence of instructions is retrieved from memory (not shown) and cached in the instruction cache 11. The fetch stage 12 controls which instructions are retrieved as the sequence of instructions and these instructions are then decoded in the decode stage 13. This decoding essentially identifies the type of each instruction, as well as any further operands specified by the instruction, and generates control signals to control the remainder of the apparatus to perform the data processing operation(s) defined by the instruction. Decoding the instructions may comprise splitting an instruction into one or more micro-ops (microoperations), and these micro-ops can be cached in the micro-op cache 14. The final stage of the pipeline before execution is the issue stage 15, where instructions (or microops) are queued pending the availability of the register values they specify as operands and the corresponding functional unit of the data processing pipeline which will carry out the defined operation. Generally, the data processing operation(s) defined by the instructions are carried out by the functional units that form part of the data processing pipeline, namely the load / store unit 17, the execute unit 18, and the execute unit 19. These latter execute units may for example be arithmetic logic units (ALUs), floating point units (FPUs), and so on. The functional units that form part of the data processing pipeline perform their data processing operations on data values which are provided from a set of registers 24 and result values of those data processing operations are returned to the set of registers 24. The load / store unit 17 is provided for the purpose of storing values from the set of registers 24 to the memory system and loading values from the memory system to the set of registers 24. The memory system comprises a number of levels of cache prior to the main memory, of the levels of cache a level 1 cache 21 and a level 2 cache 22 are shown in the figure. The LI cache 21 is private to the data processing apparatus 10 and the L2 cache 22 may be shared with another data processing apparatus, when part of a wider data processing system. The data processing apparatus 10 is also shown to comprise a branch unit 20, which monitors execution flow of the sequence of instructions and seeks to predict, based on previous execution history, whether a given branch will be taken or not. The predictions from the branch unit 20 inform the sequence of instructions caused to be fetched by the fetch stage 12. The data processing apparatus 10 further comprises extension processing circuitry 23, which is provided to support efficient performance of one or more defined functions, which have been established to be impactful and ubiquitous for the data processing operations which this data processing apparatus 10 carries out. The extension processing circuitry is closely associated with the data processing pipeline and is configured to perform the defined function (also referred to herein as a delegated task) in response to a delegation signal received from the data processing pipeline. The extension processing circuitry 23 is an example of a threadlet extension (TE) according to the present techniques. The sequence of operations it carries out to perform the defined function is referred to as a threadlet herein. The extension processing circuitry 23, although closely associated with the data processing pipeline, is configured to perform the delegated task asynchronously to the data processing operations performed by data processing pipeline. The data processing pipeline may also be referred to as the CPU herein. Threadlets are functions or collections of operations that can be executed asynchronously relative to other CPU activity once launched. The directive or command sent to the extension processing circuitry 23 to initiate the delegated task is generated in response to a delegation instruction defined for this purpose in the instruction set of the data processing pipeline. Thus, a delegation instruction progresses along the data processing pipeline in the manner that any other CPU instruction would, but when the decoding circuitry 13 identifies the extension start instruction it can signal directly to the extension processing circuitry 23. The close integration of the extension processing circuitry 23 with data processing pipeline is illustrated by the fact that the extension processing circuitry 23 has direct access to the load / store unit 17, and thus it shares the data processing pipeline’s path to memory. The extension processing circuitry 23 also has access to the set of registers 24, such that for example, the extension start instruction can specify one or more registers as operands, and the values from these registers are then passed directly to the extension processing circuitry 23 in association with the command sent to initiate the delegated task. Upon completion of the task, results of the delegated task can be returned to the register values in response to an extension synchronisation instruction received by the decode circuitry 13. In the illustrated configuration the registers 24 include scalar registers 25, vector registers 26 and an array register 27. The array register 27 is utilised by the data processing circuitry to perform array operations. The extension processing circuitry 23 is able to interact with the set of registers 24 including the array register 27 and is configured to perform tasks associated with the array operations performed by the data processing circuitry. Figure 3 schematically illustrates an alternative layout of an apparatus 30 according to some configurations of the present techniques. The apparatus 30 is provided with many of the same components as described in relation to figure 2 and, for reasons of conciseness, the description of these components will not be repeated. The apparatus 30 differs from the apparatus 10 as described in relation to figure 2 in that the array register 29 is provided as part of matrix processing circuitry 28 that is separate from the execution unit 18 and the execution unit 19. The apparatus 30 is further provided with register access circuitry 16 arranged to allow the execution unit 18 and the execution unit 19, along with the extension processing circuitry 23, to access the vector registers and the scalar registers. The matrix processing circuitry 28 operates under instruction from the processing pipeline and specific matrix processing operations issued, by the issue circuitry 15, to the matrix processing circuitry 28. The matrix processing circuitry is arranged, as will be described in further detail below, to perform matrix operations. The extension processing circuitry 23 operates as described in relation to figure 2 and is able to access the array register 29 through the matrix processing circuitry 28 to allow the extension processing circuitry 23 to perform the delegated tasks associated with the array operations that are performed by the matrix processing circuitry 28. Figure 4 schematically illustrates a further example of an apparatus 40 comprising a processing pipeline 42, extension processing circuitry 41 and matrix processing circuitry 43. The processing pipeline 42 may be arranged as described in relation to figures 2 and 3. The processing pipeline is coupled to its own LI data cache 45 which is coupled via the L2 cache 46 to the rest of the memory hierarchy. The extension processing circuitry 41 is coupled to the processing pipeline 42 and, as discussed, has access to the registers in the processing pipeline 42. The extension processing circuitry 41 is provided with its own LI cache 44 to facilitate interaction between the extension processing circuitry and the memory system. The extension processing circuitry 41, in the illustrated configuration, is therefore configured to interact with the memory independently from the processing pipeline 42. The matrix processing circuitry 43 is coupled to the processing pipeline 42 and the extension processing circuitry 41. The matrix processing circuitry 43 operates under control of the processing pipeline and performs processing operations in response to instructions received by the processing pipeline 42 and that are decoded by the decoder circuitry in the processing pipeline 42. The matrix processing circuitry 43 is provided with an array register and is arranged to perform array processing operations utilising that array register. The matrix processing circuitry 43 does not have its own path to memory and interacts with the processing pipeline to perform memory access operations. The extension processing circuity 41 is also coupled to the matrix processing circuitry 43 and is arranged to interact with it to perform one or more delegated tasks asynchronously to the operations performed by the processing pipeline 42 and asynchronously to the array processing operations performed by the matrix processing circuitry 43. Figure 5 schematically illustrates a portion of an array register in more detail. Each small box within Figure 5 represents one data element of a given size (e.g. 8, 16, 32 or 64 bits). In the example of Figure 5, the array register ZA is addressable as 32 regions ZA[0] to ZA

[31] , which are addressable in a wide variety of ways as shown: - in the examples ZA6H.D[0], ZA0H.H[7], ZA2H.S[5], ZA12H.Q[1] a horizontal slice of data from a single region ZA[i] is accessible as a vector operand, with different sized vector element sizes denoted by the .D, .H, .S, .Q notation; - in the example ZA0V.B

[22] , a vertical slice of data from a given column position

[22] within each of the 32 regions ZA[0] to ZA

[31] is accessible as a vector operand. Again, it would be possible to provide different data element sizes for the vector operand accessed as a vertical slice, similar to the horizontal slices shown for Figure 2. As shown in examples ZA7V.D[3], ZA3V.S[4], ZA1V.H[1], ZA8V.Q[0], it is also possible to access, as a single vector operand, a tile of elements where each portion of the tile is extracted from a different region of the array register ZA[0] to ZA

[31] , For example, ZA7V.D[3] comprises 4 sets of 8 elements selected from column positions [31:24] of each of ZA[7], ZA

[15] , ZA

[23] , ZA

[31] ; ZA3V.S[4] comprises 8 sets of 4 elements selected from column positions [19:16] of each of ZA[3], ZA[7], ZA

[11] , ZA

[15] , ZA

[19] , ZA

[23] , ZA

[27] and ZA

[31] ; ZA1V.H[1] comprises 16 sets of 2 elements selected from column positions [3:2] of each of the odd-numbered ZA regions, and ZA8V.Q[0] comprises two sets of 16 elements selected from column positions [15:0] of ZA[8] and ZA

[24] respectively. The array register ZA can therefore be addressed in a variety of ways and different portions of the array register may be accessible to different array operations performed by the data processing circuitry and / or by the extension processing circuitry. Figure 6 schematically illustrates a delegation instruction 61 to trigger the data processing circuitry to delegate a task to extension processing circuitry 64 according to some configurations of the present techniques. Here the delegation instruction takes the form: XSTART x9 {ZA} {p0-p4} xl7 #imm_save. The XSTART instruction 61, when decoded by decoder circuitry 62 will trigger the saving of the ZA array register using predicates pO to p4 with a base pointer in xl7 to identify the location to which the array will be saved. The content of the predicate registers pO to p4, the array register ZA, and the register xl7 is retrieved and passed from the registers 63 to the extension processing circuitry 64. The XSTART instruction returns a handle or request ID in x9 from the extension processing circuitry 64 to the registers 63. The request ID could be used, for example, by the corresponding synchronisation instruction later on. The immediate field #imm_save indicates the type of operation being performed by the extension processing circuitry (for example, if the extension processing circuitry is configured to perform multiple different types of operation) and #imm_save (or signals based on the immediate value #imm_save) is passed from the decoder circuitry 62 to the extension processing circuitry 64 to trigger the extension processing circuitry 64 to save data from the array register ZA to the location identified in xl7. Figure 7 schematically illustrates a variant of the delegation instruction 71 used to delegate a task to the extension processing circuitry 74 according to some configurations of the present techniques. This variant of the XSTART instruction 71 will instruct the extension processing circuitry to save eight consecutive vector registers that are used as part of the array processing operations. The delegation instruction 71 takes the form: XSTART x9 {z0-z7} xl7 #imm_save. The XSTART instruction 71, when decoded by the decoder circuitry 72, will trigger the saving of the vector registers z0-z7 with a base pointer in xl7 to identify the location to which the array will be saved. The content of the vector registers z0-z7 and the register xl7 is retrieved and passed from the registers 73 to the extension processing circuitry 74. The immediate field #imm_save indicates the type of operation being performed by the extension processing circuitry (for example, if the extension processing circuitry is configured to perform multiple different types of operation) and #imm_save (or signals based on the immediate value #imm_save) is passed from the decoder circuitry 72 to the extension processing circuitry 74 to trigger the extension processing circuitry 74 to save data from the array register Z A to the location identified inxl7. The extension processing circuitry 74 responds to the trigger and returns a handle or request ID in x9 from the extension processing circuitry 74 to the registers 73. The extension processing circuitry 74 then performs saving of data from the vector registers z0-z7 to the location identified by base pointer xl7. Figure 8 schematically illustrates a further variant of the delegation instruction 81 used to delegate a task to the extension processing circuitry 84 according to some configurations of the present techniques. This variant of the XSTART instruction 81 takes the same form as the XSTART instruction 61 described in relation to figure 6. However, the immediate variable #imm_load indicates that the extension processing circuitry 84 is to perform a load operation to load data into the array registers. The XSTART instruction takes the form: XSTART x9 {ZA} {p0-p4} xl7 #imm_load. The XSTART instruction 81, when decoded by decoder circuitry 82 will trigger the loading of data into the ZA array register using predicates pO to p4 with a base pointer in xl7 to identify the location from which the data will be loaded. The content of the predicate registers pO to p4, and the register xl7 is retrieved and passed from the registers 83 to the extension processing circuitry 84. The XSTART instruction returns a handle or request ID in x9 from the extension processing circuitry 84 to the registers 83 along with the content of the array register ZA that has been loaded. The request ID could be used, for example, by the corresponding synchronisation instruction later on. The immediate field #imm_load indicates the type of operation being performed by the extension processing circuitry (for example, if the extension processing circuitry is configured to perform multiple different types of operation) and #imm_load (or signals based on the immediate value #imm_load) is passed from the decoder circuitry 82 to the extension processing circuitry 84 to trigger the extension processing circuitry to load data from the location identified in xl7 into the array register ZA. Figure 9 schematically illustrates a further variant of the delegation instruction 81 used to delegate a task to the extension processing circuitry 94 according to some configurations of the present techniques. This variant of the XSTART instruction 91 takes the same form as the XSTART instruction 71 described in relation to figure 7. However, the immediate variable #imm_load indicates that the extension processing circuitry 94 is to perform a load operation to load data into the array registers. This variant of the XSTART instruction 91 will instruct the extension processing circuitry to load eight consecutive vector registers that are used as part of the array processing operations. The delegation instruction 91 takes the form: XSTART x9 {z0-z7} xl7 #imm_load. The XSTART instruction 91, when decoded by the decoder circuitry 92, will trigger the loading of data into the vector registers z0-z7 with a base pointer in xl7 to identify the location from which the data will be loaded. The content of the register xl7 is retrieved and passed from the registers 93 to the extension processing circuitry 94. The immediate field #imm_load indicates the type of operation being performed by the extension processing circuitry (for example, if the extension processing circuitry is configured to perform multiple different types of operation) and #imm_load (or signals based on the immediate value #imm_load) is passed from the decoder circuitry 92 to the extension processing circuitry 94 to trigger the extension processing circuitry to load data from the location identified in xl7 into the vector registers z0-z7. The extension processing circuitry 94 responds to the trigger and returns a handle or request ID in x9 from the extension processing circuitry 94 to the registers 93. The extension processing circuitry 94 then performs loading of data from the location identified by base pointer xl7 and returns the content of the vector registers z0-z7 to the registers 93. Figure 10 schematically illustrates an extension synchronisation instruction 101 according to some configurations of the present techniques. The extension synchronisation instruction takes the form: XSYNC x9. When decoded by the decoder circuitry 102, the synchronisation instruction 101 causes the content of register x9 to be passed from the registers 103 to the extension processing circuitry 104. The synchronisation instruction 101 triggers the decoder circuitry 102 to initiate a check of whether the delegated task having a request ID matching the contents of the register x9 has completed and will cause instructions subsequent to the synchronisation instruction to wait until the extension processing circuitry indicates that its delegated task has been completed. In some configurations the above delegation instructions can be predicated or unpredicated instructions. Furthermore, in some configurations the synchronisation instruction may be blocking (i.e., will cause instructions subsequent to the synchronisation instruction to wait until the delegated task has completed) or nonblocking (i.e., will not cause instructions subsequent to the synchronisation instruction to wait for the delegate task to complete). The non-blocking instruction may trigger the extension processing circuitry to set a status flag in a register accessible to the data processing circuitry, the status flag indicating whether or not the extension processing circuitry has completed the delegated task. In such configurations the decoder circuitry may be responsive to at least one type of branch instruction where an outcome of the branch instruction (i.e., whether the branch is taken or not taken) is dependent on the status flag. The following example illustrates a potential use case for the delegation instructions and synchronisation instructions described in the above figures. The potential use case considers the use of matrix processing circuitry to perform a sequence of matrix operations in which data is loaded into registers, an outer product operation is performed, and the results are stored. The following assembly code illustrates a possible way this could be implemented (using the Arm A-profile A64 Instruction Set Architecture using SME and SVE instructions) without using the delegation instructions: / / Load LHS columns Idlw { z4.s}, pO / Z [xl6] Idlw { z5.s}, pl / Z [xl6, #1, MUL VL] / / Load RHS rows Idlw { z6.s}, p4 / Z [xl5] Idlw { z7.s}, p5 / Z [xl5, #1, MUL VL] / / Perform outer products fmopa zaO.s, pO / M, p4 / M, z4.s, z6.s fmopa zal.s, pO / M, p5 / M, z4.s, z7.s fmopa za2.s, pl / M, p4 / M, z5.s, z6.s fmopa za3.s, pl / M, p5 / M, z5.s, z7.s [••• ] / / Store ZA0-ZA3 rows (A) movwl2, #0 stlw { za0h.s[wl2, #0] }, pO, p4, [xl7, xzr, Isl #2] stlw { zalh.s[wl2, #0] }, pO, p5, [xl7, x2, Isl #2] stlw { za2h.s[wl2, #0] }, pl, p4, [xl7, x3, Isl #2] stlw { za3h.s[wl2, #0] }, pl, p5, [xl7, x4, Isl #2] (B) [...] The instruction Idlw, e.g., Idlw { z4.s}, pO / Z [xl6 #1 MUL VL] performs a continuous load of words into 32 bit elements of the register z4 according to the scalable predicate register pO, and xl6 is the base register (with an optional immediate offset #1). The instruction frnopa, e.g., fmopa zaO.s, pO / M, p4 / M, z4.s, z6.s performs a floating point outer product and accumulate operation indicating a portion of the array register zaO.s as the output of the instruction, predicates pO and p4, and source vector registers z4.s and z6.s. The instruction stlw, e.g., stlw { za0h.s[wl2, #0] }, pO, p4, [xl7, xzr, Isl #2] performs a contiguous store of words from zaO with wl2 and the offset #0 indicating the slice index register and offset respectively, predicates pO and p4, and the base register and offset xl6 and #1. The precise format and syntax of the instructions is provided for illustrative purpose only and it will be readily apparent to the person skilled in the art that different instructions could be provided using a different instruction set architecture. In the above code sequence, the steps are each performed sequentially with data first being loaded, then subsequent to the data being loaded, the outer products are performed. Once the outer products have been performed, the data is stored before the variables are updated. As a result of the above sequence of code, the data processing circuitry spends a lot of time loading data and storing data and less of its time performing outer products. As a results, the data processing circuitry, which may include a number of optimised units for performing the outer products, spends some of its time not utilising these optimised units and, instead, performing load and store operations which could be delegated. Using the above delegation instructions and the above synchronisation instructions, the storage portion of the code (from line (A) to line (B) in the above code segment) could be rewritten as: / / store ZA0-ZA3 rows XSYNC x9, { za }, #imm_save XSTART x9, {za}, { pO - p4 }, xl7, #imm save [••• ] The XSYNC instruction causes the code to wait until a previous delegated task is finished. The first time that this instruction is encountered in the code (i.e., before any delegated tasks have been triggered), the data processing circuitry will query whether the extension processing circuitry is ready and the extension processing circuitry will indicate its readiness in response to the query. In subsequent iterations of the code, i.e., once a delegated task has been triggered, the XSYNC instruction will cause processing to pause until the delegated task is complete. For use cases in which the delegated task takes less time that the loading of data and the matrix operations, the XSYNC operation will effectively behave as a no-op. For use cases in which the offloading of data takes a larger amount of time than the loading of data and the matrix operations, the XSYNC operation will prevent the data processing circuitry from preceding with the next iteration before the offloading is complete. The XSTART operation causes the data processing circuitry to trigger a delegated task to offload the data. The extension processing circuitry is responsive to the trigger to cause the data stored in ZA0-ZA3 of the array register to be offloaded as described above. The offloading by the extension processing circuitry is, once triggered, performed asynchronously to the continued processing by the data processing circuitry and can therefore be performed in parallel by the extension processing circuitry without further input from the data processing circuitry. The use of the delegation instruction and the synchronisation instruction therefore allows the apparatus to improve the utilisation of the data processing circuitry and, hence, improve overall throughput. Figure 11 schematically illustrates an apparatus 110 according to some configurations of the present techniques. The apparatus is provided with extension processing circuitry 123 coupled to memory 124. The extension processing circuitry 123 is arranged to interact with data processing circuitry that is configured to perform array processing operations. The data processing circuitry comprises matrix multiplication circuitry 111 and vector processing circuitry 117. The data processing circuitry is provided with vector registers 119, a first physical array register 113 and a second physical array register 116. The apparatus is also provided with output data transfer channel 115 and multiplexing circuitry 114. The multiplexing circuitry 114 is configured to select between the first physical array register 113 and the second physical array register 116 and to couple the data from the selected physical array register to the output data transfer channel 115. The data processing circuitry is also provided with multiplexing circuitry 125 coupled between each of the first physical array register 113 and the second physical array register 116, and the matrix multiplication circuitry 111. The apparatus 110 is further provided with an input data channel 120 coupled between the extension processing circuitry 123 and first input multiplexing circuitry 112. The first input multiplexing circuitry 112 determines whether the input to the first physical array is provided from the matrix multiplication circuitry 111 or the extension processing circuitry 123. The input data channel 120 is also coupled between the extension processing circuitry 123 and second input multiplexing circuitry 126. The second input multiplexing circuitry 126 determines whether the input to the second physical array is provided from the matrix multiplication circuitry 111 or the extension processing circuitry 123. During a delegated task in which the extension processing circuitry 123 loads the data into or offloads the data from one of the array registers, the matrix multiplication circuitry 111 may make use of one physical array register, e.g., the first physical array register 113 for writing whilst the extension processing circuitry 123 makes use of the other physical array register, the second physical array register 116 in this example, for offloading. In such a situation, the multiplexing circuitry 114 couples the second physical array register 116 to the extension processing circuitry 123 via the output channel 115, and the second input multiplexing circuitry 126 couples the input data channel 120 to the second physical array register 116. At the same time, the matrix multiplication circuitry Illis coupled to the first physical array register 113 via the first input multiplexing circuitry 112 and the multiplexing circuitry 125. The coupling of the physical array registers is performed using array register renaming circuitry (not illustrated) and is controlled at the micro-architectural level without the knowledge of the programmer or compiler. The matrix multiplication circuitry 111 therefore sees a single array register which is provided in hardware by the first physical array register. Simultaneously, the extension processing circuitry 123 sees a single array register which is provided in hardware by the second physical array register 116. As a result, the extension processing circuitry 123 is able to either load data into the array register, or offload data from the array register whilst the matrix multiplication circuitry Illis performing one or more matrix processing operations on an alternative set of data. Subsequently, the first physical array register 113 and the second physical array register 116 may be switched using the multiplexing circuitry 125, the multiplexing circuitry 114, the first input multiplexing circuitry 112 and the second input multiplexing circuitry 126. Similarly, the vector processing circuitry 117 is coupled to the vector registers 119 via the vector multiplexing circuitry 118. The vector registers are also coupled to the extension processing circuitry 123 via the vector output channel 121 and the vector input channel 122. During a delegated task, the extension processing circuitry 123 may offload data from the vector registers 119 via the vector output channel 121 and may load data into the vector registers via the vector input channel 122. The vector multiplexing circuity 118 is provided to switch the input into the vector registers 119 according to whether data is being loaded into the vector registers 119 by the vector processing circuitry 117 or the extension processing circuitry 123. Figure 12 schematically illustrates an example use case of the extension processing circuitry to perform a delegated task. Flow begins at step S120 where a variable i is set to zero. Flow then proceeds to step S121 where the data processing circuitry loads operands into vectors for the i-th iteration of a loop. Flow then proceeds to step S122 where a matrix processing operation is performed using the operands loaded into the vectors. The output is then accumulated into the array register ZA. Flow then proceeds to step S123 where an extension synchronisation operation is executed to determine if the extension processing circuitry is ready (i.e., if it has completed any preceding delegated tasks). If, at step S123, it is determined that the extension processing circuitry is not ready, then flow remains at step S123. If, at step S123, it is determined that the extension processing circuitry is ready, then flow proceeds to step S124. At step S124 the extension processing circuitry is triggered, through execution of a delegation instruction, to offload the data that was accumulated in iteration i. Flow then proceeds to step SI25 without waiting for the offloading of data to be completed. At step S125 it is determined if there are any further operations. If, at step S125, it is determined that there are further operations, then flow proceeds to step S126 where the variable i is incremented before flow returns to step S121. If, at step S125, it is determined that there are no further operations, then flow proceeds to step SI27 where the flow ends. Figure 13 schematically illustrates an example use case of the extension processing circuitry to perform a delegated task. Flow begins at step SI30 where a variable i is set to zero. Flow then proceeds to step S131 where an initial set of vector operands are loaded for iteration i=0. The initial loading of the first set of operands may be performed by the data processing circuitry or the extension processing circuitry. Flow then proceeds to step SI32 where it is determined if the extension processing circuitry is ready (i.e., if it has completed any preceding delegated tasks). If, at step SI32, it is determined that the extension processing circuitry is not ready, then flow remains at step SI32. If, at step SI32, it is determined that the extension processing circuitry is ready, then flow proceeds to step S133. At step S133 the extension processing circuitry is triggered, through execution of a delegation instruction, to load data for iteration i+1 into the vector registers. Flow then proceeds to step S134 without waiting for the loading of data to be completed. At step SI34 the data processing circuitry performs matrix processing operations for iteration i and accumulates the results of the matrix processing operations into the array register ZA. Flow then proceeds to step S135 where the data processing circuitry offloads the data from ZA for loop iteration i. Once the offload is complete, flow then proceeds to step SI36 where it is determined if there are any further operations. If, at step S136, it is determined that there are further operations, then flow proceeds to step S137 where i is incremented before flow returns to step S132. If, at step S136, it is determined that there are no further operations, then flow proceeds to step S138 where the flow ends. It will be readily apparent to the skilled person that, in some alternative use cases, both the offloading and the loading of data could be delegated to the extension processing circuitry. Alternatively, the loading and / or offloading may be performed by the data processing circuitry and the matrix multiplication operations may be performed by the extension processing circuitry. Figure 14 schematically illustrates the timing of load operations 140, matrix operations 141 and store operations 142. In the illustrated configuration, the load operations 140 and the store operations 142 are delegated to extension processing circuitry. The matrix operations 141 are performed by the data processing circuitry. Because the load operations 140 and the store operations 142 are delegated, these operations are performed in parallel to the matrix operation. In particular, load operation 140(2) to load data for iteration i=2 is performed in parallel with the matrix operations 141(1) for iteration i=l. Subsequently, when the matrix operations 141(1) are complete, the load operations 140(3) for iteration i=3 and the store operation 142(1) for iteration i=l are performed by one or more instances of extension processing circuitry in parallel with the matrix operations 141(2) for iteration i=2. Subsequently, when the matrix operations 141(2) are complete, the load operations 140(4) for iteration i=4 and the store operation 142(2) for iteration i=2 are performed by one or more instances of extension processing circuitry in parallel with the matrix operations 141(3) for iteration i=3. In this way, the data processing circuitry is able to spend a greater portion of time performing data processing with the loading and offloading operations being delegated to the extension processing circuitry. Figure 15 schematically illustrates a sequence of steps carried out by an apparatus according to some configurations of the present techniques. Flow begins at step SI50 where instructions are received and decoded to generate control signals. The control signals control the operation of the data processing circuitry and, in response to receipt of an appropriate instruction, control the triggering of the extension processing circuitry. Flow then proceeds to step S151 where it is determined if a delegation instruction has been received. If, at step S151 it is determined that a delegation instruction has been received, then flow proceeds to step SI52 where the extension processing circuitry is triggered to perform a delegated task comprising one or more operations associated with array processing operations. Flow then returns to step SI50. If, at step SI51, it was determined that a delegation instruction had not been received, then flow proceeds to step SI53 where processing operations are performed by the data processing circuitry according to the instructions that have been received. Flow then returns to step SI50. Figure 16 illustrates a simulator implementation that may be used. Whilst the earlier described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques concerned, it is also possible to provide an instruction execution environment in accordance with the embodiments described herein which is implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software based implementation of a hardware architecture. Varieties of simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 730, optionally running a host operating system 720, supporting the simulator program 710. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple distinct instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations which execute at a reasonable speed, but such an approach may be justified in certain circumstances, such as when there is a desire to run code native to another processor for compatibility or re-use reasons. For example, the simulator implementation may provide an instruction execution environment with additional functionality which is not supported by the host processor hardware, or provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, Pages 53 - 63. To the extent that embodiments have previously been described with reference to particular hardware constructs or features, in a simulated embodiment, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuitry may be implemented in a simulated embodiment as computer program logic. Similarly, memory hardware, such as a register or cache, may be implemented in a simulated embodiment as a software data structure. In arrangements where one or more of the hardware elements referenced in the previously described embodiments are present on the host hardware (for example, host processor 730), some simulated embodiments may make use of the host hardware, where suitable. The simulator program 710 may be stored on a computer-readable storage medium (which may be a non-transitory medium), and provides a program interface (instruction execution environment) to the target code 700 (which may include applications, operating systems and a hypervisor) which is the same as the interface of the hardware architecture being modelled by the simulator program 710. Thus, the program instructions of the target code 700 may be executed from within the instruction execution environment using the simulator program 710, so that a host computer 730 which does not actually have the hardware features of the apparatus 1 discussed above can emulate these features. In particular, the simulator code 710 comprises data processing program logic 712, extension processing program logic 715 and a plurality of data structures 716 including at least one array data structure. The data processing program logic is provided with decoder program logic 714 that is responsive to receipt of one or more instructions of a sequence of instructions specifying the at least one array data structure in the data structures 716 to control the data processing program logic 712 to perform array processing operations in relation to the at least one array data structure. The decoder program logic 714 is responsive to receipt of a delegation instruction to trigger the extension processing program logic 715 to perform, as a delegated task, one or more operations associated with one of the array processing operations. In brief overall summary there is provided an apparatus, a method, and a computer program. The apparatus comprises a plurality of registers to store data, the plurality of registers comprising at least one array register. The apparatus comprises data processing circuitry for processing a sequence of instructions. The data processing circuitry comprises decoder circuitry responsive to receipt of one or more instructions specifying the at least one array register to control the data processing circuitry to perform array processing operations in relation to the at least one array register. The apparatus comprises extension processing circuitry responsive to identification, by the data processing circuitry, of a delegated task to perform the delegated task asynchronously to the data processing circuitry. The decoder circuitry is responsive to a delegation instruction to trigger the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations. In the present application, the words “configured to...” are used to mean that an element of an apparatus has a configuration able to carry out the defined operation. In this context, a “configuration” means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware which provides the defined operation, or a processor or other processing device may be programmed to perform the function. “Configured to” does not imply that the apparatus element needs to be changed in any way in order to provide the defined operation. In the present application, lists of features preceded with the phrase “at least one of’ mean that any one or more of those features can be provided either individually or in combination. For example, “at least one of [A], [B] and [C]” encompasses any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), A and B in combination (without C), A and C in combination (without B), B and C in combination (without A), or A, B and C in combination. Although illustrative configurations of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise configurations, and that various changes, additions and modifications can be effected therein by one skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims could be made with the features of the independent claims without departing from the scope of the present invention.

Claims

1. An apparatus comprising:a plurality of registers configured to store data, the plurality of registers comprising at least one array register;data processing circuitry for processing a sequence of instructions, wherein the data processing circuitry comprises decoder circuitry responsive to receipt of one or more instructions of the sequence of instructions specifying the at least one array register to control the data processing circuitry to perform array processing operations in relation to the at least one array register; andextension processing circuitry associated with the data processing circuitry and responsive to identification, by the data processing circuitry, of a delegated task to perform the delegated task asynchronously to the data processing circuitry,wherein the decoder circuitry is responsive to a delegation instruction to trigger the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations.

2. The apparatus of claim 1, wherein the extension processing circuitry is configured to perform, as one of the one or more operations, one or more pre-processing operations to prepare one or more data elements for one of the array processing operations.

3. The apparatus of claim 2, wherein the one or more pre-processing operations comprise loading data from a memory system into at least one target register of the plurality of registers.

4. The apparatus of any preceding claim, wherein the extension processing circuitry is configured to perform, as one of the one or more operations, a post-processing operation to offload data generated by one of the array processing operations.

5. The apparatus of claim 4, wherein the one or more post-processing operations comprise storing data from at least one target register of the plurality of registers to a memory system.

6. The apparatus of claim 3 or claim 5, wherein the target register is the array register.

7. The apparatus of any preceding claim, wherein the delegation instruction specifies one or more specified registers of the plurality of registers, and the decoder circuitry is responsive to the array processing instruction to indicate the one or more specified registers to the extension processing circuitry.

8. The apparatus of claim 7, wherein the one or more specified registers comprises the array register.

9. The apparatus of any preceding claim, wherein the decoder circuitry is responsive to an extension synchronisation instruction to determine whether the extension processing circuitry has completed the delegated task.

10. The apparatus of claim 9, wherein the decoder circuitry is responsive to the extension synchronisation instruction to control the extension processing circuitry to pass at least one result data value to at least one result register of the plurality of registers when the extension processing circuitry has completed the delegated task.

11. The apparatus of claim 9 or claim 10, wherein the data processing circuitry is responsive to a determination that the extension processing circuitry has not completed the delegated task to set at least one incomplete condition flag in a condition register of the set of registers.

12. The apparatus as claimed in claim 11, wherein the data processing circuitry is responsive to the at least one incomplete condition flag being set to divert from the received sequence of instructions to retrieve an alternative set of instructions and toperform a further set of data processing operations in dependence on the alternative set of instructions.

13. The apparatus of any preceding claim, wherein:the data processing circuitry comprises a data processing pipeline and matrix processing circuitry, wherein the matrix processing circuitry is configured to perform the array processing operations in relation to the at least one array register.

14. The apparatus of claim 13, wherein:the data processing pipeline is one of a plurality of data processing pipelines configured to interact with the matrix processing circuitry; andthe extension processing circuitry is one of a plurality of instances of extension processing circuitry, each instance of the extension processing circuitry coupled to a corresponding one of the data processing pipelines and configured to receive the identification of the delegated task to be performed by that instance of the extension processing circuitry from the corresponding one of the data processing pipelines.

15. The apparatus of any preceding claim, wherein the extension processing circuitry is configured to perform, as one of the one or more operations, a matrix processing operation accessing the at least one array register.

16. The apparatus of claim 15, wherein the matrix processing operation comprises reading data from the at least one array register.

17. The apparatus of claim 15 or claim 16, wherein the matrix processing operation comprises writing result data to the at least one array register.

18. The apparatus of any preceding claim, wherein the array register is a two dimensional array register storing data elements identified by coordinates in a first array direction and a second array direction.

19. The apparatus of any preceding claim, wherein the extension processing circuitry is capable of performing the one or more operations in parallel with the data processing circuitry performing the array processing operations.

20. The apparatus of any preceding claim, comprising:a plurality of physical array registers; andarray register renaming circuitry configured to map the at least one array register to one of the plurality of physical array registers,wherein the extension processing circuitry is configured to interact with one of the plurality of physical array registers other than the one of the plurality of physical array registers currently mapped to the at least one array register.

21. The apparatus of any preceding claim, comprising one or more data transfer channels coupled between the extension processing circuitry and the data processing circuitry configured to transfer data between the extension processing circuitry and the data processing circuitry when performing the delegated task.

22. The apparatus of any preceding claim, wherein the extension processing circuitry is configured to perform a plurality of different delegated tasks, and the decoder circuitry is configured to specify the delegated task to be performed from amongst the plurality of different delegated tasks.

23. The apparatus of claim 22, wherein the delegated task is specified in the delegation instruction.

24. A method of operating an apparatus comprising a plurality of registers configured to store data, the plurality of registers comprising at least one array register, the method comprising:with decoder circuitry, receiving a sequence of instructions, and in response to receipt of one or more instructions of the sequence of instructions specifying the at least one array register, performing array processing operations in relation to the at least one array register; andin response to identification of a delegated task by the data processing circuitry, causing extension processing circuitry associated with the data processing circuitry to perform the delegated task asynchronously to the data processing circuitry; andin response to a delegation instruction, triggering the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations.

25. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:a plurality of data structures configured to store data, the plurality of data structures comprising at least one array data structure;data processing program logic for processing a sequence of instructions, wherein the data processing program logic comprises decoder program logic responsive to receipt of one or more instructions of the sequence of instructions specifying the at least one array data structure to perform array processing operations in relation to the at least one array data structure; andextension processing program logic associated with the data processing program logic and responsive to identification, by the data processing program logic, of a delegated task to perform the delegated task asynchronously to the data processing program logic,wherein the decoder program logic is responsive to a delegation instruction to trigger the extension processing program logic to perform, as the delegated task, one or more operations associated with one of the array processing operations.

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