System for generating circuit layout

Abstract

To provide a system for generating circuit layouts with a new configuration.SOLUTION: A system for generating circuit layouts includes a storage part, a restriction data calculation part, and a layout data calculation part. The storage part has a function of storing circuit connection data and first restriction data. The circuit connection data relate to connection of transistors and capacitors in pixel circuits. The first restriction data include data for setting wiring intervals of transistors and capacitors and data for setting placement coordinates of transistors and capacitors. The restriction data calculation part has a function of generating second restriction data on the basis of the circuit connection data and the first restriction data and storing the second restriction data in the storage part. The second restriction data are data for setting transistors and capacitors specified in placement coordinates so as to be placed to be close thereto, The layout data calculation part generates layout data on the basis of the circuit connection data, the first restriction data and the second restriction data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a system for generating layout data relating to a circuit layout (circuit placement).

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] In the design of logic circuits for LSIs (Large Scale Integrated circuits), technologies for automatically generating circuit layouts, such as design automation tools, are becoming widespread. However, technologies for automatically generating layouts for analog circuits, such as pixel circuits in display devices, have not yet become widespread.

[0004] When determining the circuit layout of a pixel circuit, it is important to consider layout constraints, such as constraints to mitigate variations in characteristics caused by the transistor manufacturing process, and constraints to avoid signal delays due to parasitic wiring effects and capacitive coupling between nodes.

[0005] Patent Document 1 discloses a configuration for automating the design of a circuit layout of an analog circuit based on circuit layout constraints. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-155594 Summary of the Invention [Problem to be solved by the invention]

[0007] There are countless combinations of circuit layouts for the transistors and capacitors in the pixel circuit. By adding constraints to the circuit layout, data for the circuit layout of the transistors and capacitors in the pixel circuit can be generated with limited calculation processing.

[0008] On the other hand, the parasitic capacitance and signal noise of the wiring within the pixel circuit also vary depending on the circuit layout of the transistors and capacitors within the pixel circuit. The parasitic capacitance and signal noise of the wiring have a significant impact on display quality. Furthermore, pixel circuits must obtain an optimal solution that satisfies design requirements such as power consumption and signal delay within a limited area. Therefore, it is difficult to automatically generate layout data for pixel circuits and other components using computer-based processing. As a result, the current practice is to generate layout data for pixel circuits and other components manually, making use of past design experience.

[0009] An object of one embodiment of the present invention is to provide a circuit layout generation system that can reduce an influence on display quality.Another object of one embodiment of the present invention is to provide a circuit layout generation system that can shorten a design period.Another object of one embodiment of the present invention is to provide a circuit layout generation system that can reduce costs such as labor costs.Another object of one embodiment of the present invention is to provide a novel circuit layout generation system.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a circuit layout generation system having a memory unit, a constraint data calculation unit, and a layout data calculation unit, wherein the memory unit has a function of storing circuit connection data and first constraint data, the constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit, and the layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data.

[0012] One aspect of the present invention is a circuit layout generation system that includes a memory unit, a constraint data calculation unit, and a layout data calculation unit. The memory unit has a function of storing circuit connection data and first constraint data, where the circuit connection data is data related to the connections of transistors and capacitors in a pixel circuit and the first constraint data has data that sets the wiring spacing of the transistors and capacitors. The constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit. The second constraint data is data that sets transistors and capacitors connected to the same wiring to be placed close to each other. The layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data.

[0013] One aspect of the present invention is a circuit layout generation system comprising a memory unit, a constraint data calculation unit, and a layout data calculation unit, wherein the memory unit has a function of storing circuit connection data and first constraint data, the circuit connection data being data relating to the connections of transistors and capacitors in a pixel circuit, the first constraint data being data for setting the wiring spacing of the transistors and capacitors and data for setting the placement coordinates of the transistors and capacitors, the constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit, the second constraint data being data for setting the transistors and capacitors specified in the placement coordinates to be placed closely together, and the layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data.

[0014] In one aspect of the present invention, the pixel circuit is preferably a pixel circuit connected to a light emitting device.

[0015] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0016] One embodiment of the present invention can provide a circuit layout generation system that can reduce an influence on display quality. Another embodiment of the present invention can provide a circuit layout generation system that can shorten a design period. Another embodiment of the present invention can provide a circuit layout generation system that can reduce costs such as labor costs. Another embodiment of the present invention can provide a novel circuit layout generation system.

[0017] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a circuit layout generation system. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a circuit layout generation system. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a circuit layout generation system. [Figure 4] 4(A) and 4(B) are diagrams for explaining an example of the configuration of a circuit layout generation system. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a circuit layout generation system. [Figure 6] 6(A) and 6(B) are diagrams for explaining an example of the configuration of a circuit layout generation system. [Figure 7] 7(A) and 7(B) are diagrams for explaining an example of the configuration of a circuit layout generation system. [Figure 8] 8(A) and 8(B) are diagrams for explaining an example of the configuration of a circuit layout generation system. [Figure 9] 9(A) and 9(B) are diagrams for explaining an example of the configuration of a circuit layout generation system. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0020] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0021] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0022] Hereinafter, an embodiment of one aspect of the present invention will be described.

[0023] The circuit layout generation system according to one embodiment of the present invention can be applied to the generation of layout data of transistors, capacitors, etc. in a pixel circuit of a display device. The circuit layout generation system can also be referred to as a system for generating layout data of a pixel circuit.

[0024] FIG. 1 is a diagram showing an example of a hardware configuration capable of executing a circuit layout generation system according to an embodiment of the present invention.

[0025] The circuit layout generation system 100 includes an input section 10, an output section 20, a storage section 30, and a calculation section 40.

[0026] Examples of the input unit 10 include human interface devices such as a keyboard, mouse, or touch panel, cameras such as digital cameras and digital video cameras, scanners, and read-only external storage units such as CD-ROMs and DVD-ROMs. Alternatively, the input unit 10 may be configured to accept input via a communication line such as the Internet.

[0027] Examples of the output unit 20 include a display such as an EL display device or a liquid crystal display device, or may be configured to output via a communication line such as the Internet.

[0028] Examples of the storage unit 30 include a read only memory (ROM), a random access memory (RAM), a solid state drive (SSD), and a hard disk drive.

[0029] The storage unit 30 has a function of storing a plurality of data such as circuit connection data, constraint data, etc. For the sake of explanation below, Fig. 1 illustrates a storage area 31B for storing circuit connection data, and storage areas 31A and 31C for storing constraint data.

[0030] One example of the calculation unit 40 is a configuration including multiple calculation circuits such as CPUs or GPUs. The calculation unit 40 has a function capable of executing programs stored in the storage unit 30. The programs include a function for generating constraint data and a function for generating layout data. The function of the calculation unit 40 that executes the function for generating constraint data may be referred to as a constraint data calculation unit. The function of the calculation unit 40 that executes the function for generating layout data may be referred to as a layout data calculation unit.

[0031] 1, for the sake of explanation below, a constraint data calculation unit 41A is shown in which calculation unit 40 executes a program for generating new constraint data based on circuit connection data and constraint data. Also, for the sake of explanation below, a layout data calculation unit 41B is shown in which calculation unit 40 executes a program for generating pixel circuit layout data based on circuit connection data and multiple pieces of constraint data.

[0032] The circuit layout generation system 100 shown in FIG. 1 is configured to generate new constraint data in the calculation unit 40. This configuration makes it possible to reduce the amount of data related to constraint conditions stored in the storage unit 30. The new constraint data generated in the calculation unit 40 is data that excludes combinations that could result in inappropriate layout data. The new constraint data generated in the calculation unit 40 is generated based on circuit connection data and constraint data provided in advance by a designer, and is temporarily stored in the storage unit 30, after which it can be provided to the calculation unit 40. The newly generated constraint data can exclude combinations that could result in inappropriate layout data, thereby reducing the number of calculation trials required to generate optimized layout data.

[0033] Furthermore, in the circuit layout generation system 100 shown in FIG. 1, the calculation unit 40 can generate pixel circuit layout data based on circuit connection data and multiple constraint data. This allows for a shorter design period compared to creating pixel circuit layout data manually. It also reduces personnel costs. Furthermore, the number of layout data generation attempts can be increased, allowing for optimization of circuit performance.

[0034] A flowchart for generating circuit layout data for transistors, capacitors, etc. in a pixel circuit will be described below. First, a flowchart for explaining the overall processing executed by circuit layout generation system 100 will be described with reference to FIG.

[0035] Before generating the circuit layout, the designer (user) performs circuit design and verification (step S10). Circuit design and verification involves simulations to check whether the circuit operates correctly. In step S10, circuit design and verification is performed up to the placement of elements such as transistors and capacitors required for the pixel circuit, as well as wiring that provides signals to drive the elements. The pass / fail result of this circuit design and verification is determined in step S11 (PASS?).

[0036] Next, layout design is performed by the circuit layout generation system 100 (step S12). In step S12, layout data of pixel circuits including transistors, capacitors, etc. is generated, which can reduce the impact on display quality, shorten the design period, reduce costs such as labor costs, etc.

[0037] The layout data obtained in step S12 is subjected to circuit connection verification by the designer (step S13). The circuit connection verification verifies whether the circuit designed in step S10 and the layout data generated in step S12 represent the same circuit. The pass / fail of the circuit connection verification is determined in step S14 (PASS?).

[0038] The layout data that has undergone circuit connection verification in step S14 is then subjected to design rule verification by the designer (step S15). Design rule verification is carried out to confirm whether the layout data generated in step S12 satisfies the requirements for layout patterns (such as wiring width or spacing between wiring) that can be produced in the semiconductor manufacturing process, as determined by the PDK (Process Design Kit). The pass / fail decision of the design rule verification is made in step S16 (PASS?).

[0039] The layout data that has undergone design rule verification in step S16 is subjected to parasitic capacitance component extraction (step S17). Parasitic capacitance component extraction involves calculating circuit parameters that depend on the circuit layout (such as the resistance value of wiring or the capacitance value due to overlap between layout patterns) from the layout data generated in step S12.

[0040] The layout data from which the parasitic capacitance components have been extracted in step S17 is subjected to circuit performance verification by the designer (step S18). Circuit performance verification involves simulating a circuit including circuit parameters dependent on the circuit layout extracted in step S16, to confirm whether the circuit performance satisfies the design requirements sought by the designer. The pass / fail result of this circuit performance verification is determined in step S19 (PASS?).

[0041] Through the above steps, desired circuit layout data can be obtained.

[0042] Next, a detailed description will be given of a case where the circuit layout generation system of one embodiment of the present invention is applied to the layout design shown in step S12 of Fig. 2. Fig. 3A shows a flowchart illustrating a plurality of steps (subroutines) for generating layout data of transistors, capacitors, and the like in a pixel circuit.

[0043] First, the first constraint data (hereinafter referred to as the first constraint condition) stored in the storage area 31A of the storage unit 30 is read out and assigned (input) to the constraint data calculation unit 41A of the calculation unit 40 (step S20). Next, the circuit connection data stored in the storage area 31B of the storage unit 30 is read out and assigned (input) to the constraint data calculation unit 41A of the calculation unit 40 (step S21). The order of steps S20 and S21 may be reversed, or they may be performed simultaneously.

[0044] The first constraint refers to a constraint that is provided in advance by a designer. Examples include a condition (1D layout) that aligns the orientation of the source and drain of a semiconductor layer in a transistor and the orientation of the gate (back gate) and arranges them at equal intervals, a coordinate condition (wiring grid) that constrains the arrangement of each element, a condition for serial arrangement (arranging the source and drain in series) when arranging multiple transistors, a condition for parallel arrangement (arranging the source and drain in parallel) when arranging multiple transistors, and a condition related to the shape of a capacitive element. In other words, the wiring grid is a condition that divides the area where a pixel circuit is provided into multiple areas (e.g., a mesh shape) and restricts the coordinates for arranging elements. By applying the 1D layout and wiring grid, the electrical characteristics of each element can be stabilized in the generated pixel circuit layout data.

[0045] The circuit connection data corresponds to information such as a netlist. The netlist is data created by the designer during the circuit design in step S10. The netlist includes information such as the channel length and width of the transistor (transistor size), as well as connection information between terminals such as the transistor gate (back gate), source, drain, etc., and capacitor electrodes, etc. The initial information may also include information such as whether some transistors and capacitors are arranged close to each other or apart from each other. The netlist may also include information specifying the coordinates of some transistors and capacitors.

[0046] Next, second constraint data (hereinafter referred to as second constraint data) is generated based on the first constraint data and circuit connection data provided to the constraint data calculation unit 41A of the calculation unit 40 (step S22). Fig. 4(A) is a diagram schematically showing the flow of each data in steps S20 to S22. Fig. 4(A) illustrates how data D1 of the first constraint data and data D2 of the circuit connection data are provided to the constraint data calculation unit 41A of the calculation unit 40, which generates data D3 of the second constraint data and stores it in the memory area 31C of the memory unit 30.

[0047] The second constraint condition refers to a constraint condition generated by the constraint data calculation unit 41A of the calculation unit 40. For example, the second constraint condition refers to a constraint condition that refers to circuit connection data or the like and specifies coordinates for placing transistors or capacitors connected to the same wiring or terminal close to each other.

[0048] By generating second constraint conditions that take into account information about the circuit connection data in the constraint data calculation unit 41A of the calculation unit 40, the designer's circuit layout image can be incorporated when designing the circuit data, and combinations that may result in inappropriate layout data can be excluded, thereby reducing the number of trials required for optimization.

[0049] A pattern is generated based on the data D1 of the first constraint condition, the data D2 of the circuit connection data, and the data D3 of the second constraint condition generated in step S22 (step S23). If the generated pattern is normal, it is output as layout data to the output unit 20 or the like (step S24).

[0050] 3(B) shows a flowchart of the pattern generation subroutine shown in step S23. Element placement is performed by automatic placement (step S30), and it is determined whether the placement is normal or not (step S31). Next, wiring connections are performed by automatic wiring (step S32), and it is determined whether the connections are normal or not (step S33). If both the element placement and wiring connections are normal, the layout data is complete, and pattern generation is completed (step S34).

[0051] Element placement can be performed using a method based on a mechanical model, such as the cluster growth method. Alternatively, element placement for transistors and capacitors can be attempted using the Min-Cut method, pair exchange method, relaxation method, Steinberg method, etc. Furthermore, wiring connections can be attempted by applying the maze method, line search method, channel routing method, or genetic algorithm, etc.

[0052] 4B is a diagram showing a typical flow of data during the pattern generation shown in step S23. In FIG. 4B, data D1 of the first constraint condition, data D2 of the circuit connection data, and data D3 of the second constraint condition are provided to the layout data calculation unit 41B of the calculation unit 40, and the layout data L D is generated and output to the output unit 20 (thick arrow).

[0053] 5 to 9B show an example of designing a pixel circuit of a display device by using the circuit layout generation system of one embodiment of the present invention.

[0054] Fig. 5 shows a circuit diagram of a pixel circuit for driving a light-emitting element. Fig. 5 shows transistors M1 to M9, wirings G1 to G3, wirings SL, wirings AN, wirings ML, terminals PX, nodes N1 to N5, and a node GR. Note that the light-emitting element is omitted for the sake of simplicity.

[0055] The wirings G1 to G3 function as gate signal lines (scanning lines) that provide signals to control the on / off of the transistors M1 to M3, which function as switches. The wiring SL functions as a data signal line (source line or data line) that provides a data signal to the pixel circuit. The wiring AN functions as a current supply line for passing current to a light-emitting element connected to the pixel circuit. The terminal PX is a terminal to which a light-emitting element such as an organic EL is connected. The transistors M4 to M9 function as drive transistors for passing current to the light-emitting element based on a data signal. The wiring ML functions as an output line for externally measuring the current value of the drive transistor. The wiring ML also functions as a power supply line for setting the potential of the node GR or the terminal PX to a constant potential.

[0056] The circuit connection data corresponds to data that represents connections in the pixel circuit shown in Fig. 5. The data can be described as data such as SPICE (Simulation Program with Integrated Circuit Emphasis) data.

[0057] 5, information such as that the gate of transistor M1 is connected to wiring G1, one of the source or drain is connected to node GR, and the other of the source or drain is connected to wiring SL is described as SPICE data. Similarly, the connection between each transistor and wiring or node is described as SPICE data.

[0058] By adding blank lines to the SPICE data, it is possible to create data that separates wiring or transistors. Alternatively, data specifying the initial coordinates of any element can be provided.

[0059] The first constraint can be the distance between wires, the 1D layout, or the wiring grid. It is preferable not to impose constraints on global wiring, such as gate signal lines, data signal lines, current supply lines, or power supply lines, which have little impact on circuit performance. In other words, it is allowed for elements to be connected to any node on the global wiring.

[0060] Furthermore, a second constraint that constrains the arrangement of transistors can be set based on the above-described first constraint and circuit connection data. The second constraint in the example of the pixel circuit of Figure 5 is a condition for constraining the arrangement pattern of transistors M4 to M9 connected to nodes N1 to N5 and node GR.

[0061] When no position information is provided, the layout data derived from the first constraint, circuit connection data, and second constraint is weighted to determine placement. By using second constraints and other conditions, the range of element placement can be limited for optimization relative to the initial element position, allowing for automatic layout under local conditions. This reduces the number of combination patterns, enabling automatic layout within the element placement envisioned by the designer.

[0062] An example of the element placement and wiring placement can be performed as shown in the flowchart in Figure 6(A). For example, this can be expressed by steps S41 to S46, and in this case, layout data for providing four wiring layers on a semiconductor layer is obtained. That is, this is an example of determining the element placement and wiring placement of transistors M1 to M9 in a top-gate transistor.

[0063] Specifically, first, the area where the pixel circuits are to be arranged is divided into a mesh (step S41). Next, the semiconductor layers are arranged (step S42). Next, arrangement 1 of the wiring layer in the same layer as the gate electrode is performed (step S43). Next, arrangement 2 of the wiring layer in the same layer as the source electrode or drain electrode is performed (step S44). Next, arrangement 3 of the wiring layer is performed (step S45). Next, arrangement 4 of the wiring layer in the same layer as the pixel electrode is performed (step S46). Each of these steps is performed automatically by the circuit layout generation system 100.

[0064] The layers shown in steps S42 to S46 correspond to the conductive layers and semiconductor layers of the transistor in the cross-sectional view of FIG. 6B. For example, the semiconductor layer arranged in step S42 corresponds to the semiconductor layer P42 in the cross-sectional view of FIG. 6B. The wiring layer arranged in step S43 corresponds to the conductive layer P43 in the cross-sectional view of FIG. 6B. The wiring layer arranged in step S44 corresponds to the conductive layer P44 in the cross-sectional view of FIG. 6B. The wiring layer arranged in step S45 corresponds to the conductive layer P45 in the cross-sectional view of FIG. 6B. The wiring layer arranged in step S46 corresponds to the conductive layer P46 in the cross-sectional view of FIG. 6B.

[0065] The schematic diagrams of the arrangement of the conductive layers and semiconductor layers shown in Figures 7(A) to 9(B) correspond to steps S41 to S46. Note that the reference numerals in Figures 7(B) to 9(B) correspond to the reference numerals given to the wirings, nodes, etc. of the pixel circuit shown in Figure 5.

[0066] Fig. 7(A) shows an area divided into meshes in which the elements of the pixel circuit shown in Fig. 5 are arranged. By arranging elements in areas divided into meshes, it is possible to search for element arrangement and wiring paths by restricting the coordinates of the range in which elements are arranged for optimization relative to the initial position of the elements.

[0067] FIG. 7B shows the region in which the semiconductor layer P42 shown in FIG. 6B is arranged within the mesh-shaped region shown in FIG. 7A. As described above, one embodiment of the present invention is configured to generate new constraints from pre-specified constraints and circuit connection data, and generate layout data including these constraints. This reduces the pre-specified constraints and efficiently limits the conditions for generating layout data. Note that the number of divisions into the mesh-shaped region is preferably determined based on the spacing (design rules) between transistors and wiring. Dividing the region into a mesh-like region and determining the layout reduces unnecessary combinations in the automatically generated layout data, and enables the creation of many pixel circuit layout candidates.

[0068] Fig. 8(A) shows the area where the conductive layer P43 shown in Fig. 6(B) is arranged in the mesh-shaped area shown in Fig. 7(A). Note that in Fig. 8(A), the mesh-shaped area marked with an x ​​indicates an area where the conductive layer P43 is not arranged. Note that when another circuit is stacked below the pixel circuit, it is necessary to take into account parasitic components with the lower layer.

[0069] FIG. 8B shows the area in which the conductive layer P44 shown in FIG. 6B is arranged in the area divided into mesh shapes shown in FIG. 7A.

[0070] FIG. 9A shows the area where the conductive layer P45 shown in FIG. 6B is arranged in the mesh-shaped area shown in FIG. 7A. It is preferable that the capacitance provided in the overlapping area of ​​the wiring layers be as large as possible to stabilize the data potential for displaying an image and reduce parasitic components with nodes that experience potential fluctuations. Furthermore, the wiring (G1, G2, G3) has a large signal amplitude and has a significant impact on its surroundings. Therefore, it is preferable to impose a first constraint on the layout so as not to add parasitic capacitance to nodes that are sensitive to potential changes. Furthermore, it is necessary to reduce parasitic components in the wiring (G1, G2, G3) to suppress distortion of the gate signal. Furthermore, it is preferable to impose a first constraint on the node GR so that parasitic capacitance, etc., is reduced in order to maintain the potential.

[0071] 9(B) shows the area where the conductive layer P46 shown in FIG. 6(B) is arranged in the mesh-shaped area shown in FIG. 7(A). Since the wiring SL is used to supply data signals to each pixel circuit, it is preferable to impose a first constraint to reduce parasitic capacitance. The same is true for the wiring ML. On the other hand, since the wiring AN is used to supply a fixed potential, slight potential fluctuations do not affect display quality within the range in which the drive transistor operates in the saturation region.

[0072] When the schematic diagrams of the layout of the conductive and semiconductor layers shown in Figures 7(A) to 9(B) are created manually, there are many parameters that must be considered. Therefore, optimizing the layout data automatically using a circuit layout generation system, etc., allows for searching under more conditions and allows for optimization in a shorter time than when done manually.

[0073] As described above, in a circuit layout generation system according to one aspect of the present invention, the calculation unit is configured to generate new constraint data, thereby preventing the increase in data related to constraint conditions stored in the storage unit. The constraint data required to generate layout data can be appropriately modified based on the circuit connection data and constraint data and provided to the calculation unit. The newly generated constraint data incorporates the designer's circuit layout image at the time of generating the circuit connection data, and can also eliminate combinations that may result in inappropriate layouts. This reduces the number of trials required for optimization.

[0074] In addition, in the circuit layout generation system according to one embodiment of the present invention, the calculation unit can generate pixel circuit layout data based on circuit connection data and multiple constraint data. Therefore, compared to manually creating pixel circuit layout data, the design period can be shortened. Furthermore, personnel costs can be reduced. Furthermore, the number of attempts to generate layout data can be increased, thereby optimizing circuit performance.

[0075] <Additional notes regarding the present specification etc.> The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0076] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0077] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0078] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0079] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0080] In addition, in the block diagrams in this specification, components are classified by function and shown as independent blocks. However, in actual circuits, it is difficult to separate components by function, and there may be cases where a single circuit is involved in multiple functions, or where a single function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0081] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0082] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal or source (drain) electrode, etc., depending on the situation.

[0083] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0084] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0085] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0086] In this specification, a switch refers to a device that has the function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has the function of selecting and switching a path for a current to flow.

[0087] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0088] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0089] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0090] AN wiring GR node LD layout data ML wiring P42 Semiconductor layer P43 Conductive layer P44 conductive layer P45 Conductive layer P46 Conductive layer PX terminal SL wiring 10 Input section 20 Output section 30 Storage section 31A storage area 31B storage area 31C storage area 40 Arithmetic section 41A Constraint data calculation unit 41B Layout data calculation section 100 Generation System

Claims

1. A memory unit, a constraint data calculation unit, and a layout data calculation unit, and the memory unit has a function of storing circuit connection data and first constraint data, the constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit, a circuit layout generation system, wherein the layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data.

2. A memory unit, a constraint data calculation unit, and a layout data calculation unit, and the memory unit has a function of storing circuit connection data and first constraint data, the circuit connection data is data related to connections of transistors and capacitors included in a pixel circuit, the first constraint data has data for setting intervals between the transistors and the capacitors, the constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit, the second constraint data is data for setting the transistors and the capacitors connected to the same wiring to be arranged closely, a circuit layout generation system, wherein the layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data.

3. A memory unit, a constraint data calculation unit, and a layout data calculation unit, and the memory unit has a function of storing circuit connection data and first constraint data, the circuit connection data is data related to connections of transistors and capacitors included in a pixel circuit, the first constraint data has data for setting intervals between the transistors and the capacitors and data for setting arrangement coordinates of the transistors and the capacitors, the constraint data calculation unit has a function of generating second constraint data based on the circuit connection data and the first constraint data and storing the second constraint data in the memory unit, the second constraint data is data for setting the transistors and the capacitors specified by the arrangement coordinates to be arranged closely. The layout data calculation unit generates layout data based on the circuit connection data, the first constraint data, and the second constraint data, and is a circuit layout generation system.

4. In claim 2 or claim 3, The pixel circuit is a pixel circuit connected to a light-emitting element, and is a circuit layout generation system.

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