Interconnect singulation

Abstract

To provide a method for aligning interconnects, which includes trimming and forming a frame of strips, and an array of strips of interconnects.SOLUTION: A method includes: trimming and forming a frame of strips of interconnects; removing side rails from the frame of strips of interconnects to provide an array of strips of interconnects; aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects; and singulating the aligned array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects is adjacent to a strip of interconnects of the second set of strips of interconnects.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to interconnects for integrated circuit (IC) chips, and more particularly to singulating interconnects for IC chips. [Background technology]

[0002] An interconnect (alternatively called a leadframe) is a metal structure inside an integrated circuit (IC) chip package that carries signals from the die to the outside. The interconnect includes a die pad, on which the die is placed and surrounded by leads, and metal conductors that lead from the die to the external circuitry. The end of each lead closest to the die terminates in a bond pad. Small bond wires connect the die to each bond pad. A mechanical connection secures all these parts into a rigid structure, making the entire interconnect easy to handle automatically.

[0003] The die is glued or soldered to the die pad inside the interconnect, and then bond wires are attached between the die and the bond pad to connect the die to the leads. In a process called encapsulation, a plastic case is molded around the lead frame and die, leaving only the leads exposed. The leads are cut outside the plastic body, and any exposed support structure is cut away. The outer leads are then bent (formed) to the desired shape. In various examples, the interconnect is used to produce a quad flat no-lead package (QFN), a quad flat package (QFP), or a dual in-line package (DIP). Summary of the Invention

[0004] A first example relates to a method for aligning interconnects, including trimming and forming an interconnect strip frame. The interconnect strip frame includes interdigitated pins. The method further includes removing side rails from the interconnect strip frame to provide an array of interconnect strips. The method includes aligning a first set of interconnect strips in an array of interconnect strips such that pins of the first set of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips. To provide the aligned array of interconnect strips, interconnect strips of the first set of interconnect strips are adjacent to interconnect strips of the second set of interconnect strips. The method further includes singulating the aligned array of interconnect strips to provide interconnects for integrated circuit (IC) chip dies.

[0005] A second example relates to an array of interconnect strips including a first set of interconnect strips in the array of interconnect strips and a second set of interconnect strips in the array of interconnect strips, wherein the interconnect strips in the first set of interconnect strips have a first distance between an edge of each interconnect in the first strip of interconnects and a pin closest to the edge of each interconnect in the first strip of interconnects, and the interconnect strips in the second set of interconnect strips are adjacent to the interconnect strips in the first set of interconnect strips, and the interconnect strips in the second set of interconnect strips have a second distance between an edge of each interconnect in the second set of interconnect strips and a pin closest to the edge of each interconnect in the second set of interconnect strips, the first distance being different from the second distance, and wherein the pins in the first set of interconnect strips in the array of interconnect strips are interleaved with the pins in the second set of interconnect strips in the array of interconnect strips. [Brief explanation of the drawings]

[0006] [Figure 1] 1 shows a flowchart of an exemplary method for singulating interconnects from a frame of strips of interconnects.

[0007] [Figure 2] 1 illustrates a first step in an exemplary method for singulating interconnects from a frame of strips of interconnects.

[0008] [Figure 3] 1 shows a first step of an exemplary method for singulating interconnects from a frame of interconnect strips, where the interconnect strips are made transparent.

[0009] [Figure 4] 1 illustrates a second stage of an exemplary method for singulating interconnects from a frame of strips of interconnects, where pins are trimmed and formed.

[0010] [Figure 5] 10 illustrates a third step in an exemplary method for singulating interconnects from a frame of strips of interconnects, in which the side rails are removed by cutting.

[0011] [Figure 6] 10 illustrates a third stage of an exemplary method for singulating interconnects from a frame of strips of interconnects, with the side rails removed.

[0012] [Figure 7] 1 shows a close-up view of the proximity strip of interconnects.

[0013] [Figure 8] 1 illustrates a fourth step of an exemplary method for singulating interconnects from a frame of interconnect strips, with an array of interconnect strips resting on a sawing chuck table.

[0014] [Figure 9] 10 illustrates a fifth step of an exemplary method for singulating interconnects from a frame of interconnect strips, in which a pick and place (PnP) head engages a set of interconnect strips.

[0015] [Figure 10] 10 illustrates a sixth step in an exemplary method for singulating interconnects from a frame of interconnect strips, in which a PnP head lifts a set of interconnect strips.

[0016] [Figure 11] 10 illustrates a seventh step of an exemplary method for singulating interconnects from a frame of interconnect strips, in which the interconnect strips are moved into position over an imager.

[0017] [Figure 12] 10 illustrates an eighth step of an exemplary method for singulating interconnects from a frame of interconnect strips, in which the interconnect strips are moved to align pins on the interconnect strips.

[0018] [Figure 13] 10 illustrates a ninth step of an exemplary method for singulating interconnects from a frame of interconnect strips, in which the interconnect strips are moved to align pins on the interconnect strips.

[0019] [Figure 14] 10 illustrates a tenth step of an exemplary method for singulating interconnects from a frame of interconnect strips, with the PnP head lowering the set of interconnect strips onto the sawing chuck table.

[0020] [Figure 15] 10 shows an alternative frame for strips of interconnects for singulation.

[0021] [Figure 16] 1 shows an example of a singulated interconnect.

[0022] [Figure 17] 10 illustrates first and second steps of another exemplary method for singulating interconnects from a strip of interconnects.

[0023] [Figure 18] 10 illustrates third and fourth steps of another exemplary method for singulating interconnects from a strip of interconnects. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present description relates to a method for singulating interconnects (e.g., lead frames) from a frame of interconnect strips. The frame includes a strip of interconnects held together with sidewalls, i.e., a first sidewall and a second sidewall formed of plastic. The strip of interconnects within the frame are coupled with interdigitated pins. In some examples, the strip of interconnects is a high density interconnect (HyDE) strip.

[0025] The pins of the interconnect strips are trimmed and formed. Trimming and forming the pins involves removing material (e.g., plastic and / or metal) holding the interdigitated pins together and bending (forming) the pins into the desired shape. The side rails are cut from the interconnect strip frame to provide the array of interconnect strips. Cutting the side rails involves making two parallel transverse cuts across the interconnect strips to release the interconnect strips from the sidewalls. The array of interconnect strips includes a first set of interconnect strips having pins offset from pins of a second set of interconnect strips. Members of the first set of interconnect strips are adjacent to members of the second set of interconnect strips to provide the array of interconnect strips. Due to the initial state of the interdigitated pins in the interconnect strip frame, trimming and forming the pins leaves the pins still offset from one another.

[0026] Thus, the first set of interconnect strips is moved to align the pins of the first strip of interconnects with the pins of the second set of interconnect strips to provide an array of aligned strips of interconnects. To align the pins of the first set of interconnect strips with the pins of the second set of interconnect strips, the first set of interconnect strips is moved from the sawing chuck table to a position where an image of each of the interconnect strips is captured to identify an offset between the pins of each of the first set of interconnect strips and the pins of the second set of interconnect strips. Each of the interconnect strips is moved by this offset and returned to the sawing chuck table. By moving each of the interconnect strips in the first set in this manner, an aligned array of interconnect strips is provided.

[0027] The aligned array of interconnect strips is singulated to provide interconnects for integrated circuit (IC) chip dies. Singulating the aligned array of interconnect strips involves making multiple parallel cross cuts across both the first and second sets of interconnect strips. Using the described method, the need for mechanical features in the side rails (U-bars and / or S-bars) is eliminated. Instead, an image of each interconnect strip in the first set of interconnects is captured, an offset is measured, and this offset is used to move the interconnect strip to align the pins.

[0028] FIG. 1 shows a flowchart of an example method 100 for singulating interconnects (e.g., lead frames) from a frame of interconnect strips. In some examples, the interconnect strips are high density interconnect (HyDE) strips. The interconnect strips within the frame are held together with sidewalls. The interconnect strips are coupled with interdigitated pins. At 105, the pins on the interconnect strips are trimmed and formed. Trimming and forming the pins includes removing material (e.g., plastic and / or metal) that holds the interdigitated pins together and curving (forming) the pins. At 110, side rails are removed from the frame of interconnect strips to provide an array of interconnect strips by cutting. Cutting the side rails includes making two transverse cuts across the first set of interconnect strips and the second set of interconnect strips, the transverse cuts being made adjacent to each edge of the interconnect strips.

[0029] The array of interconnect strips includes a first set of interconnect strips having pins offset from the pins of the second set of interconnect strips. Members of the first set of interconnect strips are adjacent to members of the second set of interconnect strips to provide a aligned array of interconnect strips. Due to the initial state of the interdigitated pins in the interconnect strip frame, trimming and forming of the pins leaves the pins still offset from one another. In particular, in one example, a first pin of the first set of interconnect strips is closer to the edge cut (at 105) to separate the side rail from the interconnect strips than a first pin on the second set of interconnect strips. In other words, there is a first distance between the edge and the first pin of the first set of interconnect strips and a second distance between the edge and the first pin of the second interconnect strip, the first distance and the second distance being different.

[0030] At 115, the interconnect strips (both the first and second sets) are inverted and placed on the sawing chuck table. At 120, the pins of the first set of interconnect strips in the array of interconnect strips are aligned (moved) so that the pins of the first set of interconnect strips are aligned with the pins of the second set of interconnect strips in the array of interconnect strips. To align the first set of interconnect strips, a pick-and-place (PnP) head lifts each interconnect strip in the first set from the sawing chuck table and moves them to a position where an image of each respective interconnect strip in the first set is captured. The captured image is inspected to measure the offset between the pins on the first set of interconnect strips and the interconnect strips of the second set. In response to determining the offset, the interconnect strips in the first set are moved by the offset and returned to the sawing chuck table to form an aligned array of interconnect strips.

[0031] At 125, the aligned array of interconnect strips is singulated to provide interconnects for integrated circuit (IC) chip dies. Singulating the aligned array of interconnect strips includes making multiple parallel cross cuts across both the first and second set of interconnect strips. Using method 100, the need for mechanical features in the side rails (U-bars and / or S-bars) is eliminated. Instead, an image of each interconnect strip in the first set of interconnects is captured, an offset is measured, and this offset is used to move the interconnect strip to align the pins.

[0032] Figures 2-14 show stages in a method for singulating interconnects (e.g., lead frames) from a frame of strips of interconnects. For ease of explanation, Figures 2-14 use the same reference numerals to indicate the same structures.

[0033] As shown in FIG. 2, in a first step at 200, an interconnect strip frame 300 is provided. The interconnect strip includes a first set of interconnect strips 304 and a second set of interconnect strips 306. The first set of interconnect strips 304 and the second set of interconnect strips 306 are offset from one another. The interconnect strips of the frame 300 (including the first set of interconnect strips 304 and the second set of interconnect strips 306) are high density (HyDe) interconnect strips. The frame 300 includes a first side rail 308 and a second side rail 312 attached to opposite edges of the first set of interconnects 304 and the second set of interconnect strips 306. The first set of interconnects 304 and the second set of interconnect strips 306 are formed from a bar of plastic (or other molding material) that circumscribes the individual interconnects for a die to form an integrated IC chip. FIG. 3 illustrates a frame 300 in which a first set of interconnects 304 and a second set of interconnects 306 are transparent to reveal the individual interconnects with their associated die pads 316, only some of which are labeled.

[0034] Referring again to FIG. 2 , the first side rail 308 includes gaps 320 for each strip of interconnects in the first set of interconnects 304 and the second set of interconnects 306. The gaps 320 have a rectangular shape. The gaps 320 also have the same shape. Similarly, the second side rail 312 includes extension regions 324 for each strip of interconnects in the first set of interconnects 304 and the second set of interconnects 306. Each of the extension regions 324 has the same shape. The gaps 320 and extension regions 324 combined are referred to as a pedestal for the strip of interconnects. In the illustrated example, the pedestal for each strip of interconnect (the combination of the gaps 320 and extension regions 324) has the same shape.

[0035] The first set of interconnects 304 and the second set of interconnects 306 have interdigitated pins 328. In other words, pins from members in the first set of strips of interconnects 304 are interdigitated and interlocked with pins from members in the strips of the second set of interconnects 306. Also, in the first stage 200, pins from adjacent strips of interconnects are mechanically coupled; that is, an interconnect 304 of the first set adjacent to an interconnect 306 of the second set is mechanically coupled via an interdigitated pin 328.

[0036] 4, in a second step of the method, at 205, the pins of the strips of the first set of interconnects 304 and the strips of the second set of interconnects 306 are trimmed and formed to provide trimmed and formed pins 332 extending from each side of each strip of the first set of interconnects 304 and the strips of the second set of interconnects 306. Trimming the pins 332 removes material that mechanically bonds the interdigitated pins 328. Forming the pins 332 refers to curving the pins 332. The pins 332 are formed (curved) to resemble an "S" when viewed from the side.

[0037] As shown in FIG. 5 , in a third step of the method at 210, the first and second side rails 308, 312 of the interconnect strip frame 300 are removed from the frame 300 to provide an array of strips of interconnects 340. Removing the first side rail 308 includes making a first cut along a first cut line 344 across a first edge of the first set of strips of interconnects 304 and the second set of strips of interconnects 306. Similarly, removing the second side rail 312 includes making a second cut along a second cut line 348 across a second edge of the first set of strips of interconnects 304 and the second set of strips of interconnects 306, the second edge facing the first edge. FIG. 6 illustrates the array of strips of interconnects 340 separated from the first and second side rails 308, 312. FIG. 7 shows an expanded view of the area 352 labeled in FIG.

[0038] 7 , the strip of the first set of interconnects 304 is proximate to the strip of the second set of interconnects 306. A first distance 356 exists between an edge 358 of the strip of the first set of interconnects 304 and a first pin 362, i.e., the pin closest to edge 358. A second distance 366 exists between an edge 370 of the strip of the second set of interconnects 306 and a first pin 374, i.e., the pin closest to edge 370. Second distance 366 is shorter than first distance 356. That is, first pin 374 is closer to edge 370 of the strip of the interconnects 306 than first pin 362 is to edge 358 of the strip of the first set of interconnects 304. Edges 358 of the strips of the first set of interconnects 304 and edges 370 of the strips of the second set of interconnects 306 are formed by first cuts along first cut lines 344 shown in FIG.

[0039] 8 , in the fourth step of the method at 215, the strips of the first set of interconnects 304 and the strips of the second set of interconnects 306 are inverted and placed on a sawing chuck table 380 beneath a pick-and-place (PnP) head 384. The sawing chuck table 380 includes a first set of side pillars 388 and a second set of side pillars 392. The first side pillars 388 and the second side pillars 392 are paired and spaced apart to provide a resting place for a strip of interconnect, i.e., a strip of the first set of interconnects 304 or a strip of the second set of interconnects 306. The first side pillars 388 and the second side pillars 392 are shaped to avoid contact with pins 332 on the strips of the first set of interconnects 304 or the strips of the second set of interconnects 306.

[0040] 9, in the fifth step of the method at 220, the PnP head 384 moves down along the longitudinal axis to engage the strips of the second set of interconnects 306. Also, the PnP head 384 does not engage the strips of the first set of interconnects 304. In other words, the PnP head 384 engages every other strip of interconnects.

[0041] In the sixth step of the method, at 225, the PnP head 384 rises along the vertical axis to raise the second set of strips of interconnects 306 off the sawing chuck table 380. In other words, the PnP head 384 pulls every other strip of interconnects upwardly and off the sawing chuck table 380.

[0042] As shown in FIG. 11 , in the seventh step of the method at 230, the PnP head 384 moves the strip of the second set of interconnects 306 from an initial position along a first horizontal direction perpendicular to the vertical direction. FIG. 11 shows a single example of the strip of the second set of interconnects 306 for ease of explanation. Also, the PnP head 384 is transparent for clarity. More specifically, in FIG. 11 , the strip of the second set of interconnects 306 is moved away from the sawing chuck table 380 in the direction indicated by arrow 396 by the PnP head 384 in its initial position. The strip of the second set of interconnects 306 is moved until the strip of the second set of interconnects 306 overlaps an imager 400 (e.g., an optical sensor), which captures an image of the strip of the second set of interconnects 306. More specifically, the image of the second set of strips of interconnects 306 captured by imager 400 reveals the locations of pins 332 .

[0043] The controller 402 (or other computing platform) compares the image of the strips of the second set of interconnects 306 with the predetermined locations of the pins 332 of the strips of the first set of interconnects 304 to determine the offset required for the strips of the second set of interconnects 306. The offset for the strips of the second set of interconnects 306 defines the distance the strips of the second set of interconnects 306 need to be moved to align the pins 332 of the strips of the second set of interconnects 306 with the strips of the first set of interconnects 304 (still on the sawing chuck table 380). In some examples, the controller 402 is implemented as a computing platform that includes a processing unit (e.g., a processor core) that accesses and executes machine-readable instructions and non-transitory memory that stores the machine-readable instructions. In other examples, the controller 402 incorporates the machine-readable instructions.

[0044] 12 , in the eighth step of the method at 235, the PnP head 384 moves the strips of the second set of interconnects 306 a measured offset in a second horizontal direction that is perpendicular to the first horizontal direction and perpendicular to the vertical direction. In some examples, a controller 402 controls the movement of the PnP head 384. More specifically, the PnP head 384 moves these strips of the second set of interconnects 306 a measured offset in a direction indicated by arrow 404 that is perpendicular to arrow 396. In response to moving the strips of the second set of interconnects 306 in the second horizontal direction by the measured offset, the PnP head 384 moves the strips of the second set of interconnects 306 in a direction indicated by arrow 408 (opposite the direction of arrow 396) to return the strips of the second set of interconnects 306 to the sawing chuck table 380.

[0045] 13 , in the ninth step of the method at 240, the PnP head 384 moves down along the vertical axis to the corresponding first side pillar 388 and second side pillar 392 of the sawing chuck table 380 to release the strips of the second set of interconnects 306. In other words, the PnP head 384 releases every other strip of interconnects onto the sawing chuck table 380. Because the strips of the second set of interconnects 306 have been moved by the determined offset (as described in FIG. 12 ), the pins 332 of the strips of the first set of interconnects 304 are aligned with the pins 332 of the strips of the second set of interconnects 306, thereby forming an aligned array of strips of interconnects 398. The aligned array of interconnect strips is positioned such that the pins 332 of the strips of the first set of interconnects 304 are aligned to within about 25 microns or less with the strips of interconnects 306. Unless otherwise stated, in this description, "about" before a value means + / - 10 percent of the stated value.

[0046] 14, in a tenth step of the method at 245, in response to returning the strip of the second set of interconnects 306 to the sawing chuck table 380, the aligned array of strips of interconnects 398 (including both the strips of the first set of interconnects 304 and the strips of the second set of interconnects 306) is singulated into individual interconnects. As shown in FIG. 14, the array of interconnects 340 is cross-cut (sawed) as indicated by cut lines 420, 424, 428, 429, 432, and 436 to singulate the individual interconnects. As shown, the cuts are made along the same lines, i.e., cut lines 420, 424, 428, 429, 432, and 436, by aligning the pins 332 of the strip of the second set of interconnects 306 with the pins 332 of the strip of the first set of interconnects 304. In other words, a straight cut is possible to singulate the interconnects by aligning the pins 332 of the array of strips of interconnects 304 to form a aligned array of strips of interconnects 398. The example illustrated in Figure 14 has six cuts characterized by cut lines 420, 424, 428, 429, 432, and 436, although in other examples there are more or fewer cuts. The resulting singulated interconnect is a dual in-line package (DIP) interconnect.

[0047] Also, aligning the pins 332 to provide an aligned array of strips of interconnects 398 as shown eliminates the need for features such as U-bars or S-bars on the first or second side rails 308, 310 to move the strips of interconnects. For example, in an alternative to the method featured in FIGS. 2-15, in some circumstances, a frame 500 with a first side rail 504 including a U-bar 508 and a second side rail 512 including an S-bar 516 can be employed in the method. For ease of explanation, the same reference numerals are used to indicate the same structures in FIGS. 2-15 and 16. The U-bars 508 and S-bars 516 are conveniently used to align the pins 332 with deformations. However, as shown with respect to FIG. 15, the U-bars 508 and S-bars 516 are unnecessary. Instead, the first and second side rails 504, 512 are removed using the operation at 210 illustrated in FIG. 5. In other words, the method for aligning pins 332 is agnostic to the presence or absence of U-bars 508 and S-bars 516 .

[0048] Figure 16 illustrates an example of an interconnect 600 that has been singulated using method 100 of Figure 1 and / or the methods described in Figures 2-14. Interconnect 600 includes a first row of pins 604 that are extruded from a body 608 in a first direction and a second row of pins 612 that are also extruded from body 608 in a second direction opposite the first direction. Interconnect 600 is a DIP interconnect.

[0049] 17 and 18 illustrate a simplified example of a method for singulating interconnects from a frame of interconnect strips. FIG. 17 illustrates first and second stages of the simplified exemplary method. More specifically, FIG. 17 illustrates an interconnect strip frame 700 and an array of interconnect strips 710. The interconnect strip frame 700 includes a first set of interconnect strips 714 and a second set of interconnect strips 718. The first set of interconnect strips 714 and the second set of interconnect strips 718 have trimmed and formed pins 722. The frame 700 includes first side rails 726 and second side rails 730 that hold the first set of interconnect strips 714 and the second set of interconnect strips 718 in place.

[0050] The first side rail 726 and the second side rail 730 are removed from the first set of strips of interconnects 714 and the second set of strips of interconnects 718 to provide an array of strips of interconnects 710. More specifically, to remove the first side rail 726, first edges of the first set of strips of interconnects 714 and the second set of strips of interconnects 718 near the first side rail 726 are cross-cut as indicated by cut line 734. Similarly, to remove the second side rail 730, second edges (opposite the first edges) of the first set of strips of interconnects 714 and the second set of strips of interconnects 718 near the second side rail 730 are cross-cut as indicated by cut line 738.

[0051] The pins 742 (e.g., first pins, only one of which is shown) closest to the first edge of the strip of the first set of interconnects 714 have a first distance, and the pins 746 (e.g., first pins, only one of which is shown) closest to the first edge of the strip of the second set of interconnects 718 have a second distance that is different from the first distance. In the illustrated example, the first distance is greater than the second distance, but in other examples, the second distance is greater than the first distance.

[0052] FIG. 18 illustrates third and fourth stages of a simplified exemplary method for singulating interconnects. More specifically, FIG. 18 shows an aligned array of strips of interconnects 800, including strips of a first set of interconnects 714 and strips of a second set of interconnects 718. The aligned array of strips of interconnects is provided by moving the strips of the second set of interconnects 718 (in FIG. 17) by a measured offset to align the pins 722. The strips of the second set of interconnects 718 are moved by the operations described with respect to FIGS. 8-13. As shown, the edges of the strips of the first set of interconnects 714 are offset from the edges of the strips of the second set of interconnects 718 to align the pins 722.

[0053] Thus, as shown, the strips of first set of interconnects 714 and the strips of second set of interconnects 718 are cut (e.g., sawed) at cut lines 804, 808, 812, 816, and 820 to provide an array of singulated interconnects 830. Each interconnect in the array of singulated interconnects 830 can be employed to implement an instance of interconnect 600 of FIG.

[0054] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the appended claims.

Claims

1. 1. A method for matching interconnects, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips; aligning a first set of interconnect strips in the array of interconnect strips such that pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein an interconnect strip of the first set of interconnect strips is adjacent to an interconnect strip of the second set of interconnect strips to provide an aligned array of interconnect strips; Singulating the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; A method comprising:

2. 10. The method of claim 1, removing side rails from the interconnect strip frame; The method includes cutting a first edge and a second edge of an interconnect strip in the interconnect strip frame.

3. 10. The method of claim 1, The method wherein side rails attached to the interconnect strip frame have seats for the interconnect strip, and the seats for the interconnect strip have the same shape.

4. 10. The method of claim 1, The method of claim 1, wherein pins of the first set of interconnect strips in the array of interconnect strips are interleaved with pins of the second set of interconnect strips in the array of interconnect strips.

5. 10. The method of claim 1, The method, wherein the interconnect strips in the interconnect strip frame include die pads for the integrated circuit (IC) chip dies.

6. 10. The method of claim 1, The method, wherein the interconnect for the die of the IC chip is a dual in-line package interconnect.

7. A method for matching interconnections, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips, said removing including severing first and second edges of the interconnect strips in the interconnect strip frame; aligning a first set of interconnect strips in the array of interconnect strips such that pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein an interconnect strip of the first set of interconnect strips is adjacent to an interconnect strip of the second set of interconnect strips to provide an aligned array of interconnect strips; moving a given interconnect strip of the first set of interconnect strips from an initial position along a first axis; measuring the offset of a pin on the given interconnect strip of the first set of interconnect strips relative to a pin of the second set of interconnect strips; moving the set of first interconnect strips by the measured offset along a second axis, the second axis being perpendicular to the first axis; returning the first set of interconnect strips to the initial position; Singulating the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; A method comprising:

8. 8. The method of claim 7, Aligning the first set of interconnect strips includes: lifting the strip of the given interconnect from a sawing chuck table to the initial position along a third axis that is perpendicular to the first axis and the second axis.

9. 9. The method of claim 8, Aligning the first set of interconnect strips includes: The method further includes, in response to said returning, lowering the strip of the given interconnect along said third axis from said initial position onto said sawing chuck table.

10. 8. The method of claim 7, The measuring capturing an image of the given interconnect strip; comparing the image of the given interconnect strip with an image of another interconnect strip; determining a distance between a pin on the given interconnect strip to a pin on another interconnect strip, the distance being an offset of the pin on the given interconnect strip; A method comprising:

11. 11. The method of claim 10, The method of claim 1, wherein pins of the first set of interconnect strips are aligned within 25 microns of pins of the second set of interconnect strips in the array of aligned interconnect strips.

12. A method for matching interconnections, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips; aligning a first set of interconnect strips in the array of interconnect strips such that pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein an interconnect strip of the first set of interconnect strips is adjacent to an interconnect strip of the second set of interconnect strips to provide an aligned array of interconnect strips; inverting the first set of interconnect strips of the array of interconnect strips and the second set of interconnect strips of the array of interconnect strips; placing the inverted first set of interconnect strips of the array of interconnect strips and the inverted second set of interconnect strips of the array of interconnect strips on a sawing chuck table; Singulating the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; A method comprising:

13. 13. The method of claim 12, the sawing chuck table includes first pillars and second pillars for the array of interconnect strips, each first pillar of the first pillars being spaced apart from a corresponding second pillar of the second pillars.

14. A method for matching interconnections, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips; aligning a first set of interconnect strips in the array of interconnect strips such that, after trimming and forming the interconnect strip frame and after removing the side rails, pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein interconnect strips of the first set of interconnect strips are adjacent to interconnect strips of the second set of interconnect strips to provide an aligned array of interconnect strips; Singulating the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; A method comprising:

15. The method of claim 14, removing side rails from the strip of interconnect; The method includes cutting a first edge and a second edge of an interconnect strip in the interconnect strip frame.

16. The method of claim 15, Singulating the array of aligned interconnect strips comprises: making parallel cross cuts in the array of aligned interconnect strips.

17. The method of claim 15, Aligning the first set of interconnect strips includes: moving a given interconnect strip of the first set of interconnect strips from an initial position along a first axis; measuring the offset of a pin on the given interconnect strip of the first set of interconnect strips relative to a pin of the second set of interconnect strips; moving the set of first interconnect strips by the measured offset along a second axis, the second axis being perpendicular to the first axis; returning the first set of interconnect strips to the initial position; A method comprising:

18. The method of claim 17, Aligning the first set of interconnect strips includes: lifting the strip of the given interconnect from a sawing chuck table to the initial position along a third axis that is perpendicular to the first axis and the second axis.

19. A method for matching interconnections, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips, said removing including severing first and second edges of the interconnect strips in the interconnect strip frame; aligning a first set of interconnect strips in the array of interconnect strips such that pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein an interconnect strip of the first set of interconnect strips is adjacent to an interconnect strip of the second set of interconnect strips to provide an aligned array of interconnect strips; making parallel cross cuts in the array of aligned interconnect strips to singulate the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; A method comprising:

20. A method for matching interconnections, comprising: Trimming and forming a frame of strips of interconnects including interdigitated pins; removing side rails from the interconnect strip frame to provide an array of interconnect strips, said removing including severing first and second edges of the interconnect strips in the interconnect strip frame; aligning a first set of interconnect strips in the array of interconnect strips such that pins of a first set of interconnect strips in the array of interconnect strips are aligned with pins of a second set of interconnect strips in the array of interconnect strips, wherein an interconnect strip of the first set of interconnect strips is adjacent to an interconnect strip of the second set of interconnect strips to provide an aligned array of interconnect strips; Singulating the array of aligned interconnect strips to provide interconnections for integrated circuit (IC) chip dies; Including, The method of claim 1, wherein the interconnect strips of the first set of interconnect strips have a first distance between an edge of each of the interconnects of the first interconnect strips and a pin closest to the edge of each of the interconnects of the first interconnect strips, and the interconnect strips of the second set of interconnect strips have a second distance different from the first distance between an edge of each of the interconnects of the second set of interconnect strips and a pin closest to the edge of each of the interconnects of the second set of interconnect strips, and the pins of the first set of interconnect strips in the array of interconnect strips are interleaved with the pins of the second set of interconnect strips in the array of interconnect strips.

21. an array of interconnect strips, a first set of interconnect strips; a second set of interconnect strips; and Including, the interconnect strips of the first set of interconnect strips have a first distance between an edge of each of the interconnects of the first interconnect strips and a pin closest to the edge of each of the interconnects of the first interconnect strips, the interconnect strips of the second set of interconnect strips are adjacent to the interconnect strips of the first set of interconnect strips, and the interconnect strips of the second set of interconnect strips have a second distance different from the first distance between an edge of each of the interconnects of the second set of interconnect strips and a pin closest to the edge of each of the interconnects of the second set of interconnect strips; an array of interconnect strips, wherein the pins of the first set of interconnect strips in the array of interconnect strips are interleaved with the pins of the second set of interconnect strips in the array of interconnect strips.

22. 22. An array of interconnect strips according to claim 21, comprising: An array of interconnect strips, wherein the pins in the first set of interconnect strips and the pins in the second set of interconnect strips are trimmed and formed.

23. 23. An array of interconnect strips according to claim 22, comprising: An array of interconnect strips, said array of interconnect strips being placed on a sawing chuck table.

24. 24. An array of interconnect strips according to claim 23, comprising: An array of interconnect strips, wherein the first distance is greater than the second distance.

25. 22. An array of interconnect strips according to claim 21, comprising: An array of interconnect strips, wherein the first set of interconnect strips and the second set of interconnect strips comprise die pads for integrated circuit (IC) chip dies.

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