Semiconductor light emitting element, light source device, and distance measuring device

Abstract

To provide a light source device that can achieve both flattening of a FFP and a reduction in the chip area due to an increase in emission diameter.SOLUTION: A light source device has a plurality of semiconductor light emitting elements arranged on a semiconductor substrate, the semiconductor light emitting elements each having a first reflecting mirror, a resonator part including an active layer, and a second reflecting mirror laminated in this order. The semiconductor light emitting elements are each provided with an electrical contact area for supplying carrier to the active layer on a surface of the second reflecting mirror on the opposite side of the active layer. The plurality of semiconductor light emitting element include a first semiconductor light emitting element provided with the contact area in a first shape, and a second semiconductor light emitting element provided with the contact area in a second shape different from the first shape.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting element, a light source device, and a distance measuring device. [Background technology]

[0002] Patent Document 1 describes an example in which two types of VCSELs (Vertical Cavity Surface Emitting Lasers) that emit beams with different far-field patterns (FFPs) are configured on the same substrate. In order to make the FFPs different, a metal member is placed in the optical path from which the beam is emitted in one of the VCSELs, causing a loss in the higher-order modes and thereby controlling the oscillating transverse modes.

[0003] Another known method for inducing losses in higher-order modes involves controlling the in-plane reflectivity of the upper mirror of a VCSEL by processing the outermost surface or patterning the dielectric layer above it, thereby selectively inducing losses in higher-order modes.

[0004] By arranging VCSELs that emit different FFPs on the same substrate and superimposing the light emitted from them, it becomes possible to flatten the FFPs emitted from the VCSEL array, or in other words, to irradiate them with more uniform light, as described in Patent Document 1.

[0005] Uniform light illumination is useful when using VCSELs as illumination sources. For example, VCSELs are used as light sources for ToF (Time of Flight) LiDAR (Light Detection and Ranging) systems. When irradiating, uniform illumination prevents areas with low light intensity, which has advantages such as preventing the failure to detect small objects in those areas.

[0006] When a VCSEL is used as illumination, for example, when used as a light source for ToF, the pulse width is short, but the optical output has a peak output of 0.1 W or more, and in some applications, it may be required up to the 100 W level. In such cases, a two-dimensional array of multiple VCSELs is arranged to emit light to achieve the required amount of light.

[0007] When a large number of VCSELs are arranged and used in an array, by increasing the emission diameter of each VCSEL, the ratio of the area actually used as the light-emitting area to the chip area of the VCSEL array can be increased. In other words, by increasing the emission diameter of each VCSEL, the chip area required for the VCSEL array can be reduced, which is advantageous in terms of coupling with the optical system and cost.

[0008] However, when the emission diameter of the VCSEL is large (typically 10 μm or more in emission diameter), it becomes impossible to selectively control the loss in the higher-order mode to control the transverse mode. Therefore, when adopting the method as in Patent Document 1, it is necessary to suppress the emission diameter to 10 μm or less in order to control the FFP, and there is a problem that it is impossible to achieve both the reduction of the chip area due to the increase in the emission diameter and the control (uniformization) of the FFP.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] An object of the present invention is to provide a light source device capable of achieving both flattening of the FFP and reduction of the chip area due to an increase in the emission diameter.

Means for Solving the Problems

[0011] One aspect of the present invention is a light source device in which a plurality of semiconductor light-emitting elements are arranged in this order on a semiconductor substrate, with a first mirror, a resonator section including an active layer, and a second mirror laminated thereon, For each of the semiconductor light-emitting elements, an electrical contact region for supplying carriers to the active layer is provided on the surface side of the second mirror opposite to the active layer, The plurality of semiconductor light-emitting elements include a first semiconductor light-emitting element having a first shape of the contact region and a second semiconductor light-emitting element having a second shape of the contact region different from the first shape, A light source device characterized by this.

Effects of the Invention

[0012] According to the present invention, it is possible to achieve both flattening of the FFP and reduction of the chip area due to expansion of the light-emitting diameter.

Brief Description of the Drawings

[0013] [Figure 1A] Top view of the VCSEL array 10 of Example 1 [Figure 1B] Cross-sectional view of the VCSEL 100 of Example 1 [Figure 1C] Cross-sectional view of the VCSEL 200 of Example 1 [Figure 2A] Diagram for explaining the current density distribution in Example 1 [Figure 2B] Diagram for explaining the current density distribution in Example 1 [Figure 2C] Diagram for explaining the beam intensity distribution in the far-field region in Example 1 [Figure 2D] Diagram for explaining the beam intensity distribution in the far-field region in Example 1 [Figure 3A] Top view of the VCSEL array 20 of Example 2 [Figure 3B] Cross-sectional view of the VCSEL 300 of Example 2 [Figure 3C] Cross-sectional view of the VCSEL 400 of Example 2 [Figure 3D] Diagram for explaining the current density distribution in Example 2 [Figure 3E] Diagram illustrating the current density distribution in Example 2 [Figure 3F] This figure illustrates the beam intensity distribution in the far-field region in Example 2. [Figure 3G] This figure illustrates the beam intensity distribution in the far-field region in Example 2. [Figure 4A] Top view of the VCSEL array 30 in Example 3 [Figure 4B] Cross-sectional view of VCSEL500 in Example 3 [Figure 4C] Top view of VCSEL500 in Example 3 [Figure 4D] Top view of VCSEL500 (modified version) of Example 3 [Figure 5A] Top view of the VCSEL array 40 in Example 4 [Figure 5B] Cross-sectional view of VCSEL600 in Example 4 [Figure 5C] Cross-sectional view of VCSEL700 in Example 4 [Figure 6] Schematic diagram of the distance measuring device in Example 6 [Modes for carrying out the invention]

[0014] [First Embodiment] The VCSEL array (light source device) 10 of the first embodiment of the present invention is configured by arranging a plurality of VCSELs (semiconductor light-emitting elements).

[0015] Figure 1A is a diagram illustrating the VCSEL arrangement in the VCSEL array 10. The VCSEL array 10 in this embodiment consists of two types of VCSELs: VCSEL100 and VCSEL200. It is composed of L. VCSEL100 emits a laser beam that is a unimodal FFP, and VCSEL200 emits a laser beam that is a bimodal FFP (see Figure 2C).

[0016] As will be described later, the VCSEL100 and VCSEL200 differ in the shape of the electrical contact area on the surface side of the upper DBR for supplying carriers to the resonator (shown by a dotted line in Figure 1A), resulting in different FFP profiles. Details will be described later.

[0017] The VCSEL array 10 in this embodiment consists of 20 VCSEL100s and 1 VCSEL200. The reason there are more VCSEL100s than VCSEL200s is that VCSEL100s have a small light-emitting area and therefore produce less light output per VCSEL. The ratio of the number of VCSELs is determined so that the intensity of the beams emitted from these is flattened when they are superimposed in the far-field region.

[0018] The configuration of each VCSEL is described below.

[0019] Figure 1B is a schematic cross-sectional view of the VCSEL 100. The VCSEL 100 is constructed by stacking a lower DBR (first reflector) 102, a semiconductor resonator section 103, and an upper DBR (second reflector) 104 on a GaAs substrate (semiconductor substrate) 101 in that order. In Figure 3, these components are in direct contact, but other components may be provided between them. Furthermore, the above description is a description of the structure and does not limit the order in which each component is manufactured.

[0020] Three quantum well layers 140 are arranged inside the resonator section 103. In a part of the upper DBR 104, Al 0.98 An insulating oxidized constriction layer 106 is formed by oxidizing GaAs by water vapor oxidation. In this embodiment, the current constriction portion formed by the oxidized constriction layer 106 is formed in the upper DBR 104, but the current constriction portion may also be formed in the lower DBR 102 or the resonator portion 103.

[0021] The resonator section 103 and the upper DBR 104 are processed into a cylindrical mesa shape and covered with an insulating film 161. An ITO (Indium Tin Oxide) layer is formed on top of the insulating film 161.

[0022] As shown in Figure 1B, an insulating film 161 with a partially removed central portion is provided on the upper surface of the mesa-shaped upper DBR 104, and the ITO layer 162 is in contact with the upper surface of the upper DBR 104 in the removed portion. In this disclosure, the portion where the insulating film 161 has been removed is referred to as an insulating opening. The ITO layer 162 is in contact with the upper surface of the upper DBR 104 in the insulating opening portion. In this embodiment, the insulating opening of the insulating film 161 is circular. In addition, a ring electrode 150 is electrically in contact with a part of the ITO layer 162. The common electrode 151 is in ohmic contact with the back surface of the GaAs substrate 101.

[0023] The carriers supplied from the ring electrode 150 are supplied to the resonator portion 103 through the insulating opening. That is, the insulating film 161, which has been partially removed in a circular shape, and the ITO layer 162, which is in contact with the upper DBR 104 at the insulating opening where the insulating film 161 has been removed, form a contact region on the surface of the upper DBR 104 (the surface opposite to the surface in contact with the active layer). The shape of the contact region in the VCSEL 100 (first shape) is circular.

[0024] The lower DBR (Distributed Bragg Reflector) 102 has an optical film thickness of λc / 4 Al 0.1 GaAs layer and Al 0.9 The structure is composed of 35 pairs of GaAs layers stacked together. λc is the central wavelength of the high-reflection band of the lower DBR102, which is 940 nm in this embodiment.

[0025] The quantum well layer 140 is made of 8 nm thick In 0.1 GaAs layer with 10nm Al 0.1 GaAs The structure is sandwiched between barrier layers. In this embodiment, three quantum well layers are arranged in the resonator section 103.

[0026] The upper DBR 104 is composed of pairs of Al layers with an optical thickness of λc / 4 and Al 0.1 GaAs layers, with 20 pairs stacked. And a part of the uppermost Al 0.9 GaAs layer is replaced by a GaAs contact layer with a thickness of 50 nm and a carrier concentration of 1×10 0.1 G cm 19 to improve the electrical contact with the transparent conductive layer (ITO layer) 162. A part of the Al -3 GaAs layer closest to the quantum well layer 140 of the upper DBR is replaced by an Al GaAs layer with a thickness of 30 nm. This Al 0.1 GaAs layer forms an insulating constriction layer 106 with insulation by oxidizing a predetermined length from the mesa end by water vapor oxidation after the mesa formation of the VCSEL 100. The diameter d1 of the insulating opening portion where the insulating film 161 is removed is 10 μm, and the diameter d2 of the semiconductor portion inside the insulating constriction layer 10 0.98 GaAs layer (that is, the portion with high conductivity where current can flow, hereinafter referred to as the non-oxidized portion) is 30 μm. Also, in a plan view, the centers of the insulating opening portion and the non-oxidized portion substantially coincide, and the insulating opening portion is included in the non-oxidized portion. Since the above non-oxidized portion is the portion where current can flow in the resonator portion 103, the diameter of the non-oxidized portion becomes the light emission diameter of the VCSEL. This is the same in this Example and Example 2 and below. 0.98 The number of pairs of the lower DBR 102 is designed to have a higher reflectivity compared to the upper DBR 104. Also, since the insulating film 161 and the ITO layer 162 provided on the upper DBR 104 are transparent and transmit light at the emission wavelength, the VCSEL 100 of this example can extract light from the side of the upper DBR 104.

[0027]

[0028]

[0029] ​​​Figure 1C shows a schematic cross-sectional view of the VCSEL200. The VCSEL200 is constructed by stacking a lower DBR (first reflector) 202, a semiconductor resonator section 203, and an upper DBR (second reflector) 204 in that order on a GaAs substrate (semiconductor substrate) 201.

[0030] Three quantum well layers 240 are arranged inside the resonator section 203. In part of the upper DBR, Al 0.98 An insulating oxidized constricted layer 206 is formed by oxidizing GaAs by water vapor oxidation.

[0031] The resonator section 203 and the upper DBR 204 are processed into a cylindrical mesa shape and covered with an insulating film 261. An ITO (Indium Tin Oxide) layer is formed on top of the insulating film 261.

[0032] As shown in Figure 1C, an insulating film 261 is provided on the upper surface of the mesa-shaped upper DBR 204, with the central part removed in an annular shape. The ITO layer 262 is in contact with the upper surface of the upper DBR 204 at this removed portion (insulating opening). The insulating opening in the VCSEL 200 is annular (ring) in shape. In addition, a ring electrode 250 is electrically in contact with a part of the ITO 262. The common electrode 251 is in ohmic contact with the back surface of the GaAs substrate 201.

[0033] The carriers supplied from the ring electrode 250 are supplied to the resonator portion 203 through the insulating opening. That is, the insulating film 261, from which a portion of the ring shape has been removed, and the ITO layer 262, which is in contact with the upper DBR 204 at the insulating opening where the insulating film 261 has been removed, form a contact region on the surface of the upper DBR 204 (the surface opposite to the surface in contact with the active layer). The shape of the contact area (second shape) in the SEL200 is annular.

[0034] The inner diameter d3 of the annular insulating opening from which the insulating film 261 has been removed is 35 μm, and the outer diameter d4 is 45 μm. The diameter d2 of the semiconductor portion inside the oxidized constriction layer 206 (i.e., the portion with high conductivity through which current can flow, hereinafter referred to as the non-oxidized portion) is 70 μm. In a plan view, the centers of the insulating opening and the non-oxidized portion are approximately coincident, and the insulating opening is included within the non-oxidized portion.

[0035] The layer structure of the VCSEL in Figure 1C is identical to that of the VCSEL in Figure 1B, as they are formed simultaneously and monolithically on the same substrate using the same crystal growth layer. Therefore, a detailed explanation of the layer structure of Figure 1C is omitted.

[0036] Referring to Figure 1A, the arrangement of VCSEL100 and VCSEL200 in the VCSEL array 10 will be further explained.

[0037] The ring electrodes 150 on the VCSEL 100 are electrically connected to each other via the wiring electrodes 172. They are also electrically connected to the wire bonding pads 170 for supplying current from an external source. The ring electrodes 250 on the VCSEL 200 are electrically connected to the wire bonding pads 270 for supplying current from an external source.

[0038] The reason why the VCSEL200 is not positioned so that it is completely surrounded by the VCSEL100, but rather at the edge of the array as shown in Figure 1A, is to allow the wiring electrodes from the VCSEL200 to be connected to the pad 270 without crossing with other wiring electrodes. In this case, there is no need to make the wiring multilayered, which is advantageous in terms of the manufacturing process and electrical crosstalk via parasitic capacitance.

[0039] In d-ToF applications, it is desirable to change the current in nanoseconds or less. Also, the current value is large compared to the current values in other general communication applications and may be 1 A or more. Therefore, when the wirings are connected by parasitic capacitance, it is a condition where an unintended current easily flows through the parasitic capacitance, and there may be a problem that the controllability of FFP by controlling the current value due to the unintended current deteriorates.

[0040] In FIG. 1A, the VCSELs 100 are arranged in a square pattern, but other arrangement methods such as a triangular pattern may be used. Also, the position, number, and shape of the wiring electrodes 172 that connect the wire bonding pads and the ring electrodes 150 of the VCSELs on each mesa have the same electrical connection effect even if they are different from the configuration shown in FIG. 1.

[0041] FIG. 2A shows the calculation result of the current density distribution injected into the active layer in the configuration of the VCSEL 100.

[0042] FIG. 2A shows the distribution of the current density flowing into the quantum well layer 140 when the diameter d1 of the active layer insulation opening changes from 5 μm to 25 μm with the oxidation constriction diameter d2 being 30 μm. The horizontal axis in FIG. 2A is the radial position when the mesa center (i.e., the center of the non-oxidized part) is set to position 0. From this, it can be seen that if the diameter d1 of the insulation opening part is up to 20 μm, a convex current density distribution can be created in the center. Thus, by setting d1 < d2, the shape of the current density distribution flowing into the current quantum well layer can be formed into a convex shape in the center, and the far-field image can be controlled. In this embodiment, d1 is 20 μm.

[0043] FIG. 2B shows the calculation result of the current density distribution injected into the active layer in the configuration of the VCSEL 200. In this embodiment, the inner diameter of the annular insulation opening part from which the insulation layer is removed is 35 μm, and the outer diameter is 45 μm. For comparison, the calculation results when the width of the insulation opening is changed to 10 μm from an inner diameter of 20 μm to 50 μm are shown. Also, the diameter d2 of the non-oxidized part of the oxidation constriction layer is 70 μm.

[0044] As shown in Figure 2B, when the inner diameter is 35 μm and the outer diameter is 45 μm, the current density distribution injected into the active layer has a peak at position 20 μm on the horizontal axis, and the current density at the minimum values ​​around positions 0 and 33 μm is similar to that under other conditions. By creating a ring-shaped current injection distribution in this way, a bimodal current density distribution can be achieved.

[0045] Figure 2C shows the intensity distribution of light emitted from VCSEL100 and VCSEL200 in the far-field region. This was obtained by estimating the intensity distribution of the 0th and 1st transverse modes from the full width at half maximum of the current density distribution shown in Figures 2A and 2B, and then obtaining the far-field image from there. Figure 2D shows the intensity distribution superimposed using the intensity ratio based on the number of VCSELs shown in Figure 1A.

[0046] From this, it can be seen that by comparing the beams from VCSEL100 and VCSEL200 and superimposing them at the designed intensity ratio, flattening is achieved mainly in the divergence angle range of -0.5 to +0.5°.

[0047] Furthermore, the strength ratio between VCSEL100 and VCSEL200 is designed to be approximately 20:1, with VCSEL100 being the main component. In addition, one VCSEL100 is used. The emission diameter per unit is small, and the amount of light that can be emitted is also small. For this reason, in the VCSEL array 10 of this embodiment, there are more VCSELs 100 than VCSELs. The VCSEL array 10 is designed so that when the beams from all the VCSELs constituting the VCSEL array 10 overlap, the intensity is flattened in the central part of the divergence angle, which in this embodiment is within a range of ±0.5°.

[0048] Next, a comparison of the array size of the VCSEL array 10 in this embodiment with that of a conventional VCSEL will be explained. As shown in Figure 1A, the VCSEL array 10 in this embodiment consists of VCSEL 100 with an emission diameter of 30 μm and VCSEL 200 with an emission diameter of 70 μm. The VCSEL 100 has a pitch of 64 μm based on its emission diameter and the size required around it. Since it is arranged with 6 horizontally and 4 vertically, the size of the VCSEL array 10 is 384 μm horizontally and 256 μm vertically.

[0049] On the other hand, in the conventional configuration, as mentioned above, the emission diameter needs to be 10 μm or less in order to control the beam shape. Therefore, let's consider the case where the emission diameter is 10 μm, and the array is arranged at a narrower pitch than in this embodiment, specifically at a pitch of 44 μm, by the difference of 20 μm in emission diameter size. In order to obtain the same optical output at the same drive current density as in this embodiment, the total emission area, which is the sum of the emission areas, should be the same as that of the VCSEL array 10 in this embodiment. Calculations show that the number of VCSELs required to obtain the same optical output as in this embodiment with the conventional configuration is approximately 225. If these are arranged as an array of 15 units vertically and horizontally, the length of the array will be 660 μm.

[0050] As described above, the VCSEL array 10 in this embodiment can achieve the same optical output in a smaller area compared to the array using VCSELs in the conventional example. This is because the VCSEL array is configured with a larger emission diameter compared to the conventional example. Furthermore, the ability to configure the VCSEL array with a larger emission diameter is made possible because the FFP can be flattened with a larger emission diameter compared to the conventional example. This is also true for this embodiment and subsequent embodiments.

[0051] [Second Example] Figure 3A shows the VCSEL array 20 using VCSEL300 and VCSEL400 in this embodiment. In this embodiment, VCSEL300, which emits a unimodal FFP laser beam, and VCSEL400, which emits a bimodal FFP laser beam, are of similar size, and both have an emission diameter of approximately 70 μm. In other words, compared to Example 1, the emission diameter of the VCSEL emitting a unimodal FFP laser beam can be made larger.

[0052] The ring electrodes 350 on the VCSEL 300 are electrically connected to each other via wiring electrodes 372, and are also electrically connected to wire bonding pads 370 for supplying current from an external source. The ring electrodes 450 on the VCSEL 400 are electrically connected to each other via wiring electrodes 472, and are also electrically connected to wire bonding pads 470 for supplying current from an external source.

[0053] The reason why VCSEL300 is not positioned so that it is completely surrounded by VCSEL400, but rather positioned at the edge of the array as shown in Figure 3A, is to allow the wiring electrodes from VCSEL300 to be connected to pad 370 without crossing with other wiring electrodes. In this case, there is no need for multi-layer wiring, which is advantageous in terms of the manufacturing process and electrical crosstalk via parasitic capacitance.

[0054] Figure 3B shows a schematic cross-sectional view of the VCSEL300. The VCSEL300 is constructed by stacking the lower DBR302, semiconductor resonator section 303, upper DBR304, and tunnel junction layer 342 in that order on top of the GaAs substrate 301.

[0055] Three quantum well layers 340 are arranged inside the resonator section 303. In a part of the upper DBR, Al 0.98 An insulating oxidized constricted layer 306 is formed by oxidizing GaAs by water vapor oxidation.

[0056] The resonator section 303, the upper DBR 304, and the tunnel junction layer 342 are processed into a cylindrical mesa shape and covered with an insulating film 361. An ITO (Indium Tin Oxide) layer is formed on top of the insulating film 361.

[0057] As shown in Figure 3B, an insulating film 361 with a partially removed central portion is provided on the upper surface of the mesa-shaped upper DBR 304, and the ITO layer 362 is in contact with the upper surface of the upper DBR 304 at this insulating opening. In this embodiment, the insulating opening of the insulating film 361 is circular. Also, a ring electrode 350 is electrically in contact with a part of the ITO 362. The common electrode 351 is in ohmic contact with the back surface of the GaAs substrate 301.

[0058] The lower DBR302 is made of Al with an optical film thickness of λc / 4. 0.1 GaAs layer and Al 0.9 The structure is composed of 35 pairs of GaAs layers stacked together. λc is the central wavelength of the high-reflection band of the lower DBR302, which is 940 nm in this embodiment.

[0059] The quantum well layer 340 is made of 8 nm thick In 0.1 GaAs layer with 10nm Al 0.1 GaAs The structure is sandwiched between barrier layers. In this embodiment, three quantum well layers are arranged in the resonator section 303.

[0060] The upper DBR304 is made of Al with an optical film thickness of λc / 4. 0.1 GaAs layer and Al 0.9 It is composed of 20 pairs of GaAs layers stacked together, with each pair representing one GaAs layer. The Al layer closest to the quantum well layer 340 of the upper DBR is... 0.1 Part of the GaAs layer is made of Al with a thickness of 30 nm. 0.98 Placed in a GaAs layer It has been replaced. This Al 0.98 After the mesa formation of the VCSEL300, the GaAs layer is oxidized from the mesa edge to a predetermined length by water vapor oxidation from the mesa sidewall, thereby forming an insulating oxidized constricted layer 306.

[0061] The tunnel junction layer 342 has a carrier concentration of 5 × 10 19 cm -3 The above doped p-type GaAs layer (p-type semiconductor layer) and carrier concentration 1 × 10 19 cm -3 It is composed of the above-mentioned doped n-type GaAs layer (n-type semiconductor layer). Thus, the tunnel junction layer has a carrier concentration of 1 × 10⁻⁶ 18 cm -3 Because the p-type and n-type layers exceeding a certain value are in direct contact, current can also flow in the reverse direction through a thin depletion layer formed at the pn interface due to the tunneling effect.

[0062] The lower DBR302 is designed with a number of pairs such that it has a higher reflectivity compared to the upper DBR304. In addition, the insulating film 361 and ITO layer 362 provided on the upper DBR304 are transparent at the emission wavelength and transmit light, so the VCSEL300 in this embodiment can extract light from the side of the upper DBR306.

[0063] The VCSEL300 has the same configuration as in Example 1, in that an opening exists in a part of the insulating film on the upper part of the mesa, but in this example, a tunnel junction layer 342 is present. The contact region in the VCSEL300 is formed by an insulating film 361 having an insulating opening provided on the n-type GaAs layer of the tunnel junction layer, and an ITO layer (transparent conductive film) 362 that is in contact with the upper DBR304 in the insulating opening portion where the insulating film 361 has been removed. In this example, because the tunnel junction layer 342 is present, the preferred diameter d6 of the insulating opening and the diameter d5 of the non-oxidized portion are different from those in Example 1. The effects of this will be explained below.

[0064] The diameter d6 of the insulating opening where the insulating film 361 has been removed is 20 μm, and the diameter d5 of the non-oxidized portion inside the oxidation constriction layer 506 is 70 μm. The effect of this will be explained based on the calculation results in Figure 3D. In Figure 3D, the current density distribution is calculated when d5 is fixed at 70 μm and d6 is varied. From Figure 3D, it can be seen that the current density distribution remains convex in the center up to d6 = 20 μm. It can also be seen that current can be injected up to the boundary between the oxidized and non-oxidized portions, i.e., position 35 μm in Figure 3D. When d6 is 30 μm or more, the point where the current density is maximum is no longer at the center of the non-oxidized portion, i.e., position 0 in Figure 3D. In other words, the convex state in the center is gone. Thus, in this embodiment, compared to Embodiment 1, the mesa top By providing a tunnel junction layer 342, a current density distribution with a convex center can be achieved even over a larger area.

[0065] Figure 3C shows a schematic cross-sectional view of the VCSEL 400. The layer configuration from the back electrode 451 to the tunnel junction layer 442 is the same as that of the VCSEL 300. As shown in Figure 3C, the tunnel junction layer 442 is processed into an annular shape. That is, the surface of the upper DBR 404 of the VCSEL 400 has an annular tunnel junction layer with areas where the tunnel junction layer is provided and areas where it is not. The inner diameter d3 of the annular tunnel junction layer 442 is 35 μm and the outer diameter d4 is 45 μm. An ITO layer 462 is provided on the upper surface of the tunnel junction layer 442 and on the upper surface of the upper DBR 404 where the tunnel junction layer 442 is not provided (at least a part of it). A ring electrode 450 is placed on the ITO layer 462. An insulating film 461 is provided on the mesa sidewall.

[0066] In this embodiment, the tunnel junction layer 342 of the VCSEL 300 is not removed except for the portion in contact with the ITO layer 362, and is distributed across the entire upper surface of the upper DBR 304. On the other hand, in the VCSEL 400, the tunnel junction layer 442 is processed to be annular. Therefore, in the VCSEL 400, the tunnel junction layer 442 does not have the function of spreading the current laterally, and the shape of the portion of the tunnel junction layer 442 that was not removed determines the distribution of the current injected into the DBR 404. The current distribution injected into the active layer 440 is determined by the diffusion of current within the upper DBR 404. In other words, it is the same as the VCSEL 200 of Embodiment 1. Therefore, the size of the annulus of the tunnel junction layer 442 is the same as in Embodiment 1, and the active The current density distribution injected into layer 440 will also be the same.

[0067] The difference between removing the tunnel junction layer or not lies in the difference in the degree of lateral current diffusion necessary to form a favorable current distribution in the same non-oxidized portion with a diameter of 70 μm. VCSEL300 utilizes the effect of lateral current diffusion by taking advantage of the high conductivity of the n-type layer forming the tunnel junction layer 342. On the other hand, in VCSEL400, a more favorable current injection distribution can be obtained by not utilizing the conductivity of the n-type layer of the tunnel junction layer 462, so the tunnel junction layer 442 is processed to form an annular shape by removing the unnecessary portion.

[0068] Furthermore, the above-mentioned current diffusion effect can be obtained even if the tunnel junction layer 342 of the VCSEL 300 is provided only in a portion of the upper surface of the upper DBR 304, including the insulating opening. For example, the tunnel junction layer 342 may be formed to include the mesa center and have a diameter larger than d5, so as to encompass the entire non-oxidized portion of the oxidized constriction layer 306 in a plan view.

[0069] Figure 3E shows the calculated current injection distribution into the active layer when current is injected from an annular region with an inner diameter of 30 μm and an outer diameter of 40 μm, with and without the removal of the tunnel junction layer 442 (except for the annular portion with an inner diameter of 30 μm and an outer diameter of 40 μm). From this, it can be seen that when the layer is not removed, the ratio of the maximum value near 17 μm in the lateral direction to the minimum value near 31 μm in the lateral direction is 1.65, whereas when the layer is removed except for the annular portion, the ratio to the minimum value is approximately 7.04 times. From this, it can be seen that a current distribution closer to an oscillation mode with a bimodal lateral intensity distribution is obtained when the layer is removed except for the annular portion, and the configuration shown in Figure 3C is more preferable.

[0070] Figure 3F shows the intensity distribution of light emitted from VCSEL300 and VCSEL400 in the far-field region. This was obtained by estimating the intensity distribution of the 0th and 1st transverse modes from the full width at half maximum of the current density distribution shown in Figures 3D and 3E, and then obtaining the far-field image from there. Figure 3G shows the intensity distribution superimposed based on the intensity ratio according to the number of VCSELs shown in Figure 3A. The intensity ratio is designed to be 1:3 for VCSEL300 and VCSEL400, and the component from VCSEL400 is dominant. Therefore, in the VCSEL array 20 of this embodiment, there are more VCSEL400s.

[0071] Figure 3G shows that by superimposing the beams from VCSEL300 and VCSEL400 at the designed intensity ratio, flattening is achieved mainly in the divergence angle range of -0.5 to +0.5°. Furthermore, comparing the base of the superimposed beam shape shown in Figure 2D of Example 1, the base of Example 1 (Figure 2D) extends to about ±2°, while in this example (Figure 3G) it is reduced to about ±1.5°. Since the width of the flattened beam is in the range of ±0.5° in both cases, it can be seen that the shape of this example is closer to a rectangle.

[0072] Furthermore, in Examples 1 and 2, the range exceeding ±0.5° may be shielded with an optical aperture or the like, and only the flattened portion may be used. In this case, a smaller width of the shading in the range exceeding ±0.5° outside the flattened area results in less light loss due to shielding. In other words, when using an optical aperture, this example is preferable to Example 1 in that it results in less light loss.

[0073] [Third Embodiment] Figure 4A shows the VCSEL array 30 of this embodiment. In this embodiment, in addition to the VCSEL300 and VCSEL400 used in Embodiment 2, a VCSEL500 is also provided. Details of VCSEL300 and VCSEL400 are omitted as they were explained in Embodiment 2.

[0074] Figure 4B shows a schematic cross-sectional view of the VCSEL500. Components of the VCSEL500 that are identical to those of the VCSEL400 are given the same part numbers, and their explanations are omitted. The difference from the VCSEL400 is that, in addition to the annular tunnel joint layer 442, a tunnel joint layer 542 is located on the upper DBR, and is connected to electrically independent ITO layers 562 and 563, respectively. That is, the upper DBR of the VCSEL500 is provided with two contact areas, each connected to a different power source. The tunnel joint layer 542 is circular and is located within the inner diameter of the annular tunnel joint layer 442.

[0075] Figure 4C shows a top view of the VCSEL500. This diagram primarily illustrates the shape of the tunnel junction layer, and for illustrative purposes, the ITO layer 562 and the upper electrode 450 are omitted.

[0076] Figures 4B and 4C show that the tunnel junction layer 442 and tunnel junction layer 542 are electrically independent. The tunnel junction layer 442 is an annular shape with a portion cut out, and by injecting current from here, it creates a bimodal current density distribution similar to that of the VCSEL 400. On the other hand, the tunnel junction layer 542 is circular, similar to the VCSEL 100, and creates a unimodal current density distribution. Therefore, by controlling the ratio of current from these two tunnel junction layers, it is possible to control the FFP. The center of the tunnel junction layer 542 (circular) coincides with the center of the non-oxidized portion (the portion with high conductivity through which current can flow) of the oxidized constriction layer 406. The contact region of the tunnel junction layer 542 includes the center of the non-oxidized portion in a plan view and is contained within the entire non-oxidized portion. Similarly, the center of the tunnel junction layer 442 (annular) coincides with the center of the non-oxidized portion and is contained within the entire non-oxidized portion in a plan view. Furthermore, the tunnel joint layer 442 and the tunnel joint layer 542 are spaced apart from each other, with the tunnel joint layer 542 being contained within the annular tunnel joint layer 442 (inner diameter portion), and the tunnel joint layer 442 surrounding the tunnel joint layer 542.

[0077] Referring to Figure 4A, the arrangement of each VCSEL in the VCSEL array 30 will be explained further.

[0078] The ring electrodes 350 on VCSEL300 are electrically connected to each other via wiring electrodes 372, and are also electrically connected to wire bonding pads 370 for supplying current from an external source. The ring electrodes 450 on VCSEL400 are electrically connected to each other via wiring electrodes 472, and are also electrically connected to wire bonding pads 470 for supplying current from an external source. The two ring electrodes 450 and electrode 563 of VCSEL500 are connected to each other via wiring electrodes 572 and 573, respectively, and are also connected to pads 580 and 581.

[0079] In this embodiment, the configuration shown in Figure 4A is adopted to reduce electrical crosstalk by avoiding multi-layer wiring, but other configurations may also be used.

[0080] In this embodiment, the advantageous effects of having VCSEL500 will be explained. In this embodiment, when the balance of optical output from VCSEL300 and VCSEL400 is disrupted due to driving conditions including ambient temperature and changes over time, the FPP from VCSEL500 can be controlled to correct the FPP shape of the entire array to a desirable shape. To control the FPP of VCSEL500, as described above, the current injected into the two tunnel junction layers 442 and 542 of VCSEL500 can be controlled.

[0081] According to this embodiment, the FFP can be corrected by the VCSEL500, which contributes to improving the reliability of the ToF system. For example, this is the case when the light output decreases due to a failure in either the VCSEL300 or the VCSEL400.

[0082] If either VCSEL300 or VCSEL400 fails, causing a decrease in optical output from the array and deterioration of FFP flatness, the FPP shape can be corrected as described above. Specifically, by controlling the current injected through ITO layers 562 and 563 connected to VCSEL500, the FFP and optical output can be restored to within the ToF system's predetermined range. Therefore, the number of VCSELs is designed so that the array configuration provides the necessary optical output for the ToF system without driving VCSEL500 at its maximum rated current. In the event of failure, the current injected into VCSEL500 can be increased to restore both FFP flatness and optical output, allowing the ToF system to maintain the same characteristics as before the failure.

[0083] Regarding the flatness of the FFP, in a ToF system, based on the image captured by the imaging side, abnormalities in the FFP on the light source side can be detected from the common density information contained in the density of images captured from multiple different objects. Furthermore, when checking for accuracy in inspections rather than actual use, correction can be applied using images captured by illuminating a plane with constant reflectivity.

[0084] In this embodiment, VCSEL300, VCSEL400, and VCSEL500 are arranged in a single array, and the beams from VCSEL300 and VCSEL400 are used as a base, with VCSEL500 used for correction. On the other hand, as a modification, an array configuration consisting only of VCSEL500 also achieves the effect of suitably controlling the FFP. In this configuration, the number of wiring electrodes increases compared to the embodiment in Figure 4A, the configuration becomes more complex, and depending on the arrangement of VCSEL500 in the array, multi-layer wiring may be required. However, an advantage of using only VCSEL500 is that the distribution of illumination light can be made symmetrical from the far-field region to the closer region. Specifically, in the configuration of this embodiment, different types of VCSELs are arranged in a clustered area within the array, so when illuminating an object in a region closer than the far-field region, the distribution of illumination light reflects the arrangement of VCSELs in the array, resulting in an asymmetric intensity distribution. This phenomenon becomes more pronounced as you move from the far-field region to the near-field region. On the other hand, when using only VCSEL500s, the array arrangement is uniform, so although the intensity distribution of illumination light changes as you move from the far-field to the near-field, symmetry is maintained, which is an advantage.

[0085] Furthermore, the far-field and near-field regions mentioned above include not only the region defined by the beam emitted from the VCSEL, but also the near-field region of the beam after it has been transformed by an optical system such as a lens in a ToF system. The length of the near-field region after transformation by the optical system is often longer than the length of the near-field region defined by the beam characteristics immediately after VCSEL emission, and depending on the design of the optical system, symmetry in this near-field region may be important.

[0086] Furthermore, in the above embodiment, an ITO layer (transparent conductive film) 563 is used for the tunnel junction layer 542 of the VCSEL500, but a metal material wiring may be used instead of a transparent conductive film.

[0087] Figure 4D shows a top view of the VCSEL 500 according to this modified example. As described above, the metal wiring 564 is used to connect to the tunnel junction layer 542. However, an ITO layer (transparent conductive film) 566 is provided on the upper surface of the tunnel junction layer 542, and the metal wiring 564 and the ITO layer 566 are electrically connected.

[0088] In this modified example, since the light extraction efficiency decreases due to light shielding by the metal wiring 564, an insulating film 565 is provided beneath the metal wiring 564. The optical thickness of the insulating film 565 is λc / 4. This reduces the reflectivity beneath the metal wiring 564, thereby hindering laser oscillation and mitigating the decrease in light extraction efficiency caused by light shielding by the metal wiring 564.

[0089] [Fourth embodiment] Figure 5A shows a VCSEL array 40 using VCSEL600 and VCSEL700 in this embodiment. In Figure 5A, the wiring electrodes and contact area shapes are not shown. In this embodiment, the VCSEL600, which emits a unimodal FFP laser beam, and the VCSEL700, which emits a bimodal FFP laser beam, are of similar size, and both have an emission diameter of approximately 70 μm. The emission diameter and the arrangement of VCSELs within the VCSEL array are the same as in Embodiment 2, but the VCSELs in this embodiment differ from Embodiment 2 in that they emit light from the back surface of the GaAs substrate, as will be explained in the descriptions of Figures 5B and 5C below.

[0090] Figure 5B shows a schematic cross-sectional view of the VCSEL600. The VCSEL600 is constructed by stacking a lower DBR602, a semiconductor resonator section603, an upper DBR604, and a tunnel junction layer642 on a GaAs substrate601.

[0091] Three quantum well layers 640 are arranged inside the resonator section 603. In a part of the upper DBR, Al 0.98 An insulating oxidized constricted layer 606 is formed by oxidizing GaAs by water vapor oxidation.

[0092] The resonator portion 603, the upper DBR 604, and the tunnel junction layer 642 are processed into a cylindrical mesa shape and covered with an insulating film 661. As shown in Figure 5B, the insulating film 661 has an insulating opening provided by partially removing the central part. An upper electrode 650 is formed on the insulating film 661 and covers the mesa-shaped semiconductor resonator portion 603, the upper DBR 604, the insulating film 661, and its insulating opening. The upper electrode 650 is made of a metallic material. The insulating opening is circular, and the upper electrode 650 is in electrical contact with the tunnel junction layer 642. The common electrode 651 is in ohmic contact with the back surface of the GaAs substrate 601, and the light-emitting portion is removed in a circular shape.

[0093] The lower DBR602 has an optical film thickness of λc / 4 Al 0.1 GaAs layer and Al 0.9 The structure is composed of 24 pairs of GaAs layers stacked together. λc is the center wavelength of the high-reflection band of the lower DBR602, which is 940 nm in this embodiment. The quantum well layer 640 is made of 8 nm thick In 0.1 GaAs layer with 10nm Al 0.1 The structure is sandwiched between GaAs barrier layers. In this embodiment, three quantum well layers are arranged in the resonator section 603.

[0094] The upper DBR604 is made of Al with an optical film thickness of λc / 4. 0.1 GaAs layer and Al 0.9 It is constructed by stacking 40 pairs of GaAs layers, with each pair representing one layer. And the top layer is Al 0.1 G A portion of the aAs layer has a thickness of 50 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3 GaAs container It has been replaced with a ct layer, improving electrical contact with the upper electrode 650. The Al is closest to the quantum well layer (active layer) 640 of the upper DBR. 0.1 A portion of the GaAs layer is 3 0nm Al 0.98 It has been replaced by a GaAs layer. 0.98 The GaAs layer is formed by oxidizing a predetermined length from the mesa edge by water vapor oxidation from the mesa sidewall after the mesa formation of VCSEL600, thereby creating an insulating oxidized constriction layer 606. The tunnel junction layer 642 has a carrier concentration of 5 × 10⁻⁶. 19 cm -3 A doped p-type GaAs layer and carrier A concentration 1 × 10 19 cm -3 It is composed of doped n-type GaAs layers.

[0095] The upper DBR604 is designed with a higher number of pairs compared to the lower DBR602, and the VCSEL600 in this embodiment can extract light from the back side of the substrate.

[0096] The effect of the tunnel junction layer 642 in this embodiment, and the relationship between the preferred insulating aperture diameter and the diameter of the non-oxidized portion, are the same as in the VCSEL300 of Example 2, so a detailed explanation is omitted.

[0097] Figure 5C shows a schematic cross-sectional view of the VCSEL700. The layer configuration from the back electrode 751 to the tunnel junction layer 742 is the same as that of the VCSEL600. As shown in Figure 5C, the tunnel junction layer 742 is processed into an annular shape on the outermost surface of the upper DBR704. An insulating film 761 is provided on the mesa sidewall. The inner diameter d3 of the annular tunnel junction layer 742 is 35 μm, and the outer diameter d4 is 45 μm. The surface electrode 750 covers the upper DBR704, the insulating film 761, and the tunnel junction layer 742. The surface electrode 750 is in direct contact with the DBR704, but the current mainly flows through the annular tunnel junction layer 742. This is because the surface electrode 750 is an electrode material that can make ohmic contact with the n-type GaAs layer, and makes Schottky contact with the DBR704.

[0098] The upper DBR704 is designed with a higher number of pairs compared to the lower DBR702, and the VCSEL700 in this embodiment can extract light from the back side of the substrate.

[0099] In the VCSEL700, the effect of current propagation through the tunnel junction layer 742 is the same as in the VCSEL400 of Example 2, so a detailed explanation is omitted here.

[0100] [Fifth Example] Figure 6 shows a light detection and ranging (LiDAR) device using the VCSEL array (surface-emitting laser array) 20 described in Example 2 as a light source.

[0101] As shown in Figure 6, the distance measuring device 1000 consists of an overall control unit 1010, a VCSEL array driver 1020, a VCSEL array 20, a light-emitting optical system 1040, a light-receiving optical system 1060, a light-receiving image sensor 1070, and a distance data processing unit 1080.

[0102] In this embodiment, the VCSEL array described in Example 2 is used, but the present invention is not limited thereto, and VCSEL arrays described in other embodiments may also be used.

[0103] In Figure 6, the light-emitting optical system 1040 and the light-receiving optical system 1060 are represented by a single convex lens-shaped component. Although it is depicted, it is not composed of only one convex lens system, but rather multiple lenses It is composed of a combination of lens groups. The light-receiving image sensor 1070 is an image sensor in which light sensors capable of detecting the timing of light reception are arranged in a two-dimensional array.

[0104] The operation of the distance measuring device 1000 is outlined below. First, the overall control unit 1010 sends a drive signal to the surface-emitting laser array driver 1020. Upon receiving the drive signal, the surface-emitting laser array driver 1020 injects a predetermined current into the surface-emitting laser array 1030, causing the surface-emitting laser array 1030 to oscillate. The laser light generated by the surface-emitting laser array 1030 passes through the light-emitting optical system 1040 and strikes the object to be measured 1200. The reflected light reflected from the object to be measured 1200 passes through the light-receiving optical system 1060 and enters the light-receiving image sensor 1070. The distance data processing unit 1080 only needs to be electrically connected to the light-receiving image sensor 1070. Therefore, it may be located in the same package as the light-receiving image sensor 1070, or it may be mounted in a separate package and electrically connected by a circuit board or the like.

[0105] The electrical signal pulses output from each pixel of the light-receiving image sensor 1070 are input to the distance data processing unit 1080. The distance data processing unit 1080 calculates distance information in the direction of light propagation from the time (detection timing) of the electrical signal pulses output from each pixel of the light-receiving image sensor 1070 and the emission timing of the surface-emitting laser array driver 1020, and generates and outputs 3D information.

[0106] In this way, the distance measuring device 1000 can output three-dimensional information.

[0107] The distance measuring device 1000 can be applied in the automotive sector to control systems that prevent collisions with other vehicles and to control systems that automatically follow other vehicles. Furthermore, it can be used in mobile objects (mobile devices) such as ships, aircraft, or industrial robots, as well as in mobile object detection systems. Moreover, it can be widely applied to devices that utilize three-dimensional recognition of objects, including distance information.

[0108] The uses of 3D information are not limited to those mentioned above. For example, distance information can be used in image processing. When acquiring an image of real space and overlaying a virtual object onto it, using 3D information of real space allows the virtual object to be displayed seamlessly on top of the real world. Furthermore, by acquiring 3D information at the time of image acquisition, the blur effect can be corrected after shooting based on the 3D information. [Explanation of Symbols]

[0109] 100,200:VCSEL 101,201: GaAs substrate (semiconductor substrate) 102,202: Lower DBR (First reflector) 103,203: Semiconductor resonator section 104.204: Upper DBR (Second reflector)

Claims

1. A light source device comprising a semiconductor substrate and a plurality of semiconductor light emitting elements each having a first reflector, a resonator portion including an active layer, and a second reflector stacked in this order on the semiconductor substrate, Each of the semiconductor light emitting elements has an electrical contact region provided on a surface side of the second reflector opposite to the active layer, the electrical contact region being used to supply carriers to the active layer; The plurality of semiconductor light emitting elements include a first semiconductor light emitting element having a contact region with a first shape, and a second semiconductor light emitting element having a contact region with a second shape different from the first shape, each of the semiconductor light emitting elements has a current confinement portion having a circular low conductivity region and a high conductivity region inside the circular low conductivity region, in at least one of the first reflector, the resonator portion, and the second reflector; In a plan view, the contact region of the first semiconductor light emitting element overlaps with a center of gravity of a light emitting region defined by the current confinement portion. A light source device characterized by:

2. the first shape is circular; The second shape is annular. The light source device according to claim 1 .

3. The contact region is included in a highly conductive region of the current confinement portion in a plan view.

3. The light source device according to claim 1.

4. a center of the first shape and a center of the second shape coincide with a center of a highly conductive region of the current confinement portion in a plan view; The light source device according to claim 1 .

5. At least one of the plurality of semiconductor light emitting devices the contact region is composed of an insulating film provided on the second reflecting mirror, a portion of which has been removed, and a conductive film in contact with the second reflecting mirror at the portion where the insulating film has been removed. The light source device according to claim 1 .

6. At least one of the plurality of semiconductor light emitting devices an n-type semiconductor layer and a tunnel junction layer thereunder are provided on a surface of the second reflector opposite to a surface in contact with the active layer; the contact region is composed of an insulating film provided on the n-type semiconductor layer, a portion of which has been removed, and a conductive film in contact with the n-type semiconductor layer at the portion where the insulating film has been removed. The light source device according to claim 1 .

7. The tunnel junction layer has a carrier concentration of 1×10 １９ cm -３ The above p-type and n-type layers are directly Consists of two adjacent The light source device according to claim 6 .

8. At least one of the plurality of semiconductor light emitting devices the surface of the second reflector has a region where an n-type semiconductor layer and a tunnel junction layer are provided and a region where they are not provided, a conductive film is provided in a region where the tunnel junction layer is provided and in at least a part of a region where the tunnel junction layer is not provided; 5. A light source device according to claim 1.

9. the plurality of semiconductor light emitting elements include a third semiconductor light emitting element having a first contact region and a second contact region on the surface of the second reflector, the first contact region and the second contact region being connected to different power sources; The light source device according to claim 1 .

10. the first contact region is a region including a center of the second reflector, the second contact region is a region separated from the first contact region and surrounding the second contact region; The light source device according to claim 9 .

11. Each of the plurality of semiconductor light emitting devices is the reflectance of the first reflector is higher than the reflectance of the second reflector, a transparent conductive film is provided on a front surface side of the second reflecting mirror, The light is emitted from the front surface side of the second reflecting mirror. The light source device according to claim 1 .

12. Each of the plurality of semiconductor light emitting devices is the reflectance of the first reflector is lower than the reflectance of the second reflector; Emitting light through the semiconductor substrate; The light source device according to claim 1 .

13. A light source device according to any one of claims 1 to 12, a sensor for detecting reflected light of light emitted from the light source device; A processing unit that acquires distance information based on a detection timing of the reflected light; A distance measuring device comprising:

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