Wide band gap transistor with nanolaminated insulating gate structure and method for manufacturing wide band gap transistor

Abstract

To provide a wide band gap transistor and a method for manufacturing a wide band gap transistor, which allow the limitations in the prior art to be overcome or mitigated.SOLUTION: A wide band gap transistor includes: a semiconductor structure (2) including at least one wide band gap semiconductor layer (14, 16, 103, 105) of gallium nitride (GaN) or silicon carbide (SiC); an insulating gate structure (8); and a gate electrode (7; 18; 100c), separated from the semiconductor structure (2; 15; 102) by the insulating gate structure (8; 17; 110). The insulating gate structure (8; 17; 110) contains a mixture of aluminum, hafnium and oxygen.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a wide-bandgap transistor having a nanolaminated insulated gate structure and a method for manufacturing a wide-bandgap transistor. [Background technology]

[0002] As is well known, semiconductor materials having a wide bandgap (WBG), particularly a bandgap energy value Eg greater than 1.1 eV, low on-state resistance (RON), high thermal conductivity, high operating frequency, and high charge carrier saturation rate, are particularly suitable for manufacturing electronic components for power applications such as MOSFETs, JFETs, HEMTs (high electron mobility transistors), and MISHEMTs (metal-insulator-semiconductor high electron mobility transistors).

[0003] A material with similar properties and intended for use in manufacturing electronic components is silicon carbide (SiC) in its different polytypes (e.g., 3C-SiC, 4H-SiC, 6H-SiC).

[0004] Another example of a material that is usefully used for this purpose is gallium nitride (GaN). For example, high-mobility field-effect transistors are known to be based on the formation of a layer of high-mobility two-dimensional electron gas (2DEG) at a heterojunction, which is the interface between semiconductor materials having different band gaps. For example, HEMT transistors are known to be based on a heterojunction between a layer of aluminum gallium nitride (AlGaN) and a layer of gallium nitride (GaN).

[0005] In power transistors made of SiC or GaN, the use of high dielectric constants is beneficial for forming insulated gate structures. Indeed, these materials allow for a reduction in both the electric field and the on-state resistance RON of the device within the insulated gate structure, and further offer advantages in terms of threshold voltage.

[0006] The problem with currently used high-dielectric-constant materials is linked to their tendency to degrade when exposed to high temperatures. In particular, at temperatures commonly reached in some processes of manufacturing wide-bandgap devices, pure high-dielectric-constant materials tend to crystallize, and the phase change can increase the leakage current of the device. For example, the formation of ohmic contacts typically requires a high-temperature annealing process and can cause crystallization of high-dielectric-constant dielectrics. As a result, the process flow must be structured so that processes requiring high temperatures are carried out before the formation of the insulating gate structure. However, this process sequence may require additional processes that are otherwise unnecessary, which leads to increased manufacturing costs. For example, additional photolithography may be required to define the ohmic contacts separately from the insulating gate structure.

[0007] On the other hand, materials such as silicon oxides can withstand much higher temperatures without degradation, but they do not possess a dielectric constant sufficient to achieve the high performance often required. [Overview of the project] [Problems that the invention aims to solve]

[0008] The object of the present invention is to provide a wide bandgap transistor and a method for manufacturing a wide bandgap transistor that can eliminate or alleviate the above-mentioned limitations. [Means for solving the problem]

[0009] According to the present invention, a wide bandgap transistor and a method for manufacturing a wide bandgap transistor are provided as defined in claims 1 and 7, respectively.

[0010] To better understand the present invention, several embodiments of the invention are described below with reference to the accompanying drawings, purely as non-limiting examples. [Brief explanation of the drawing]

[0011] [Figure 1] A cross-sectional view of a wide-bandgap transistor according to one embodiment of the present invention. [Figure 2] (a) is a magnified detail view of the transistor in Figure 1 in a step of a process according to one embodiment of the present invention, (b) is a detail view of (a) in a subsequent processing step, and (c) is a detail view of (A) in a subsequent processing step of a process according to a different embodiment of the present invention. [Figure 3] Cross-sectional view of a wide-bandgap transistor based on a different embodiment of the present invention. [Figure 4] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to a further embodiment of the present invention. [Figure 5] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to a further embodiment of the present invention. [Figure 6] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to a further embodiment of the present invention. [Figure 7] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to a further embodiment of the present invention. [Figure 8] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to a further embodiment of the present invention. [Figure 9] Cross-sectional view of a wide-bandgap transistor based on a further embodiment of the present invention. [Figure 10] A cross-sectional view of a semiconductor wafer in one of the successive steps of a process according to yet another embodiment of the present invention. [Figure 11] Cross-sectional view of a wide-bandgap transistor based on a further embodiment of the present invention. [Figure 12] Cross-sectional view of a semiconductor wafer in a certain step of successive steps of a process based on a further embodiment of the present invention. [Figure 13] Cross-sectional view of a semiconductor wafer in a certain step of successive steps of a process based on a further embodiment of the present invention. [Figure 14] Cross-sectional view of a semiconductor wafer in a certain step of successive steps of a process based on a further embodiment of the present invention. [Figure 15] Cross-sectional view of a semiconductor wafer in a certain step of successive steps of a process based on a further embodiment of the present invention. [Figure 16] Cross-sectional view of a semiconductor wafer in a certain step of successive steps of a process based on a further embodiment of the present invention.

Mode for Carrying Out the Invention

[0012] The present invention particularly relates to the manufacture of an insulating gate structure in a wide-bandgap transistor. Referring to FIG. 1, generally, a wide-bandgap transistor 1 has a semiconductor structure 2 in which at least one layer is made of a wide-bandgap semiconductor material such as gallium nitride (GaN) or silicon carbide (SiC), a source electrode 3, a drain electrode 4, and a gate electrode 7 separated from the semiconductor structure 2 by an insulating gate structure 8. More specifically, in the case of a GaNHEMT device, the semiconductor structure 2 includes an aluminum gallium nitride (AlGaN) and GaN hetero-structure - an AlGaN / GaN hetero-structure, or in the case of a SiCMOSFET, a SiC substrate with a high doping level (e.g., 10 18 electrons / cm 3 or more) and a SiC epitaxial layer with a lower doping level (e.g., 10 15 10 16 electrons / cm 3 in some cases.

[0013] The insulated gate structure 8, illustrated in detail in Figures 2(a)-(c), comprises a mixture of aluminum, hafnium, and oxygen. More specifically, the insulated gate structure 8 is obtained by alternating sequential conformal deposition of multiple aluminum oxide layers 8a and multiple hafnium oxide layers 8b having nanometer thicknesses to form a gate laminate 8' (Figure 2(a)), followed by an annealing process (Figures 2(b), (c)). The aluminum oxide layers 8a and hafnium oxide layers 8b have thicknesses between, for example, 0.5 nm and 10 nm, are amorphous, and are obtained by atomic layer deposition (ALD). The number of layers 8a and 8b is determined so that the overall thickness of the insulated gate structure 8 has a desired value between, for example, 30 nm and 60 nm. In a non-restrictive example, all of the aluminum oxide layers 8a and hafnium oxide layers 8b have equal thicknesses.

[0014] During the annealing process, at the interface between layers 8a and 8b, aluminum oxide and hafnium oxide diffuse and mix. Therefore, at least at each interface, a mixture of aluminum, hafnium, and oxygen exists. Depending on the initial thicknesses of the aluminum oxide layer 8a and the hafnium oxide layer 8b, the duration and temperature of the annealing process, in the final insulating gate structure 8, the initial layered structure may be partially retained (Fig. 2(b)), or alternatively, may be lost (Fig. 2(c)). The annealing process can be carried out by heating the gate stack 8' between 500°C and 950°C, preferably between 600°C and 800°C, for example to an annealing temperature of 800°C. The annealing duration can be between 30 seconds and 600 seconds. However, the annealing temperature and the annealing duration are selected to avoid crystallization of the insulating gate structure 8 due to the diffusion and mixing of aluminum oxide and hafnium oxide. The dielectric constant and crystallization temperature of the insulating gate structure 8 are intermediate between those of aluminum oxide and those of hafnium oxide. Therefore, the insulating gate structure 8 has a satisfactory dielectric constant value and, at the same time, can withstand, for example, the thermal stress generated during the manufacturing process of the power device for the formation of ohmic contacts without structural deformation. Since the gate structure does not need to be protected from exposure to high temperatures, it is possible to optimize the process flow so as to avoid unnecessary processes, for example by reducing the number of photolithography steps.

[0015] FIG. 3 shows a HEMT device 10 comprising the insulating gate structure obtained as described above. The HEMT device 10 includes a substrate 12 made of, for example, silicon or silicon carbide (SiC) or aluminum oxide (Al 23 and a channel layer 14 made of intrinsic gallium nitride (GaN) extending on the substrate 12, and a layer made of intrinsic aluminum gallium nitride (AlGaN) or Al x a 1-x , AlInGaN, In x a1-x , Al x n 1-x The system includes a barrier layer 16 made of a compound based on a tertiary or quaternary alloy of gallium nitride such as l, an insulating gate structure 17 extending on the surface 16a of the barrier layer 16 opposite to the channel layer 14, and a gate electrode 18 extending over the insulating gate structure 17 between the source electrode 20 and the drain electrode 22.

[0016] The channel layer 14 and the barrier layer 16 form a heterostructure 13, which has a heterojunction 13a at its interface with each other. Therefore, the heterostructure 13 extends between the bottom side of the channel layer 14, which is part of the interface with the substrate 12 located below, and the upper side 16a of the barrier layer 16.

[0017] The substrate 12, channel layer 14, and barrier layer 16 will collectively be referred to as the semiconductor structure 15. The active region 13a defined within the semiconductor structure 15 accommodates the conductive channel of the HEMT device 10 during use. In the embodiment shown in Figure 3, the gate electrode 18 extends over the insulated gate structure 17 in the zone corresponding to the active region 13a.

[0018] The insulated gate structure 17, provided as illustrated with reference to Figures 2(a)-(c), comprises a mixture of aluminum, hafnium, and oxygen. More specifically, the insulated gate structure 17 is obtained by alternating conformal deposition (deposition) of multiple aluminum oxide layers 17a and multiple hafnium oxide layers 17b having a thickness of nanometers or sub-nanometers, followed by an annealing process. The aluminum oxide layers 17a and hafnium oxide layers 17b are amorphous, i.e., non-crystalline.

[0019] In further embodiments not shown, the semiconductor body 15 and the wells therein, which serve as active regions 13a, can be appropriately doped or have a single or multiple layers of intrinsic GaN or GaN alloy, depending on design preferences.

[0020] In the embodiment shown in Figure 3, the source region 20 and drain region 22, which are made of a conductive material such as a metal, extend exclusively through the insulating gate layer 17 until they reach the surface 16a of the barrier layer 16, without penetrating deeply into the barrier layer 16.

[0021] In an embodiment not shown, the source region 20 and the drain region 22 extend over a portion of the thickness of the barrier layer 16 and terminate within the barrier layer 16.

[0022] In a further embodiment not shown, the source region 20 and the drain region 22 extend deep into the semiconductor body 15, completely penetrating the barrier layer 16, and terminating at the interface between the barrier layer 16 and the channel layer 14.

[0023] In a further embodiment not shown, the source region 20 and the drain region 22 further extend partially through the channel region 14 and terminate within the channel layer 14.

[0024] An example of a manufacturing method (process) for the HEMT device 10 will be described below with reference to Figure 4-9.

[0025] Referring first to Figure 4, the semiconductor wafer 30 is made of, for example, silicon or silicon carbide (SiC) or aluminum oxide (Al 23 The substrate 12 is made of the following materials. A channel layer 14 of gallium nitride (GaN) and a barrier layer 16 of aluminum gallium nitride (AlGaN) are formed on the substrate 12, extending over the channel layer 14. As described above, the barrier layer 16 and the channel layer 14 form a heterostructure 13 and a heterojunction 13a.

[0026] Next, as explained with reference to Figure 2(a), a gate stack 17' is formed. In particular, the gate stack 17' is obtained by alternately conformally depositing (depositing) multiple aluminum oxide layers 17a and multiple hafnium oxide layers 17b (HfO2), each having a nanometer thickness, until the desired overall thickness is reached. The aluminum oxide layers 17a and hafnium oxide layers 17b are amorphous and formed by atomic layer deposition (ALD), a method that ensures conformal properties of the structure and extremely precise thickness control.

[0027] Subsequently (Figure 5), for example, a first sacrificial layer 25 of resist is formed on the gate stack 17' and its shape is defined by a first photolithography process. The first sacrificial layer 25 has openings 26 for forming the source electrode 20 and the drain electrode 22. The first sacrificial layer 25 is used as a mask for selectively etching the gate stack 17' through the openings 26.

[0028] Referring to Figure 6, following the deposition of the metal layer or multilayer and the lift-off of the first sacrificial layer 25, the source electrode 20 and drain electrode 22 are formed at positions corresponding to the respective openings 26.

[0029] Next, an annealing process is carried out at a temperature between 500°C and 950°C, preferably between 600°C and 800°C, in order to form ohmic contacts. Simultaneously, the adjacent aluminum oxide layer 17a and hafnium oxide layer 17b diffuse to each other at their respective interfaces, and an insulating gate structure 17 is formed from the remaining portion of the gate laminate 17', as shown in Figure 7. The number and thickness of the aluminum oxide layers 17a and hafnium oxide layers 17b, the annealing temperature, and the annealing period are selected according to design requirements so that the insulating gate structure 17 retains traces of the starting layers 17a and 17b (as in the example in Figure 2(b)) or does not retain them (as in the example in Figure 2(c)), and crystallization is avoided.

[0030] Next, a second sacrificial layer 27 (Figure 8) is formed on the insulated gate structure 17, the source electrode 20, and the drain electrode 22, and its shape is defined by a second photolithography process. The second sacrificial layer 27 has an opening 28 for forming the gate electrode 18.

[0031] Following the deposition of the metal layer or multilayer and the lift-off of the second sacrificial layer 27 by (plasma or wet) etching, the gate electrode 18 is formed at the position corresponding to the opening 28. Optionally, a further annealing process can be performed after the deposition of the metal layer or multilayer, for example at 400°C.

[0032] After the conventional (not shown) final processing steps and dicing of the semiconductor wafer 30, the HEMT apparatus 10 shown in Figure 3 is obtained.

[0033] During the annealing period, the diffusion of the aluminum oxide layer 17a and the hafnium oxide layer 17b avoids crystallization of the material during the subsequent high-temperature processing step, resulting in a single intrinsic Al 23 This makes it possible to maintain a typically intermediate high dielectric constant value between that of HfO2. In particular, its resistance to high temperatures allows for the formation of the gate laminate 17' before forming the source and drain electrodes, each with ohmic contacts, without material degradation. Thus, a single photolithography process and a single annealing process can be used to define the insulated gate structure 17 and form the source and drain electrodes, each with ohmic contacts.

[0034] In the case of Figure 9, which represents a different embodiment, the gate region indicated by reference numeral 38 can be of the recessed type, and the insulating gate structure 40 is not flat. In this case, the barrier layer 16 is selectively plasma-etched to open the trench 41 before forming the insulating multilayer 40' conformally attached by ALD (Figure 10).

[0035] Referring to Figure 11, the vertical MOSFET 100 includes a silicon carbide (SiC) semiconductor structure 102, with a drain electrode 100a on the back side 102a of the semiconductor structure 102 and a source electrode 100b and gate electrode 100c on the front side 102b of the semiconductor structure 102. The semiconductor structure 102 includes a substrate 103 (one of which defines the back side 100a) and an epitaxial layer 105 (one of which defines the front side 102b of the semiconductor structure 102), both of which have a first conductivity type, for example, N-type. However, the N-type SiC substrate 103 has an even higher first doping level (for example, 10 18 Number of children / cm 3 The upper layer has a lower second doping level (for example, 10 15 10 16 Number of children / cm 3 It has.

[0036] Here, the body well 107, which has a second conductivity type that is P-type, is formed inside the epitaxial layer 108 and contains a source region 108 of a first conductivity type that is N+ in particular and a contact region 109 of a second conductivity type that is P+ in particular and adjacent to each source region 108. The epitaxial layer 105 defines a current spread layer (CSL), in which the body well 107 is embedded.

[0037] The body wells 107 are typically separated from each other by a distance of less than 1 μm, for example, 0.6 μm. The portions of the body wells 107 and the epitaxial layer 105 present between them form a parasitic JFET region.

[0038] The insulated gate structure 110 extends on the front side 102a of the semiconductor structure 102 over the epitaxial layer 105 (or, if present, over the enhancement layer 6) between the source regions 108, and a gate electrode 100c is provided thereon. The insulated gate structure 110, provided as already illustrated with reference to Figures 2(a)-(c), comprises a mixture of aluminum, hafnium, and oxygen. More specifically, the insulated gate structure 110 is obtained by alternating conformal deposition of a plurality of aluminum oxide layers and a plurality of hafnium oxide layers having a thickness of nanometers or sub-nanometers, followed by an annealing process.

[0039] Referring to Figures 12 to 16, an example of a process (method) for manufacturing the MOSFET 100 is described below.

[0040] First, referring to Figure 12, the semiconductor wafer 130 has a substrate 103 on which an epitaxial layer 105 is grown to form a semiconductor structure 102. Subsequently, body wells 107, source regions 108, and contact regions 109 are formed by ion implantation of different doping species. After the ion implantation, an activation annealing process is carried out at a high temperature, for example, exceeding 1600°C.

[0041] Next, referring to Figure 13, a gate stack 110' is formed as described with reference to Figure 2(a). In particular, the gate stack 110' is obtained by the alternating conformal deposition (deposition) of multiple aluminum oxide layers 110a and multiple hafnium oxide layers 110b, each having a nanometer thickness, until the desired overall thickness is reached. The aluminum oxide layers 110a and hafnium oxide layers 110b are formed by atomic layer deposition (ALD).

[0042] As shown in Figure 14, a first sacrificial layer 112 of resist is formed on the gate stack 110' and its shape is defined by a first photolithography process. The first sacrificial layer 112 has an opening 113 for forming the source electrode 100b and is used as a mask for selectively etching the gate stack 110'.

[0043] Referring to Figure 15, following the deposition of a metal layer or multilayer on the front side 102b of the semiconductor structure 102 and the lift-off of the first sacrificial layer 112, source electrodes 100b are formed at positions corresponding to each opening 113. Simultaneously with or after deposition on the front side 102b, a metal layer or multilayer is deposited on the back side 102a of the semiconductor structure 102 to form a drain electrode 100a. Before depositing the drain electrode 100a, the substrate 103 can be mechanically thinned (polished) and exposed to laser annealing.

[0044] Once the drain electrode 100a and source electrode 100b are formed, an annealing process is carried out, for example, at an annealing temperature of 800 degrees for silicide formation. In this process, the gate laminate 110' is heated to the annealing temperature, and the aluminum oxide 110a and hafnium oxide 110b of the gate laminate 110' diffuse and mix at the interface. Thus, at least at the interface, a mixture of aluminum, hafnium, and oxygen is present. Depending on the initial thickness of the aluminum oxide layer 8 and the hafnium oxide layer 8b, the duration and temperature of the annealing process, the initial layered structure may be partially maintained in the final insulated gate structure 110 (as in the example in Figure 2(b)) or, alternatively, lost (as in the example in Figure 2(c)).

[0045] After annealing, referring to Figure 16, a metal layer or multilayer 115 of a different material from the material used for the source electrode 100b is deposited on the insulated gate structure 110 and on the source electrode 100b, and then a second sacrificial layer 120 of resist is formed on a portion of the metal layer or multilayer 115 and its shape is defined by a second photolithography process. The second sacrificial layer 120 has an opening 121 for forming the gate electrode 100c. The second sacrificial layer 120 is used as a mask for selectively etching the metal layer or multilayer 115 through the opening 121, for example by plasma etching. Thus, the gate electrode 100c is obtained.

[0046] After a conventional and not-shown final processing step and dicing of the semiconductor wafer 30, the MOSFET 100 shown in Figure 11 is obtained.

[0047] The insulated gate structure 117 and its manufacturing method (process) described above offer two advantages, for example, enabling the use of a high dielectric constant dielectric as a gate insulator in a SiCMOSFET instead of silicon oxide. Specifically, on the one hand, the high dielectric constant allows for the localization of the highest electric field value within the epitaxial layer 105. Thus, it is possible to optimize both the thickness of the same epitaxial layer 105 and the on-state resistance RON. On the other hand, the process is simplified because the post-annealing step after oxide oxidation at high temperatures (1100-1200°C) is eliminated.

[0048] Although specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and it is of course possible to make various modifications and alterations without departing from the technical scope of the present invention.

Claims

1. In wide bandgap transistors, a semiconductor structure (2; 15; 102) including at least one wide bandgap semiconductor layer (14, 16; 103, 105) of gallium nitride (GaN) or silicon carbide (SiC); Insulated gate structure (8; 17; 110), a gate electrode (7; 18; 100c) spaced from the semiconductor structure (2; 15; 102) by the insulated gate structure (8; 17; 110); wherein the insulated gate structure (8; 17; 110) comprises a mixture of aluminum, hafnium and oxygen.

2. 2. The transistor of claim 1, wherein the semiconductor structure (15) comprises a heterostructure (13) including a channel layer (14) of gallium nitride (GaN) and a barrier layer (14) of a material selected from the group consisting of aluminum gallium nitride (AlGaN) and a ternary alloy of aluminum and gallium, or a quaternary alloy of aluminum and gallium, with a heterojunction (13a) formed at an interface between the channel layer (14) and the barrier layer (16).

3. The semiconductor structure (102) a silicon carbide (SiC) substrate (103) having a conductivity type and a first doping level; an epitaxial layer (105) of silicon carbide (SiC) having said conductivity type and a second doping level lower than said first doping level; 2. The transistor of claim 1, comprising:

4. The insulated gate structure (8; 17; 110) is made of aluminum oxide (Al ２ O ３ and a plurality of first regions (2a; 17a) including hafnium oxide (HfO ２ 4. A transistor according to claim 1, wherein the second region (2b:17b) is at least partially layered.

5. 5. A transistor according to claim 4, wherein the first region (2a; 17a) and the second region (2b; 17b) have a thickness between 1 nm and 5 nm.

6. 2. A transistor according to claim 1, wherein said insulated gate structure (8; 17; 110) is amorphous.

7. 1. A method of fabricating a wide bandgap transistor, comprising: forming a semiconductor structure (2; 15; 102) including at least one wide bandgap semiconductor layer (14, 16; 103, 105) of gallium nitride (GaN) or silicon carbide (SiC); forming an insulated gate structure (8; 17; 110) on said semiconductor structure (2; 15; 102); forming a gate electrode (7; 18; 100c) on the insulated gate structure (8; 17; 110); wherein the insulated gate structure (8; 17; 110) comprises a mixture of aluminum, hafnium and oxygen.

8. forming the semiconductor structure (2; 15; 102), 8. The method of claim 7, comprising forming a heterostructure (13) comprising a gallium nitride (GaN) channel layer (14) and an aluminum gallium nitride (AlGaN) barrier layer (16), with a heterojunction (13a) formed at an interface between the channel layer (14) and the barrier layer (16).

9. forming the semiconductor structure (102) forming a substrate (103) of silicon carbide (SiC) having a conductivity type and a first doping level; forming an epitaxial layer (105) of silicon carbide (SiC) having said conductivity type and a second doping level lower than said first doping level; 8. The method of claim 7, comprising:

10. forming the insulated gate structure (8; 17; 110); depositing a plurality of aluminum oxide layers (8a; 17a; 110a) and a plurality of hafnium oxide layers (8b; 17b; 110b) in alternating succession to form a gate stack (8'; 17'; 110'); and carrying out annealing so as to diffuse and mix the aluminum oxide of the aluminum oxide layer (8a; 17a; 110a) and the hafnium oxide of the hafnium oxide layer (8b; 17b; 110b) at the interface between the adjacent aluminum oxide layer (8a; 17a; 110a) and hafnium oxide layer (8b; 17b; 110b); 10. The method of any one of claims 7 to 9, comprising:

11. Performing annealing 11. A method according to claim 10, comprising heating the gate stack (8'; 17'; 110') to an annealing temperature for an annealing period, the annealing temperature and the annealing period being selected to prevent the insulated gate structure (8; 17; 110) from crystallizing.

12. 11. A method according to claim 10, wherein the temperature is between 500 and 950°C, preferably between 600 and 800°C, and the annealing duration is between 30 and 600 seconds.

13. 11. The method of claim 10, wherein the successively depositing comprises depositing by atomic layer deposition (ALD).

14. 11. A method according to claim 10, wherein the aluminium oxide layer (8a; 17a; 110a) and the hafnium oxide layer (8b; 17b; 110b) have a thickness between 0.5 nm and 10 nm.

15. 11. A method according to claim 10, comprising forming at least one source electrode (3; 20; 100b) and drain electrode (4; 20; 100a) after forming the gate stack (8'; 17'; 110').

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