RC snubber with poly silicon resistor and capacitor formed from junction termination edge

Abstract

To provide an apparatus damping oscillations within a semiconductor device.SOLUTION: An apparatus 200 includes a junction termination edge 260, and a unipolar power transistor and an RC snubber 201 which are coupled in parallel. The RC snubber 201 has a capacitor 220 between a poly silicon structure 221 and a semiconductor substrate 212, the capacitor being part of the junction termination edge 260. The capacitor 220 has a p-n junction. The RC snubber 201 has a poly silicon resistor 218 between a source 244 of the unipolar power transistor and a first layer 214 forming the capacitor 220. The unipolar transistor and the RC snubber 201 are coupled in parallel. The RC snubber 201 and the unipolar power transistor are formed monolithically on the semiconductor substrate 212.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to the field of damping vibrations in semiconductor devices. [Background technology]

[0002] Various types of transistors, such as silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) and other types of transistors, can be used for applications in the high power and high voltage range, for example, in traction and wind energy applications. Such applications can utilize high currents and large power modules or parallel-connected modules. The operation of these transistors can result in relatively high commutation inductances, for example, in the range of 20 nH to 100 nH per commutation path. If the load current is rapidly switched off in one of these transistors, commutation oscillations can be triggered. Commutation oscillations can result in electromagnetic interference and / or non-compliance with electromagnetic interference limits. This type of commutation oscillation is undesirable for applications utilizing high load currents. Summary of the Invention [Problem to be solved by the invention]

[0003] This Summary is provided to guide a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Means for solving the problem]

[0004] In one embodiment of the technology presented herein, an apparatus is provided. The apparatus includes a junction termination edge. The apparatus includes a unipolar power transistor. The apparatus includes an RC snubber coupled in parallel within the unipolar power transistor. The RC snubber and the unipolar power transistor are monolithically formed on a semiconductor substrate. The RC snubber includes a capacitor. The capacitor is between a polysilicon structure and the semiconductor substrate and is part of the junction termination edge. The capacitor includes a pn junction. The RC snubber includes a polysilicon resistor. The polysilicon resistor is between a source of the unipolar power transistor and a first layer forming the capacitor.

[0005] To the accomplishment of the foregoing and related ends, the following description and the annexed drawings set forth certain illustrative aspects and implementations, which are indicative of but some of the various ways in which the one or more aspects may be employed. Other aspects, advantages and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a component block diagram illustrating an apparatus comprising a half-bridge including two transistors, each coupled in parallel to an RC snubber formed on the same semiconductor substrate. [Figure 2] 1 is a cross section of a device comprising a transistor coupled in parallel to an RC snubber formed on the same semiconductor substrate. [Figure 3] FIG. 1 is a plan view of a device comprising a transistor coupled in parallel to an RC snubber formed on the same semiconductor substrate. [Figure 4] FIG. 1 is a plan view of a device comprising a transistor coupled in parallel to an RC snubber formed on the same semiconductor substrate. DETAILED DESCRIPTION OF THE INVENTION

[0007] The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be apparent, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing the claimed subject matter.

[0008] In the field of electronics, transistors such as silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs), silicon carbide junction gate field effect transistors (SiC JFETs), unipolar power transistors, etc., may be used for switching in various applications, such as high power and / or high voltage applications. When a device's transistor is switched, it may trigger commutation oscillations, thus causing unwanted vibrational energy within the device that can adversely affect the device's operation. For example, when a transistor is used as a power transistor with a high voltage (e.g., voltages above 600 volts), commutation oscillations are triggered, and switching off the transistor is very fast, resulting in commutation oscillations. These commutation oscillations may be high-frequency LC oscillations that adversely affect the device's operation. For example, commutation oscillations may result in electromagnetic interference (EMI) that affects the proper operation of the device. In one example of EMI, a transistor may initially be in an off state. While in the on state, the drain and source voltages of the transistor are low. When the transistor is switched off, the voltage begins to increase until it reaches a DC voltage. The current begins to decrease during normal operating mode and therefore oscillations begin to occur, which cause undesirable electromagnetic interference.

[0009] One technique for damping commutation oscillations within a device involves using insulated gate bipolar transistor (IGBT) components or unipolar components, such as SiC MOSFETs, that can operate with high gate resistance values. However, this can result in increased switching losses that adversely affect the overall efficiency of the device. Another technique that can be used to help damp commutation oscillations within a device involves the use of RC networks / snubbers. RC snubbers can be used in power electronics to react to high-frequency LC oscillations and damp these types of oscillations. The capacitor in the RC snubber induces current through a resistor to damp the oscillations, which also results in unacceptable losses. These RC snubbers are external to the transistor being damped, for example, on the load connection or on the auxiliary connection. This creates a leakage inductance (parasitic inductance) between the RC snubber and the transistor (chip).

[0010] Therefore, as provided herein, an RC snubber is incorporated into a device to damp oscillations of the device's unipolar power transistor. The RC snubber and the unipolar power transistor are coupled together in parallel. The RC snubber and the unipolar power transistor are monolithically formed on the same semiconductor substrate, and thus the RC snubber and the unipolar power transistor are incorporated together in the same semiconductor device; for example, the resistor (polysilicon resistor) and capacitor of the RC snubber are formed from the layer of material that forms the unipolar power transistor, and thus the RC snubber is formed as part of the unipolar power transistor. In addition, the capacitor may be formed as part of the junction termination edge of the device; for example, the p-type material of the junction termination edge forms the capacitor. Because the RC snubber is incorporated into the device and formed on the same semiconductor substrate as the unipolar power transistor, the RC snubber can be positioned closer to (as part of) the unipolar power transistor than if the RC snubber were external to the unipolar power transistor. This provides improved damping of oscillations and reduces leakage inductance that would otherwise result from an RC snubber external to the device and unipolar power transistor. Because the RC snubber is integrated into the unipolar power transistor, less area in the device is consumed by the RC snubber. Integrating the RC snubber into the unipolar power transistor allows scaling out for devices with a large number of unipolar power transistors, because each unipolar power transistor has its own integrated RC snubber.

[0011] The disclosed RC snubber offers various advantages over external RC snubbers and other techniques used to damp oscillations, such as oscillations in applications with a high L×I product, where L×I corresponds to the product of the commutation inductance (e.g., inductance 102 in FIG. 1 ) and the current flowing through it. With this RC snubber, there are no additional / external components used as an RC snubber because the RC snubber is integrated into the device and the unipolar power transistor. Because the RC snubber is integrated into the unipolar power transistor, e.g., in the area under the gate pad that is already part of the device, very little additional area is consumed by the RC snubber. Because the device is sufficiently cooled, the RC snubber provides dissipation of power losses within the RC snubber. Because the RC snubber does not involve parasitic inductance, it can directly act on and damp oscillations. Because the RC snubber is integrated into each device / transistor, the RC snubber scales with the number of parallel devices / transistors in the module.

[0012] In one embodiment, the resistor of the RC snubber is a polysilicon resistor comprising polysilicon. Polysilicon resistors provide improved isolation compared to resistors formed from other types of materials. Polysilicon resistors can also sustain higher overshoot voltages than resistors formed from other types of materials. In one embodiment, the polysilicon resistor has a resistance value between about 90 ohms and about 110 ohms, for example, about 100 ohms, or any other resistance value.

[0013] In one embodiment, the RC snubber capacitor is formed from the p-type material of the junction termination edge of the device. The junction termination edge provides an edge termination around the main device component of the device, such as a unipolar power transistor. In this manner, the junction termination edge is used to control the electric field at a point within the device. The RC snubber capacitor can be embedded (formed) within the junction termination edge because it surrounds the unipolar power transistor and covers a significant area of ​​the device (e.g., 10% of the area). Thus, the capacitor can be formed from the junction termination edge and have a specific capacitance, such as 10% of the output capacitance of the unipolar power transistor.

[0014] FIG. 1 shows a module 100 including a device with an RC snubber 110. The device further includes a DC link capacitor 104. The DC link capacitor 104 provides a low impedance path for switching current and may be used as an intermediate circuit capacitor to provide energy storage. The module 100 may be connected to a load 120. The module 100 includes a first body diode 108. In one embodiment, the module 100 includes a first unipolar power transistor, and the first body diode 108 is between the drain and source of the first unipolar power transistor. The first body diode 108 is formed by the pn junction of the first unipolar power transistor between its source and drain. The module 100 may include any number of unipolar power transistors, such as a second unipolar power transistor having a second body diode 106 between its drain and source. The second body diode 106 is formed by the pn junction of the second unipolar power transistor between the source and drain of the second unipolar power transistor. The unipolar power transistor of the module 100 selectively couples the load 120 to one of a DC link potential 122 or ground 124. The DC link potential may be 600 V, 1200 V, 1800 V, or even 3.3 kV or higher in some embodiments. Ground 124 may be 0 V or even below 0 V in some embodiments. The module 100 has a parasitic inductance corresponding to an inductance 102, e.g., the inductance of the connection between the DC link capacitor 104 and the module 100.

[0015] In one embodiment, the first unipolar power transistor and / or the second unipolar power transistor are SiC MOSFET transistors. In one embodiment, the first unipolar power transistor and / or the second unipolar power transistor are SiC JFET transistors. In one embodiment, the first unipolar power transistor and / or the second unipolar power transistor are three-terminal transistors because the RC snubber is integrated into the unipolar power transistor without requiring an additional terminal for connecting to an external RC snubber.

[0016] The module 100 may include any number of RC snubbers 110, such as a first RC snubber 111 integrated within a first unipolar power transistor and coupled in parallel to the first unipolar power transistor, and a second RC snubber 113 integrated within a second unipolar power transistor and coupled in parallel to the second unipolar power transistor. The first RC snubber 111 and the first unipolar power transistor are monolithically formed on a first semiconductor substrate. In one embodiment, the first semiconductor substrate comprises a silicon carbide substrate. In one embodiment, the first semiconductor substrate comprises a gallium nitride substrate. The second RC snubber 113 and the second unipolar power transistor are monolithically formed on a second semiconductor substrate. In one embodiment, the second semiconductor substrate comprises a silicon carbide substrate. In one embodiment, the second semiconductor substrate comprises a gallium nitride substrate.

[0017] The first RC snubber 111 includes a first capacitor 114 and a first resistor 112, e.g., a polysilicon resistor. The first capacitor 114 is located between a polysilicon structure of the first unipolar power transistor and a first semiconductor substrate. The polysilicon structure may be connected to the source of the first unipolar power transistor. The polysilicon structure separates the drain of the first unipolar power transistor from the gate of the first unipolar power transistor. The first capacitor 114 includes a p-n junction, e.g., a p-n junction of the first unipolar power transistor, that forms the first body diode 108. The p-n junction may include a first layer comprising p-type material and a second layer comprising n-type material. The second layer is located between the first layer and the second semiconductor substrate. The first capacitor 114 is located on the output side of the first unipolar power transistor. The first capacitor 114 may be formed as part of a junction termination edge of the module 100. In one embodiment, the first capacitor 114 is formed from the p-type material of the junction termination edge.

[0018] The first resistor 112 is located between the source of the first unipolar power transistor and the first layer forming the first capacitor 114. In one embodiment, the first resistor 112 and the first capacitor 114 are electrically coupled to each other. In one embodiment, the first resistor 112 is coupled to a snubber electrode of the first RC snubber 111 by a snubber contact, and the first resistor 112 connects the snubber electrode to the first layer. In one embodiment, the first resistor 112 includes a polysilicon structure, and the first resistor 112 is formed between the snubber electrode and the first layer. In one embodiment, the first resistor 112 is connected to the source of the first unipolar power transistor by a source contact. In one embodiment, the first resistor 112 is connected to a test pad by a test pad contact, and the first resistor 112 can be measured using the test pad contact.

[0019] The second RC snubber 113 includes a second capacitor 118 and a second resistor 116, e.g., a polysilicon resistor. The second capacitor 118 is located between the polysilicon structure of the second unipolar power transistor and the second semiconductor substrate. The polysilicon structure may be connected to the source of the second unipolar power transistor. The polysilicon structure separates the drain of the second unipolar power transistor from the gate of the second unipolar power transistor. The second capacitor 118 includes a p-n junction, e.g., a p-n junction of the second unipolar power transistor, forming the second body diode 106. The p-n junction may include a first layer comprising p-type material and a second layer comprising n-type material. The second layer is located between the first layer and the second semiconductor substrate. The second capacitor 118 is located on the output side of the second unipolar power transistor. The second capacitor 118 may be formed as part of the junction termination edge of the module 100. In one embodiment, the second capacitor 118 is formed from the p-type material of the junction termination edge.

[0020] The second resistor 116 is located between the source of the second unipolar power transistor and the first layer forming the second capacitor 118. In one embodiment, the second resistor 116 and the second capacitor 118 are electrically coupled to each other. In one embodiment, the second resistor 116 is coupled to a snubber electrode of the second RC snubber 113 by a snubber contact, and the second resistor 116 connects the snubber electrode to the first layer. In one embodiment, the second resistor 116 includes a polysilicon structure, and the second resistor 116 is formed between the snubber electrode and the first layer. In one embodiment, the second resistor 116 is connected to the source of the second unipolar power transistor by a source contact. In one embodiment, the second resistor 116 is connected to a test pad by a test pad contact, and the second resistor 116 can be measured using the test pad contact.

[0021] In one embodiment, the module 100 may include an RC snubber layer. The RC snubber layer may include an RC snubber used to damp oscillations in a unipolar power transistor. The RC snubber layer may include multiple resistors, such as polysilicon resistors. To distribute losses from the RC snubber, the resistors may be implemented as a resistive bridge positioned around one or more sides of the gate pad of the unipolar power transistor, distributing the resistance and thereby distributing losses from the RC snubber that damps oscillations.

[0022] It should be appreciated that with reference to Figures 2-4, an embodiment of an RC snubber incorporated within a unipolar power transistor is further described.

[0023] 2 shows a cross section of device 200 including an RC snubber 201, which is integrated into a unipolar power transistor of device 200. Device 200 includes an active trench transistor cell region 202 in which one or more unipolar power transistors are located. In one embodiment, a source 244 of the unipolar power transistor is located within active trench transistor cell region 202. Device 200 includes a gate pad region 204 in which a gate pad for a gate 207 of device 200 is formed. Device 200 includes a semiconductor substrate 212. In one embodiment, semiconductor substrate 212 includes a silicon carbide substrate. In one embodiment, the silicon carbide substrate includes an n + In one embodiment, the semiconductor substrate 212 comprises a gallium nitride substrate. It should be appreciated that the semiconductor substrate 212 may comprise other materials.

[0024] Apparatus 200 includes a first layer 214. In one embodiment, first layer 214 is a drift zone layer, e.g., an n-drift zone layer. In one embodiment, first layer 214 is positioned on a semiconductor substrate 212 of apparatus 200. In one embodiment, first layer 214 is an n-doped drift zone comprising n-type material. In one embodiment, first layer 214 is an n-type layer that forms a portion of capacitor 220 of RC snubber 201.

[0025] The device 200 includes a second layer 210. In one embodiment, the second layer 210 is an anode layer, e.g., a p + The second layer 210 is a p-type anode layer. In one embodiment, the second layer 210 is connected to the source 244. In one embodiment, the second layer 210 is positioned on the first layer 214 of the device 200. In one embodiment, the second layer 210 is a p-type layer that forms a portion of the capacitor 220 of the RC snubber 201. In this manner, the first layer 214 as an n-type layer and the second layer 210 as a p-type layer form a p-n junction of the capacitor 220 of the RC snubber 201. The p-n junction protects the drain 242 of the unipolar power transistor of the device 200. In one embodiment, the device 200 includes a junction termination edge 260. In one embodiment, the junction termination edge 260 includes a p-type material. The capacitor 220 may be formed from the junction termination edge 260, for example, the capacitor 220 may be formed from the p-type material of the junction termination edge 260. In this manner, capacitor 220 of RC snubber 201 may be embedded within (or form part of) junction termination edge 260 because junction termination edge 260 surrounds the unipolar power transistor and covers a significant area (e.g., 10% of the area) of device 200. Thus, capacitor 220 can be formed from junction termination edge 260 and have a particular capacitance, such as 10% of the output capacitance of the unipolar power transistor.

[0026] The device 200 includes a third layer 222. In one embodiment, the third layer 222 is a gate oxide layer. In one embodiment, the third layer 222 includes a gate oxide material, such as a silicon dioxide material, a high-k material, a dielectric material, etc. In one embodiment, the third layer 222 is positioned on the second layer 210.

[0027] The device 200 includes a polysilicon structure 221, e.g., an s-poly plate. In one embodiment, the polysilicon structure 221 is positioned on a third layer 222, e.g., a gate oxide layer. In one embodiment, the polysilicon structure 221 is positioned within the gate pad region 204. In one embodiment, the polysilicon structure 221 is used to separate the drain 242 of the unipolar power transistor from the gate 207 of the unipolar power transistor. In one embodiment, the gate 207 includes a conductive material. In one embodiment, the conductive material includes aluminum copper (AlCu) or other metallic or conductive material. In one embodiment, the polysilicon structure 221 is connected to a source snubber potential (Ssn). In one embodiment, the resistor 218 is a polysilicon resistor, which is formed as part of the polysilicon structure 221 and / or as part of the other polysilicon material 266. In one embodiment, resistor 218 is coupled to snubber electrode 261 of RC snubber 201 by snubber contact 264, and resistor 218 connects snubber electrode 261 to second layer 210. In one embodiment, resistor 218 is formed between snubber electrode 261 and second layer 210. In one embodiment, second layer 210 is connected to source 244 of first unipolar power transistor through resistor 218 and source contact 262, and source contact 262 connects resistor 218 to source 244. In one embodiment, resistor 218 is connected to a test pad by a test pad contact, and resistance 218 can be measured using the test pad contact. In one embodiment, resistor 218 has a resistance value between about 90 ohms and about 110 ohms, for example, about 100 ohms, or any other resistance value.

[0028] The device 200 comprises an interlayer dielectric (ILD) layer 208. In one embodiment, the ILD layer 208 comprises a low-k material, for example, a material having a k value (dielectric constant) below about 3.9. Some low-k materials have k values ​​below about 3.5, and may have k values ​​below about 2.5. Some examples of low-k materials are SiO x C y H z , SiO x , SiCN, oxygen-doped SiC (ODC), nitrogen-doped SiC (NDC), tetraethyl orthosilicate (TEOS), or other suitable material, where x, y, and z are integers greater than or equal to 1. In one embodiment, a portion of ILD layer 208 in gate pad region 204 is positioned between gate 207 of the unipolar power transistor and polysilicon structure 221. In one embodiment, another portion of ILD layer 208 in active trench transistor cell region 202 is positioned on polysilicon trench gate structure 224 in active trench transistor cell region 202. In one embodiment, the polysilicon trench gate structure 224 in the active trench transistor cell region 202 is positioned between the ILD layer 208 and the third layer 222 (e.g., a gate oxide layer), e.g., the ILD layer 208 is positioned adjacent to the top surface of the polysilicon trench gate structure 224 and the third layer 222 (e.g., the gate oxide layer) is positioned adjacent to one or more of the bottom surface, first side surface, and / or second side surface of the polysilicon trench gate structure 224.

[0029] The device 200 includes a source structure 206. In one embodiment, the source structure 206 includes a source 244 of a unipolar power transistor. In one embodiment, the source structure 206 includes a conductive material. In one embodiment, the conductive material includes aluminum copper (AlCu) or other metallic or conductive material. In one embodiment, a first dimension (e.g., height) of the source structure is between about 3 μm and about 7 μm, such as about 5 μm or any other size. In one embodiment, a portion of the source structure 206 in the active trench transistor cell region 202 is positioned on a polysilicon trench gate structure 224. In one embodiment, another portion of the source structure 206, such as a source snubber potential (Ssn), is positioned between the source 244 of the unipolar power transistor and the gate 207 of the unipolar power transistor.

[0030] The device 200 includes a contact metal structure 232. In one embodiment, the contact metal structure 232 is positioned within the active trench transistor cell region 202. In one embodiment, the contact metal structure 232 is positioned within the active trench transistor cell region 202 between portions of the ILD layer 208 that cover the polysilicon trench gate structure 224.

[0031] The apparatus 200 includes a source material structure 230. In one embodiment, the source material structure 230 includes n + In one embodiment, the source material structure 230 is positioned within the active trench transistor cell region 202 beneath one or more contact metal structures 232.

[0032] The device 200 includes a body structure 228. In one embodiment, the body structure 228 includes a p - In one embodiment, the body structure 228 is positioned within the active trench transistor cell region 202 below the source material structure 230.

[0033] The apparatus 200 includes a structure 226. In one embodiment, the structure 226 includes n - In one embodiment, structure 226 is positioned below body structure 228 within active trench transistor cell region 202.

[0034] In one embodiment, source material structure 230, body structure 228, and structure 226 form an npn structure that is used as a channel for a unipolar power transistor through which current can flow.

[0035] The device 200 includes an RC snubber 201, which is integrated into and formed as part of the device 200 and the unipolar power transistor. The RC snubber 201 and the unipolar power transistor are coupled in parallel. In particular, the RC snubber 201 and the unipolar power transistor are monolithically formed on a semiconductor substrate 212. That is, the RC snubber 201 and the unipolar power transistor are formed on the same semiconductor substrate 212. The RC snubber 201 includes a resistor 218 and a capacitor 220. In one embodiment, the resistor 218 includes a polysilicon material 266, which may be connected to the source 244 of the unipolar power transistor (e.g., connected to a portion of the source structure 206 positioned over the resistor 218). In one embodiment, the resistance value of the resistor 218 and the capacitance Coss of the capacitor 220 (e.g., 20 pF, 50 pF, etc.) can be adjusted using different widths and lengths for the resistor 218.

[0036] In one embodiment, resistor 218 is positioned below source 244 of the unipolar power transistor, e.g., below source structure 206. In one embodiment, resistor 218 is positioned below snubber electrode 261. In one embodiment, resistor 218 may connect source 244 to snubber electrode 261. Resistor 218 may be positioned on second layer 210. Polysilicon material 266 may be part of the unipolar power transistor, and thus RC snubber 201 is incorporated into device 200 as part of the unipolar power transistor. Thus, RC snubber 201 can be formed without additional layers and components within device 200.

[0037] Capacitor 220 is positioned between polysilicon structure 221 and semiconductor substrate 212. In one embodiment, capacitor 220 is formed as part of junction termination edge 260. In one embodiment, capacitor 220 comprises a p-n junction. The p-n junction comprises p-type material of second layer 210 (e.g., an anode layer). The p-n junction comprises n-type material of first layer 214 (e.g., a drift zone layer). The p-n junction is used to protect drain 242 of unipolar power transistor. Capacitor 220 is electrically connected to resistor 218. In this manner, resistor 218 and capacitor 220 of RC snubber 201 are incorporated within device 200 and unipolar power transistor to damp oscillations associated with unipolar power transistors being switched between states; the oscillations would otherwise cause electromagnetic interference that would adversely affect the operation of device 200.

[0038] 3 shows a top view 300 of device 200. In one embodiment, polysilicon material 266 forming resistor 218 is connected to source 244 by source contact 262. Source 244 is part of active transistor region 270 of device 200. In one embodiment, polysilicon material 266 forming resistor 218 is connected to a test pad by test pad contact 304. Resistor 218 may also be connected to or comprise the polysilicon material of polysilicon structure 221. In one embodiment, polysilicon material 266 has a meander shape such that polysilicon material 266 loops back and forth one or more times.

[0039] FIG. 4 shows a plan view 400 of the device 200. The junction termination edge 260 is positioned between the first layer 214 and the second layer 210. The capacitor 220 is formed as part of the junction termination edge 260; for example, the capacitor 220 comprises the p-type material of the junction termination edge 260. The capacitor 220 is formed between the drain 242 and the resistor 218. The capacitor 220 is connected to the resistor 218. The resistor 218 is connected to the source 244. The resistor 218 is formed from a polysilicon material 266. A source contact 262 connects the polysilicon material 266 (and the resistor 218) to a source structure 206. The source structure 206 is between the polysilicon material 266 and the active transistor region 270. A snubber contact 264 connects the polysilicon material 266 (and the resistor 218) to a snubber electrode 261. The resistor 218 is formed on the second layer 210.

[0040] The RC snubber 201 of the device 200 provides improved attenuation of oscillations without using additional components (e.g., components external to the unipolar power transistor). This is because the RC snubber 201 is integrated into the device 200 and the unipolar power transistor (e.g., the resistors and capacitors of the RC snubber 201 are formed from parts of the unipolar power transistor). Because the RC snubber 201 is integrated into the device 200 and the unipolar power transistor, for example, in the area under the gate 207 (gate pad) that is already part of the device 200, very little additional area is consumed by the RC snubber 201. Because the device 200 is sufficiently cooled, the RC snubber 201 provides dissipation of power losses within the RC snubber 201. Because the RC snubber 201 does not include parasitic inductance, it can directly act on and attenuate oscillations. Because an RC snubber is integrated within each device / transistor, the number of RC snubbers 201 corresponds to the number of parallel devices / transistors in the module. Because the RC snubber 201 is integrated within the unipolar power transistor, as opposed to being external to the unipolar power transistor, the leakage inductance that would otherwise occur between an external RC snubber and the unipolar power transistor is reduced or eliminated. The RC snubber 201 also damps the switching behavior of the unipolar power transistor.

[0041] One embodiment of the subject matter of the present disclosure comprises an apparatus comprising: a junction termination edge, a unipolar power transistor, and an RC snubber, the RC snubber being between a polysilicon structure and a semiconductor substrate and being part of the junction termination edge, the RC snubber comprising a capacitor comprising a pn junction, and a polysilicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor, the unipolar power transistor and the RC snubber being coupled in parallel, and the RC snubber and the unipolar power transistor being monolithically formed on the semiconductor substrate.

[0042] According to some embodiments, the semiconductor substrate comprises a silicon carbide substrate.

[0043] According to some embodiments, the pn junction comprises a first layer of p-type material and a second layer of n-type material.

[0044] According to some embodiments, the second layer is between the first layer and the semiconductor substrate.

[0045] According to some embodiments, the polysilicon resistor comprises a polysilicon structure, the polysilicon resistor being between a snubber electrode and the first layer of the snubber.

[0046] According to some embodiments, the polysilicon resistor is connected to a snubber electrode of the snubber by a snubber contact, the polysilicon resistor connecting the snubber electrode to the first layer.

[0047] According to some embodiments, a polysilicon structure separates the drain of the unipolar power transistor from the gate of the unipolar power transistor.

[0048] According to some embodiments, the polysilicon resistor is connected to the source by a source contact.

[0049] According to some embodiments, the resistor is electrically coupled to the capacitor.

[0050] According to some embodiments, the first layer comprises a p-type material.

[0051] According to some embodiments, the unipolar power transistor comprises a three-terminal transistor.

[0052] According to some embodiments, the unipolar power transistor comprises at least one of a silicon carbide metal oxide semiconductor field effect transistor (MOSFET) or a silicon carbide junction gate field effect transistor (JFET).

[0053] According to some embodiments, the capacitor includes a junction termination edge of p-type material.

[0054] According to some embodiments, the semiconductor substrate comprises a gallium nitride substrate.

[0055] According to some embodiments, the apparatus comprises an RC snubber layer, the RC snubber layer comprising an RC snubber and a plurality of resistors, the plurality of resistors comprising a resistor.

[0056] One embodiment of the subject matter of the present disclosure comprises an apparatus comprising: a unipolar power transistor; an RC snubber; the RC snubber being between a polysilicon structure and a semiconductor substrate, the RC snubber comprising a capacitor comprising a pn junction; and a polysilicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor, the unipolar power transistor and the RC snubber being coupled in parallel, and the RC snubber and the unipolar power transistor being monolithically formed on the semiconductor substrate.

[0057] According to some embodiments, the polysilicon resistor comprises a polysilicon structure.

[0058] According to some embodiments, the polysilicon resistor is connected to the source by a source contact and to the snubber electrode of the snubber by a snubber contact.

[0059] According to some embodiments, the polysilicon resistor is connected to a test pad by a test pad contact.

[0060] One embodiment of the subject matter of the present disclosure comprises an apparatus comprising: a junction termination edge, a unipolar power transistor, and an RC snubber, the RC snubber being between a polysilicon structure and a semiconductor substrate and being part of the junction termination edge, the RC snubber comprising a capacitor comprising a pn junction, and a resistor between a source of the unipolar power transistor and a first layer forming the capacitor, the unipolar power transistor and the RC snubber being coupled in parallel, and the RC snubber and the unipolar power transistor being monolithically formed on the semiconductor substrate.

[0061] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0062] As used in the application, the terms "component," "module," "system," "interface," and the like are intended to generally refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution. One or more components may be localized on one computer and / or distributed among two or more computers.

[0063] Furthermore, the claimed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and / or engineering techniques to generate software, firmware, hardware, or any combination thereof, to control a computer to implement the disclosed subject matter. The term "article of manufacture," as used herein, is intended to encompass a computer program accessible from any computer-readable device, carrier, or media. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope or spirit of the claimed subject matter.

[0064] Various operations of embodiments are provided herein. In one embodiment, one or more of the described operations may comprise computer-readable instructions stored on one or more computer-readable media that, when executed by a computing device, cause the computing device to perform the described operations. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily order dependent. Alternative orders will be recognized by those skilled in the art having the benefit of this description. Additionally, it should be understood that not all operations are necessarily present in each embodiment provided herein.

[0065] Any aspect or design described herein as "exemplary" should not be construed as necessarily advantageous over other aspects or designs. Rather, use of the term "exemplary" is intended to present one possible aspect and / or implementation that may belong to the technology presented herein. Such an example is not intended to be required or limiting of such technology. Various embodiments of such technology may include such an example alone or in combination with other features, and / or may vary from and / or omit the illustrated example.

[0066] As used in this application, the term "or" is intended to mean an inclusive "or," rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X uses A or B" is intended to mean any of the natural inclusive permutations. That is, if X uses A, X uses B, or X uses A and B, "X uses A or B" is satisfied under any of the above examples. Additionally, the singular indefinite article used in this application and the appended claims generally may be construed to mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. Also, unless otherwise specified, terms such as "first," "second," etc. are not intended to imply temporal or spatial aspects, order, etc. Rather, such terms are used merely as identifiers, names, etc. for features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, two different elements, two identical elements, or the same element.

[0067] Also, while the disclosure has been illustrated and described with respect to one or more embodiments, equivalent substitutes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. The disclosure includes all such modifications and alternatives and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond to any component that performs the specified function of the described component (e.g., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs that function in the exemplary embodiment of the disclosure set forth herein, unless otherwise specified. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments, as may be desirable or advantageous for any given application or particular use. Furthermore, to the extent that the terms "comprise," "have," or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprises."

Claims

1. a junction termination edge; a unipolar power transistor; RC snubber and An apparatus comprising: The RC snubber is a capacitor between the polysilicon structure and the semiconductor substrate, the capacitor being part of the junction termination edge and comprising a pn junction; a polysilicon resistor between the source of the unipolar power transistor and a first layer forming the capacitor; Equipped with the unipolar power transistor and the RC snubber are coupled in parallel; the RC snubber and the unipolar power transistor are monolithically formed on the semiconductor substrate; Device.

2. 10. The device of claim 1, wherein the pn junction comprises the first layer of p-type material and a second layer of n-type material.

3. The device of claim 2 , wherein the second layer is between the first layer and the semiconductor substrate.

4. 2. The apparatus of claim 1, wherein the polysilicon resistor comprises the polysilicon structure, the polysilicon resistor being between a snubber electrode of the snubber and the first layer.

5. the polysilicon resistor is connected to a snubber electrode of the snubber by a snubber contact, the polysilicon resistor connecting the snubber electrode to the first layer; 10. The apparatus of claim 1.

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