Operation method of power transistor circuit

Abstract

To provide a method.SOLUTION: A method includes switching off a power transistor circuit (1) within an electronic circuit. The electronic circuit includes a power source (2), a load circuit (3), and a power transistor circuit (1) connected between the power source (2) and the load circuit (3). The step of switching off the power transistor circuit (1) includes a step of operating at least one power transistor (10;101, 10n) included in the power transistor circuit (1) in an avalanche mode, and as a result, at least a portion of the energy stored in the electronic circuit before the step of switching off the power transistor circuit (1) is dissipated in the at least one power transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure generally relates to the operation of power transistor circuits. [Background technology]

[0002] Power transistor circuits, which include one or more power transistors, are widely used as electronic switches in various types of electronic circuits. In electronic circuits that include (parasitic) inductance, switching off a power transistor circuit, that is, switching off at least one power transistor in the power transistor circuit, can increase the voltage of the entire power transistor circuit due to the energy stored in the inductance.

[0003] A clamp circuit may be connected in parallel to the power transistor circuit. The clamp circuit is configured to clamp the voltage to a voltage level lower than the breakdown voltage of at least one power transistor, thereby dissipating the energy stored in the inductance. However, the clamp circuit increases the cost and complexity of the overall circuit. [Overview of the Initiative] [Means for solving the problem]

[0004] An example relates to a method. The method includes the step of switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power supply, a load circuit, and a power transistor circuit connected between the power supply and the load circuit. The step of switching off the power transistor circuit includes operating at least one power transistor contained in the power transistor circuit in avalanche mode, so that at least a portion of the energy stored in the electronic circuit before the step of switching off the power transistor circuit is consumed in at least one power transistor.

[0005] Examples will be described below with reference to the drawings. The drawings function to illustrate specific principles, and only the aspects necessary for understanding these principles are shown. The drawings are not to scale. In the drawings, the same reference numerals denote similar features.

Brief Description of the Drawings

[0006] [Figure 1] A circuit diagram of an electronic circuit including a power supply, a load circuit, and a power transistor circuit connected between the power supply and the load circuit is shown. [Figure 2] A signal diagram showing switching off the power transistor circuit is shown, and switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in avalanche mode. [Figure 3] An electronic circuit including a current sensor in addition to the type shown in FIG. 1 is shown. [Figure 4] A signal diagram showing switching off the power transistor circuit in the electronic circuit according to FIG. 3 under an overload condition is shown. [Figure 5] An electronic circuit including a power consumption element connected in parallel to the power transistor circuit in addition to the type shown in FIG. 3 is shown. [Figure 6] A signal diagram showing switching off the power transistor circuit in the electronic circuit according to FIG. 5 under an overload condition is shown. [Figure 7] Various examples of the power transistor circuit are shown. [Figure 8] Various examples of the power transistor circuit are shown. [Figure 9] Various examples of the power transistor circuit are shown. [Figure 10] Various examples of the power transistor circuit are shown. [Figure 11] Various examples of the power transistor circuit are shown. [Figure 12] Various examples of the power transistor circuit are shown. [Figure 13]Shows various examples of a power transistor circuit. [Figure 14] Shows various examples of a power transistor circuit. [Figure 15] Shows an example of a control circuit configured to control a power transistor circuit. [Figure 16] Shows a signal diagram of a drive signal generated by a control circuit according to an example. **Mode for Carrying Out the Invention**

[0007] In the following detailed description, the accompanying drawings are referred to. The drawings form part of the description and show, for the purpose of explanation, examples of how the present invention can be used and implemented. It should be understood that the features of the various embodiments described in this specification may be combined with each other as long as there is no specific description to the contrary.

[0008] FIG. 1 shows a circuit diagram of an electronic circuit according to an example. The electronic circuit includes a power supply 2, a load circuit 3, and a power transistor circuit 1 connected between the power supply 2 and the load circuit 3. The power supply 2 is configured to provide a supply voltage V2.

[0009] According to an example, the supply voltage V2 is a DC (direct current) voltage and the power supply 2 is a DC power supply. The DC power supply 2 can be implemented in various ways. Examples of the DC power supply 2 include a battery, a PV (photoelectric) module, or a power converter configured to convert an AC input voltage received from a power transmission network into, for example, the DC supply voltage V2, but are not limited thereto.

[0010] According to another example, the power supply 2 is an AC (alternating current) power supply and the supply voltage V2 is an alternating voltage. The AC power supply is, for example, a power transmission network. According to an example, the frequency of the AC supply voltage V2 is less than 100 Hz.

[0011] The voltage level (when the supply voltage is a DC voltage) or amplitude (when the supply voltage is an AC voltage) of the supply voltage V2 provided by power supply 2 depends on the requirements of the load circuit 3. For example, the voltage level or amplitude of the supply voltage V2 is selected from between 100V and 6000V, and in particular from between 400V and 2000V.

[0012] For example, a power transistor circuit 1 connected between a power supply 2 and a load circuit 3 acts as an electronic switch that operates in either an ON or OFF state. In the ON state, the power transistor circuit 1 connects the power supply 2 to the load circuit 3, so the load voltage V3 received between the input nodes 31 and 32 of the load circuit 3 is substantially equal to the voltage V2 supplied by the power supply 2 (the total voltage V1 of the power transistor circuit 1 is negligible compared to the supply voltage V2 and the load voltage V3). In the OFF state, the power transistor circuit 1 disconnects the connection between the power supply 2 and the load circuit 3, so the load voltage V3 is zero, and the total voltage V1 of the power transistor circuit 1 is substantially equal to the supply voltage V2.

[0013] The load circuit 3 may include any type of electrical load that can be driven by the supply voltage V2 provided by the power supply 2. The load circuit 3 may include a single load, such as a motor, or it may include a network of multiple loads. For example, the load circuit 3 includes at least one power converter, which is configured to receive the supply voltage V2 from the power supply 2 and generate a DC or AC (alternating current) voltage configured to drive each load when the power transistor circuit 1 is ON. Note that the load circuit 3 may include at least one electronic switch configured to switch on or off each load contained within the load circuit 3. For example, the power transistor circuit 1 is used only to connect the load circuit 3 to the power supply or to disconnect the load circuit 3 from the power supply 2. Therefore, when the power transistor circuit 1 is ON, the current level of the current I1 flowing from the power supply 2 through the power transistor circuit 1 to the load circuit 3 is dominated by the load circuit 3.

[0014] For example, the electronic circuit further includes a control circuit 5 configured to drive a power transistor circuit 1, and driving the power transistor circuit includes operating the power transistor circuit 1 in an on state or an off state. For example, the control circuit 5 is configured to generate a drive signal Sdrv, which is received by the power transistor circuit 1. The drive signal Sdrv may have an on level that switches the power transistor circuit 1 on or an off level that switches the power transistor circuit 1 off.

[0015] In one example, the control circuit 5 includes a circuit configured to determine whether to switch the power transistor circuit 1 on or off. In another example, the control circuit 5 receives a control signal Sctrl, which contains information on whether to switch the power transistor circuit 1 on or off. In this example, the control circuit 5 is configured to generate a drive signal Sdrv based on the control signal Sctrl.

[0016] Referring to Figure 1, the electronic circuit may include inductors 41, 42, and 43 for connecting the power supply 2, the power transistor circuit 1, and the load circuit 3 to each other. For example, these inductors include a first inductor 41 connected between the first node 21 of the power supply 2 and the first node 11 of the power transistor circuit 1, a second inductor 42 connected between the second node 12 of the power transistor circuit 1 and the first node 31 of the load circuit 3, and a third inductor 43 connected between the second node 22 of the power supply 2 and the second node 32 of the load circuit 3. These inductors may include, for example, cables, conductor rails, or a combination thereof.

[0017] Inevitably, the inductors 41, 42, and 43 connecting the power supply 2, the power transistor circuit 1, and the load circuit 3 have parasitic inductance. These parasitic inductances are represented by inductor 44 in the electronic circuit according to Figure 1. Inductor 44 in Figure 1 represents any parasitic inductance in the electronic circuit where energy is magnetically stored when the power transistor circuit 1 is ON, and this type of energy is dissipated when the power transistor circuit 1 is switched OFF. For example, the total parasitic inductance is less than 20 mH (millihenry), less than 5 mH, less than 500 μH (microhenry), less than 100 μH, or even less than 10 μH.

[0018] For example, in an electronic circuit where power supply 2 is an AC power supply, the maximum total parasitic inductance is between 50 μH and 20 mH. In an electronic circuit where power supply 2 is a DC power supply, the maximum total parasitic inductance is, for example, between 0.5 μH and 20 μH.

[0019] The power transistor circuit 1 includes at least one power transistor, which will be described in detail below with reference to examples in this specification. In the electronic circuit according to Figure 1, switching off the power transistor circuit 1 involves operating at least one power transistor in avalanche mode, so that at least a portion of the energy stored in the parasitic inductance of the electronic circuit is dissipated within the at least one power transistor. This will be described below with reference to Figure 2.

[0020] Figure 2 shows a signal diagram of the drive signal Sdrv, the overall voltage V1 of the power transistor circuit 1, and the current I1 flowing through the power transistor circuit 1 to the load circuit 3 during the period when the power transistor circuit 1 changes from the ON state to the OFF state. Referring to the above, when the drive signal Sdrv has an ON level, the power transistor circuit 1 is ON, and when the drive signal Sdrv has an OFF level, it is OFF. For illustrative purposes only, in the example shown in Figure 2, the ON level of the drive signal Sdrv is represented by a high signal level, and the OFF level of the drive signal Sdrv is represented by a low signal level. In fact, the magnitude and sign of the drive signal Sdrv depend on the specific embodiment of the power transistor circuit. This will be described in further detail below in this specification.

[0021] Referring to Figure 2, before the first moment t1, power transistor circuit 1 is in the ON state. In this operating state, the voltage V1 of the entire power transistor circuit 1 is lower than the supply voltage V2 provided by power supply 2. In the ON state of power transistor circuit 1, the voltage level of the voltage V1 of the entire power transistor circuit 1 is substantially given by the current level of the current I1 multiplied by the ON resistance of power transistor circuit 1. The ON resistance of power transistor circuit 1 is the electrical resistance between the first circuit node 11 and the second circuit node 12 of power transistor circuit 1 in the ON state. The ON resistance of power transistor circuit 1 depends on the particular embodiment of power transistor circuit 1 and the type of transistor device contained within power transistor circuit 1. For example, according to one example, the ON resistance of power transistor circuit 1 is in the range between 1 milliohm (mΩ) and several tens of mΩ.

[0022] Referring to Figure 2, the drive signal Sdrv changes from on level to off level at the first moment t11, so that the power transistor circuit 1 switches off and the electrical connection between the power supply 2 and the load circuit 3 is interrupted. While the power transistor circuit 1 is on, energy is magnetically stored in the parasitic inductance. This energy causes the voltage V1 across the power transistor circuit 1 to increase after the first moment t11, and the voltage V1 increases until it reaches the avalanche breakdown level Vavl at the second moment t12. The avalanche breakdown level Vavl is the voltage level at which avalanche breakdown occurs in at least one power transistor contained within the power transistor circuit 1. The voltage V1 is clamped at the avalanche breakdown level Vavl and remains substantially at this voltage level Vavl until the energy stored in the parasitic inductance 44 is consumed. After the energy is consumed, the current I1 through power transistor circuit 1 reaches zero at the third moment t13, and the voltage V1 across power transistor circuit 1 decreases to the voltage level of the supply voltage V2 provided by power supply 2.

[0023] When power transistor circuit 1 is switched on for the next time, as shown in the fourth moment t14 in Figure 2, the voltage V1 across power transistor circuit 1 decreases again to a voltage level defined by the on-resistance of power transistor circuit 1 and the current level of the current I1 flowing through power transistor circuit 1.

[0024] It should be noted that there may be a delay time between the first moment t11 ​​when the drive signal Sdrv changes from the on level to the off level, and the moment when the power transistor circuit 1 switches off. However, this type of delay time is not shown in Figure 2.

[0025] For example, power transistor circuit 1 has a low switching frequency, for example, less than 1 Hz, 10 -1 Less than Hz or 10 -2 It operates even at frequencies below Hz. For example, operating power transistor circuit 1 at a low switching frequency involves a delay time between switching power transistor circuit 1 off and switching power transistor circuit 1 on again (only after it has been switched off), for example, the delay time between moments t11 and t14 in Figure 2 being at least 1 second (s), at least 10 seconds, or at least 100 seconds.

[0026] For example, power transistor circuit 1 is part of or forms part of the battery main switch. The "battery main switch" is an electronic switch between the load circuit and the battery in a vehicle. The battery main switch is configured to conduct (uninterruptedly) for a relatively long period, for example, while the vehicle is running. This can last for several hours.

[0027] In other examples, the power transistor circuit 1 is part of or forms an electronic fuse (e-fuse). This is further explained below with reference to Figures 3 and 4 of this specification.

[0028] When the power transistor circuit 1 is switched off, the energy stored in the parasitic inductance 44 of the electronic circuit depends on the inductance of the parasitic inductor 44 and the current level of the current I1 when the circuit is switched off, as follows. Ep=1 / 2·Lp·Ioff 2 (1) Here, Ep represents the stored energy, Lp represents the sum of the parasitic inductances (the inductances of the inductors 44 that represent these parasitic inductances), and Ioff represents the current level of the load current I1 when the power transistor circuit 1 is switched off. The energy that can be dissipated by at least one power transistor without being damaged or destroyed in avalanche mode depends on the specific type of power transistor and is usually obtainable from the power transistor's datasheet. For example, the energy that can be dissipated in one avalanche event is between 100 mJ (millijoules) and 400 mJ, and especially between 200 mJ and 400 mJ.

[0029] Figure 3 shows a variation of the electronic circuit shown in Figure 1. The electronic circuit according to Figure 3 is based on the electronic circuit according to Figure 1, and additionally includes a current sensor 6, which is configured to measure the current I1 passing through the power transistor circuit 1 and generate a current sensing signal CS. The current sensing signal CS represents the current level of the current I1 passing through the power transistor circuit 1. For example, the signal level of the current sensing signal CS is proportional to the current level of the current I1. Any type of current sensor may be used to sense the current I1 and provide the current sensing signal CS. Examples of current sensors 6 include, but are not limited to, inductive current sensors, Hall sensors, and shunt resistors.

[0030] The control circuit 5 receives a current sensing signal CS. For example, the control circuit 5 is configured to switch off the power transistor circuit 1 when it detects that the current I1 has reached an overcurrent level based on the current sensing signal CS. For example, the overcurrent level Ioc is selected to be higher than the current level of current I1 that can occur under normal operating conditions of the load circuit 3. The overcurrent level Ioc can occur under an overload condition. An overload condition can result, for example, from a short circuit in the load circuit 3.

[0031] Figure 4 shows the signal diagram of the drive signal Sdrv, the overall voltage V1 of power transistor circuit 1, and the current I1 through power transistor circuit 1 during the period in which an overload condition occurs. For illustrative purposes, assuming that power transistor circuit 1 is ON, a fault occurs in load circuit 3 at the first moment t21, increasing the load current I1. This type of fault may include, for example, a short circuit in load circuit 3.

[0032] Referring to Figure 4, due to a fault in the load circuit 3, the load current I1 increases after the first moment t21, so the load current I1 reaches the overcurrent level Ioc at the second moment t22, and the power transistor circuit 1 switches off at the third moment t23. After the third moment t23, the voltage V1 across the power transistor circuit 1 increases rapidly due to the energy stored in the parasitic inductance 44, and reaches the avalanche breakdown level Vavl at the fourth moment t24.

[0033] Referring to Figure 4, there is a delay time Td1 between the second moment t21 when the load current I1 reaches the overcurrent level Ioc and the third moment t22 when the power transistor circuit 1 switches off. This delay time Td1 is due to an unavoidable delay, which occurs in connection with detecting that the load current I1 has reached the overcurrent level Ioc, and switching off the power transistor circuit 1 upon detecting that the load current I1 has reached the overcurrent level Ioc. For example, the control circuit 5 and the power transistor circuit 1 are implemented such that the delay time Td1 is less than 500 nanoseconds (ns), less than 200 nanoseconds, or even less than 100 nanoseconds.

[0034] Referring to Figure 4, after the fourth moment t24, the voltage V1 of the entire power transistor circuit 1 is clamped to the avalanche breakdown level Vavl. After the fourth moment t23, the load current I1 decreases until it reaches zero at the fifth moment t25, so the voltage V1 of the entire power transistor circuit 1 decreases to the voltage level of the voltage V2 provided by power supply 2.

[0035] In the scenario shown in Figure 4, the energy stored in the parasitic inductance and consumed within the power transistor circuit 1 is also given by equation (1), where Ioff is the current level of the load current I1 at the third instant t23 when the power transistor circuit 1 switches off. Due to the delay time Td1, this current level Ioff is higher than the overcurrent level Ioc. For example, if the fault in the load circuit 3 that increases the load current I1 is a short circuit in the load circuit, the increase in load current is, dI1 / dt=V2 / Lp (2) Given by, where V2 is the voltage level of the supply voltage V2 and Lp represents the parasitic inductance. In this example, the current level Ioff of the load current I1 when the switch is turned off is, Ioff = Ioc + V2 / Lp·Td1 (3) It is given by . Therefore, considering the energy that can be consumed in at least one power transistor in avalanche mode based on the parasitic inductance Lp and delay time Td1, the overcurrent level Ioc is optimally adjustable in the control circuit 5. For example, the current flowing through the power transistor circuit 1 in avalanche mode should not exceed a predetermined threshold. In this example, selecting the overcurrent level Ioc further includes selecting the overcurrent level Ioc so that it does not exceed a predetermined current threshold.

[0036] In another example, the power transistor circuit 1 and control circuit 5 operate as e-fuses. In this example, in addition to comparing the current sensing signal CS with a signal representing an overcurrent threshold, or instead, the control circuit 5 monitors the load current I1 (by monitoring the current sensing signal CS over a specific period of time) and switches off according to the time characteristics of the current I1. In one example, the control circuit 5 operates as an e-fuse. 2 The power transistor circuit 1 is switched off according to the t-curve. This may include comparing the load current with different current threshold levels, each current threshold level being associated with a different maximum period, and whenever the load current I1 reaches a certain threshold and continues to flow for the maximum period associated with that threshold, the power transistor circuit 1 is switched off.

[0037] In the following, switching off the power transistor circuit 1 by the control circuit 5 due to a load current I1 is referred to as current-induced switch-off. For example, after current-induced switch-off, once power is consumed and the voltage V1 of the entire power transistor circuit 1 reaches the supply voltage level V2, the control circuit 5 is configured to switch on the power transistor circuit 1 again after a certain delay time. In another example, each control signal S CTRL The control circuit 5 is configured to switch on the power transistor circuit 1 again only when it receives a signal from the control circuit 5.

[0038] For example, control signal S CTRL These are generated by electronic circuits in response to mechanical actions by the user, such as buttons and keys.

[0039] In both the scenario shown in Figure 2 and the scenario shown in Figure 4, the duration of the clamp period Tclamp, which is the period during which power is consumed within the power transistor circuit 1, depends on the avalanche voltage level Vavl, the current level Ioff when the switch is turned off, and the voltage level of the supply voltage V2, as follows: Tclamp=(Lp·Ioff) / (Vavl-Vbat) (4)

[0040] Figure 5 shows a further variation of the electronic circuit according to Figure 1. The electronic circuit according to Figure 5 is based on the electronic circuit according to Figure 1, and in addition includes a power consumption element 7 connected in parallel with the power transistor circuit 1. The current sensor 6, described with reference to Figure 3, is optional. That is, implementing an electronic circuit with a power consumption element 7 in parallel with the power transistor circuit 1 is independent of implementing the control circuit 5 using the current sensor 6 to detect overcurrent scenarios.

[0041] In one example, the power consumption element 7 is an MOV (metal oxide varistor). The MOV has a threshold voltage and is configured to conduct and consume power when the total voltage of the MOV reaches the threshold voltage level. In the example shown in Figure 5, the total voltage of the MOV 7 is the same as the total voltage V1 of the power transistor circuit 1.

[0042] However, MOV is relatively slow. That is, there is a considerable delay between the moment the overall MOV voltage reaches the threshold voltage level and the moment the MOV begins to conduct and clamps the overall MOV voltage to the voltage level given by the threshold voltage level. In particular, in applications where the increasing voltage of the overall MOV is due to energy stored in the parasitic inductance, the overall MOV voltage can increase to a voltage level significantly higher than the threshold voltage level before the MOV begins to conduct. The delay time of MOV is, for example, between 100 ns (nanoseconds) and 500 ns.

[0043] In the electronic circuit according to Figure 5, MOV7 is selected such that its threshold voltage level is lower than the avalanche breakdown voltage level of power transistor circuit 1. This is shown in Figure 6, which shows the signal diagram of the drive signal Sdrv, the overall voltage V1 of power transistor circuit 1, and the current I1 through power transistor circuit 1 during the period when power transistor circuit 1 is switched off.

[0044] In Figure 6, t31 represents the first moment when power transistor circuit 1 switches off, and the voltage V1 increases until it reaches the avalanche breakdown voltage level Vavl of at least one power transistor contained within power transistor circuit 1. Referring to the above, the threshold voltage level Vth of MOV7 is lower than the avalanche breakdown voltage level Vavl. However, due to the slow switching behavior of MOV7, the voltage V1 of the power transistor circuit and MOV7 as a whole rises above the threshold voltage level Vth and is clamped to the avalanche breakdown voltage level Vavl by power transistor circuit 1 until MOV7 switches on and clamps the voltage V1 to the threshold voltage level Vth. The voltage V1 of the power transistor circuit and MOV7 as a whole remains substantially at the threshold voltage level Vth until energy is consumed and the load current I1 reaches zero at a third moment t33.

[0045] For example, the power transistor circuit 1 and MOV are adapted to each other such that the threshold voltage level Vth of MOV is selected from between 80% and 95% of the avalanche breakdown voltage level of power transistor circuit 1.

[0046] In a parallel circuit having power transistor circuit 1 and MOV7, power transistor circuit 1 ensures that the voltage V1 is clamped to the avalanche breakdown voltage level Vavl, thereby ensuring that a portion of the energy previously stored in the parasitic inductance 44 is consumed. When MOV is switched on, the voltage V1 of the entire power transistor circuit 1 drops below the avalanche breakdown voltage level Vavl, so that power transistor circuit 1 no longer operates in avalanche mode, and the remaining energy still stored in the parasitic inductance is consumed in MOV7. MOV7 and power transistor circuit 1 may be adapted to each other so that MOV7 has a higher power dissipation capacity than power transistor circuit 1. For example, MOV7 is selected such that the energy that can be consumed in MOV7 without damage is at least 10 times the energy that can be consumed in power transistor circuit 1.

[0047] Based on the above, power transistor circuit 1 can be implemented in various ways. Different examples of implementing power transistor circuit 1 are described below.

[0048] As shown in the example in Figure 7, the power transistor circuit includes a single power transistor, for example, a single power MOSFET 10. The power MOSFET is either silicon (Si)-based or silicon carbide (SiC)-based. "Si-based" includes the integration of the active region, e.g., the source, drift, and drain regions of the power MOSFET, within a single-crystal silicon semiconductor body. "SiC-based" includes the integration of the active region of the power MOSFET within a SiC semiconductor body. The avalanche breakdown voltage level of the power MOSFET 10 depends on the particular embodiment. Si-based MOSFETs are available with rated voltages up to 800V. SiC-based power MOSFETs are available with rated voltages up to 1.7kV (1700V). "Rated voltage" is the voltage that the MOSFET can reliably withstand without operating in avalanche mode. The avalanche breakdown voltage level is typically 5% to 10% higher than the rated voltage stop capability.

[0049] For example, a power transistor is a superjunction transistor. A superjunction transistor can be implemented, for example, as a silicon (Si)-based transistor or a silicon carbide (SiC)-based transistor. Furthermore, a superjunction transistor can be implemented, for example, as a MOSFET or JFET.

[0050] Referring to Figure 7, the power MOSFET includes a gate node G, a drain node D, and a source node S, and further includes a drain-source path between the drain node D and the source node S. The MOSFET is a voltage-controlled device that switches on or off depending on the drive voltage (gate-source voltage) received between the gate node and the source node. For example, the drive voltage received by the MOSFET is the drive signal Sdrv provided by the control circuit 5 (not shown in Figure 7).

[0051] Power MOSFETs can be implemented as n-type MOSFETs or p-type MOSFETs, and as enhancement (normally-off) devices or depletion (normally-on) devices. For illustrative purposes only, the circuit code shown in Figure 7 represents an n-type enhancement MOSFET.

[0052] A power MOSFET has a threshold voltage, which defines the voltage level of the drive voltage (gate-source voltage) that causes the MOSFET to switch between on-level and off-level. Whether the threshold voltage is positive or negative depends on the type of MOSFET. In an n-type enhancement MOSFET, for example, the threshold voltage is a positive voltage. Furthermore, when the drive voltage is higher than the threshold voltage, the n-type enhancement MOSFET is on, and when the drive voltage is lower than the threshold voltage, it is off. In a p-type enhancement MOSFET, for example, the threshold voltage is a negative voltage. Furthermore, when the drive voltage is lower than the negative threshold voltage, the p-type enhancement MOSFET is on, and when the drive voltage is higher than the negative threshold voltage, it is off.

[0053] Referring to Figure 7, the drain-source path of the power MOSFET, which may also be called the load path, is connected between the first node 11 and the second node 12 of the power transistor circuit 1. When the power MOSFET is ON, the load path conducts the load current I1.

[0054] Figure 8 shows a power transistor circuit 1 following another example. In this example, power transistor circuit 1 consists of multiple power MOSFETs 101, 10 connected in parallel. n This includes, each receiving a drive signal as Sdrv between its respective gate node G and its respective source node S. "Connected in parallel" means that each MOSFET 101, 10 nThe drain-source path includes being connected in parallel between the first circuit node 11 and the second circuit node 12 of the power transistor circuit 1. In the example shown in FIG. 8, the power transistor circuit 1 includes two power MOSFETs. However, this is merely an example. Any number of power MOSFETs can be connected in parallel.

[0055] The power MOSFETs 101, 10 connected in parallel n have the same avalanche breakdown voltage level. After the power transistor circuit 1 is switched off, each of the power MOSFETs 101, 10 n operates in the avalanche mode, and the power consumed is shared by several power MOSFETs.

[0056] Necessarily, the avalanche breakdown voltage levels of the power may be (slightly) different. Thus, when the voltage across the entire load path of the parallel MOSFETs 101, 10 n increases, one of the MOSFETs may start operating in the avalanche mode, and simultaneously, one or more of the other MOSFETs in the parallel circuit may still operate in the blocking state. Nevertheless, the following effects protect against the first MOSFET starting to operate in the avalanche mode from being damaged or destroyed. The power consumed by the MOSFET operating in the avalanche mode increases the temperature of the MOSFET. Further, the avalanche breakdown voltage level is temperature-dependent and increases with increasing temperature. Thus, initially, the temperature of the MOSFET starting to operate in the avalanche mode starts to increase, so the level of the avalanche breakdown voltage of this MOSFET increases, the voltage across the entire MOSFET parallel circuit increases, and one or more of the other MOSFETs may start operating in the avalanche mode.

[0057] In another example shown in Figure 9, the power transistor circuit 1 includes a single power transistor 10 implemented as a JFET (junction field-effect transistor), which receives a drive signal as a drive voltage (gate-source voltage) between the gate node G and the source node S. The JFET can be implemented as an n-type device or a p-type device. For illustrative purposes only, the circuit code shown in Figure 9 represents an n-type JFET.

[0058] Since JFETs are normally-on devices, they are ON when the drive voltage (gate-source voltage) is zero. n-type JFETs have a negative threshold voltage and are OFF when the drive voltage is less than the negative threshold voltage. p-type JFETs have a positive threshold voltage and are OFF when the drive voltage is greater than the positive threshold voltage.

[0059] According to another example shown in Figure 10, the power transistor circuit 1 consists of several JFETs 101, 10 of the same type connected in parallel. n It includes, and each receives the drive signal Sdrv as the drive voltage.

[0060] Figure 11 shows a power transistor circuit following another example. In this example, the power transistor circuit includes a power transistor 10 implemented as a normally-on transistor and a further transistor 13 implemented as a normally-off transistor. In one example, power transistor 10 is a JFET and the further transistor 13 is an enhancement MOSFET.

[0061] The normally-on transistors and normally-off transistors are connected in series between the first node 11 and the second node 12 of the power transistor circuit 1. That is, in the example shown in Figure 11, the drain-source path of the JFET 10 is connected in series with the drain-source path of the enhancement MOSFET 13, and the series circuit including the drain-source paths of the JFET 10 and MOSFET 13 is connected between the first circuit node 11 and the second circuit node 12 of the power transistor circuit 1.

[0062] The normally-on transistor 10 and the normally-off transistor 13 form a cascode circuit, and the normally-off transistor 13 receives the drive signal Sdrv as the drive voltage and controls the operating state of the normally-on transistor 10. Since the latter is achieved by connecting the normally-on transistor 10 and the normally-off transistor 13 to each other, the drive voltage received by the normally-on transistor 10 is equal to the load path voltage of the normally-off transistor 13. More specifically, in the example shown in Figure 11, the operating state of the JFET 10 is controlled by the MOSFET 13 that receives the drive signal Sdrv between its gate node G1 and its source node S1. Since the gate node of the JFET 10 is connected to the enhancement MOSFET 13, the gate-source voltage of the JFET 10 is equal to the drain-source voltage of the enhancement transistor 13. For illustrative purposes only, in the example shown in Figure 11, the enhancement transistor 13 is an n-type enhancement transistor. In this example, the gate node G of JFET10 is connected to the source node S1 of enhancement transistor 13, and the drain node D1 of enhancement transistor 13 is connected to the source node S of JFET10.

[0063] Since the threshold voltage of JFET10 is negative, JFET10 is ON when its gate-source voltage is zero. Therefore, when the enhancement MOSFET13 is switched ON by the drive signal Sdrv, JFET10 is ON. When the enhancement transistor 13 is switched OFF, the drain-source voltage of the enhancement transistor 13 increases, so the gate-source voltage of JFET10 becomes negative, and JFET10 switches OFF when its gate-source voltage falls below its threshold voltage level. The voltage blocking capability of the enhancement MOSFET13 can be higher than the magnitude of the threshold voltage of JFET10 and much lower than the voltage blocking capability of JFET10. For example, the voltage blocking capability of the enhancement transistor 13 can be selected from between 10V and 50V.

[0064] As described above, the operating state of the normally-on transistor 10 is controlled by the normally-off transistor 13, so the cascode circuit operated by the drive signal Sdrv behaves like a normally-off device. The power transistor configured to operate in avalanche mode and consume power is the normally-on transistor 10 in the cascode circuit.

[0065] Figure 12 shows a further variation of the power transistor circuit 1 according to Figure 9. The power transistor circuit 1 according to Figure 12 has multiple normally-on transistors 101, 10 n These include, and these have their load paths connected in parallel. Low voltage normally-off transistor 13 is normally-on transistor 101, 10 n It controls the drive voltage received by each of them. For the sake of explanation, normally off transistor 13 is an enhancement MOSFET, and normally on transistors 101, 10 n In the example shown in Figure 12, this is a JFET.

[0066] Figure 13 shows a further variation of the power transistor circuit according to Figure 11. The power transistor circuit according to Figure 13 includes multiple cascode circuits of the type shown in Figure 11, connected in parallel. Each of these cascode circuits has normally-on power transistors 101, 101 connected in series with the power transistors. n (JFET in the example shown in Figure 13) and low-voltage normally-off transistors 131, 13 n (In the example shown in Figure 13, this includes an enhancement MOSFET). Enhancement transistors 131, 13 n Each receives the same drive signal, Sdrv.

[0067] In the example shown in Figures 11 to 13, at least one power transistor 10, 101-10 n When the voltage between the first circuit node 11 and the second circuit node 12 of the power transistor circuit 1 increases so that the overall voltage level reaches the avalanche breakdown voltage level of at least one power transistor, at least one power transistor 10, 101-10 n It operates in avalanche mode. For example, a voltage clamping element (not shown in Figures 11 to 13) is connected in parallel to the load path of at least one (low-voltage) normally-off transistor 13. The voltage clamping element may include, for example, one or more Zener diodes or MOVs. The voltage clamping element is connected to at least one normally-off transistor 13, 131-133 n The voltage level of the entire load path is at least one normally off transistor 13, 131-13 n The voltage is configured to clamp so that it remains below the avalanche breakdown voltage level, and as a result, at least one normally-off transistor 13, 131-13 n It does not enter avalanche mode (on the other hand, at least one power transistor 10, 101-10 n (It operates in avalanche mode).

[0068] The power transistor circuit 1 according to each of the examples shown in Figures 7, 8 and 11 to 13 is a unidirectional blocking power transistor circuit. This includes the fact that when the voltage between the first circuit node 11 and the second circuit node 12 has a first polarity, the power transistor circuit 1 is configured to block, and when the voltage between the first circuit node 11 and the second circuit node 12 has a second polarity opposite to the first polarity, it conducts independently of the drive signal Sdrv. The "second polarity" refers to power transistors 10, 101-10 according to Figures 7 to 8. n Body diode or low-voltage normally-off transistor 13, 131-13 n The internal body diodes are forward-biased, resulting in these transistors having polarities that conduct independently of their respective drive signals, Sdrv.

[0069] However, the power transistor circuit 1 is not limited to being implemented as a unidirectional blocking power transistor circuit, but may also be implemented as a bidirectional blocking power transistor circuit. The bidirectional blocking power transistor circuit 1 is a power transistor circuit configured to block independently of the voltage polarity between the first circuit node 11 and the second circuit node 12 (as long as the voltage is below the avalanche breakdown voltage level).

[0070] Figure 14 shows an example of a bidirectional blocking power transistor circuit 1. In this example, the power transistor circuit 1 consists of two bidirectional blocking normally-off transistors 10 connected in series. I , 10 II This includes two normally off transistors 10 for illustrative purposes. I , 10 II Each of these is an enhancement MOSFET. I , 10 II Each of these includes a body diode, represented by its respective diode symbol in the example shown in Figure 14. Two MOSFETs 10 I , 10 IISince they are connected in series, the body diode is connected anti-series. Referring to Figure 14, this is two MOSFETs 10 I , 10 II This may include the fact that the source node S is connected. For example, as shown in Figure 14, two MOSFETs 10 I , 10 II Each of them receives the same drive signal Sdrv.

[0071] The power transistor circuit 1 shown in Figure 14 consists of two normally-off transistors 10 I , 10 II It should be noted that this is not limited to including only these. In other examples (not shown), a bidirectional blocking power transistor circuit includes several first transistors connected in parallel and several second transistors connected in parallel, such that the body diodes in the first parallel circuit and the body diodes in the second parallel circuit are in an anti-series configuration, and the first parallel circuit including the first transistors is connected in series with the second parallel circuit including the second transistors.

[0072] Figure 15 shows an example of a control circuit 5. In the example shown in Figure 15, the control circuit 5 includes a logic circuit 51, a driver 52, and a gate resistor 53. The driver 52 is configured to generate a drive signal Sdrv based on a drive voltage Vdrv and depending on a control signal S51 received from the logic circuit 51. The control signal S51 is, for example, a logic signal that indicates whether the power transistor circuit 1 should be switched on or switched off. Since the driver 52 is configured to generate the drive signal Sdrv based on the control signal S51, the power transistor circuit 1 is switched on when the control signal S51 indicates that the power transistor circuit 1 should be switched on, and the power transistor circuit 1 is switched off when the control signal S51 indicates that the power transistor circuit 1 should be switched off.

[0073] The gate resistance 53 is due to the unavoidable line resistance between the driver 52 and the power transistor circuit 1. For illustrative purposes only, the power transistor circuit 1 is implemented by a single power MOSFET in the example shown in Figure 15. In this case, the gate resistance 53 is due to the line resistance between the driver 52 and the gate node G of the power MOSFET 10.

[0074] Inevitably, in a MOSFET, a capacitance exists between the gate node G and the drain node D, which is commonly called gate-drain capacitance. When the MOSFET is off and the overall drain-source voltage of the MOSFET rapidly increases, the capacitive coupling between the drain node D and the gate node G, due to the gate-drain capacitance, increases the potential of the gate node G, which can cause the MOSFET to unintentionally switch on.

[0075] According to an example shown in Figure 16, the drive signal Sdrv received by power transistor circuit 1, which includes one or more n-type enhancement MOSFETs, is generated such that the off-level of the drive signal is at a negative voltage level, which can help prevent the power MOSFETs from accidentally switching on when the drain-source voltage rapidly increases in avalanche mode. In this example, the off-level of the drive signal Sdrv is selected from between -2V and -8V, so the magnitude of the off-level is between 2V and 8V.

[0076] Some of the embodiments described above can be summarized below with reference to the numbered examples.

[0077] (Example 1) A method comprising the step of switching off a power transistor circuit in an electronic circuit, the electronic circuit comprising a power supply connected between a power supply and a load circuit, a load circuit and a power transistor circuit, the step of switching off the power transistor circuit comprising the step of operating at least one power transistor contained in the power transistor circuit in avalanche mode, so that at least a portion of the energy stored in the electronic circuit before the step of switching off the power transistor circuit is consumed in at least one power transistor.

[0078] (Example 2) The method of Example 1, wherein at least one power transistor includes exactly one power transistor.

[0079] (Example 3) The method of Example 1, wherein at least one power transistor includes two or more power transistors.

[0080] (Example 4) At least one power transistor is a normally-off transistor, in any of the ways of Examples 1 to 3.

[0081] (Example 5) The normally-off transistor is a MOSFET, using the method in Example 4.

[0082] (Example 6) At least one power transistor is a normally-on transistor, in any way of Examples 1 to 3.

[0083] (Example 7) The normally-on transistor is a JFET, using the method of Example 6.

[0084] (Example 8) At least one power transistor is a superjunction transistor, in any way of Examples 1 through 7.

[0085] (Example 9) At least one power transistor is one of silicon-based or silicon carbide-based power transistors, in any of the methods of Examples 1 to 8.

[0086] (Example 10) A power transistor circuit comprising a first circuit node connected to a power supply and a second circuit node connected to a load circuit, wherein at least one power transistor includes a load path, and the load path of at least one power transistor is directly connected between the first circuit node and the second circuit node, in any way of Examples 1 to 9.

[0087] (Example 11) The power transistor circuit includes a first circuit node connected to a power supply and a second circuit node connected to a load circuit, and at least one power transistor is included in a cascode circuit, and the cascode circuit includes further transistors in addition to the at least one power transistor, and the cascode circuit is directly connected between the first circuit node and the second circuit node, in any way of Examples 1 to 9.

[0088] (Example 12) Any method of Examples 1 to 11, wherein both the electronic circuit and the power transistor circuit lack a clamping circuit configured to clamp the voltage of at least one power transistor to a voltage level lower than the avalanche breakdown voltage level of at least one power transistor.

[0089] (Example 13) The electronic circuit includes a clamping element connected in parallel to a power transistor circuit, and after at least one power transistor has been operating in avalanche mode, the clamping element is configured to conduct and clamp the voltage of the entire power transistor circuit to a voltage level lower than the avalanche breakdown voltage level of at least one power transistor, in any way of Examples 1 to 11.

[0090] (Example 14) The power supply is configured to provide a DC voltage, at least one power transistor has an avalanche breakdown voltage level, at least one power transistor operates in avalanche mode when the voltage across the load path of at least one power transistor reaches the avalanche breakdown voltage level, and at least one power transistor is adapted to the DC voltage such that the avalanche breakdown voltage level is between 120% and 150% of the DC voltage level, in any way of Examples 1 to 13.

[0091] (Example 15) Any method of Examples 1 to 14, wherein the step of switching off a power transistor circuit includes applying a drive voltage having an off-level between the gate node and source node of at least one power transistor, the polarity of the off-level being the opposite of the polarity of the on-level which is configured to switch on at least one power transistor.

[0092] (Example 16) The off-level magnitude is between 2V and 8V, as in Example 15.

[0093] (Example 17) The step of switching off a power transistor circuit includes applying a drive voltage by a drive circuit that has an off-level between the gate node and source node of at least one power transistor, and the resistance between the output of the drive circuit and the gate node is less than 10 ohms, in any of the methods in Examples 1 to 16.

[0094] (Example 18) The total inductance in the electronic circuit is less than 20 millihenries, using any method from Examples 1 to 17.

[0095] (Example 19) The switching frequency of the power transistor circuit is less than 1 Hz, using any method from Examples 1 to 18.

[0096] (Example 20) The time delay between switching off the power transistor circuit and switching on the power transistor circuit again is longer than 1 second, using any of the methods in Examples 1 through 19.

Claims

1. 1. A method comprising: The method comprises the step of switching off a power transistor circuit (1) in an electronic circuit, The electronic circuit comprises a power supply (2), a load circuit (3), and the power transistor circuit (1) connected between the power supply (2) and the load circuit (3); The step of switching off the power transistor circuit (1) includes switching off at least one power transistor (10; 10) included in the power transistor circuit (1). １ , 10 ｎ ) in an avalanche mode, so that at least a portion of the energy stored in the electronic circuit before the step of switching off the power transistor circuit (1) is dissipated in the at least one power transistor. method.

2. said at least one power transistor comprises exactly one power transistor (10); The method of claim 1.

3. The at least one power transistor comprises two or more power transistors (10 １ , 10 ｎ ) The method of claim 1.

4. said at least one power transistor (10; 10 １ , 10 ｎ ) is a normally-off transistor, The method of claim 1.

5. said at least one power transistor (10; 10 １ , 10 ｎ ) is a normally-on transistor, The method of claim 1.

6. said at least one power transistor (10; 10 １ , 10 ｎ ) is a superjunction transistor, The method of claim 1.

7. The power transistor circuit (1) comprises a first circuit node (11) connected to the power supply (2) and a second circuit node (12) connected to the load circuit (3); said at least one power transistor (10; 10 １ , 10 ２ ) comprises a load path; said at least one power transistor (10; 10 １ , 10 ２ ) the load path is directly connected between the first circuit node (11) and the second circuit node (12); The method of claim 1.

8. The power transistor circuit (1) comprises a first circuit node (11) connected to the power supply (2) and a second circuit node (12) connected to the load circuit (3); said at least one power transistor (10; 10 １ , 10 ２ ) is included in the cascode circuit, The cascode circuit includes the at least one power transistor (10; 10 １ , 10 ２ ) plus further transistors (14;14 １ , 14 ２ ) The cascode circuit is directly connected between the first circuit node (11) and the second circuit node (12). The method of claim 1.

9. Both the electronic circuit and the power transistor circuit (1) are connected to the at least one power transistor (10; 10 １ , 10 ２ ) the overall voltage across said at least one power transistor (10; 10 １ , 10 ２ ) lacking a clamp circuit configured to clamp to a voltage level below the avalanche breakdown voltage level of the The method of claim 1.

10. The electronic circuit includes a clamping element (7) connected in parallel to the power transistor circuit (1), said at least one power transistor (10; 10 １ , 10 ２ After the at least one power transistor (10; 10) has been operating in the avalanche mode, the clamping element (7) becomes conductive and applies a voltage (V1) across the power transistor circuit (1) to the at least one power transistor (10; 10). １ , 10 ２ ) configured to clamp to a voltage level below the avalanche breakdown voltage level of The method of claim 1.

11. the power supply (2) is configured to provide a DC voltage (V2); said at least one power transistor (10; 10 １ , 10 ｎ ) has an avalanche breakdown voltage level, and said at least one power transistor (10; 10 １ , 10 ｎ ) is connected to said at least one power transistor (10; 10 １ , 10 ｎ ) operates in the avalanche mode when the voltage (V1) across the load path of said at least one power transistor (10; 10 １ , 10 ｎ ) is adapted to the DC voltage (V2) so that the avalanche breakdown voltage level is between 120% and 150% of the voltage level of the DC voltage (V2); The method of claim 1.

12. The step of switching off the power transistor circuit (1) comprises switching off the at least one power transistor (10; 10 １ , 10 ｎ applying a driving voltage (S5) having an off level between a gate node (G) and a source node (S) of the transistor; The polarity of the off-level is the polarity of the at least one power transistor (10; 10 １ , 10 ｎ ) is configured to switch on the on level of the opposite polarity, The method of claim 1.

13. The step of switching off the power transistor circuit (1) comprises: a driving circuit (52) for driving the at least one power transistor (10; 10 １ , 10 ｎ applying a driving voltage (S5) having an off level between a gate node (G) and a source node (S) of the transistor; the resistance between the output of the driver circuit (52) and the gate node (G) is less than 10 ohms; The method of claim 1.

14. The switching frequency of the power transistor circuit (1) is less than 1 Hz. The method of claim 1.

15. the time delay between switching off the power transistor circuit (1) and switching it on again is greater than 1 second; The method of claim 1.

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