Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density

Abstract

To provide a method to introduce an integrated sequence during which a shallow trench is etched and filled before a deep trench is etched and filled, for fabricating conductive deep trenches in conjunction with shallow trench isolations in a semiconductor device.SOLUTION: A method includes introducing an integrated sequence during which a shallow trench is etched (210) and filled (220) before a deep trench is etched (230) and filled (240). Thus, the method advantageously reduces cone defects and process complexity associated with the formation of a conductive deep trench within a shallow trench isolation structure. Fabricated under the integrated sequence, the conductive deep trench may extend through a shallow trench dielectric layer and into a substrate, where the top surfaces of both the conductive deep trench and the shallow trench dielectric layer are substantially cone free.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] Conductive deep trenches are employed in high power semiconductor devices with numerous applications. In integrated circuit dies, conductive deep trenches can function as isolation barriers that separate high voltage components from low voltage components. In discrete components, conductive deep trenches can function as field plates and gate electrodes for high power transistors. Conductive deep trenches can be formed alongside shallow trench isolation such that one or more conductive deep trenches can overlap within a shallow trench isolation structure. However, the process of fabricating trenches with different depths can be complex and prone to defects. Summary of the Invention

[0002] To fabricate conductive deep trenches in conjunction with shallow trench isolation in semiconductor devices, the described approach introduces an integrated sequence in which a shallow trench is etched and filled before a deep trench is etched and filled. The described approach advantageously reduces cone defects along the top surface of the shallow trench isolation structure, thereby minimizing defect density in the semiconductor device. And, by integrating the deep trench formation process with the shallow trench formation process, the described approach advantageously reduces the process complexity of fabricating semiconductor devices.

[0003] In one implementation, for example, the present description introduces a method that includes forming a shallow trench in a first region of a substrate, forming a dielectric layer filling the shallow trench and overlying the substrate, and forming a deep trench in a second region of the substrate within the first region. Before the deep trench is formed, the dielectric layer has a substantially planar surface over and across the shallow trench, and after the deep trench is formed, it extends from and through the dielectric layer.

[0004] In another implementation, for example, the present description introduces a method that includes forming a shallow trench in a first region of a substrate, forming a shallow trench oxide layer filling the shallow trench, forming a hard mask layer covering the shallow trench oxide layer, and forming a deep trench in a second region within the first region of the substrate. Before the deep trench is formed, the hard mask layer has a substantially planar surface, and after the deep trench is formed, it extends from and through the shallow trench oxide layer.

[0005] In yet another implementation, for example, the present description introduces a device that includes a substrate having a surface conforming along a plane, a shallow trench dielectric layer extending into the substrate from the plane a first depth, and a deep trench structure extending into the substrate from the plane through the shallow trench dielectric layer a second depth greater than the first depth. [Brief description of the drawings]

[0006] [Figure 1A] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1B] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1C] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1D] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1E] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1F]1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect. [Figure 1G] 1A-1D show partial cross-sectional views of a semiconductor device during a process for fabricating a deep trench followed by a shallow trench with a pyramidal defect.

[0007] [Figure 2A] 1 shows a flow chart of an exemplary method for fabricating a shallow trench followed by a deep trench without pyramidal defects, according to one aspect of the present description.

[0008] [Figure 2B] 1 shows a flow chart of an exemplary method for forming a dielectric layer filling a shallow trench and overlying a substrate, according to one aspect of the present description.

[0009] [Figure 3A] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3B] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3C] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3D] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3E] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3F] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3G]2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3H] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. [Figure 3I] 2A and 2B show partial cross-sectional views of an example semiconductor device during a manufacturing process implementing the example method of FIGS. 2A and 2B according to one aspect of the present description. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Like numbers indicate like elements in the various drawings. The drawings are not drawn to scale.

[0011] Deep trench structures are found in many semiconductor devices, such as high voltage analog devices. In high voltage applications, the deep trench structures may include conductive fillers, which may function as field plates to reduce electric field density or as gate electrodes of vertical transistors (e.g., vertically diffused MOS transistors). The deep trench structures may be formed in conjunction with shallow trench structures. As shown in Figures 1A-1G, for example, a semiconductor device 100 may be fabricated in a sequence in which a deep trench 122 is formed before a shallow trench 133 is formed.

[0012] 1A, semiconductor device 100 may be a discrete component device (e.g., a single transistor device) or an integrated circuit having multiple transistor devices. In an early stage of the fabrication sequence, a pad oxide layer 112, a nitride cap layer 114, and a hard mask layer 116 are sequentially formed on the top surface of semiconductor substrate 102. Pad oxide layer 112 serves the function of stress relief between silicon and subsequent layers, and may include silicon dioxide grown in a thermal oxidation process. Nitride cap layer 114 serves the function of an exclusion film that allows selective oxidation, and may include silicon nitride (e.g., Si SiO 2 ) that is deposited under a low pressure chemical vapor deposition (LPCVD) furnace process. 3 N 4 ). The hard mask layer 116 acts as a hard mask during a subsequent deep trench etch process and may include silicon dioxide deposited under a plasma enhanced chemical vapor deposition (PECVD) process.

[0013] Next, a photoresist mask 118 is deposited and patterned with openings that expose the deep trench (DT) regions 104 of the substrate 102. The photoresist mask 118 serves to mask the hard mask layer and may include a photosensitive organic material that is applied, exposed, and developed.

[0014] 1B, a DT etch process 121 is performed to form a deep trench 122. The DT etch process 121 may include multiple subsequences. In one implementation, for example, a hard mask etch may first be performed to remove the hard mask layer 116 exposed by the patterned photoresist mask 118, and then a silicon etch may be performed to remove the nitride cap layer 114, the pad oxide layer 112, and the substrate 102 exposed by the etched hard mask layer 116. During the silicon etch, the photoresist mask layer 118 is also removed, leaving the hard mask layer 116 to prevent areas outside the DT region 104 from being etched.

[0015] After the DT etch process 121, a dielectric liner deposition process is performed to cover the sidewalls of the deep trench 122. For example, a DT oxide liner 124 is deposited on the sidewalls of the deep trench 122 under a dielectric liner deposition process 123, as shown in FIG. 1C. In one implementation, the dielectric liner deposition 123 may include low pressure chemical vapor deposition of an oxide target. Following the dielectric liner deposition process 123, a deep trench dielectric etch process may be performed to achieve a uniform liner thickness along the sidewalls of the deep trench 122.

[0016] 1D , a polysilicon deposition process 125 is performed to fill deep trench 122 with a conductive material. This forms a DT fill structure 126 in deep trench 122. DT fill structure 126 may abut DT oxide liner 124. Alternatively, DT fill structure 126 may abut directly on the sidewall of deep trench 122 where DT oxide liner 124 is not present. During polysilicon deposition process 125, a DT fill seam 127 may form along the vertical center of DT fill structure 126. The dimensions of DT fill seam 127 may depend on the aspect ratio of deep trench 122.

[0017] After the DT fill structure 126 is formed, a chemical mechanical polishing process is performed to remove excess polysilicon material above the deep trench 122. At this point, a conductive deep trench 129 is formed. The remaining nitride cap layer 114 and pad oxide layer 112 are then removed and redeposited to complete the deep trench formation sequence and in preparation for the shallow trench formation sequence.

[0018] Referring to FIG. 1E, a photoresist mask 131 is deposited and patterned on the nitride cap layer 114 to expose the shallow trench (ST) region 106 of the semiconductor substrate 102. Generally, the ST region 106 covers a larger area than the DT region 104, which may be located entirely within the ST region 106. After the photoresist mask 131 is patterned, a shallow trench etch process is performed. Referring to FIG. 1F, for example, the shallow trench etch process 132 may include a silicon etch to remove the nitride cap layer 114 and the pad oxide layer 112 exposed by the photoresist mask 131. During the silicon etch, the DT fill seam 127 may trap remnants from the nitride cap layer 114 and the pad oxide layer 112, which may slow the etch rate around the DT fill seam 127. This slower etch may lead to the formation of one or more polysilicon pyramids 128 near the DT fill seam 127.

[0019] When the shallow trench etch 132 is completed, a shallow trench 133 is formed. As a result of the shallow trench etch 132, the DT structure 129 is then recessed from a first plane 107 aligned with the top surface of the substrate 102 to a second plane 108 aligned with the bottom surface of the shallow trench 133. After the shallow trench 133 is formed, a dielectric liner may be deposited on and aligned with the sidewalls of the shallow trench 133. Then, as shown in FIG. 1G, a shallow trench fill process 134 is performed to fill the shallow trench 133 with a dielectric layer 135. The shallow trench fill process 134 may include a thermal oxide growth process or an oxide deposition process. Due to the polysilicon pyramid 128, the dielectric layer 135 may produce a dielectric pyramid 136 protruding from the top surface of the dielectric layer 135.

[0020] Although FIG. 1G shows only a single dielectric cone 136 and a single polysilicon cone 128, in reality, a semiconductor device (e.g., device 100) manufactured under the above-mentioned process may produce many more dielectric cones and silicon cones in a small area. The dielectric cones may be subsequently removed during a chemical mechanical polishing process. Nevertheless, the polysilicon cone 128 remains under the dielectric layer 135. Since the dielectric layer 135 is mostly transparent, the polysilicon cone 128 is visible or detectable by one or more inspection devices. Thus, the polysilicon cone 128 may interfere with one or more inspection processes for detecting structural defects of the semiconductor device. As a result, yield-related problems may remain undetected by the inspection process. These undetected yield-related problems ultimately affect the yield of mass production of semiconductor devices.

[0021] To reduce or eliminate inspection problems related to pyramid formation, the present description introduces a method for fabricating a semiconductor device with overlapping shallow and deep trench structures that can prevent pyramid formation. According to one aspect of the present description, FIG. 2A shows a flow chart of an exemplary method 200 for fabricating a shallow trench followed by a deep trench without pyramid defects. The method 200 begins with step 210 of forming a shallow trench in a first region of a substrate. Unlike the process as depicted in FIGS. 1A-1G, the method 200 allows the shallow trench to be formed before the deep trench. For illustration, FIGS. 3A-3I show partial cross-sectional views of an exemplary semiconductor device 300 during a fabrication process implementing the method 200.

[0022] Referring to Figure 3A, for example, a semiconductor device 300 is in an early stage of a manufacturing process. The semiconductor device 300 may be a discrete component device (e.g., a single transistor device) or may be an integrated circuit having multiple transistor devices. Before step 210 is performed, a pad oxide layer 112 and a nitride cap layer 114 are sequentially formed on a top surface of the semiconductor substrate 102. The process parameters for forming the pad oxide layer 112 and the nitride cap layer 114 are essentially the same as those described in connection with Figure 1A.

[0023] During step 210, a photoresist mask 131 is deposited and patterned with an opening that exposes a shallow trench (ST) region 106 (e.g., a first region) of the substrate 102. After the photoresist mask 131 is patterned, a shallow trench etch process is performed. With reference to FIG. 3B, for example, a shallow trench etch process 132 may include a silicon etch to remove the nitride cap layer 114 and the pad oxide layer 112 exposed by the photoresist mask 131. Upon completion of the shallow trench etch 132, a shallow trench 133 is formed.

[0024] Method 200 then proceeds to step 220, which includes forming a dielectric layer that fills the shallow trenches and covers the substrate. In accordance with one aspect of the present description, the dielectric layer has a substantially planar surface overlying and extending across the shallow trenches. This substantially planar surface advantageously allows for more precise deposition and patterning of a photoresist mask for etching the deep trenches. Although step 220 may be performed by forming a single dielectric layer that fills the shallow trenches (e.g., shallow trench 133), multiple dielectric layers may be formed during step 220.

[0025] For example, FIG. 2B shows a method 220A for forming at least two dielectric layers filling a shallow trench and covering a substrate. The method 220A starts with step 222, which involves forming a shallow trench oxide layer filling the shallow trench. The shallow trench oxide layer may be considered as a first oxide layer filling the shallow trench and may be thermally grown on the etched surface of the shallow trench. As shown in FIG. 3C, for example, a first dielectric formation process 134A is performed to form a first dielectric layer 135A. The first dielectric formation process 134A may be a thermal oxidation process or an oxide deposition process (e.g., high density plasma deposition). The first dielectric layer 135A is a shallow trench oxide layer because it fills the entire shallow trench 133 located between the first plane 107 and the second plane 108 of the substrate 102. The first plane 107 is aligned along the top surface of the substrate 102 and the second plane 108 is aligned along the bottom surface of the shallow trench 133 .

[0026] After forming the shallow trench oxide layer, method 220A proceeds to step 224, which involves forming a hard mask layer overlying the shallow trench oxide layer. The hard mask layer can be considered as a second oxide layer overlying the first oxide layer. In one implementation, the second oxide layer can have a lower oxide density than the first oxide layer. The cost of forming an oxide layer with a lower oxide density is less than the cost of forming an oxide layer with a higher oxide density. Advantageously, the two-step approach provided by method 220A helps to reduce the cost of forming a dielectric layer that fills and covers the shallow trenches, as defined by step 220 in method 200.

[0027] As shown in FIG. 3D, for example, a second dielectric formation process 134B is performed to form a second dielectric layer 135B. The second dielectric formation process 134B can be a thermal oxidation process or an oxide deposition process (e.g., TEOS plasma enhanced chemical vapor deposition). The second dielectric layer 135B is a hard mask layer because it serves as a hard mask during a subsequent deep trench etching process. The second dielectric layer (or hard mask layer) 135B has a substantially flat surface 136. According to one embodiment of the present description, the surface of the second dielectric layer (or hard mask layer) 135B is substantially flat when it is sufficiently flat to allow accurate placement and patterning of a photoresist mask to etch a deep trench in the shallow trench 133. In particular, the substantially flat surface 136 can have an aspect ratio defined by the height (H) of the surface over a width (W) wide enough to function as a deep trench aperture.

[0028] In one implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially flat surface 136 with an aspect ratio of less than 0.4. In another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially flat surface 136 with an aspect ratio of less than 0.2. In yet another implementation, for example, the second dielectric layer (or hard mask layer) 135B has a substantially flat surface 136 with an aspect ratio of less than 0.1. The substantially flat surface 136 can be achieved by adjusting some process parameters for forming the first and / or second dielectric layers 135A and 135B. For example, the substantially flat surface 136 can be achieved when the second dielectric layer 135B has a thickness equal to or greater than the thickness of the first dielectric layer 135A.

[0029] Referring again to FIG. 2A, the method 200 proceeds to step 230, which involves forming a deep trench in a second region within the first region of the substrate. As shown in FIG. 3E, a deep trench (DT) etch process 121 is performed to form a deep trench 122A in the deep trench region 104, which may be, for example, a second region within the first region (e.g., 106) of the substrate 102. The DT etch process 121 may include multiple subsequences. In one implementation, for example, a hard mask etch may be performed first to remove the second and first dielectric layers 135B and 135A exposed by the patterned photoresist mask 118, and then a silicon etch may be performed to remove the substrate 102 exposed by the second dielectric layer 135B, which functions as a hard mask layer. During the silicon etch, the photoresist mask layer 118 is also removed, leaving the second dielectric layer (or hard mask layer) 135B to prevent areas outside the DT region 104 from being etched.

[0030] As a result of the DT etch process 121, the deep trench 122A extends through the second and first dielectric layers 135B and 135A. The deep trench 122A has a trench depth d2 that is greater than the trench depth d1 of the shallow trench 133, which in turn has a trench aperture that is wider (e.g., less than the width of the ST region 106) than the trench aperture of the deep trench 122A (e.g., less than the width of the DT region 104).

[0031] According to one embodiment of the present description, the DT etch process 121 is integrated with a shallow trench isolation process (e.g., steps 210-220; Figures 3A-3D). The described integration provides several advantages from a process perspective. First, the described integration reduces the total number of processing steps for fabricating a deep trench structure within a shallow trench structure. For example, redeposition of the pad oxide layer 112 and the cap nitride layer 114 (see, e.g., Figures 1D-1E) can be eliminated. This is because the shallow trench dielectric layers (e.g., 135A and 135B) can serve the functions of the pad oxide and cap nitride layers 112 and 114 during the DT etch process 121.

[0032] Second, the sequence of forming a shallow trench followed by a deep trench also helps prevent cone formation, as shown in later figures, because the deep trench fill structure 126A is no longer etched and is then covered by the shallow trench dielectric layers (e.g., 135A and 135B), reducing the opportunity for etch contaminants to become trapped and accumulate in the DT fill seam 127A of the DT structure 129A.

[0033] Third, the described integrated process overcomes a phenomenon known as deep trench pattern distortion due to thickness variations in the photoresist on the shallow trench dielectric layer (e.g., 135A and 135B). By forming a photoresist mask 118 on the substantially flat surface 136 of the second dielectric layer (or hard mask layer) 135B, the deep trench pattern dimensions (e.g., openings exposing the DT regions 106) can be critically controlled to achieve deep trench etch depth uniformity.

[0034] After forming the deep trench, method 200 proceeds to step 240, which involves forming a dielectric liner interfacing the dielectric layer in the shallow trench and the sidewalls of the deep trench. As shown in Figure 3F, for example, a DT oxide liner 124A is deposited on the etched sidewalls of dielectric layers 135A and 135B and on the sidewalls of deep trench 122A under a dielectric liner deposition process 123. In one implementation, dielectric liner deposition 123 can include low pressure chemical vapor deposition of an oxide target.

[0035] 1E and 1F which underlies shallow trench 133, DT oxide liner 124A extends upward to interface with first and second dielectric layers 135A and 135B in and above shallow trench 133. Following dielectric liner deposition process 123A, a deep trench dielectric etch process may be performed to achieve a uniform liner thickness along the sidewalls of deep trench 122A.

[0036] After forming the dielectric liner, method 200 proceeds to step 250, which includes forming a fill structure that is laterally bounded by the dielectric layer in the shallow trench and the sidewall of the deep trench. As shown in FIG. 3G, for example, a polysilicon deposition process 125 is performed to fill deep trench 122A with a conductive material. As a result, DT fill structure 126A is formed in deep trench 122A. DT fill structure 126A may abut DT oxide liner 124A and may be laterally bounded by dielectric layers 134A and 135B. During polysilicon deposition process 125, DT fill seam 127A may be formed along the vertical center of DT fill structure 126A. The dimensions of DT fill seam 127A may depend on the aspect ratio of deep trench 122A. Unlike DT fill seam 127 as shown and described in FIGS. 1F-1G, DT fill seam 127A is not subjected to further etching. Therefore, the DT fill seam 127A is unlikely to contribute to subsequent cone formation as shown and described in FIG. 1G.

[0037] After the DT filler structure 126 is formed, a chemical mechanical polishing process is performed to remove excess polysilicon material above the deep trench 122. Referring to FIG. 3H, for example, a chemical mechanical polishing process 310 is performed to remove the remaining nitride cap layer 114 and pad oxide layer 112. After the chemical mechanical polishing process 310, the semiconductor device 300 includes a deep trench structure 129A that extends downward and into a shallow trench structure 137. The shallow trench structure 137 includes a shallow trench dielectric layer 135A that extends from a first plane 107 that is aligned with the top surface of the substrate 102. The shallow trench structure 137 further extends into the substrate 102 by a first depth d1. The deep trench structure 129A extends from a first plane 107 that is aligned with the top surface of the substrate 102. The deep trench structure 129 penetrates the shallow trench dielectric layer 135A and the second plane 108 aligned with the bottom surface of the shallow trench 133. The deep trench structure 129 extends further into the substrate 102 a second depth d2 that is greater than the first depth d1.

[0038] The DT fill structure 126A of the deep trench structure 129A includes a polysilicon plate having an upper side and a lower side. The upper side has a first width and is located in the shallow trench 133. The lower side has a second width and is located in the deep trench 122A. In one implementation, the first width is greater than the second width. The DT oxide liner 124A interfaces between the upper side of the polysilicon plate and the shallow trench dielectric layer 135A. The DT oxide liner 124A also interfaces between the lower side of the polysilicon plate and the substrate 102. In one implementation, the DT oxide liner 124A has a lower oxide density than the shallow trench dielectric layer 135A.

[0039] At this stage of the fabrication process (see, e.g., FIG. 3H), the semiconductor device 300 is substantially free of cones about the top surface of the deep trench structure 129, as well as the shallow trench structure 137. The semiconductor device 300 may be prepared for further processing, which may include the formation of one or more dielectric layers over the deep trench structure 129, as well as the shallow trench structure 137. With reference to FIG. 3I, for example, a dielectric deposition process 320 may be performed to form a dielectric layer 322 covering the DT top surface 128A as well as the top surfaces of the substrate 102 and the shallow trench structure 137. In the event that the DT fill structure 126A is not further etched, subsequent deposition of a dielectric layer thereon is unlikely to result in any cone formation.

[0040] In this description, the term "configured to" describes the structural and functional characteristics of one or more tangible, non-transient components. For example, the term "configured to" may be understood to have a particular configuration that is designed or dedicated to perform a certain function. Within this understanding, if a device includes a tangible, non-transient component that can be enabled, activated, or powered to perform the certain function, then such a device is "configured to" perform the certain function. Although the term "configured to" may encompass configurability, it does not require that the device being described be configurable at any given time.

[0041] In particular, with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components correspond, unless otherwise indicated, to any component that performs the specified function (e.g., is functionally equivalent) of the described component, even though it is not structurally equivalent to the described structure. Also, although a particular feature of this description has been described with respect to only one of several implementations, such feature can be combined with one or more other features of other implementations, as may be desirable and advantageous for any given or particular application.

[0042] In this description, relative terms such as "about," "approximately," "substantially," "in the vicinity," "within the approximation," "sufficient to," "maximum," and "minimum" applied to features of an integrated circuit and / or semiconductor device may be understood in the context of manufacturing tolerances of a particular process for fabricating the integrated circuit and / or semiconductor device, and these relative terms may be understood within the context of performing one or more functions with the integrated circuit and / or semiconductor device.

[0043] More specifically, for example, the terms "substantially the same," "substantially equal," and "about the same" express a quantitative relationship between two objects. This quantitative relationship may favor two objects being equal by design, but understands that a certain amount of variation may be introduced by the manufacturing process. In one aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor, where the first and second resistors are intended to have identical resistances, but the manufacturing process still introduces slight variations between the first and second resistances. Thus, the first resistance may be substantially equal to the second resistance, even if the manufactured first and second resistors exhibit a slight difference in resistance. This slight difference may be within 5% of the design target. In another aspect, a first resistor may have a first resistance that is substantially equal to a second resistance of a second resistor, where the process variation is known a priori, such that the first and second resistances may be preset at slightly different values ​​to account for the known process variation. Thus, the first resistance can be made substantially equal to the second resistance even if the design values ​​of the first and second resistances are preset to include a small difference to account for known process variations, which may be within 5% of the design target.

[0044] Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Also, although features may be described above as acting in certain combinations, one or more features from a claimed combination may in some cases be omitted from such combinations, and the claimed combinations may be directed to subcombinations or variations of the subcombinations.

[0045] Similarly, although operations are shown in the figures in a particular order, this does not require that such operations be performed in the particular order shown, or in a sequential order, or that all of the operations shown be performed, to achieve desired results. In some situations, multitasking and parallel processing may be advantageous. Also, the separation of various system components in the above-described embodiments does not require such separation in all embodiments.

[0046] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the invention.

Claims

1. A semiconductor device, a semiconductor substrate having a top surface; a trench formed in the semiconductor substrate; a conductive fill structure within the trench; an insulator between the semiconductor substrate and the conductive fill structure, the insulator including an upper portion having a top surface at a top surface of the semiconductor substrate and a lower portion forming a corner with the upper portion and extending from the corner to a bottom of the trench; 10. A semiconductor device comprising:

2. A semiconductor device according to claim 1, a semiconductor device, wherein the upper portion of the insulator has a lower surface that extends from the corner and laterally away from the conductive fill structure; 3. The semiconductor device of claim 1, The semiconductor device, wherein the conductive fill structure comprises polysilicon.

4. The semiconductor device of claim 1, The semiconductor device, wherein the conductive fill structure has a seam that intersects a top surface of the conductive fill structure.

5. The semiconductor device of claim 1, A semiconductor device, wherein the insulator comprises silicon oxide.

6. The semiconductor device of claim 1, The semiconductor device further includes a dielectric layer overlying and contacting the insulator and the conductive fill structure.

7. The semiconductor device of claim 4, The semiconductor device further includes a dielectric layer overlying and contacting the insulator and the conductive fill structure.

8. A method for forming a semiconductor device, comprising: forming a first trench in a semiconductor substrate; filling the first trench with an insulator; forming a second trench within the first trench, the second trench having a first sidewall in the insulator at an upper portion and a second sidewall in the semiconductor substrate at a lower portion; A method comprising:

9. The method of claim 8, The method further includes forming a dielectric liner covering a first sidewall and a second sidewall of the second trench.

10. The method according to claim 9, The method further includes filling the second trench with a conductive material over the dielectric liner.

11. The method according to claim 10, The method, wherein the conductive material comprises polysilicon.

12. The method of claim 10, The method, wherein the conductive material includes a seam in the second trench.

13. The method of claim 10, The method further includes removing the insulator, the dielectric liner, and the conductive material over a top surface of the semiconductor substrate.

14. The method of claim 10, The method wherein the dielectric liner has a lower density than the insulator.

15. The method of claim 10, The method wherein the insulator is formed by a thermal oxidation process.

16. The method of claim 10, The method, wherein the insulator comprises a first dielectric layer formed by a thermal oxidation process and a second dielectric layer formed by a plasma deposition process.

17. The method of claim 10, The method, wherein the insulator includes a first dielectric layer formed by a first plasma oxide deposition process and a second dielectric layer formed by a second plasma oxide deposition process.

18. The method of claim 17, The method, wherein the first plasma oxide deposition process is a high density plasma oxide deposition process and the second plasma oxide deposition process is a TEOS chemical vapor deposition process.

19. A method for forming a semiconductor device, comprising: forming a first trench in a semiconductor substrate; forming a first dielectric layer in the first trench; forming a second dielectric layer in the first trench and over the first dielectric layer; forming a second trench within the first trench, the second trench having first sidewalls including sidewalls of the first and second dielectric layers at an upper portion and second sidewalls of the semiconductor substrate at a lower portion; A method comprising:

20. The method of claim 19, The method further includes forming a dielectric liner covering a first sidewall and a second sidewall of the second trench.

21. The method of claim 20, The method further includes filling the second trench with a conductive material over the dielectric liner.

22. The method of claim 21, The method, wherein the conductive material comprises polysilicon.

23. The method of claim 21, The method, wherein the conductive material includes a seam in the second trench.

24. The method of claim 21, The method further includes removing the first and second dielectric layers, the dielectric liner, and the conductive material over the top surface of the semiconductor substrate.

25. The method of claim 20, The method wherein the dielectric liner is less dense than the first dielectric layer.

26. The method of claim 19, The method, wherein the first dielectric layer is formed by a thermal oxidation process and the second dielectric layer is formed by a plasma deposition process.

27. The method of claim 19, The method, wherein the first dielectric layer is formed by a high density plasma deposition process and the second dielectric layer is formed by a TEOS chemical vapor deposition process.

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