Semiconductor device

Abstract

To provide a semiconductor device including a source region and a drain electrode whose resistance is reduced without depending on a silicon nitride contained in a protection insulation layer.SOLUTION: A semiconductor device includes: an oxide insulation layer; an oxide semiconductor layer on the oxide insulation layer; a gate insulation layer that is in contact with the oxide semiconductor layer on the oxide semiconductor layer; and a gate electrode on the gate insulation layer. The oxide semiconductor layer includes: a channel region that is overlapped with the gate electrode; and a source region and a drain region that are not overlapped with the gate electrode. In the source region and a boundary between the drain region and the gate insulation layer, the contaminant concentration in the drain region and on the surface of the drain region is 1×1019 cm-3 or more.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. [Background technology]

[0002] In recent years, semiconductor devices using oxide semiconductors as channels instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single crystal silicon have been developed (see, for example, Patent Documents 1 to 6). Semiconductor devices including such oxide semiconductors can be formed with a simple structure and a low-temperature process, similar to semiconductor devices including amorphous silicon. In addition, semiconductor devices including oxide semiconductors are known to have higher field-effect mobility than semiconductor devices including amorphous silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] In an oxide semiconductor, carriers are generated when hydrogen is trapped in oxygen defects. By utilizing this mechanism, in a semiconductor device, oxygen defects are formed in an oxide semiconductor layer, and hydrogen is supplied to the formed oxygen defects, thereby forming a source region and a drain region in the oxide semiconductor layer having a higher carrier concentration than a channel region electrically connected to a source electrode and a drain electrode. Silicon nitride contains a large amount of hydrogen. Therefore, by forming silicon nitride as a protective insulating layer of a semiconductor device and supplying hydrogen contained in the silicon nitride to the source region and the drain region, a source region and a drain region having low resistance can be formed. In other words, a protective insulating layer containing silicon nitride was necessary to reduce the resistance of the source region and the drain region.

[0005] An object of one embodiment of the present invention is to provide a semiconductor device including source and drain regions with reduced resistance, without relying on silicon nitride contained in a protective insulating layer. [Means for solving the problem]

[0006] A semiconductor device according to an embodiment of the present invention includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on the oxide semiconductor layer and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region not overlapping with the gate electrode. At interfaces between the source region and the gate insulating layer, and between the gate insulating layer and the gate insulating layer, the impurity concentrations at the surfaces of the source region and the drain region are 1×10 19 cm -3 That's all. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a schematic enlarged partial cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 4] 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1 is a graph showing the correlation between the boron concentration at the surface of the source region and the drain region and the sheet resistance in an example sample and a comparative example sample. [Figure 14] 4 is a schematic cross-sectional view illustrating a hydrogen trapping region that traps hydrogen supplied from a protective insulating layer. FIG. [Figure 15] 1 is a graph showing the electrical characteristics of Example Sample 1-1 to Example Sample 1-4. [Figure 16] 1 is a graph showing the electrical characteristics of Example Samples 2-1 to 2-4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0009] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a semiconductor device, the semiconductor device and the pixel electrode may overlap in a planar view.

[0010] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] A semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 to 12. The semiconductor device 10 can be used, for example, in a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.

[0014] [1. Configuration of Semiconductor Device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Fig. 2 is a schematic plan view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Specifically, Fig. 1 is a cross-sectional view taken along line A-A' in Fig. 2.

[0015] As shown in FIG. 1, the semiconductor device 10 includes a substrate 100, a light-shielding layer 105, a nitride insulating layer 110, a first oxide insulating layer 120, a second oxide insulating layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a source electrode 201, and a drain electrode 203. The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 covers the upper surface and end surfaces of the light-shielding layer 105 and is provided on the substrate 100. The first oxide insulating layer 120 is provided on the nitride insulating layer 110. The second oxide insulating layer 130 has a predetermined pattern and is provided on the first oxide insulating layer 120. The oxide semiconductor layer 140 has a pattern similar to that of the second oxide insulating layer 130 and is provided on the second oxide insulating layer 130. The gate insulating layer 150 covers the upper surface and end surface of each of the second oxide insulating layer 130 and the oxide semiconductor layer 140, and is provided on the first oxide insulating layer 120. The gate electrode 160 overlaps the oxide semiconductor layer 140 and is provided on the gate insulating layer 150. The gate insulating layer 150 has openings 171 and 173 through which a part of the upper surface of the oxide semiconductor layer 140 is exposed. The source electrode 201 is provided on the gate insulating layer 150 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the gate insulating layer 150 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. The source electrode 201 and the drain electrode 203 are in contact with the surface of the gate insulating layer 150 that is in contact with the gate electrode 160. In the following, when the source electrode 201 and the drain electrode 203 are not particularly distinguished from each other, they may be collectively referred to as the source-drain electrode 200.

[0016] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH with respect to the gate electrode 160. That is, the oxide semiconductor layer 140 includes the channel region CH overlapping with the gate electrode 160, and the source region S and the drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has a semiconductor property. Each of the source region S and the drain region D has a conductor property. Therefore, the carrier concentration of the source region S and the drain region D is higher than the carrier concentration of the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0017] 2, each of the light-shielding layer 105 and the gate electrode 160 has a certain width in the D1 direction and extends in the D2 direction perpendicular to the D1 direction. In the D1 direction, the width of the light-shielding layer 105 is larger than the width of the gate electrode 160. The channel region CH completely overlaps with the light-shielding layer 105. In the semiconductor device 10, the D1 direction corresponds to the direction in which a current flows from the source electrode 201 to the drain electrode 203 through the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0018] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used as the substrate 100. A rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used as the substrate. A flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used as the substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-mentioned resin substrate. Note that a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0019] The light-shielding layer 105 can reflect or absorb external light. As described above, the light-shielding layer 105 is provided to have an area larger than the channel region CH of the oxide semiconductor layer 140, and therefore can block external light incident on the channel region CH. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof can be used as the light-shielding layer 105. Furthermore, when electrical conductivity is not required, the light-shielding layer 105 does not necessarily need to contain a metal. For example, a black matrix made of a black resin can be used as the light-shielding layer 105. Furthermore, the light-shielding layer 105 may have a single-layer structure or a laminated structure. For example, the light-shielding layer 105 may have a laminated structure of a red color filter, a green color filter, and a blue color filter.

[0020] The nitride insulating layer 110 can prevent impurities (e.g., sodium, etc.) contained in the substrate 100 or impurities (e.g., water, etc.) entering from the outside from diffusing into the oxide semiconductor layer 140. For example, a nitride containing silicon or aluminum can be used as the nitride insulating layer 110. Specifically, silicon nitride (SiN x ), silicon oxynitride (SiN x O y), Aluminum Nitride (AlN x ), or aluminum oxide nitride (AlN x O y ) or the like can be used. The nitride insulating layer 110 may have a single layer structure or a stacked layer structure.

[0021] Each of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 can suppress the diffusion of hydrogen into the channel region CH. In particular, if a hydrogen trapping region, which will be described later, is formed in at least one of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150, this effect is high. Each of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 can be made of an oxide containing, for example, silicon or aluminum. Specifically, each of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ) can be used. The oxide contained in the second oxide insulating layer 130 is different from the oxide contained in the first oxide insulating layer 120. Since the second oxide insulating layer 130 is formed into a predetermined pattern by etching, it is preferable that the first oxide insulating layer 120 and the second oxide insulating layer 130 be oxides having different etching rates. Aluminum oxide is preferably used as the second oxide insulating layer 130. Each of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 may have a single-layer structure or a stacked-layer structure.

[0022] In this embodiment, a configuration in which the second oxide insulating layer 130 is not provided may also be applied.

[0023] Here, silicon oxynitride (SiO x N y) and aluminum oxide nitride (AlO x N y ) are oxides that contain a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Silicon oxynitride (SiN x O y ) and aluminum oxide nitride (AlN x O y ) are nitrides that contain a smaller proportion of oxygen than nitrogen (x>y).

[0024] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, can be used for each of the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a laminated structure.

[0025] As the oxide semiconductor layer 140, an oxide semiconductor containing two or more metal elements including an indium (In) element is used. As metal elements other than the indium element, a gallium (Ga) element, a zinc (Zn) element, an aluminum (Al) element, a hafnium (Hf) element, an yttrium (Y) element, a zirconium (Zr) element, and a lanthanoid are used. The oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. However, in order to improve the electrical characteristics, it is preferable that the oxide semiconductor layer 140 has a polycrystalline structure. In particular, it is preferable that the crystal structure of the source region S and the drain region D is the same as the crystal structure of the channel region CH.

[0026] When the oxide semiconductor layer 140 has a polycrystalline structure, it is preferable to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio as the oxide semiconductor layer 140. When the ratio of indium is large, the oxide semiconductor layer 140 is more likely to crystallize. In addition, it is preferable to contain gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not inhibited by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0027] A detailed manufacturing method of the oxide semiconductor layer 140 will be described later in the manufacturing method of the semiconductor device 10, but the oxide semiconductor layer 140 can be formed by sputtering. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 140 are substantially the same. In this case, the composition of the metal elements of the oxide semiconductor layer 140 can be specified based on the composition of the metal elements of the sputtering target. When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor film may be specified by using an X-ray diffraction (XRD) method. Specifically, the composition of the metal elements of the oxide semiconductor film can be specified based on the crystal structure and lattice constant of the oxide semiconductor film obtained by the XRD method. Furthermore, the composition of the metal elements of the oxide semiconductor layer 140 can also be specified by using an X-ray fluorescence analysis or an Electron Probe Micro Analyzer (EPMA) analysis. Note that the oxygen element contained in the oxide semiconductor layer 140 varies depending on the sputtering process conditions and the like, and is not limited to the above.

[0028] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using a Poly-OS (Polycrystalline Oxide Semiconductor) technique. In the following, an oxide semiconductor having a polycrystalline structure may be described as a Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0029] [2. Hydrogen trapping area configuration] Fig. 3 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device 10 according to one embodiment of the present invention. Specifically, Fig. 3 is an enlarged cross-sectional view of a region P in Fig. 1. Note that the region P shown in Fig. 3 is a region in the vicinity of the drain region D, but the vicinity of the source region S also has a similar configuration to the region P.

[0030] Although details will be described later, the source region S and the drain region D of the oxide semiconductor layer 140 are formed by ion implantation of an impurity using the gate electrode 160 as a mask. As the impurity, for example, boron (B), phosphorus (P), argon (Ar), or nitrogen (N) is used. By the ion implantation, oxygen defects are formed in the source region S and the drain region D of the oxide semiconductor layer 140. Then, hydrogen is trapped in the formed oxygen defects, thereby reducing the resistance of the source region S and the drain region D.

[0031] The ion implantation is performed through the gate insulating layer 150. At this time, dangling bond defects DB (marked with x in FIG. 3) are formed in the gate insulating layer 150 by the ion implantation. In addition, in the ion implantation, the impurity has a distribution in the depth direction, and the impurity is implanted not only in the gate insulating layer 150 but also in the first oxide insulating layer 120 and the second oxide insulating layer 130. Therefore, dangling bond defects DB are formed in the first oxide insulating layer 120 and the second oxide insulating layer 130. Note that, as described above, the impurity is implanted by using the gate electrode 160 as a mask, so that the impurity is not implanted in the region overlapping with the gate electrode 160, and therefore no dangling bond defects DB are formed.

[0032] When the amount of dangling bond defects DB in a certain region exceeds a predetermined value, that region functions as a hydrogen trap region that traps hydrogen. That is, when dangling bond defects DB exceeding a predetermined amount of defects are formed in the gate insulating layer 150, a hydrogen trap region is formed in the gate insulating layer 150. The hydrogen trap region is formed by ion implantation and does not overlap with the gate electrode 160. As will be described in detail later, at the interface between the gate insulating layer 150 and the oxide semiconductor layer 140 (specifically, the source region S and the drain region D), when the impurity concentration at the surface of the source region S and the drain region D is 2×10 17 cm -3 When the concentration is equal to or higher than this, a hydrogen trapping region is formed in the gate insulating layer 150. In order for the semiconductor device 10 to have good electrical characteristics, the impurity concentration at the surfaces of the source region S and the drain region D must be 2×10 19 cm -3 More preferably, it is equal to or greater than this.

[0033] Here, the "impurity concentration at the surface" refers to the impurity concentration near the surface. The "surface vicinity" refers to a region included in a depth of 4 nm from the interface between the gate insulating layer 150 and the oxide semiconductor layer 140 (or the upper surface of the oxide semiconductor layer 140) in the film thickness direction of the oxide semiconductor layer 140. However, the depth near the surface is not limited to 4 nm. For example, the depth near the surface may be 1 / 5 of the film thickness of the oxide semiconductor layer 140 based on the film thickness of the oxide semiconductor layer 140. The impurity concentration may be a value converted from the dose of ion implantation, or may be a value measured by analysis such as secondary ion mass spectroscopy (SIMS).

[0034] As described above, the dangling bond defects DB are formed not only in the gate insulating layer 150 but also in the first oxide insulating layer 120 and the second oxide insulating layer 130. Therefore, the first oxide insulating layer 120 and the second oxide insulating layer 130 may also have hydrogen trapping regions that do not overlap with the gate electrode 160. The hydrogen trapping regions of the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer can significantly suppress the diffusion of hydrogen into the channel region CH.

[0035] When silicon oxide is used as the first oxide insulating layer 120, silicon dangling bond defects DB are formed in the first oxide insulating layer 120. When aluminum oxide is used as the second oxide insulating layer 130, aluminum dangling bond defects DB are formed in the second oxide insulating layer 130. In this way, different types of dangling bond defects DB are formed in the first oxide insulating layer 120 and the second oxide insulating layer 130, and it is also possible to differentiate the hydrogen trapping performance in the hydrogen trapping region.

[0036] Since hydrogen is trapped in the hydrogen trapping regions, the hydrogen trapping regions not overlapping with the gate electrode 160 have a higher hydrogen concentration than the regions overlapping with the gate electrode 160 .

[0037] The configuration of the semiconductor device 10 has been described above, but the semiconductor device 10 described above is a so-called top-gate type transistor. The semiconductor device 10 can be modified in various ways. For example, when the light-shielding layer 105 is conductive, the semiconductor device 10 may be configured such that the light-shielding layer 105 functions as a gate electrode, and the nitride insulating layer 110, the first oxide insulating layer 120, and the second oxide insulating layer 130 function as gate insulating layers. In this case, the semiconductor device 10 is a so-called dual-gate type transistor. When the light-shielding layer 105 is conductive, the light-shielding layer 105 may be a floating electrode or may be connected to the source electrode 201. Furthermore, the semiconductor device 10 may be a so-called bottom-gate type transistor in which the light-shielding layer 105 functions as a main gate electrode.

[0038] [3. Method for Manufacturing Semiconductor Device 10] A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 4 to Fig. 12. Fig. 4 is a flowchart showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figs. 5 to 12 are schematic cross-sectional views showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention.

[0039] 4, the method for manufacturing the semiconductor device 10 includes steps S1010 to S1110. Steps S1010 to S1110 will be described in order below, but the order of the steps may be reversed in the method for manufacturing the semiconductor device 10. Furthermore, the method for manufacturing the semiconductor device 10 may include additional steps.

[0040] In step S1010, a light-shielding layer 105 having a predetermined pattern is formed on the substrate 100 (see FIG. 5). The light-shielding layer 105 is patterned by using a photolithography method.

[0041] In step S1020, the nitride insulating layer 110 and the first oxide insulating layer 120 are formed in this order on the light-shielding layer 105 (see FIG. 6). The nitride insulating layer 110 and the first oxide insulating layer 120 are formed by using a CVD method. For example, a silicon nitride film and a silicon oxide film are formed as the nitride insulating layer 110 and the first oxide insulating layer 120, respectively. The silicon nitride film and the silicon oxide film can also be formed successively in the same chamber by changing the reactive gas.

[0042] In a step described later, dangling bond defects having a hydrogen trapping function are formed in a predetermined region of the first oxide insulating layer 120. Therefore, the first oxide insulating layer 120 does not need to be a film containing excess oxygen that becomes a hydrogen trap, and is preferably a dense film with few defects that is formed at 350° C. or higher. When the first oxide insulating layer 120 is a film containing excess oxygen, the reliability of the semiconductor device 10 is reduced. However, by forming the first oxide insulating layer 120 as a dense film, the reliability of the semiconductor device 10 can be improved.

[0043] The thickness of the nitride insulating layer 110 is, for example, 50 nm to 500 nm, preferably 150 nm to 300 nm, and the thickness of the first oxide insulating layer 120 is, for example, 50 nm to 500 nm, preferably 150 nm to 300 nm.

[0044] In step S1030, the second oxide insulating film 135 and the oxide semiconductor film 145 are formed on the first oxide insulating layer 120 (see FIG. 7). The second oxide insulating film 135 and the oxide semiconductor film 145 are formed by a sputtering method. An aluminum oxide film is formed as the second oxide insulating film 135. The thickness of the second oxide insulating film 135 is, for example, 1 nm to 30 nm, preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. The thickness of the oxide semiconductor film 145 is, for example, 10 nm to 100 nm, preferably 15 nm to 70 nm, and more preferably 15 nm to 40 nm.

[0045] The oxide semiconductor film 145 in step S1030 is amorphous. In the Poly-OS technique, in order for the oxide semiconductor layer 140 to have a uniform polycrystalline structure in the substrate surface, it is preferable that the oxide semiconductor film 145 after film formation and before heat treatment is amorphous. Therefore, it is preferable that the film formation conditions of the oxide semiconductor film 145 are conditions under which the oxide semiconductor layer 140 immediately after film formation is not crystallized as much as possible. When the oxide semiconductor film 145 is formed by a sputtering method, the oxide semiconductor film 145 is formed while controlling the temperature of the film formation target (the substrate 100 and the layer formed on the substrate 100) to 100° C. or less, preferably 80° C. or less, and more preferably 50° C. or less. In addition, the oxide semiconductor film 145 is formed under a condition of low oxygen partial pressure. The oxygen partial pressure is 2% or more and 20% or less, preferably 3% or more and 15% or less, and more preferably 3% or more and 10% or less.

[0046] In step S1040, the second oxide insulating film 135 and the oxide semiconductor film 145 are patterned (see FIG. 8). The second oxide insulating film 135 and the oxide semiconductor film 145 are patterned by photolithography. The second oxide insulating film 135 and the oxide semiconductor film 145 may be etched by wet etching or dry etching. In the wet etching, an acidic etchant may be used. As the etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, or hydrofluoric acid may be used. Since the oxide semiconductor film 145 in step S1040 is amorphous, the oxide semiconductor film 145 can be easily patterned into a predetermined shape by wet etching. In addition, the second oxide insulating film 135 can also be patterned into a predetermined shape by using the oxide semiconductor film 145 as a mask. In this way, the second oxide insulating layer 130 is formed.

[0047] In step S1050, a heat treatment is performed on the oxide semiconductor film 145. Hereinafter, the heat treatment performed in step S1050 is referred to as "OS annealing". In the OS annealing, the oxide semiconductor film 145 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the target temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. The OS annealing crystallizes the oxide semiconductor film 145, and the oxide semiconductor layer 140 having a polycrystalline structure (i.e., the oxide semiconductor layer 140 including Poly-OS) is formed.

[0048] In step S1060, the gate insulating layer 150 is formed on the second oxide insulating layer 130 and the oxide semiconductor layer 140 (see FIG. 9). The gate insulating layer 150 is formed by using a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is 50 nm to 300 nm, preferably 60 nm to 200 nm, and more preferably 70 nm to 150 nm.

[0049] In step S1070, a heat treatment is performed on the oxide semiconductor layer 140. Hereinafter, the heat treatment performed in step S1070 is referred to as "oxidation annealing." When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen defects are formed on the upper surface and side surfaces of the oxide semiconductor layer 140. When oxidation annealing is performed in a state in which the oxide semiconductor layer 140 is surrounded by the second oxide insulating layer 130 and the gate insulating layer 150, oxygen is supplied to the oxide semiconductor layer 140 via the second oxide insulating layer 130 and the gate insulating layer 150, and the oxygen defects in the oxide semiconductor layer 140 are repaired.

[0050] In step S1080, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see FIG. 10). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned by photolithography.

[0051] In step S1090, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see FIG. 11). The source region S and the drain region D are formed by ion implantation. The ion implantation can be performed using an ion doping device or an ion implantation device. Specifically, impurities are implanted into the oxide semiconductor layer 140 through the gate insulating layer 150 using the gate electrode 160 as a mask. For example, boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like is used as the implanted impurity. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen defects are formed by the ion implantation, and hydrogen is trapped in the formed oxygen defects. This reduces the resistance of the source region S and the drain region D. On the other hand, in the channel region CH that overlaps with the gate electrode 160, impurities are not implanted, so that oxygen defects are not formed and the resistance of the channel region CH does not reduce.

[0052] In step S1090, impurities are also implanted into the gate insulating layer 150, the second oxide insulating layer 130, and the first oxide insulating layer 120. Dangling bond defects DB are formed in the gate insulating layer 150, the second oxide insulating layer 130, and the first oxide insulating layer 120 by ion implantation. That is, hydrogen trapping regions caused by the dangling bond defects DB are formed in each of the gate insulating layer 150, the second oxide insulating layer 130, and the first oxide insulating layer 120. Since the hydrogen trapping regions are formed by ion implantation, the hydrogen trapping regions contain impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N).

[0053] In the ion implantation in step S1090, the impurity concentration at the surface of the source region S and the drain region D at the interface between the gate insulating layer 150 and the oxide semiconductor layer 140 (specifically, the source region S and the drain region D) is 1×10 19 cm -3 As described above, the process parameters of the ion implantation (e.g., dose amount, acceleration voltage, plasma power, etc.) are controlled. For example, the dose amount is 1×10 14 cm -2 or higher and the acceleration voltage is 20 keV or higher, but the process parameters are not limited to these.

[0054] The concentration of impurities on the surface of the oxide semiconductor layer 140 is 1×10 19 cm -3 In this case, sufficient oxygen defects are formed in the source region S and the drain region D. Furthermore, dangling bond defects DB are formed and hydrogen is generated in the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150. In this case, even if a protective insulating layer containing silicon nitride is not provided on the gate insulating layer 150, hydrogen generated in the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 is supplied to the oxygen defects formed in the source region S and the drain region D. Therefore, the resistance of the source region S and the drain region D is sufficiently reduced.

[0055] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150 (see FIG. 12). By forming the openings 171 and 173, the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0056] In step S1110, a source electrode 201 is formed on the gate insulating layer 150 and inside the opening 171, and a drain electrode 203 is formed on the gate insulating layer 150 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed as the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning one conductive film that has been deposited. Through the above steps, the semiconductor device 10 shown in FIG. 1 is manufactured.

[0057] The manufacturing method of the semiconductor device 10 is not limited to the above steps. For example, a step of forming a protective insulating layer may be included after step S1110. In this embodiment, since the source region S and the drain region D have sufficiently low resistance in step S1090, a configuration in which the protective insulating layer does not contain silicon nitride is also possible. For example, a planarizing film such as a polyimide resin can be used as the protective insulating layer.

[0058] As described above, in the semiconductor device 10 according to one embodiment of the present invention, a hydrogen trapping region is formed in the gate insulating layer 150, and oxygen defects are formed in the source region S and the drain region D. In addition, hydrogen is generated in the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 by ion implantation. When the impurity concentration at the surface of the source region S and the drain region D reaches 1×10 19 cm -3 If the above is the case, sufficient oxygen defects are formed in the source region S and the drain region D. In this case, hydrogen generated in the first oxide insulating layer 120, the second oxide insulating layer 130, and the gate insulating layer 150 is supplied to the oxygen defects formed in the source region S and the drain region D. Therefore, the semiconductor device 10 includes the source region S and the drain region D with reduced resistance and has electrical characteristics with suppressed depletion, regardless of whether or not a protective insulating layer containing silicon nitride is formed. EXAMPLES

[0059] The semiconductor device 10 will be described in further detail based on a fabricated sample.

[0060] [1. Preparation of Example Samples] As Example 1, the above-mentioned manufacturing method was used to control the acceleration voltage and the dose amount, and the concentration of impurities (boron) on the surfaces of the source and drain regions was 1×10 19 cm -3 The above four semiconductor devices (Example Sample 1-1 to Example Sample 1-4) were manufactured. In Example 2, a protective insulating layer containing silicon nitride was provided, and the concentration of impurities (boron) on the surfaces of the source and drain regions was 1×10 19 cm -3 The above four semiconductor devices (Example Sample 2-1 to Example Sample 2-4) were fabricated. Specifically, in Example 2, after step S1090, a protective insulating layer containing silicon nitride was formed. Thereafter, similarly to steps S1100 and S1110, openings were formed in the protective insulating layer and the gate insulating layer, and a source electrode and a drain electrode were formed so as to be electrically connected to the source region and the drain region, respectively, through the openings.

[0061] [2. Preparation of Comparative Example Sample] As Comparative Example 1, a manufacturing method similar to that of Example 1 was used, and the acceleration voltage and the dose were controlled to make the concentration of impurities (boron) on the surfaces of the source and drain regions 1×10 19 cm -3 Nine semiconductor devices (Comparative Example Sample 1-1 to Comparative Example Sample 1-9) were fabricated, each of which had a thickness of less than 1×10. Also, as Comparative Example 2, a protective insulating layer containing silicon nitride was provided using the same manufacturing method as in Example 2, and the concentration of impurities (boron) on the surfaces of the source and drain regions was 1×10. 19 cm -3 Nine semiconductor devices (Comparative Example Sample 2-1 to Comparative Example Sample 2-9) having a density of less than 100 μm were fabricated.

[0062] In both the example sample and the comparative sample, the oxide semiconductor layer contained indium, and the atomic ratio of indium to all metal elements was 50% or more. The oxide semiconductor layer had an amorphous structure before OS annealing, but was crystallized after OS annealing to have a polycrystalline structure. That is, the oxide semiconductor layer in both the example sample and the comparative sample contained Poly-OS.

[0063] The boron concentrations in the surfaces of the source and drain regions in the example samples are shown in Table 1. The boron concentrations in the surfaces of the source and drain regions in the comparative sample are shown in Table 2. The boron concentrations were calculated from the dose amount in ion implantation.

[0064] [Table 1]

[0065] [Table 2]

[0066] [3. Measurement of sheet resistance] 13 is a graph showing the correlation between the boron concentration in the surface of the source region and the drain region and the sheet resistance in the example sample and the comparative sample. For convenience of explanation, the graph in FIG. 13 shows that the boron concentration in the comparative sample 1-1 and the comparative sample 2-1 is 2×10 15 cm -3 The plot is taken as

[0067] The graph shown in FIG. 13 is divided into three ranges based on the concentration of boron at the surface of the source and drain regions. The first range is 2×10 17 cm -3 the second range is less than 2×10 17 cm -3 More than 1×10 19 cm -3and the third range is 1 x 10 19 cm -3 These are the ranges. Comparative Example Samples 1-1 to 1-6 and Comparative Example Samples 2-1 to 2-6 belong to the first range. Comparative Example Samples 1-7 to 1-9 and Comparative Example Samples 2-7 to 2-9 belong to the second range. Example Samples 1-1 to 1-4 and Example Samples 2-1 to 2-4 belong to the third range.

[0068] In the first range, the sheet resistance of the source region and drain region of Comparative Sample 1-1 to Comparative Sample 1-6 is larger than the sheet resistance of the source region and drain region of Comparative Sample 2-1 to Comparative Sample 2-6. Since Comparative Sample 2-1 to Comparative Sample 2-6 are provided with a protective insulating layer containing silicon nitride, sufficient hydrogen is supplied from the protective insulating layer to the source region and drain region. Therefore, the source region and drain region of Comparative Sample 2-1 to Comparative Sample 2-5 are made low-resistance. On the other hand, Comparative Sample 1-1 to Comparative Sample 1-6 are not provided with a protective insulating layer containing silicon nitride. Therefore, hydrogen is not supplied to the source region and drain region of Comparative Sample 1-1 to Comparative Sample 1-6, and the resistance is not reduced.

[0069] Thus, the first range is a range in which the resistance of the source region and the drain region is reduced by the supply of hydrogen from the protective insulating layer containing silicon nitride. However, in the first range, sufficient oxygen defects are not formed in the source region and the drain region. Therefore, the hydrogen supplied to the source region and the drain region diffuses into the channel region without being trapped in the source region and the drain region. Therefore, in the first range, it is difficult to obtain electrical characteristics that indicate switching performance.

[0070] In the second range, as can be seen from the trends of Comparative Example 2-7 to Comparative Example 2-9, the sheet resistance of the source region and the drain region increases. Similarly, in Comparative Example Sample 1-7 to Comparative Example Sample 1-9, the sheet resistance of the source region and the drain region tends to decrease overall, but there is a range where the sheet resistance of the source region and the drain region increases. Here, the reason for the increase in the sheet resistance of the source region and the drain region will be described with reference to FIG. 14.

[0071] FIG. 14 is a schematic cross-sectional view illustrating a hydrogen trapping region that traps hydrogen supplied from the protective insulating layer 170. As shown in FIG.

[0072] 14, when sufficient dangling bond defects DB are formed in the gate insulating layer 150 to form a hydrogen trapping region, the supply of hydrogen from the protective insulating layer 170 containing silicon nitride to the source region S and the drain region D is suppressed by the hydrogen trapping region. Therefore, although the source region S and the drain region D have oxygen defects, hydrogen is not supplied to the oxygen defects, and the sheet resistance of the source region S and the drain region D increases.

[0073] Thus, the second range is a range in which a hydrogen trapping region is formed in the gate insulating layer by ion implantation. In the second range, hydrogen is preferentially trapped in the hydrogen trapping region, so that the supply of hydrogen to the source region and the drain region is suppressed. Therefore, in the second range, the contact resistance between the source region and the source electrode and the drain electrode, respectively, is increased, and the current flowing through the channel region is suppressed. As a result, electrical characteristics with a reduced on-current are obtained.

[0074] In the third range, the sheet resistance of the source region and the drain region of Example Sample 1-1 to Example Sample 1-4 is 1×10 2or less, which is comparable to the sheet resistance of the source region and drain region of Example Sample 2-1 to Example Sample 2-4. That is, in Example Sample 1-1 to Example Sample 1-4, the resistance of the source region and drain region is sufficiently reduced even without the supply of hydrogen from the protective insulating layer.

[0075] Thus, in the third range, sufficient oxygen defects are formed in the source and drain regions by ion implantation, and as a result, hydrogen is supplied from the first oxide insulating layer and the second oxide insulating layer to the oxygen defects in the source and drain regions. That is, the amount of hydrogen supplied to the source and drain regions is controlled according to the oxygen defects, so that the diffusion of hydrogen into the channel region is suppressed. Therefore, electrical characteristics that exhibit switching performance and suppress depletion are obtained.

[0076] [4. Measurement of electrical characteristics] FIG. 15 is a graph showing the electrical characteristics of Example Sample 1-1 to Example Sample 1-4. FIG. 16 is a graph showing the electrical characteristics of Example Sample 2-1 to Example Sample 2-4. Each of the graphs shown in FIG. 15 and FIG. 16 shows the electrical characteristics of 26 samples having a channel width W / channel length L=4.5 μm / 3.0 μm. The vertical axis of the graph showing the electrical characteristics shows the drain current Id, and the horizontal axis shows the gate voltage Vg. The measurement conditions for the electrical characteristics of each sample are as shown in Table 3.

[0077] [Table 3]

[0078] As shown in Figures 15 and 16, in all of Example Sample 1-1 to Example Sample 1-4, which do not have a protective insulating layer containing silicon nitride, and Example Sample 2-1 to Example Sample 2-4, which have a protective insulating layer containing silicon nitride, switching performance was exhibited and electrical characteristics with suppressed depletion were obtained.

[0079] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0080] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0081] 10: semiconductor device, 100: substrate, 105: light shielding layer, 110: nitride insulating layer, 120: first oxide insulating layer, 130: second oxide insulating layer, 135: second oxide insulating film, 140: oxide semiconductor layer, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 171: opening, 173: opening, 200: source / drain electrode, 201: source electrode, 203: drain electrode

Claims

1. an oxide insulating layer; an oxide semiconductor layer on the oxide insulating layer; a gate insulating layer on the oxide semiconductor layer and in contact with the oxide semiconductor layer; a gate electrode on the gate insulating layer, The oxide semiconductor layer is a channel region overlapping the gate electrode; a source region and a drain region that do not overlap with the gate electrode, At the interface between the source and drain regions and the gate insulating layer, the impurity concentration at the surface of the source and drain regions is 1×10 １９ cm －３ That is all for the semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the impurity is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has a polycrystalline structure.

4. The sheet resistance of the source and drain regions is 1×10 ２ 2. The semiconductor device according to claim 1, wherein the resistance is equal to or less than kΩ / sq.

5. The semiconductor device according to claim 1 , wherein said oxide insulating layer contains aluminum oxide.

6. further comprising a source electrode and a drain electrode connected to the source region and the drain region, respectively; The semiconductor device according to claim 1 , wherein the source electrode and the drain electrode are in contact with a surface of the gate insulating layer that is in contact with the gate electrode.

7. 2. The semiconductor device according to claim 1, wherein said gate insulating layer includes a hydrogen trapping region that traps hydrogen.

8. 8. The semiconductor device according to claim 7, wherein said hydrogen trapping region is formed by said impurity being implanted using said gate electrode as a mask.

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