Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device which is less damaged during processing and in which the generation of interface states on the crystal surface or junction interface is suppressed, thereby obtaining good device characteristics.SOLUTION: A semiconductor device includes a semiconductor layer having a groove-shaped opening, and the semiconductor layer is made of β-Ga2O3 crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001), the longitudinal direction of the groove is parallel to the intersection of the plane orientation of the first main surface and the (100) plane, the longitudinal sidewall of the groove is a (100) facet plane, and the bottom of the groove has a single (-101) plane orientation where the groove width is greater than 0 μm and less than 2.0 μm.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] β-Ga2O3 has a wider band gap (approximately 4.6 eV) than SiC or GaN, and a breakdown electric field strength approximately 20 times that of Si, making it highly anticipated for use primarily in power semiconductors. β-Ga2O3 single crystal substrates can be manufactured by methods such as floating zone (FZ), Czochralaki (CZ), Vertical Bridgeman (VB), and Edge-Defined Film-Fed Growth (EFG), and high-quality 6-inch substrates produced by the EFG method in particular have been commercially available.

[0003] For this reason, research and development of Schottky barrier diodes (SBDs) and metal oxide semiconductor transistors (MOSFETs) using β-Ga2O3 materials is being actively conducted. In this research, the breakdown voltage of these devices is theoretically improved, and structural studies such as trenches and fins that enable normally-off operation even for β-Ga2O3, a unipolar semiconductor, are also being conducted, and many prototype results have been reported, as can be seen in Non-Patent Documents 1 and 2.

[0004] Currently, these structures are formed by processing using anisotropic dry etching (reactive ion etching). However, it has been pointed out that using anisotropic dry etching to form trenches and fins in β-Ga2O3 power devices can cause problems related to damage and defects, as described below.

[0005] (1) When dry etching is used, the sidewall surfaces of the trenches and fins that are formed are damaged during processing, so that after dry etching, it is necessary to remove the damage through a wet process using an alkali or acid. (2) The sidewalls formed by dry etching do not reflect the facets of the crystal, and therefore have a large density of dangling bonds, which leads to an increase in the crystal surface state and junction interface state density, degrading device characteristics. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] F. Otsuka et al.,Appl.Phys.Express,15,016501(2022)https: / / doi.org / 10.35848 / 1882-0786 / ac4080 [Non-Patent Document 2] W. Li et al., IEEE International Electron Devices Meeting (IEDM), (2019) https: / / doi.org / 10.1109 / IEDM19573.2019.8993526 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention aims to solve the problems associated with the above-mentioned conventional β-Ga2O3 semiconductor devices having a trench or fin structure, and to provide a semiconductor device using a β-Ga2O3 semiconductor that is suitable for microfabrication, in which processing damage is reduced and the occurrence of interface states at the crystal surface or junction interface is suppressed, resulting in good device characteristics, and in particular, to provide a power device making use of the characteristics of the β-Ga2O3 semiconductor, and a method for manufacturing the same. [Means for solving the problem]

[0008] The configuration of the present invention is shown below. (Configuration 1) A semiconductor layer having a groove, the semiconductor layer is made of β-Ga2O3 crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001); a longitudinal direction of the groove is parallel to an intersection line between a plane orientation of the first main surface and a (100) plane, the longitudinal sidewalls of the groove are (100) facets; The semiconductor device, wherein the bottom of the groove has a (-101) plane orientation in a location where the width of the groove is greater than 0 μm and is 2.0 μm or less. (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the bottom of the groove has a plane orientation of (-101) and (001) where the width of the groove is 2.0 μm or more. (Configuration 3) 3. The semiconductor device according to structure 1 or 2, wherein a longitudinal sidewall of the trench is inclined at 13.7° with respect to a plane perpendicular to the first main surface. (Configuration 4) A semiconductor layer having a groove, the semiconductor layer is made of β-Ga2O3 crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (−102); a longitudinal direction of the groove is parallel to an intersection line between a plane orientation of the first main surface and a (100) plane, At least one sidewall of the groove in the longitudinal direction is a (100) facet and is perpendicular to the first main surface. (Configuration 5) A semiconductor layer having a groove, the semiconductor layer is made of β-Ga2O3 crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001); a longitudinal direction of the groove is parallel to an intersection line between a plane orientation of the first main surface and a {310} plane; the longitudinal sidewalls of the grooves are {310} faceted; the bottom of the groove has a (001) plane orientation, A semiconductor device, wherein a longitudinal sidewall of the groove is inclined at 8.4° with respect to a plane perpendicular to the first main surface. (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein at least a portion of at least one side surface of the groove is a channel. (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, comprising a Fin-type MOSFET structure having a linear-protruding semiconductor layer formed by the plurality of trenches. (Configuration 8) an anode electrode is formed on at least a part of a three-dimensional structure having the side surface and the bottom portion, via an insulating film disposed on at least a part of the side surface and the bottom surface of the groove; The semiconductor device according to any one of structures 1 to 5, wherein the anode electrode has a Tench type MOSSBD structure in which the anode electrode is in Schottky contact with the semiconductor layer in a part of the three-dimensional structure. (Configuration 9) A power device having the semiconductor device according to any one of configurations 1 to 8. (Configuration 10) preparing a semiconductor layer made of β-Ga2O3 crystal having a first main surface with a (001) or (-102) crystal orientation; forming an etching mask on the first main surface, the etching mask having a groove-shaped opening with a longitudinal direction parallel to an intersection line between the first main surface and one or more crystal planes selected from the group consisting of (100) and {310}; selectively etching the β-Ga2O3 crystal exposed in the openings of the mask at 300° C. or higher and 1200° C. or lower under atmospheric pressure using a reducing gas. (Configuration 11) 11. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is at least one gas selected from the group consisting of hydrogen halide gas and hydrogen gas. (Configuration 12) 11. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is hydrogen chloride gas. Effect of the Invention

[0009] According to the present invention, there is provided a semiconductor device having a trench or fin structure using a β-Ga2O3 semiconductor suitable for microfabrication, which has good device characteristics due to less processing damage and suppression of the generation of interface states at the crystal surface or junction interface, in particular a power device making use of the characteristics of the β-Ga2O3 semiconductor, and a method for manufacturing the same. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view illustrating the structure of a β-Ga2O3 structure according to the present invention. [Diagram 2] FIG. 2 is a flow chart showing the manufacturing process of the β-Ga2O3 fin structure of the present invention. [Diagram 3] 1A to 1C are process diagrams showing, in cross-section, the manufacturing process of the β-Ga2O3 structure of the present invention. [Figure 4] 1A to 1C are cross-sectional views showing a process for manufacturing a trench MOS SBD according to the present invention. [Diagram 5] 1A to 1C are cross-sectional views showing a process for manufacturing a trench MOS SBD according to the present invention. [Figure 6] 1A to 1C are cross-sectional views showing a process for manufacturing a trench MOS SBD according to the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a manufacturing process of a trench MOS SBD according to the present invention. [Figure 8] FIG. 2 is a cross-sectional view illustrating the element structure of a vertical FinFET. [Figure 9] 1 is a surface SEM photograph showing an etching state when selective etching is performed on a circular window. [Figure 10] These surface SEM images show the etching state when selective etching is performed on radial linear windows, where (a) the orientation of the linear windows is in 10° increments, and (b) the orientation is along the main in-plane direction. [Figure 11] FIG. 11 is a selective etching characteristic diagram showing the in-plane anisotropy of the under-etching amount in a polar coordinate system. [Figure 12]

[0010] This is an SEM photograph after selective etching of a linear window mask pattern having different azimuth window widths and mask widths. [Figure 13]

[0010] (a) and (b) are SEM photographs showing the cross-sectional shape after selective etching for a linear window in the orientation, and (c) is a schematic cross-sectional diagram created based on the photographs. (a) shows the case where the window width is 1.2 μm and the mask width is 2.8 μm, and (b) shows the case where the window width is 5.5 μm and the mask width is 1.0 μm. Note that carbon is deposited to prevent surface deformation due to focused ion beam processing. [Figure 14] FIG. 1(a) is an SEM photograph showing the cross-sectional shape of a linear window in the [−130] orientation after selective etching, and FIG. 1(b) is a schematic cross-sectional diagram created based on the photograph. [Figure 15] This is an SEM image showing the selective etching process when a (-102) substrate is used. The pattern is a radial linear window, and the orientation is in 10° increments. [Figure 16] 13 is an SEM photograph showing selective etching of linear windows with different window widths and mask widths in the

[0010] direction when a (-102) substrate is used. [Figure 17] FIG. 1(a) is an SEM photograph showing the cross-sectional processed shape after selective etching of a linear window with a window width of 1.4 μm in the

[0010] orientation and a mask width of 2.6 μm when using a (-102) substrate, and FIG. 1(b) is a schematic cross-sectional diagram created based on the photograph. [Figure 18] 1 is a SEM photograph showing a cross-sectional processed shape after selective etching of a linear window having a window width of 0.5 μm in the

[0010] direction and a mask width of 5.7 μm when using a (−102) plane substrate. [Figure 19] FIG. 2 is an explanatory diagram showing the configuration of an HVPE apparatus used as a reduction heat treatment apparatus in the examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Embodiment 1) In the first embodiment, a trench structure 101 (see FIG. 1) having a groove (trench) used in fabricating a β-type Ga2O3 (β-Ga2O3) power semiconductor device will be described. Here, the trench structure 101 is made of a β-Ga2O3 semiconductor layer 11 having a trench formed under an opening 13 of a mask 12, and as will be described later, the side surface 11 of the trench α , 11 β , bottom 11 γ , the structure is characterized by the angle θ of the side surface with respect to the vertical plane.

[0012] The trench structure 101 of the present invention described in the first embodiment includes a semiconductor layer 11 having a groove, the semiconductor layer 11 being made of β-Ga2O3 crystal, the crystal plane orientation of the first main surface of the semiconductor layer 11 being (001), the longitudinal direction of the groove being parallel to the intersection line of the plane orientation of the first main surface and the (100) plane, and the bottom 11 of the groove being γ is a structure having a (-101) plane orientation in the area where the width of the groove exceeds 0 μm and is 2.0 μm or less.

[0013] With this structure, the side surface 11 of the semiconductor layer 11 α and 11 β The side surface 11 of the semiconductor layer 11 made of β-Ga2O3 crystals formed with the most stable (100) facet has the smallest surface energy. α and 11 β The sidewall 11 has few dangling bonds and a small surface state density. Therefore, the semiconductor device of the first embodiment using the sidewall has excellent electrical characteristics, such as excellent leakage current, mobility, reliability, and breakdown voltage. In particular, the sidewall 11 made of the (100) facet has excellent electrical characteristics. α and 11 β A semiconductor device using this as a channel layer or drift layer has excellent electrical characteristics, reliability, and quality stability.

[0014] In addition, in the trench structure 101, the bottom 11 of the trench is 2.0 μm or more in the area where the width of the trench is 2.0 μm or more. γThe first major surface is not only (-101) but also (001). γ The facet configuration can be controlled by the groove width.

[0015] The second trench structure 101 of the present invention described in the first embodiment includes a semiconductor layer 11 having a trench, the semiconductor layer 11 being made of β-Ga2O3 crystal, the crystal plane orientation of the first main surface of the semiconductor layer 11 being (-102), the longitudinal direction of the trench being parallel to the intersection line of the plane orientation of the first main surface and the (100) plane, and the sidewalls 11 in the longitudinal direction of the trench being α and 11 β is perpendicular to the first main surface, i.e., θ is 0.

[0016] This structure allows the longitudinal side walls 11 of the groove to α and 11 β The (100) facet surface is stable, and the semiconductor layer side wall 11 made of β-Ga2O3 crystals α and 11 β As a result, the crystal plane is free from problems of crystal surface state and junction interface state density, and the semiconductor device fabricated using this structure, particularly the side surface 11 consisting of the (100) facet, is very stable. α and 11 β A semiconductor device using this as a channel layer or drift layer has excellent electrical characteristics, reliability, and quality stability. The second trench structure 101 has a longitudinal sidewall 11 α and 11 β is perpendicular to the first main surface of semiconductor layer 11, that is, θ is 0, and therefore, the method has the advantage of being easy to handle, including processing.

[0017] A third trench structure 101 of the present invention described in the first embodiment includes a semiconductor layer 11 having a trench, the semiconductor layer 11 being made of β-Ga2O3 crystal, a first main surface of the semiconductor layer has a crystal plane orientation of (001), a longitudinal direction of the trench is parallel to an intersection line between the plane orientation of the first main surface and a {310} plane, a sidewall in the longitudinal direction of the trench is a {310} facet plane, a bottom of the trench has a plane orientation of (001), and the sidewall in the longitudinal direction of the trench is inclined at an angle of 8.4° with respect to a plane perpendicular to the main surface.

[0018] This structure allows the longitudinal side walls 11 of the groove to α and 11 β The {310} facets are stable, and the side walls 11 of the semiconductor layer made of β-Ga2O3 crystals α and 11 β As a result, the crystal plane is free of problems of crystal surface state and junction interface state density, and the semiconductor device fabricated using this structure, especially the side surface 11 consisting of the {310} facet, is very stable. α and 11 β A semiconductor device using this as a channel layer or drift layer has excellent electrical characteristics, reliability, and quality stability.

[0019] Next, a method for manufacturing the trench 101 will be described with reference to FIG. 2, which is a flow chart, and FIG. 3, which is a cross-sectional process diagram.

[0020] In the first step, a semiconductor layer 11a made of a β-Ga2O3 crystal semiconductor whose crystal plane is a (001) plane or a (-102) plane is prepared (step S11 in FIG. 2, FIG. 3(a)). As the semiconductor layer 11a, a β-Ga2O3 crystal substrate manufactured by the FZ, CZ, VB, or EFG method may be used, or a β-Ga2O3 epitaxial layer formed on a β-Ga2O3 crystal substrate by the HVPE (Halide Vapor Phase Epitaxy) method, the MOCVD (Metal Organic Chemical Vapor Deposition) method, or both a β-Ga2O3 crystal substrate and a β-Ga2O3 epitaxial layer may be used.

[0021] In the second step, an etching mask 12 is formed having groove-shaped openings whose longitudinal direction is aligned in a direction parallel to the intersection line between the substrate surface and one or more crystal planes selected from the group consisting of (100) and {310} (step S12). Specifically, a thin film 12a made of an etching hard mask such as SiO2 is formed on the semiconductor layer 11a (FIG. 3(b)), and a resist pattern 15 having groove-shaped openings is formed thereon (FIG. 3(c)). x , SiON, SiN X Alternatively, silicon may be used. In this example, the etching mask pattern is a groove-shaped opening, focusing on the grooves, but as shown in FIG. 3(c), if the mask is surrounded by grooves, it can be considered as a fin-shaped pattern, which is a linear protrusion pattern. Next, using the resist pattern 15 as a mask, wet etching or dry etching is performed to form openings 13 in the thin film 12a (FIG. 3(d)), and then the resist pattern 15 is stripped using oxygen plasma ashing, ozone ashing, or a resist stripping solution to form an etching mask 12 having groove-shaped openings 13 (FIG. 3(e)). Here, the thickness of the mask 12 is preferably 1 nm or more and 1000 nm or less. If the thickness is less than 1 nm, defects are likely to occur. The mask 12 is a dummy that is not essential to the semiconductor device to be manufactured, and from the viewpoint of suppressing the generation of cracks in the mask, the thickness is preferably 1000 nm or less.

[0022] In the third step, the semiconductor layer 11a made of β-Ga2O3 is dry etched using a reducing gas. This etching is preferably performed under atmospheric pressure at a temperature environment of 300°C to 1200°C, preferably 500°C to 1100°C. Atmospheric pressure makes it easier to handle and increases the etching speed, improving productivity. In addition, by setting the temperature within the above range, a high etching speed can be obtained, improving productivity. Since this is crystal face selective etching, the processed side surface 11 can be easily etched even at high temperatures with a high etching speed.α or 11 β The etched surfaces are (100) or {310} faces, resulting in stable and less defective sides. In addition, because no plasma is used, damage to the etched surface is kept to a negligible level.

[0023] The reducing gas may be one or more gases selected from the group consisting of hydrogen halide gas and hydrogen gas. Among them, hydrogen chloride gas (HCl gas) is preferably used because it is relatively easy to handle and can achieve a sufficient etching rate. Since the etching is performed under atmospheric pressure, it is preferable to add a carrier gas in addition to the reducing gas for etching. Examples of the carrier gas include nitrogen gas and noble gases such as argon gas, krypton gas, and neon gas. Among these, nitrogen gas is particularly preferred because it is easy to handle and relatively inexpensive. As will be mentioned in the examples, the time required for etching at a 2 μm level is 5 minutes, and this selective etching using a reducing gas has high productivity. By the above method, a trench structure 101 is manufactured in which a desired trench is formed in the semiconductor layer 11 made of β-Ga2O3 (step S13, FIG. 3(f)).

[0024] The openings of the mask 12 can be finely processed by using a thin film 12a such as SiO2 which is easy to process. Therefore, with this method, it is possible to easily manufacture a fine trench structure 101 using β-Ga2O3.

[0025] (Embodiment 2) In the second embodiment, a trench metal oxide semiconductor Schottky barrier diode (Trench MOS SBD) 201, which is one of the semiconductor devices suitable for power applications, will be described, along with a manufacturing method thereof.

[0026] A method for manufacturing the trench MOSSBD (201) will be described with reference to FIGS.

[0027] First, a sample is prepared in which a β-Ga2O3 epitaxial layer 53a is formed on a β-Ga2O3 substrate 51 (FIG. 4(a)). Here, the β-Ga2O3 substrate 51 has a first main surface with a plane orientation of (001) or (-102). As for impurities, Si, Sn, etc. are added at 10 18 cm -3 Over 10 20 cm -3 The β-Ga2O3 substrate 51 may be formed by any of the FZ, CZ, VB and EFG methods, but it is preferable to use the EFG method in terms of mass production cost and quality. The β-Ga2O3 epitaxial layer 53a can be formed by using HVPE, MOCVD, and low pressure CVD. The first main surface of the β-Ga2O3 epitaxial layer 53a has a surface orientation of (001) or (-102). Since unevenness formed by epitaxial growth deteriorates device performance, it is preferable to polish the β-Ga2O3 epitaxial layer 53a by CMP or the like after the layer is formed. The impurities in the β-Ga2O3 epitaxial layer 53a are Si, Sn, Ge, etc. 15 cm -3 Over 10 17 cm -3 The following doped ones can be preferably used. The thickness of the β-Ga2O3 epitaxial layer 53a is not particularly limited, but may be, for example, 1 μm or more and 50 μm or less.

[0028] In the following description of Trench MOSSBD(201), the surface orientation of the first main surface is (001), but when a β-Ga2O3 substrate 51 with a (-102) surface orientation is used, the surface orientation (001) can be replaced with (-102). In the drawings, when the surface orientation (001) is used, an inclined groove (opening) pattern is formed, but when the surface orientation (-102) is used, a vertical groove pattern is formed.

[0029] Next, a mask 52 that serves as an etching hard mask is formed on the β-Ga2O3 epitaxial layer 53a (FIG. 4(b)). As the material for the mask 52, SiO2 is preferably used. x , SiON, SiN x Alternatively, a material such as Si that has a slow etching rate with respect to the reducing etching gas of β-Ga2O3 and can be easily peeled off by dry etching using a fluorine-based gas or wet etching using a hydrofluoric acid-based aqueous solution may be used.

[0030] Thereafter, the β-Ga2O3 epitaxial layer 53a is etched using a reducing gas with the mask 52 as an etching mask to form a β-Ga2O3 semiconductor layer 53 having a groove pattern (FIG. 4(c)). As described above, the reducing gas may be one or more gases selected from the group consisting of hydrogen halide gas and hydrogen gas, and hydrogen chloride gas (HCl gas) is particularly preferred. The pressure may be atmospheric pressure, which is easy to handle, and the etching temperature may be 300°C or more and 1200°C or less. In particular, a temperature of 500°C or more and 1100°C or less is preferable because it allows a flat facet to be obtained at a high etching rate and improves the manufacturing throughput of the Trench MOSSBD (201). Thereafter, the mask 52 is removed by dry etching, wet etching, or both (FIG. 5(a)).

[0031] 5(b), an insulating film 54a is conformally formed. The insulating film 54a is preferably made of a material having few levels and defects and excellent withstand voltage, such as HfO2, Al2O3, SiO2, Ta2O5, or HfSiO x , Si3N4, and SiON. A single layer film or a laminated film selected from these films may be used. There is no particular restriction on the film formation method, and examples include CVD, sputtering, and ALD (Atomic Layer Deposition), with the ALD method being particularly preferred because it has fewer defects and is excellent in conformal deposition. The thickness of the insulating film 54a is not particularly limited, but may be in the range of 10 nm to 100 nm.

[0032] 5(c), the first insulating film 54 is processed by removing the upper surface portion of the insulating film 54a so as to expose at least the upper surface portion 55 (the surface that will later become a Schottky junction) of the β-Ga2O3 semiconductor layer 53. Examples of the processing method include a CMP (Chemical Mechanical Polishing) method, an etch-back method, and a combination of these.

[0033] Thereafter, an insulating film 56a is deposited (FIG. 6(a)), and then a resist pattern 57 having an opening exposing a desired region where a groove (trench) is to be formed is formed (FIG. 6(b)). Here, the insulating film 56a is, for example, SiO x , SiON, SOG (Spin on Glass), and polyimide. Examples of the method for forming the insulating film include a CVD method, a sputtering method, and a coating method. Thereafter, the insulating film 56a is etched (FIG. 6(c)), and then the resist pattern 57 is removed by oxygen gas ashing, ozone treatment, and a stripping solution, etc., to form a second insulating film 56 on at least a part of the field portion other than the trench region (FIG. 7(a)).

[0034] Next, after thoroughly cleaning the upper surface portion 55 of the β-Ga2O3 semiconductor layer 53 where β-Ga2O3 is exposed and the exposed surface of the first insulating film 54, a conductive film 58a which serves as an anode is formed on the surface (upper surface) on the β-Ga2O3 semiconductor layer 53 side, and a conductive film 59 which serves as a cathode is formed on the back surface side (Figure 7(b)). Here, examples of the conductive film 58a include Pt, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, and Cu. Examples of the method for forming the conductive film 58a include a vapor deposition method, a sputtering method, and an MOCVD method. The conductive film 59 may be at least one selected from the group consisting of Ti, Al, Au, Pt, and ITO, or an alloy containing at least one selected from these groups. The conductive film 59 may be formed by deposition, sputtering, MOCVD, or the like. It is preferable that the conductive film 59 is in ohmic contact with the β-Ga2O3 substrate 51. In consideration of this, it is also preferable that the doping of the β-Ga2O3 substrate 51 is controlled and the conductive film 59 is a laminated film.

[0035] Finally, the conductive film 58a is processed by lithography and etching to produce a trench MOS BD (201) having a desired anode electrode 58 and cathode electrode (conductive film) 59 (FIG. 7(c)). The anode electrode 58 may be formed by a lift-off method instead of the formation method by film formation, lithography, and etching.

[0036] In the manufactured trench MOSSBD (201), the semiconductor 53 made of β-Ga2O3 comes into Schottky contact with the anode electrode 58, and the side surface of the β-Ga2O3 semiconductor 53 in the groove reflects the facets of the crystal, resulting in a low density of dangling bonds, and therefore low crystal defects and low interface state density on the crystal surface. This high-quality β-Ga2O3 semiconductor 53, combined with the trench MOSSBD structure that brings out high breakdown voltage characteristics, makes the manufactured trench MOSSBD (201) a high-voltage diode with excellent leakage current characteristics that are particularly suitable for power devices.

[0037] (Embodiment 3) In the third embodiment, a vertical FinFET (203), which is one of the semiconductor devices suitable for power applications, will be described.

[0038] As shown in FIG. 8, the vertical FinFET (203) includes a substrate 71 made of β-Ga2O3, a β-Ga2O3 semiconductor layer (epitaxial β-Ga2O3 layer) 72, a fin (β-Ga2O3) 73 made of β-Ga2O3, an insulating film 75 that functions as a gate insulating film, a gate electrode 76, an insulating layer 77 that serves to electrically isolate the gate electrode from the source electrode, etc., and a n-type insulating film 78 that provides ohmic contact between the fin 73 and the source electrode 79 and has the function of reducing the contact resistance. + layer 78, and a drain electrode 80.

[0039] The substrate 71 is made of Si or Sn, etc., at 1000 nm in terms of electrical resistance. 18 cm -3 Over 10 20 cm -3 The β-Ga2O3 semiconductor layer 72 is preferably doped with a dopant amount of 10 15 cm -3 Over 10 17 cm -3 The following β-Ga2O3 crystal is used, and its thickness is preferably 1 μm or more and 50 μm or less. The fin 73 is formed in the same manner as in the first embodiment by etching the β-Ga2O3 semiconductor layer (the epitaxially formed β-Ga2O3 layer) with a reducing gas using an etching hard mask (not shown). 15 cm -3 Over 10 17 cm -3 It is preferable that the thickness of the fin 73 be set to the following value: The surface layer of the side surface of the fin 73 functions as a channel layer. The insulating film (gate insulating film) 75 may be made of SiO2, HfO2, HfSiO x The so-called High-k films such as Al2O3 and Si3N4 can be preferably used. The thickness of the film is preferably 10 nm or more and 100 nm or less.

[0040] Pt, Cr, Au, Ni, Ag, Ru, Rh, Pd, W, Mo, Ta, PolySi and Cu can be preferably used for the gate electrode 76, and at least one selected from the group consisting of Ti, Al, Au, Pt and ITO, or an alloy containing at least one selected from these groups, can be preferably used for the source electrode 79 and the drain electrode 80. Considering adhesion, which is important in microfabrication, for example, a laminated film in which Ti, Al and Pt are laminated in this order from the bottom can be preferably used for the source electrode 79, and a two-layer film in which Ti and Au are laminated in this order from the bottom can be preferably used for the drain electrode. The insulating layer 77 is, for example, SiO x , SiON, SOG (Spin on Glass), and polyimide. n + The layer 78 can be formed by ion implantation. The dopants are Si and Sn, and the dopant amounts are 10 18 cm -3 Over 10 20 cm -3 The thickness can be 50 nm or more and 500 nm or less. + Layer 78 is not easy to fabricate and may be omitted depending on the doping of fin 73 .

[0041] The vertical FinFET (203) is manufactured by the method described in the first embodiment, in which an epitaxial β-Ga2O3 layer is dry-etched with a reducing gas under atmospheric pressure to prepare a fin structure having fins 73, an insulating film (gate insulating film) 75 is formed by a CVD method, a sputtering method, or the like, a gate electrode 76 is formed in an area including at least a part of the side surface of the fin 73 by a deposition method, a sputtering method, a CVD method, a MOCVD method, or the like, an insulator layer 77 is formed by a sputtering method, a CVD method, or a coating method, and a source electrode 79 and a drain electrode 80 are formed thereon.

[0042] The vertical FinFET (203) is a semiconductor device having the trench structure 101 described in embodiment 1, in which a gate electrode is arranged to cover at least both side surfaces (the second and fourth sides) of a fin, which is a linear protrusion formed by a plurality of the trenches. In the vertical FinFET (203), the side of the fin 73 made of β-Ga2O3 semiconductor that serves as the channel layer reflects the facets of the crystal and has a low density of dangling bonds, so that the crystal defects and the interface state density of the crystal surface are low. The combination of the fin 73 made of such high-quality β-Ga2O3 semiconductor and the vertical FinFET structure that can bring out excellent electrical characteristics results in an FET with excellent current characteristics.

[0043] The channel layer in the vertical FinFET (203) is preferably as large as possible in order to obtain a large current. The surface area of ​​the vertical FinFET structure can be increased by forming a large number of fins per unit area by microfabrication. According to the present invention, it is possible to form fine fins 73 with high packing density and a high aspect ratio. Therefore, the vertical FinFET (203) according to the fourth embodiment has excellent electrical characteristics, which are particularly suitable for power devices. EXAMPLES

[0044] Example 1 <Sample preparation> First, a β-Ga2O3 substrate 11a was prepared by the EFG method (FIG. 3(a)), and an amorphous SiO2 (12a) was formed on the substrate 11a (FIG. 3(b)). Here, the β-Ga2O3 substrates used were (001) and (-102) surface substrates manufactured by Novel Crystal Technology. Amorphous SiO2 (12a) was formed by plasma enhanced chemical vapor deposition using tetraethoxysilane (TEOS) as a precursor, and the thickness was set to 100 nm.

[0045] After that, a resist pattern 15 having a groove-shaped opening pattern was formed (Fig. 3(c)). After that, wet etching was performed using a hydrofluoric acid buffer solution (Fig. 3(d)), and the resist pattern 15 was subsequently peeled off to form a mask 12 made of SiO2 having groove-shaped openings 13 (Fig. 3(e)). Here, the resist was peeled off using acetone and oxygen plasma ashing, and the exposed parts of the β-Ga2O3 substrate were degreased.

[0046] After that, the sample was heated to 1038°C using a halide vapor phase epitaxy (HVPE) device as a reduction heat treatment device, and HCl gas was introduced to perform selective etching for 5 minutes to fabricate a trench structure 101 as an evaluation sample (Figure 3(f)). The amount of HCl gas introduced was 5 sccm, and refined N2 gas (dew point <-110°C) was also introduced as a carrier gas at the same time as the HCl gas, and the etching process was performed under atmospheric pressure. The partial pressure of the HCl gas at this time was 63 Pa.

[0047] The HVPE equipment 2001 is an in-house manufactured equipment, and an overview of the equipment is shown in FIG. The HVPE apparatus 2001 includes a reactor 1001 that can be heated to a desired temperature by a heater 1012 . The reactor 1001 is equipped with a gallium precursor supply source 1002 (unused), an oxygen precursor supply source supply pipe 1006 (unused), an etching gas supply pipe 1008, and a substrate holder 1010, and the gas supplied to the reactor 1001 made of quartz is exhausted through an exhaust pipe 1011. An etching gas supply pipe 1008 supplies a predetermined amount of an etching gas 1009 to a sample placed on a substrate holder 1010 . A reducing gas is used as the etching gas 1009. In this embodiment, HCl gas is used, which has low reactivity with quartz and is easy to handle.

[0048] <Evaluation> The etched samples were evaluated by observation using a scanning electron microscope (SEM) SU8230 (Hitachi High-Tech).

[0049] First, the circular window pattern was examined from the surface with an SEM. The results are shown in Figure 9, and it can be seen that the mask area was not etched, but the window area was etched. The etching status in the depth direction of several microns, as well as the surface layer, can be observed from the light and shade conditions. Furthermore, observation at an accelerating voltage of 10 kV shows that there is an etched area below the mask, indicating under-etching. The shape formed by this under-etching is a flat hexagon, and it is clear that there is an in-plane anisotropy in the under-etching rate.

[0050] To evaluate the in-plane anisotropy in detail, the results of observing the radial window pattern from the top are shown in Fig. 10. Note that there are two types of window orientations, (a) at 10° intervals and (b) the main in-plane orientation, as shown in the figure. The in-plane anisotropy of the amount of under-etching on the surface obtained by observation is shown in FIG. [hkl] represents the direction rotated 90° counterclockwise from the in-plane [hkl] direction around the axis perpendicular to the plane. As can be seen from Figure 11, the amount of underetching is small in certain directions. The directions with the smallest amount of underetching are [-100] and

[0100] , and the second smallest is n

[0130] , n [-130] , n [1-30] , n [-1-30] This result corresponds to the flat hexagonal structure shown in Figure 10. Here, in both cases, a slight difference in the amount of etching is observed between the

[0100] side and the [-100] side (upper and lower sides of the pole figures).

[0051] Since an orientation in which the amount of under-etching is small is useful in the process, a groove-shaped opening (stripe window) extending in the <0010> direction was evaluated in more detail. Figure 12 shows SEM images of a trench (window width 1.2 μm, mask width 2.8 μm) and a fin (window width 5.5 μm, mask width 1.0 μm) created by selective etching with controlled mask and window widths. It shows that submicron fins can also be formed.

[0052] Furthermore, as shown in Figure 13, cross sections of these structures were cut out using a Focused Ion Beam System (FIB) and observed using an SEM. (a) in the figure shows the case where the window width is small, and it can be seen that a trench structure was formed. (b) shows the case where the mask width is small, and it can be seen that a submicron fin was formed. In both cases, the sidewall surface is composed of the (100) facet, which has the smallest surface energy density (see Figure 13(c) where the processing status is traced).

[0053] Due to the crystal structure, the (100) facet is inevitably not vertical but inclined at 13.7°. Also, if we look at the bottom of the trench, when the window width is small and the trench width is small, the bottom is made up entirely of (-102) planes, but when the window width is large and the trench width is wide, the bottom is made up not only of (-102) planes but also of the (001) plane, which is the substrate surface.

[0054] Cross-section observation was also performed for the orientation with the second smallest amount of underetching. Figure 14 shows the etched cross-section of a groove-shaped opening with a window direction of [-130]. ​​The bottom is composed only of the (001) plane, and the sidewalls have (310) facets, tilting at 8.4°. In this case, regardless of the window width, the bottom is composed entirely of the (001) plane, and the sidewalls are nearly vertical, which is thought to be useful for forming fins. However, the amount of underetching is large. For this reason, from the perspective of forming fine trench patterns, we believe that groove-shaped openings with a window direction of

[0010] , which has the least amount of underetching, are highly useful.

[0055] The (-102) substrate is considered to be a highly useful trench for device applications because the (-102) and (100) sidewalls are perpendicular to each other. Furthermore, by using a (-102) substrate, it is believed that a trench structure with vertical (100) facet sidewalls and a bottom composed only of (-102) can be obtained for all mask widths. Therefore, an evaluation was performed by preparing a β-Ga2O3 substrate 11 having a (-102) plane. It should be noted that the substrate was confirmed to be a substrate having a (-102) plane by X-ray diffraction measurement.

[0056] First, in the same way as in the evaluation using the (001) substrate mentioned above, the radial window pattern was observed from above using an SEM to evaluate the in-plane anisotropy of under-etching. The results are shown in Figure 15. As a result, it can be seen that the amount of under-etching is smallest when the windows (groove-like openings) are oriented in the

[0010] direction. This is thought to be because the side of the groove is a (100) facet.

[0057] Next, the fabricated trench (window width 1.4 μm, mask width 2.6 μm) and fin (window width 0.5 μm, mask width 5.7 μm) were observed using an SEM. The results are shown in Figure 16, and show that a structure with neatly arranged facets was formed.

[0058] Furthermore, the cross sections of these structures were cut out using a Focused Ion Beam System (FIB) and observed using a SEM. The inclination angle was 54°, and a protective film made of carbon was formed on the surface to prevent surface deformation. Figure 17(a) is an SEM photograph of a small window width, and (b) is a trace based on that photograph. It can be seen that the trench sidewalls have a trench structure with a (100) facet. The bottom of the trench is between the (-102) and (-101) faces, and cannot be determined. Figure 18 shows an SEM image of a fin with a wide window, and the fin sidewall has a (100) facet surface, just like the narrow window. The surface at the bottom of the groove is relatively rough, and is not composed of any specific facets, just like Figure 17. [Industrial Applicability]

[0059] The present invention provides a semiconductor device using a β-Ga2O3 semiconductor suitable for microfabrication, which can obtain good device characteristics by suppressing the generation of interface states, etc. Here, this semiconductor device has a trench or fin structure, has high breakdown voltage, and brings out the characteristics of the β-Ga2O3 semiconductor with a wide band gap, and is particularly suitable as a high-performance power device. Power devices are used in a variety of fields, including powertrains for EVs and hybrid vehicles, power supplies for servers, renewable energy equipment, industrial equipment, and railroad cars, and are considered essential devices for realizing a smart society. For this reason, we believe that this invention will have a large impact on society and a large influence on industry. [Explanation of symbols]

[0060] 11 β-Ga2O3 semiconductor layer ((grooved) semiconductor layer) 11a β-Ga2O3 semiconductor layer (semiconductor layer) 12 Mask (SiO2) 12a Thin film (SiO2) 13 Aperture 15 Resist pattern 51 Substrate (β-Ga2O3 substrate) 52 Mask (SiO2) 53 β-Ga2O3 semiconductor layer 53a β-Ga2O3 epitaxial layer 54 First insulating film 54a Insulating film 55 β-Ga2O3 exposed part (Schottky connection part) 56 Second insulating film 56a Insulating film 57 Resist Pattern 58 Electrode (anode electrode) 58a Conductive film 59 Conductive film (cathode electrode) 71 Substrate (β-Ga2O3) 72 β-Ga2O3 semiconductor layer (epitaxial β-Ga2O3 layer) 73 Fin (β-Ga2O3) 75 Insulating film (gate insulating film) 76 Gate electrode 77 Insulating Layer 78 n + layer 79 Source Electrode 80 Drain electrode 101 Trench structure (evaluation sample) 201 Trench SBDMOS 203 Vertical FinFET 301 Semiconductor device, fin structure, trench structure 1001 Reactor 1002 Gallium raw material supply source 1003 Gallium metal 1004 Gallium compound gas (halogen gas) 1005 Gallium source gas supply pipe 1006 Oxygen raw material supply pipe 1007 Oxygen source gas 1008 Etching gas supply pipe 1009 Etching gas (reducing gas) 1010 PCB Holder 1011 Exhaust pipe 1012 Heater 2001 HVPE equipment

Claims

1. a semiconductor layer having a groove; The semiconductor layer is β-Ga ２ O ３ It consists of crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001), a longitudinal direction of the groove is parallel to an intersection line between the plane orientation of the first main surface and the (100) plane; the longitudinal sidewalls of the groove are (100) facets; The semiconductor device, wherein the bottom of the groove has a (-101) plane orientation in a location where the width of the groove is greater than 0 μm and not greater than 2.0 μm.

2. 2. The semiconductor device according to claim 1, wherein the bottom of said groove has a plane orientation of (-101) and (001) in a location where the width of said groove is 2.0 μm or more.

3. The longitudinal sidewalls of the groove are inclined at 13.7° with respect to a plane perpendicular to the first main surface.

3. The semiconductor device according to claim 1.

4. a semiconductor layer having a groove; The semiconductor layer is β-Ga ２ O ３ It consists of crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (−102), a longitudinal direction of the groove is parallel to an intersection line between the plane orientation of the first main surface and the (100) plane, At least one sidewall of the trench in the longitudinal direction is a (100) facet and is perpendicular to the first main surface.

5. a semiconductor layer having a groove; The semiconductor layer is β-Ga ２ O ３ It consists of crystals, the crystal plane orientation of the first main surface of the semiconductor layer is (001), a longitudinal direction of the groove is parallel to an intersection line between the plane orientation of the first main surface and the {310} plane; the longitudinal sidewalls of the grooves are {310} facets; the bottom of the groove has a (001) plane orientation, A semiconductor device, wherein a sidewall of the trench in the longitudinal direction is inclined at an angle of 8.4° with respect to a plane perpendicular to the first main surface.

6. The semiconductor device according to claim 1 , 4 or 5 , wherein at least a portion of at least one side surface of said groove is a channel.

7. 6. The semiconductor device according to claim 1, further comprising a Fin-type MOSFET structure having a linear protruding semiconductor layer formed by a plurality of said grooves.

8. an anode electrode is formed on at least a part of a three-dimensional structure having the side surface and the bottom portion of the groove, via an insulating film arranged on at least a part of the side surface of the groove and on a bottom surface of the groove; 6. The semiconductor device according to claim 1, wherein said anode electrode has a Tench-type MOSSBD structure in which said anode electrode is in Schottky contact with said semiconductor layer in a part of said three-dimensional structure.

9. A power device comprising the semiconductor device according to claim 1 , 4 or 5 .

10. β-Ga having a first main surface with a plane orientation of (001) or (−102) ２ O ３ providing a crystalline semiconductor layer; forming an etching mask on the first main surface, the etching mask having a groove-shaped opening with a longitudinal direction parallel to an intersection line between the first main surface and one or more crystal planes selected from the group consisting of (100) and {310}; The β-Ga exposed through the opening of the mask is then etched using a reducing gas at atmospheric pressure at a temperature of 300° C. or higher and 1200° C. or lower. ２ O ３ A method for manufacturing a semiconductor device, comprising selectively etching a crystal.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is at least one gas selected from the group consisting of hydrogen halide gas and hydrogen gas.

12. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the reducing gas is hydrogen chloride gas.

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