Manufacturing method of semiconductor device
Patent Information
- Application Number
- JP2023001709
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-01-10
- Publication Date
- 2025-01-08
- Estimated Expiration
- 2043-01-10
AI Technical Summary
The diffusion of implanted impurities in SiC substrates leads to imprecise formation of impurity regions, making it difficult to achieve high precision in forming p-type or n-type regions during ion implantation.
A method involving two conductivity type impurity implantation steps, where the concentration distributions are controlled to ensure the second peak value overlaps with the decreasing region of the first peak value, allowing for precise formation of the first conductivity type region.
This method enables high-precision formation of impurity regions, reducing the area of the first conductivity type region and enhancing the control over impurity distribution, thereby improving the accuracy of semiconductor device manufacturing.
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Abstract
Description
[Technical field]
[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.
[0002] Patent Document 1 discloses a technique for ion-implanting impurities into a SiC substrate (that is, a semiconductor substrate made of silicon carbide). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Patent Publication No. 2021-015978 Summary of the Invention [Problem to be solved by the invention]
[0004] When ions are implanted into a SiC substrate, the implanted impurities are diffused over a wide area. This makes it difficult to form an impurity implanted region with high accuracy. Since thermal diffusion of impurities is difficult to occur during activation annealing in a SiC substrate, forming an impurity implanted region with high accuracy during ion implantation leads to improved accuracy in forming a p-type or n-type region. This specification proposes a technology for forming an impurity implanted region with high accuracy during ion implantation into a SiC substrate. [Means for solving the problem]
[0005] The method for manufacturing a semiconductor device disclosed in this specification includes a first step of implanting a first conductivity type impurity into a SiC substrate, and a second step of implanting a second conductivity type impurity into the SiC substrate, the first step and the second step being performed to satisfy the following conditions: in the thickness direction of the SiC substrate, a concentration distribution of the first conductivity type impurity implanted in the first step has a first peak value that is a maximum value and a decreasing region in which the first conductivity type impurity concentration continuously decreases with increasing distance from the position of the first peak value, in the thickness direction of the SiC substrate, a concentration distribution of the second conductivity type impurity implanted in the second step has a second peak value that is a maximum value, the position of the second peak value overlaps with a region in the decreasing region having a first conductivity type impurity concentration that is 10% or more of the first peak value, the position of the first peak value is a first conductivity type region, and at least a part of the specific region is a second conductivity type region.
[0006] One of the first conductivity type region and the second conductivity type region is p-type and the other is n-type. That is, when the first conductivity type region is p-type, the second conductivity type region is n-type, and when the first conductivity type region is n-type, the second conductivity type region is p-type.
[0007] Moreover, the first peak value, the second peak value, and the decreasing region are identified based on a distribution graph from which noise occurring during measurement of the impurity concentration has been removed.
[0008] Moreover, either the first step or the second step may be carried out first.
[0009] In this manufacturing method, the concentration distribution of the first-conductivity-type impurity implanted in the first step has a first peak value, which is a maximum value, and a decrease region in which the first-conductivity-type impurity concentration continuously decreases with increasing distance from the position of the first peak value. The decrease region is a region in which the impurity is implanted due to variations in the implantation depth during ion implantation. In addition, in this manufacturing method, the position of the second peak value of the concentration distribution of the second-conductivity-type impurity implanted in the second step overlaps with a specific region in the decrease region that has a first-conductivity-type impurity concentration of 10% or more of the first peak value. At least a part of the specific region becomes the second-conductivity-type region. Therefore, the first-conductivity-type region can be formed by limiting it to the vicinity of the position of the first peak value. In this way, according to this manufacturing method, the first-conductivity-type region can be formed with high accuracy. [Brief description of the drawings]
[0010] [Figure 1] FIG. 2 is an explanatory diagram of the first step of the first embodiment. [Diagram 2] FIG. 2(a) is a cross-sectional view showing the concentration distribution of the p-type impurity implanted in the first step of Example 1, and FIG. 2(b) is a graph showing the concentration distribution of the p-type impurity at the position of line AA. [Diagram 3] FIG. 2 is an explanatory diagram of the first process of the second step in Example 1. [Figure 4] FIG. 4(a) is a diagram showing the effective p-type impurity concentration distribution in a cross section after the second step of Example 1 is carried out, and FIG. 4(b) is a graph showing the impurity concentration distribution at the position of line AA. [Diagram 5] FIG. 2 is an explanatory diagram of the second process of the second step in Example 1. [Figure 6] 1 is a cross-sectional view of a MOSFET manufactured by the manufacturing method of the first embodiment. [Figure 7] FIG. 1 is an explanatory diagram of the first step of Example 2. [Figure 8] FIG. 8(a) is a cross-sectional view showing the concentration distribution of the p-type impurity implanted in the first step of Example 2, and FIG. 8(b) is a graph showing the concentration distribution of the p-type impurity at the position of line AA. [Figure 9] FIG. 13 is an explanatory diagram of the second step of the second embodiment. [Figure 10] FIG. 10(a) is a diagram showing the effective p-type impurity concentration distribution in a cross section after the second step of Example 2 is carried out, and FIG. 10(b) is a graph showing the impurity concentration distribution at the position of line AA. [Figure 11] 1 is a cross-sectional view of a MOSFET manufactured by the manufacturing method of the first embodiment. [Figure 12] FIG. 12 is an explanatory diagram of the manufacturing process of the MOSFET in FIG. [Figure 13] FIG. 12 is an explanatory diagram of the manufacturing process of the MOSFET in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0011] In the exemplary manufacturing method disclosed herein, the position of the second peak value may overlap with the specific region that is shallower than the position of the first peak value.
[0012] In one example of the manufacturing method disclosed in the present specification, the position of the second peak value may overlap with the specific region that is located deeper than the position of the first peak value.
[0013] Note that the above "shallow" means that the implantation distance of the impurity in the first step is short, and the above "deep" means that the implantation distance of the impurity in the first step is long.
[0014] The manufacturing method of the example disclosed in the present specification may further include a step of forming a mask having an opening on a surface of the SiC substrate. In this case, in the first step, a first conductive type impurity may be implanted into the SiC substrate through the mask, and in the second step, a second conductive type impurity may be implanted into the SiC substrate through the mask.
[0015] When implanting through a mask, the first conductivity type impurity is likely to diffuse laterally (i.e., in a direction parallel to the surface of the semiconductor substrate) in the first step. By carrying out the second step using the same mask as in the first step, the second conductivity type impurity can be diffused laterally in the second step. This makes it possible to limit the area in which the first conductivity type region is formed in the lateral direction as well.
[0016] In one example of the manufacturing method disclosed herein, the opening may have a width of 3.5 μm or less.
[0017] In one example of the manufacturing method disclosed in the present specification, a semiconductor device manufactured by the manufacturing method may have an element region and a p-type guard ring extending to surround the periphery of the element region, and in this case, the first conductivity type region formed at the position of the first peak value may be the guard ring.
[0018] In one example of the manufacturing method disclosed in the present specification, a semiconductor device manufactured by the manufacturing method may have a superjunction structure in which a plurality of p-type layers and a plurality of n-type layers are alternately arranged in a drift region in a lateral direction, and the first conductivity type region formed at the position of the first peak value may be the p-type layer of the superjunction structure. EXAMPLES
[0019] The method for manufacturing the semiconductor device of the first embodiment includes a mask forming step, a first step of implanting a p-type impurity into the SiC substrate, and a second step of implanting an n-type impurity into the SiC substrate.
[0020] In the mask formation step, as shown in FIG. 1, a mask 70 is formed on the upper surface 12a of the SiC substrate 12. The mask 70 has an opening 72. The SiC substrate 12 is made of n-type SiC. The n-type impurity concentration of the SiC substrate 12 is, for example, 1×10 15 cm -3 That's about it.
[0021] After the mask formation process, the first process is performed. In the first process, as shown in FIG. 1, p-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. Therefore, the p-type impurities are implanted into the SiC substrate 12 from the upper surface 12a in the opening 72. Here, the p-type impurities are implanted along the thickness direction of the SiC substrate 12. Here, the p-type impurities are implanted multiple times while changing the acceleration energy. As a result, the p-type impurities are implanted at approximately the same concentration into each of the depths D1, D2, and D3.
[0022] FIG. 2 shows the concentration distribution of p-type impurities after the first process is performed. FIG. 2(a) shows the same cross section as FIG. 1, and the concentration of p-type impurities is represented by the density of the hatching. FIG. 2(b) shows the concentration distribution of p-type impurities at the position of line AA in FIG. 2(a). Note that graphs G1 to G7 in FIG. 2(b) respectively show the results of performing the first process by changing the width W of the opening 72. Also, graph G8 in FIG. 2(b) shows the result of performing the first process without the mask 70 for reference.
[0023] As described above, in the first step, p-type impurities are implanted to a plurality of depths D1, D2, and D3. Therefore, within the depth range including the depths D1, D2, and D3, the p-type impurity concentration is a high value (for example, 8×10 17 cm -3) and is distributed almost uniformly. In the following, the region where the p-type impurity concentration is distributed almost uniformly at a high value is referred to as the main region 50. A peak value Pmax of the p-type impurity is formed in the main region 50. Above and below the main region 50, there are decrease regions 52 and 54 in which the p-type impurity concentration continuously decreases with increasing distance from the main region 50. Note that FIG. 2(b) shows the decrease region 52 of the graph G7 as an example. The decrease regions 52 and 54 are regions formed due to variations in the injection depth of the p-type impurity in the first step. The decrease region 52 is formed on the upper side of the main region 50 (i.e., on the shallower side in the injection direction of the p-type impurity). In the decrease region 52, the p-type impurity concentration continuously decreases toward the upper side. The decrease region 54 is formed on the lower side of the main region 50 (i.e., on the deeper side in the injection direction of the p-type impurity). In the decrease region 54, the p-type impurity concentration continuously decreases toward the lower side.
[0024] Moreover, an increase region 56 exists above the decrease region 52. In the increase region 56, the p-type impurity concentration is higher than that at the upper end of the decrease region 52. The increase region 56 is a region into which the p-type impurity scattered and reflected by the mask 70 is injected. Therefore, as shown in the graph G8 of FIG. 2(b), if the mask 70 does not exist, the increase region 56 is not formed. Moreover, as shown in the graphs G1 to G7 of FIG. 2(b), the smaller the width W of the opening 72, the higher the p-type impurity concentration in the increase region 56 tends to be. This is believed to be because the smaller the width W of the opening 72, the more p-type impurity is scattered and reflected by the mask 70.
[0025] 2(a), a peripheral region 58 in which p-type impurities are distributed at a low concentration is formed at a position adjacent to the main region 50 in the lateral direction (i.e., the direction perpendicular to the ion implantation direction). The peripheral region 58 is a region in which p-type impurities scattered and reflected by the mask 70 are implanted.
[0026] As described above, in the first step, the p-type impurity is implanted not only into the main region 50, which is the implantation target of the p-type impurity, but also into the surrounding decrease region 52, decrease region 54, increase region 56, and peripheral region 58.
[0027] After the first step, the second step is performed. In the second step, n-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. Therefore, the n-type impurities are implanted into the SiC substrate 12 from the upper surface 12a in the opening 72. Here, the n-type impurities are implanted along the thickness direction of the SiC substrate 12. The implantation depth and implantation concentration of the n-type impurities in the second step are set corresponding to the p-type impurity concentration distribution formed in the first step. In the following, the second step will be described using as an example a case where p-type impurities are implanted in the first step as shown in graph G7 of FIG. 2(b). The second step includes a first process of implanting n-type impurities into the upper side of the main region 50 and a second process of implanting n-type impurities into the lower side of the main region 50.
[0028] In the first process, as shown in FIG. 3, n-type impurities are implanted multiple times while changing the acceleration energy above the main region 50. As a result, n-type impurities are implanted to multiple depths in the region above the main region 50. FIG. 4(b) shows a graph G10 of the concentration distribution of n-type impurities implanted in the SiC substrate 12 in the first process, superimposed on a graph G7. Moreover, the region 52a in FIG. 4(b) is a region in the decrease region 52 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the first process, n-type impurities are implanted at least once to a depth in the region 52a. In the example shown in FIG. 4(b), n-type impurities are implanted into the decrease region 52 at depths D11, D12, and D13 including the depths D12 and D13 in the region 52a. Here, in the depths D11 to D13, the n-type impurities are implanted at a higher concentration as the depth approaches the main region 50. That is, the n-type impurity is injected at the highest concentration at the depth D13 closest to the main region 50, and at the lowest concentration at the depth D11 farthest from the main region 50. Therefore, in the decrease region 52, a peak value Nmax1 of the n-type impurity is formed at the depth D13 in the region 52a. Here, the n-type impurity is also injected at a plurality of depths in the increase region 56. Here, the n-type impurity is injected so that the n-type impurity concentration is higher than the p-type impurity concentration in the range above the depth D13.
[0029] In the second process, as shown in FIG. 5, n-type impurities are injected multiple times while changing the acceleration energy below the main region 50. As a result, n-type impurities are injected to multiple depths in the region below the main region 50. FIG. 4(b) shows a graph G11 of the concentration distribution of n-type impurities injected into the SiC substrate 12 in the second process, superimposed on a graph G7. Moreover, the region 54a in FIG. 4(b) is a region in the decrease region 54 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the second process, n-type impurities are injected at least once to a depth in the region 54a. In the example shown in FIG. 4(b), n-type impurities are injected into the decrease region 54 at depths D21 and D22 including the depth D21 in the region 54a. Here, in the depths D21 and D22, the closer the depth is to the main region 50, the higher the concentration of n-type impurities is injected. That is, n-type impurities are injected at a higher concentration at the depth D21 than at the depth D22. Therefore, in the reduced region 54, a peak value Nmax2 of the n-type impurity is formed at the depth D21. Here, the n-type impurity is implanted so that the n-type impurity concentration is higher than the p-type impurity concentration in the range below the depth D21. Furthermore, when the n-type impurity is implanted in the second process, the n-type impurity is scattered and reflected by the mask 70. The n-type impurity scattered and reflected by the mask 70 is implanted into the peripheral region 58.
[0030] As described above, in the second step, n-type impurities are implanted into the decrease region 52, the decrease region 54, the increase region 56, and the peripheral region 58. The graph G13 in FIG. 4(b) shows an effective p-type impurity concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. That is, the graph G13 shows a distribution of values obtained by subtracting the values of the graphs G10 and G11 from the values of the graph G7. As shown in FIG. 4(b), the effective p-type impurity concentrations in the decrease region 52, the decrease region 54, and the increase region 56 are lowered by implanting the n-type impurity into these regions. FIG. 4(a) shows a distribution of the effective p-type impurity concentration in the same cross section as FIG. 5. As shown in FIG. 4(a), the effective p-type impurity concentration in the peripheral region 58 is lowered by implanting the n-type impurity into the peripheral region 58. In the decrease region 52, the decrease region 54, the increase region 56, and the peripheral region 58, the n-type impurity concentration is higher than the p-type impurity concentration, except in the vicinity of the main region 50. Therefore, the effective p-type impurity concentration is a positive value in the main region 50 and its vicinity, and the effective p-type impurity concentration is a negative value in the other regions.
[0031] Next, the SiC substrate 12 is annealed. This activates the p-type impurities and n-type impurities implanted into the SiC substrate 12. The region with a positive effective p-type impurity concentration becomes the p-type region 20, and the region with a negative effective p-type impurity concentration (i.e., the region with a higher n-type impurity concentration than the p-type impurity concentration) becomes the n-type region 22. That is, the p-type region 20 is formed in the hatched region in FIG. 4(a), and the region not hatched in FIG. 4(a) remains as the n-type region 22. As described above, the effective p-type impurity concentration is a positive value in the main region 50 and its vicinity, so that the p-type region is formed in the main region 50 and its vicinity. At least a part of the regions 52a and 54a adjacent to the main region 50 becomes an n-type region, so that the range in which the p-type region is formed can be narrowed. In this way, according to this manufacturing method, the p-type region 20 can be formed in a region narrower than the region implanted with the p-type impurity in the first step.
[0032] FIG. 6 shows a MOSFET (metal-oxide-semiconductor field effect transistor) as a specific example of a semiconductor device manufactured by the manufacturing method of the first embodiment. The SiC substrate 12 has an element region 60 and an outer periphery region 61. In the element region 60, a MOSFET structure is formed having an n-type source region 62, a p-type body region 63, a trench gate electrode 64, a bottom p-type region 65, an n-type drift region 66, and an n-type drain region 67. The trench gate electrode 64 is a gate electrode disposed in a trench and is insulated from the SiC substrate 12 by a gate insulating film. The bottom p-type region 65 is in contact with the bottom surface of the trench. The outer periphery region 61 is provided around the element region 60. A drift region 66 is distributed in the outer periphery region 61. A plurality of p-type guard rings 68 are provided in the outer periphery region 61. Each guard ring 68 is provided inside the drift region 66. When the SiC substrate 12 is viewed from above, each guard ring 68 has a rectangular ring shape that goes around the periphery of the element region 60. Each guard ring 68 is disposed at the same depth as the bottom p-type region 65. Each guard ring 68 is formed after the element region 60 is formed. In the step of forming each guard ring 68, a mask 70 is formed on the upper surface 12a of the SiC substrate 12, and the first step (i.e., implantation of p-type impurities) and the second step (i.e., implantation of n-type impurities) can be performed through the mask 70. According to this method, a small guard ring 68 can be formed, and the MOSFET can be miniaturized.
[0033] In the above-described first embodiment, in the second step, n-type impurities are implanted into both the upper and lower sides of the main region 50. However, in the second step, n-type impurities may be implanted into only one of the upper and lower sides of the main region 50. When n-type impurities are implanted into the upper side of the main region 50 through the mask 70, the decrease region 52 and the increase region 56 can be made into n-type. When n-type impurities are implanted into the lower side of the main region 50 through the mask 70, the decrease region 54 and the peripheral region 58 can be made into n-type.
[0034] In the above-mentioned embodiment 1, the impurity injection in the first and second steps was performed through the mask 70. However, the impurity injection in the first and second steps may be performed without the mask. Even in such a configuration, a small p-type region can be formed by injecting n-type impurities into the decrease region of the graph G8 in FIG. 2(b). However, when the p-type impurity is injected through a mask, the problem of the p-type impurity being injected into the increase region 56 and the peripheral region 58 occurs significantly. In particular, as shown in FIG. 2(b), when the width of the opening of the mask is 3.5 μm or less, the problem of the p-type impurity being injected into the increase region 56 and the peripheral region 58 occurs more significantly. Therefore, when the width of the opening of the mask is 3.5 μm or less, a higher effect of suppressing the expansion of the p-type region can be obtained by using the technology disclosed in this specification. EXAMPLES
[0035] In the second embodiment, the mask forming step is carried out in the same manner as in the first embodiment, after which the first and second steps are carried out.
[0036] In the first step of the second embodiment, as shown in FIG. 7, p-type impurities are ion-implanted into the SiC substrate 12 through a mask 70. Here, the p-type impurities are implanted multiple times while changing the acceleration energy. Unlike the first embodiment, the p-type impurities are implanted at equal intervals in the depth range from the upper surface 12a of the SiC substrate 12 to a depth D100. Here, the p-type impurities are implanted at approximately the same concentration for each depth.
[0037] FIG. 8 shows the concentration distribution of p-type impurities after the first step is performed. More specifically, FIG. 8(a) shows the same cross section as FIG. 7, and the concentration of p-type impurities is represented by the density of hatching. FIG. 8(b) shows the concentration distribution of p-type impurities at the position of line AA in FIG. 8(a) by graph G100. Within the depth range from upper surface 12a to depth D100, the p-type impurity concentration is high (for example, 8×10 17 cm -3) is distributed almost uniformly. Hereinafter, the region in which the p-type impurity concentration is distributed almost uniformly will be referred to as main region 150. A peak value Pmax of the p-type impurity is formed within main region 150. Below main region 150, there exists decrease region 154 in which the p-type impurity concentration continuously decreases with increasing distance from main region 150. Decrease region 154 is a region formed due to variations in the implantation depth of the p-type impurity in the first process.
[0038] 8(a), a peripheral region 158 in which p-type impurities are distributed at a low concentration is formed at a position adjacent to the main region 150 in the lateral direction (i.e., the direction perpendicular to the ion implantation direction). The peripheral region 158 is a region in which the p-type impurities scattered and reflected by the mask 70 are implanted.
[0039] After the first process, the second process is performed. In the second process, n-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. The implantation depth and implantation concentration of the n-type impurities in the second process are set corresponding to the p-type impurity concentration distribution formed in the first process. In the second process, as shown in FIG. 9, n-type impurities are implanted multiple times under the main region 150 while changing the acceleration energy. As a result, n-type impurities are implanted to multiple depths in the region under the main region 150. FIG. 10(b) shows a graph G101 of the concentration distribution of n-type impurities implanted into the SiC substrate 12 in the second process superimposed on the graph G100. Moreover, the region 154a in FIG. 10(b) is a region in the decrease region 154 that has a p-type impurity concentration higher than 10% of the peak value Pmax. In the second process, n-type impurities are implanted at least once to a depth in the region 154a. In the example shown in FIG. 10(b), n-type impurities are implanted into the reduced region 154 at depths D121 and D122 including the depth D121 in the region 154a. Here, at the depths D121 and D122, the n-type impurities are implanted at a higher concentration as the depth approaches the main region 150. That is, the n-type impurities are implanted at a higher concentration at the depth D121 than at the depth D122. Therefore, in the reduced region 154, a peak value Nmax of the n-type impurities is formed at the depth D121. Here, the n-type impurities are implanted so that the n-type impurity concentration is higher than the p-type impurity concentration in the range below the depth D121. Also, when the n-type impurities are implanted in the second step, the n-type impurities are scattered and reflected by the mask 70. The n-type impurities scattered and reflected by the mask 70 are implanted into the peripheral region 158.
[0040] As described above, in the second step, n-type impurities are implanted into the reduced region 154 and the peripheral region 158. A graph G102 in FIG. 10(b) shows an effective p-type impurity concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. As shown in FIG. 10(b), the effective p-type impurity concentration in the reduced region 154 is reduced by implanting n-type impurities into the reduced region 154. FIG. 10(a) shows the distribution of the effective p-type impurity concentration in the same cross section as FIG. 9. As shown in FIG. 10(a), the effective p-type impurity concentration in the peripheral region 158 is reduced by implanting n-type impurities into the peripheral region 158. In the reduced region 154 and the peripheral region 158, the n-type impurity concentration is higher than the p-type impurity concentration except for the vicinity of the main region 150. Therefore, the effective p-type impurity concentration is a positive value in the main region 50 and its vicinity, and the effective p-type impurity concentration is a negative value in other regions.
[0041] Next, the SiC substrate 12 is annealed. This activates the p-type impurities and n-type impurities implanted into the SiC substrate 12. The region with a positive effective p-type impurity concentration becomes the p-type region 120, and the region with a negative effective p-type impurity concentration (i.e., the region where the n-type impurity concentration is higher than the p-type impurity concentration) becomes the n-type region 122. That is, the p-type region 120 is formed in the hatched region in FIG. 10(a), and the region not hatched in FIG. 10(a) remains as the n-type region 122. As described above, the effective p-type impurity concentration is a positive value in the main region 150 and its vicinity, so that the p-type region is formed in the main region 150 and its vicinity. In particular, since at least a part of the region 154a adjacent to the main region 150 becomes an n-type region, the range in which the p-type region is formed can be narrowed. In this way, according to this manufacturing method, the p-type region 120 can be formed in a region narrower than the region where the p-type impurity is implanted in the first step.
[0042] FIG. 11 shows a MOSFET as a specific example of a semiconductor device manufactured by the manufacturing method of the second embodiment. A MOSFET structure having an n-type source region 62, a p-type body region 63, a trench-type gate electrode 64, a drift region 66, and an n-type drain region 67 is formed in a SiC substrate 12. The drift region 66 has a superjunction structure in which a plurality of p-type regions 66a and a plurality of n-type regions 66b are arranged alternately in the lateral direction. Each of the p-type region 66a and the n-type region 66b has a long shape in the thickness direction of the SiC substrate 12. In the manufacturing method of this MOSFET, first, as shown in FIG. 12, the drift region 66 is formed on the drain region 67 by epitaxial growth. At this stage, the entire drift region 66 is composed of a low-concentration n-type region. Next, as shown in FIG. 13, a mask 70 is formed on the upper surface of the drift region 66, and impurities are injected through the mask 70 to form a plurality of p-type regions 66a. At this time, by applying the technology of the second embodiment, the formation range of the p-type region 66a can be accurately controlled. The n-type regions remaining between the p-type regions 66a become n-type regions 66b. Then, an epitaxial layer is formed on the drift region 66, and the source region 31, the body region 32, the trench gate electrode 36, and the like are formed in the formed epitaxial layer, thereby completing the MOSFET shown in FIG.
[0043] In the above-mentioned second embodiment, the first and second impurity injection processes are performed through the mask 70. However, the first and second impurity injection processes may be performed without the mask. Even in such a configuration, a small p-type region can be formed by injecting n-type impurities into the reduced region 154. However, when the p-type impurities are injected through a mask, a problem occurs in that the p-type impurities are injected into the peripheral region 158. In particular, when the width of the opening of the mask is 3.5 μm or less, the problem of the p-type impurities being injected into the peripheral region 158 becomes more prominent. Therefore, when the width of the opening of the mask is 3.5 μm or less, a higher effect of suppressing the expansion of the p-type region can be obtained by using the technology disclosed in this specification.
[0044] In the above-mentioned Examples 1 and 2, p-type impurities were ion-implanted in the first step, and n-type impurities were ion-implanted in the second step. However, n-type impurities may be ion-implanted in the first step, and p-type impurities may be ion-implanted in the second step.
[0045] In addition, in the above-mentioned Examples 1 and 2, the second step is carried out after the first step, but the first step may be carried out after the second step.
[0046] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of the objectives itself has technical utility. [Explanation of symbols]
[0047] 12: SiC substrate, 50: main region, 52, 54: reduction region, 70: mask, 72: opening
Claims
1. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); A second step of implanting a second conductivity type impurity into the SiC substrate; having The first and second steps satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductive type impurity implanted in the first step has a first peak value (Pmax) which is a maximum value, and a decreasing region (52, 54) in which the first conductive type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, a concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has a second peak value (Nmax1, Nmax2) that is a maximum value. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration of 10% or more of the first peak value. The position of the first peak value is in a first conductivity type region. At least a part of the specific region is a second conductivity type region. This is carried out to satisfy the condition that The position of the second peak value overlaps with the specific region (54a) that is located deeper than the position of the first peak value. Manufacturing method.
2. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); A second step of implanting a second conductivity type impurity into the SiC substrate; having The first and second steps satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductive type impurity implanted in the first step has a first peak value (Pmax) which is a maximum value, and a decreasing region (52, 54) in which the first conductive type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, a concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has a second peak value (Nmax1, Nmax2) that is a maximum value. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration of 10% or more of the first peak value. The position of the first peak value is in a first conductivity type region. At least a part of the specific region is a second conductivity type region. This is carried out to satisfy the condition that A semiconductor device manufactured by the manufacturing method has an element region (60) and a p-type guard ring (68) extending so as to surround the periphery of the element region, the first conductivity type region formed at the position of the first peak value is the guard ring; Manufacturing method.
3. A method for manufacturing a semiconductor device, comprising: A first step of implanting a first conductivity type impurity into a SiC substrate (12); A second step of implanting a second conductivity type impurity into the SiC substrate; having The first and second steps satisfy the following conditions: In the thickness direction of the SiC substrate, the concentration distribution (G7) of the first conductive type impurity implanted in the first step has a first peak value (Pmax) which is a maximum value, and a decreasing region (52, 54) in which the first conductive type impurity concentration continuously decreases with increasing distance from the position of the first peak value. In the thickness direction of the SiC substrate, a concentration distribution (G10, G11) of the second conductivity type impurity implanted in the second step has a second peak value (Nmax1, Nmax2) that is a maximum value. The position of the second peak value overlaps with a specific region (52a, 54a) in the decrease region that has a first conductivity type impurity concentration of 10% or more of the first peak value. The position of the first peak value is in a first conductivity type region. At least a part of the specific region is a second conductivity type region. This is carried out to satisfy the condition that The semiconductor device manufactured by the manufacturing method has a superjunction structure in which a plurality of p-type layers (66a) and a plurality of n-type layers (66b) are alternately arranged in a lateral direction in a drift region (66), the first conductivity type region formed at the position of the first peak value is the p-type layer of the superjunction structure; Manufacturing method.