Semiconductor device

Abstract

To provide a semiconductor device which has an active part.SOLUTION: A semiconductor device includes: a first conductive type drift region which is provided in a semiconductor substrate; a second conductive type base region which is provided above the drift region; a gate pad which is provided above the semiconductor substrate; an emitter electrode which is provided above the semiconductor substrate; a gate trench part 40 which is provided on a front surface of the semiconductor substrate in an active part 120; and a gate wiring part 50 which connects the gate pad to the gate trench part. The gate wiring part comprises a first gate trench wiring part which extends in a predefined direction and a second gate trench wiring part which extends in a direction different from the first gate trench wiring part and intersects the first gate trench wiring part at an intersection part. The emitter electrode is provided above the intersection part 510.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes a "semiconductor device capable of improving electrical performance." [Prior art document] [Patent documents] [Patent Document 1] JP 2020-136315 A [Patent Document 2] JP 2019-091892 A [Patent Document 3] JP 2017-103400 A Summary of the Invention

[0003] An aspect of the present invention provides a semiconductor device having an active portion, the semiconductor device comprising: a first conductivity type drift region provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a gate pad provided above the semiconductor substrate; an emitter electrode provided above the semiconductor substrate; a gate trench portion provided on a front surface of the semiconductor substrate in the active portion; and a gate wiring portion for connecting the gate pad and the gate trench portion, the gate wiring portion having a first gate trench wiring portion extending in a predetermined direction and a second gate trench wiring portion extending in a direction different from the first gate trench wiring portion and intersecting with the first gate trench wiring portion at an intersection portion, and the emitter electrode is provided above the intersection portion.

[0004] The semiconductor device may include a trench bottom region of a second conductivity type provided in contact with a bottom of the gate trench portion.

[0005] In any of the above semiconductor devices, a doping concentration of the trench bottom region may be lower than a doping concentration of the base region.

[0006] In any of the above semiconductor devices, the trench bottom region may be provided in contact with a bottom portion of the intersection portion.

[0007] Any of the above semiconductor devices may further include a well region of a second conductivity type provided above the drift region, and the trench bottom region provided in contact with a bottom of the intersection may be connected to the well region.

[0008] Any of the above semiconductor devices may further include a well region of a second conductivity type provided above the drift region, and the trench bottom region may be connected to the well region.

[0009] In any of the above semiconductor devices, the trench bottom region may extend from one end of the second gate trench wiring portion provided in the outer periphery of the semiconductor device to the other end of the second gate trench wiring portion provided in the outer periphery.

[0010] Any of the above semiconductor devices may further include a well region of a second conductivity type provided above the drift region, and the trench bottom region may include a first trench bottom portion and a second trench bottom portion provided apart from the first trench bottom portion and connected to the well region.

[0011] Any of the above semiconductor devices may further include a well region of a second conductivity type provided above the drift region. The intersection may be provided inside the well region in a cross section parallel to a depth direction of the semiconductor substrate, and a lower end of the intersection may be shallower than a lower end of the well region.

[0012] In any of the above semiconductor devices, the well region may be provided extending from one end of the second gate trench wiring portion provided in the outer periphery of the semiconductor device to the other end of the second gate trench wiring portion provided in the outer periphery.

[0013] In any of the above semiconductor devices, the active portion may have a first active region and a second active region, and the emitter electrode may be provided across the second gate trench wiring portion from the first active region to the second active region in a top view.

[0014] In any of the above semiconductor devices, the active portion may have a first active region and a second active region, and the first gate trench wiring portion may extend from the first active region to the second active region and connect a gate trench portion of the first active region to a gate trench portion of the second active region.

[0015] In any of the above semiconductor devices, the second gate trench wiring portion may include a plurality of second gate trench wiring portions, each of which may have the intersection portion with the first gate trench wiring portion.

[0016] In any of the semiconductor devices described above, a width of the second gate trench wiring portion may be wider than a width of the first gate trench wiring portion.

[0017] In any of the semiconductor devices described above, the gate wiring portion may be provided in an outer periphery of the semiconductor device, connected to an end of the second gate trench wiring portion in the outer periphery, and may have a gate metal layer made of a metal.

[0018] In any of the semiconductor devices described above, the gate wiring portion may be provided on an outer periphery of the semiconductor device, connected to an end of the second gate trench wiring portion at the outer periphery, and may have a gate runner made of polysilicon.

[0019] In any of the semiconductor devices described above, the gate wiring portion may include a third gate trench wiring portion provided on an outer periphery of the semiconductor device and connected to an end of the second gate trench wiring portion at the outer periphery.

[0020] Any of the above semiconductor devices may further include a plating film provided on the emitter electrode above the intersection.

[0021] Any of the above semiconductor devices may further include an emitter region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region, and the emitter electrode may be provided above the emitter region.

[0022] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0023] [Figure 1A] 1 shows an example of the top surface of the semiconductor device 100. [Figure 1B] 1B shows an example of an enlarged view of a region R in FIG. 1A. [Figure 1C] 1C shows an example of a cross section taken along line aa' in FIG. 1B. [Figure 1D] 1C shows an example of a cross section taken along line bb' in FIG. 1B. [Figure 1E] 1C shows an example of a cross section taken along the line cc' in FIG. 1B. [Figure 1F] 1C shows an example of a cross section taken along line dd' in FIG. 1B. [Diagram 2] 1B shows an example of a view in which a trench bottom region 60 is projected onto the upper surface of region R in FIG. 1A. [Diagram 3] 1 shows an example of an enlarged view of a region R in a modified example of the semiconductor device 100. FIG. [Figure 4A] 1 shows an example of a view in which a trench bottom region 60 is projected onto the upper surface of a region R in a modified example of the semiconductor device 100. [Figure 4B] 1 shows an example of a dd' cross section of a modified example of the semiconductor device 100. FIG. [Diagram 5] 1 shows an example of a dd' cross section of a modified example of the semiconductor device 100. FIG. [Figure 6A] 1 shows an example of an enlarged view of a region R in a modified example of the semiconductor device 100. FIG. [Figure 6B] 1 shows an example of a dd' cross section of a modified example of the semiconductor device 100. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0028] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0030] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0031] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0032] When the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. When the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.

[0033] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite polarities.

[0034] In this specification, the SI system of units is used. In this specification, distance and length units may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). For numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 16 The display of 1E-16 is 1 x 10 -16 Shows.

[0035] 1A shows an example of the top surface of a semiconductor device 100. The semiconductor device 100 of this example includes a gate wiring portion 50, a gate pad 112, an active portion 120, an edge termination structure portion 140, a peripheral portion 150, and a crossing portion 160.

[0036] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 in this example is a silicon substrate. In this specification, when the term "top view" is used, it means a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has an edge 102. The semiconductor substrate 10 also has a front surface 21 and a back surface 23, as described below.

[0037] The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is omitted in the figure.

[0038] The active section 120 may have a first active region 121, a second active region 122, and a third active region 123. The number of active regions in the active section 120 is not limited to this. The active section 120 may have at least two active regions, and may have four or more active regions. The first active region 121 and the second active region 122 may be provided at a distance from each other. The second active region 122 and the third active region 123 may be provided at a distance from each other. Similarly, when the active section 120 has four or more active regions, the respective active regions may be provided at a distance from each other. The active regions in this example are provided at a distance from each other in the Y-axis direction, but multiple active regions may be provided at a distance from each other in the X-axis direction.

[0039] The crossing portion 160 is a region between a plurality of spaced apart active regions. That is, the crossing portion 160 may separate the first active region 121 from the second active region 122, and may separate the second active region 122 from the third active region 123. In this example, the crossing portion 160 is a region extending in the X-axis direction, but may be a region extending in the Y-axis direction.

[0040] The outer periphery 150 is a region between the active portion 120 and the edge 102. That is, the outer periphery 150 may be a region surrounding the first active region 121, the second active region 122, the third active region 123, and the crossing portion 160.

[0041] The gate pad 112 is provided above the semiconductor substrate 10. A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to a gate trench portion 40 of the active portion 120. The gate trench portion 40 will be described later.

[0042] The gate wiring portion 50 is provided in the outer periphery portion 150 and the crossing portion 160 in a top view. The gate wiring portion 50 connects the gate pad 112 and the gate trench portion 40. By providing the gate wiring portion 50 in the crossing portion 160, it is possible to reduce the variation in wiring length from the gate pad 112 for each region of the semiconductor substrate 10. The gate wiring portion 50 provided in the outer periphery portion 150 and the gate wiring portion 50 provided in the crossing portion 160 may have different configurations or the same configuration. The configuration of the gate wiring portion 50 will be described later.

[0043] Edge termination structure 140 is provided on front surface 21 of semiconductor substrate 10. Edge termination structure 140 is provided in outer periphery 150 when viewed from above. Edge termination structure 140 relieves electric field concentration on the front surface 21 side of semiconductor substrate 10. Edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf provided in an annular shape surrounding active portion 120.

[0044] Fig. 1B shows an example of an enlarged view of region R in Fig. 1A. The semiconductor device 100 of this example includes, on a front surface 21 of a semiconductor substrate 10, a dummy trench portion 30, a gate trench portion 40, a gate wiring portion 50, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The semiconductor device 100 of this example also includes an emitter electrode 52 provided above the front surface 21 of the semiconductor substrate 10.

[0045] The dummy trench portions 30 are provided on the front surface 21 of the semiconductor substrate 10 in the active portion 120. The dummy trench portions 30 are trench portions electrically connected to the emitter electrode 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portions 30 may have two extension portions 31 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 33 connecting the two extension portions 31.

[0046] It is preferable that at least a part of the connection portion 33 is formed in a curved shape. By connecting the ends of the two extension portions 31 of the dummy trench portion 30, electric field concentration at the ends of the extension portions 31 can be alleviated.

[0047] The gate trench portion 40 is provided on the front surface 21 of the semiconductor substrate 10 in the active portion 120. The gate trench portion 40 is provided extending in a predetermined extension direction (in this example, the Y-axis direction). The gate trench portion 40 is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the gate trench portion 40 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0048] The semiconductor device 100 of this example has a structure in which one gate trench portion 40 and two dummy trench portions 30 are repeatedly arranged. That is, the semiconductor device 100 of this example has the gate trench portion 40 and the dummy trench portion 30 in a ratio of 1:2. For example, the semiconductor device 100 has I-shaped gate trench portions 40 and U-shaped dummy trench portions 30 alternately.

[0049] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, and the ratio of the dummy trench portions 30 may be the same as the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 3:2. In addition, the semiconductor device 100 may not have dummy trench portions 30, with all trench portions being gate trench portions 40.

[0050] The base region 14 is a region of a second conductivity type provided above a drift region 18, which will be described later. The base region 14 is, for example, a P-type region.

[0051] The emitter region 12 is provided above the drift region 18 and is a region of a first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, an N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions to the other. The emitter region 12 is also provided below the contact hole 54.

[0052] Moreover, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0053] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. The contact region 15 in this example is, for example, a P+ type. The contact region 15 in this example is provided on the front surface 21. The contact region 15 may be provided in the X-axis direction from one to the other of the two trench portions. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0054] The well region 17 is a second conductivity type region provided above the drift region 18. The well region 17 is, for example, a P+ type. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The boundary between the well region 17 and the base region 14 in the X-axis direction may be the boundary between the outer periphery portion 150 and the active portion 120. The boundary between the well region 17 and the base region 14 in the Y-axis direction may be the boundary between the crossing portion 160 and the active portion 120.

[0055] The emitter electrode 52 is provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween. The interlayer insulating film 38 is omitted in FIG. 1B. A contact hole 54, a contact hole 55, and a contact hole 56 are provided penetrating the interlayer insulating film 38. The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The emitter electrode 52 is provided above the gate wiring portion 50 provided in the crossing portion 160. The emitter electrode 52 and the gate wiring portion 50 are insulated from each other.

[0056] The emitter electrode 52 is made of a material containing a metal. At least a portion of the emitter electrode 52 may be made of a metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 may have a barrier metal layer made of titanium or a titanium compound under the region made of aluminum or the like.

[0057] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the active portion 120. The contact holes 54 may be formed above the base region 14. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided extending in the extension direction.

[0058] The contact hole 55 connects the gate metal layer 540 of the gate wiring portion 50 and the gate conductive portion in the second gate trench wiring portion 514. The gate metal layer 540 will be described later. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0059] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug layer made of tungsten or the like may be formed.

[0060] The gate wiring section 50 includes a first gate trench wiring section 512 and a second gate trench wiring section 514 .

[0061] The first gate trench wiring portion 512 extends in a predetermined direction. In this example, the first gate trench wiring portion 512 is provided extending in the Y-axis direction. The first gate trench wiring portion 512 may be provided extending from the first active region 121 to the second active region 122. The first gate trench wiring portion 512 may connect the gate trench portion 40 of the first active region 121 and the gate trench portion 40 of the second active region 122. In other words, the gate trench portion 40 and the first gate trench wiring portion 512 may be electrically connected to each other.

[0062] The first gate trench wiring portion 512 and the gate trench portion 40 may have the same configuration. That is, the width of the first gate trench wiring portion 512 and the width of the gate trench portion 40 may be the same, and the depth of the first gate trench wiring portion 512 and the depth of the gate trench portion 40 may be the same. However, the width of the first gate trench wiring portion 512 and the width of the gate trench portion 40 may be different, and the depth of the first gate trench wiring portion 512 and the depth of the gate trench portion 40 may be different. The first gate trench wiring portion 512 and the gate trench portion 40 may be integrally formed in the same process. However, the first gate trench wiring portion 512 and the gate trench portion 40 may be formed in different processes. The boundary between the first gate trench wiring portion 512 and the gate trench portion 40 may be the boundary between the active portion 120 and the crossing portion 160.

[0063] The first gate trench wiring portion 512 may include a plurality of first gate trench wiring portions 512. The number of the plurality of first gate trench wiring portions 512 and the number of the plurality of gate trench portions 40 in the active portion 120 may be the same. That is, the first gate trench wiring portion 512 may connect all of the gate trench portions 40 provided in the first active region 121 and the gate trench portions 40 provided in the second active region 122 to each other. However, the number of the plurality of first gate trench wiring portions 512 and the number of the plurality of gate trench portions 40 in the active portion 120 may be different, and some of the plurality of gate trench portions 40 provided in the plurality of active regions may not be connected to each other across the plurality of active regions.

[0064] The second gate trench wiring portion 514 may extend in a direction different from that of the first gate trench wiring portion 512, and may intersect with the first gate trench wiring portion 512 at an intersection 510. In this example, the second gate trench wiring portion 514 extends in the X-axis direction different from the Y-axis direction in which the first gate trench wiring portion 512 extends. The first gate trench wiring portion 512 and the second gate trench wiring portion 514 may be electrically connected at the intersection 510.

[0065] The intersection 510 may be provided inside the well region 17 in a cross section parallel to the depth direction of the semiconductor substrate 10, and the lower end may be shallower than the lower end of the well region 17. That is, the diffusion depth of the well region 17 may be deeper than the depth of the first gate trench wiring portion 512 and the second gate trench wiring portion 514, and may be deeper than the depth of the intersection 510. By providing the intersection 510 inside the well region 17, it is possible to alleviate electric field concentration at the bottom of the intersection 510. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 100.

[0066] The second gate trench wiring portion 514 may include a plurality of second gate trench wiring portions 514. In this example, the second gate trench wiring portion 514 includes four second gate trench wiring portions 514. In this example, the second gate trench wiring portion 514 has a U-shape. That is, the second gate trench wiring portion 514 may have two extension portions extending along an extension direction (in this example, the X-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion connecting the two extension portions. The second gate trench wiring portion 514 may have a similar U-shape at the end portion in the +X-axis direction. That is, the second gate trench wiring portion 514 may have a loop shape.

[0067] The second gate trench wiring portions 514 may each have an intersection 510 with the first gate trench wiring portion 512. In this example, the second gate trench wiring portions 514 each have four intersections 510 in the illustrated region R. The number of intersections 510 in each of the second gate trench wiring portions 514 may be the same as the number of the first gate trench wiring portions 512.

[0068] The well region 17 may be provided extending from one end of the second gate trench wiring portion 514 provided in the outer periphery 150 of the semiconductor device 100 to the other end of the second gate trench wiring portion 514 provided in the outer periphery 150. In other words, all intersections 510 where the multiple first gate trench wiring portions 512 and the multiple second gate trench wiring portions 514 intersect may be provided inside the well region 17.

[0069] The width W1 of the first gate trench wiring portion 512 and the width W2 of the second gate trench wiring portion 514 may be the same. This allows the first gate trench wiring portion 512 and the second gate trench wiring portion 514 to be formed in the same process. However, the width W1 of the first gate trench wiring portion 512 and the width W2 of the second gate trench wiring portion 514 may be different, and the first gate trench wiring portion 512 and the second gate trench wiring portion 514 may be formed in different processes.

[0070] The gate wiring section 50 of this example has a first gate trench wiring section 512 and a second gate trench wiring section 514 in the crossing section 160. As a result, since there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, the semiconductor device 100 can be flattened, and the patterning accuracy can be improved even in a large diameter wafer. Since the first gate trench wiring section 512 and the second gate trench wiring section 514 have a trench structure, the resistance value of the gate wiring section 50 can be reduced compared to the case where a gate runner structure of the same width is provided above the semiconductor substrate 10. In addition, since there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, a full surface etchback is possible, and the number of masks can be reduced.

[0071] The emitter electrode 52 may be provided above the intersection 510. That is, the emitter electrode 52 may be provided across the second gate trench wiring portion 514 from the first active region 121 to the second active region 122 in a top view.

[0072] FIG. 1B shows an example of an enlarged view of the region R in FIG. 1A. The region R includes the first active region 121, the second active region 122, the crossing portion 160, and the outer peripheral portion 150 located in the -X-axis direction of the active portion 120. The region including the second active region 122, the third active region 123, the crossing portion 160, and the outer peripheral portion 150 located in the -X-axis direction of the active portion 120 may have a similar configuration to the region R. The region including the first active region 121, the second active region 122, the crossing portion 160, and the outer peripheral portion 150 located in the +X-axis direction of the active portion 120 may have a similar configuration that is mirror-symmetric to the region R. The region including the second active region 122, the third active region 123, the crossing portion 160, and the outer peripheral portion 150 located in the +X-axis direction of the active portion 120 may have a similar configuration that is mirror-symmetric to the region R.

[0073] For example, in any of the regions, the gate wiring portion 50 may have a first gate trench wiring portion 512 and a second gate trench wiring portion 514, and the first gate trench wiring portion 512 and the second gate trench wiring portion 514 may intersect at an intersection 510. The first gate trench wiring portion 512 may connect the gate trench portion 40 of the first active region 121 to the gate trench portion 40 of the second active region 122, and may connect the gate trench portion 40 of the second active region 122 to the gate trench portion 40 of the third active region 123. In any of the regions, the emitter electrode 52 may be provided above the intersection 510. That is, the emitter electrode 52 may be provided as a single electrode across a plurality of active regions without being divided by the gate wiring portion 50.

[0074] Providing the emitter electrode 52 above the intersection 510 can reduce the parasitic inductance of the semiconductor device 100, compared to a case in which the emitter electrode 52 is provided separated by the gate wiring portion 50. Reducing the parasitic inductance can suppress oscillations that occur when the semiconductor device 100 is turned on or short-circuited.

[0075] 1C shows an example of the a-a' cross section in FIG. 1B. The a-a' cross section is a YZ plane passing through well region 17 in outer periphery 150. In the a-a' cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, and collector electrode 24.

[0076] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0077] The buffer region 20 is a first conductivity type region provided on the back surface 23 side of the semiconductor substrate 10 relative to the drift region 18. In this example, the buffer region 20 is, for example, an N type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. The buffer region 20 may be omitted.

[0078] The collector region 22 is provided below the buffer region 20. The collector region 22 has a second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0079] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0080] The second gate trench wiring portion 514 has a gate trench, a gate insulating film 5142, and a gate conductive portion 5144 formed on the front surface 21. The gate insulating film 5142 is formed to cover the inner wall of the gate trench. The gate insulating film 5142 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 5144 is formed inside the gate trench, further inside than the gate insulating film 5142. The gate insulating film 5142 insulates the gate conductive portion 5144 from the semiconductor substrate 10. The gate conductive portion 5144 is formed of a conductive material such as polysilicon. The second gate trench wiring portion 514 may be covered by an interlayer insulating film 38 on the front surface 21.

[0081] The second gate trench wiring portion 514 may be provided inside the well region 17. That is, the depth of the well region 17 may be deeper than the depth of the second gate trench wiring portion 514 in the depth direction of the semiconductor substrate 10.

[0082] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this. The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO) film.

[0083] 1D shows an example of the b-b' cross section in FIG. 1B. The b-b' cross section is a cross section passing through the first active region 121, the crossing portion 160, and the second active region 122, and is a YZ plane passing through the contact hole 54 in the active portion 120. In the b-b' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a plating film 53, and a collector electrode 24. The emitter electrode 52 and the plating film 53 are formed above the semiconductor substrate 10 and the interlayer insulating film 38. The semiconductor device 100 of this example may include an accumulation region 16. The accumulation region 16 will be described later.

[0084] The trench bottom region 60 is a region of a second conductivity type. In this example, the trench bottom region 60 is, for example, a P-- type. The doping concentration of the trench bottom region 60 may be lower than the doping concentration of the base region 14. The trench bottom region 60 may be connected to the well region 17.

[0085] The trench bottom region 60 may have a first trench bottom portion 62 and a second trench bottom portion 64. The second trench bottom portion 64 may be provided spaced apart from the first trench bottom portion 62 and connected to the well region 17.

[0086] The dummy trench portion 30 may have the same structure as the second gate trench wiring portion 514. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 by an interlayer insulating film 38.

[0087] An emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 and the second gate trench wiring portion 514 are insulated from each other by the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. A contact hole 56 may also be provided penetrating the interlayer insulating film 38.

[0088] The plating film 53 is formed above the emitter electrode 52. The plating film 53 is formed of a conductive material such as a metal. The material of the plating film 53 may include at least one of gold, palladium, and nickel. The plating film 53 may also be formed below the collector electrode 24. By forming the plating film 53 above the emitter electrode 52, the contact characteristics with the bonding wire and the lead frame via the solder or the like can be improved, and the electrical connection with an external device can be ensured.

[0089] The plating film 53 may be formed above the emitter electrode 52 over the entire emitter electrode 52. As described above, the emitter electrode 52 may be provided from the first active region 121 to the second active region 122, beyond the second gate trench wiring portion 514. Therefore, the semiconductor device 100 may include the plating film 53 provided on the emitter electrode 52 above the intersection portion 510.

[0090] Fig. 1E shows an example of the c-c' cross section in Fig. 1B. The c-c' cross section is a cross section passing through the first active region 121 and the outer circumferential portion 150, and is an XZ plane passing through the emitter region 12 in the active portion 120.

[0091] The accumulation region 16 is a region of a first conductivity type provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided. The doping concentration of the accumulation region 16 may be higher than the doping concentration of the drift region 18. The dose of ion implantation of the accumulation region 16 is 1.0E+12 cm -2 Above, 3.0E+13cm -2 By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be increased, and the on-voltage of the semiconductor device 100 can be reduced.

[0092] The gate trench portion 40 may have the same structure as the second gate trench wiring portion 514 and the dummy trench portion 30. The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21 side. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench and is formed on the inner side of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate trench portion 40 may be covered on the front surface 21 by an interlayer insulating film 38.

[0093] The trench bottom region 60 is provided in contact with the bottom of the gate trench portion 40. The trench bottom region 60 may be provided in contact with the bottom of the dummy trench portion 30. The trench bottom region 60 of this example is provided in contact with the bottoms of the gate trench portion 40 and the dummy trench portion 30.

[0094] The trench bottom region 60 of this example is provided so as to extend from the lower end of one of the trench parts to the lower end of the other opposing trench part in the trench arrangement direction of the multiple trench parts. The trench bottom region 60 may be provided so as to extend from the lower end of one of the trench parts to the lower end of the other opposing trench part, beyond the lower end of the other opposing trench part, to the lower end of the trench part adjacent to the other opposing trench part. In other words, the trench bottom region 60 may be provided so as to extend beyond the lower ends of two or more trench parts.

[0095] By providing the trench bottom region 60 in contact with the bottom of the gate trench portion 40, it is possible to suppress a rise in potential around the gate trench portion 40 when the semiconductor device 100 is turned on, and to suppress the dV / dt of the semiconductor device 100. This makes it possible to reduce the generation of noise associated with the switching operation of the semiconductor device 100.

[0096] As described above, the trench bottom region 60 has the first trench bottom part 62 and the second trench bottom part 64 that is provided at a distance from the first trench bottom part 62 and is connected to the well region 17. That is, the active part 120 may have a trench bottomless region 66 in which the trench bottom region 60 is not provided. By providing the trench bottomless region 66, the electron barrier is lowered, and the on-loss Eon can be reduced. When the semiconductor device 100 is turned on, injection of electrons may start first in the trench bottomless region 66, and then the current flow through the active part 120 in which the trench bottom region 60 is provided may start.

[0097] The emitter region 12 is provided above the first trench bottom portion 62. The emitter region 12 does not have to be provided above the second trench bottom portion 64 or in the trench bottomless region 66. By not providing the emitter region 12 in the trench bottomless region 66, the trench bottomless region 66 becomes more likely to function as a trigger when current begins to flow.

[0098] The base region 14 may be provided above the trench bottom region 60 and in the trench bottomless region 66. By providing the base region 14 in the trench bottomless region 66, the trench bottomless region 66 can act as a trigger when current begins to flow.

[0099] The accumulation region 16 may be provided above the trench bottomless region 66 and in the trench bottomless region 66. The accumulation region 16 in this example is provided only above the first trench bottom portion 62.

[0100] The gate wiring section 50 has a gate runner 520 and a gate metal layer 540. The gate runner 520 and the gate metal layer 540 are connected via a contact hole 55 provided in the interlayer insulating film 38. The contact hole 55 may be provided penetrating the interlayer insulating film 38, similar to the contact holes 54 and 56.

[0101] The gate runner 520 is provided in the outer periphery 150 of the semiconductor device 100. The gate runner 520 is provided above the semiconductor substrate 10 with an oxide film 39 sandwiched therebetween. The gate runner 520 may be formed of a conductive material such as polysilicon. The gate runner 520 in this example is made of polysilicon.

[0102] The oxide film 39 may be formed by oxidizing or nitriding the semiconductor of the semiconductor substrate 10. The oxide film 39 may be formed in the same process as the insulating film provided in the trench. However, the oxide film 39 may be formed in a process different from that of the insulating film provided in the trench. The oxide film 39 insulates the gate runner 520 from the semiconductor substrate 10.

[0103] The gate metal layer 540 is provided in the outer periphery 150 of the semiconductor device 100. The gate metal layer 540 is provided above the semiconductor substrate 10 with the interlayer insulating film 38 sandwiched therebetween. The gate metal layer 540 is formed of a material containing metal. The material of the gate metal layer 540 may be the same as or different from the material of the emitter electrode 52.

[0104] The gate metal layer 540 and the emitter electrode 52 are provided separately from each other, so that the emitter electrode 52 and the gate wiring portion 50 are insulated from each other.

[0105] The plating film 53 may be provided above the gate metal layer 540. However, the plating film 53 does not have to be provided above the gate metal layer 540.

[0106] Fig. 1F shows an example of the dd' cross section in Fig. 1B. The dd' cross section is a cross section passing through the outer periphery portion 150 and the crossing portion 160, and is an XZ plane passing through the first gate trench wiring portion 512 in the crossing portion 160.

[0107] The first gate trench wiring portion 512 may have the same structure as the second gate trench wiring portion 514, the dummy trench portion 30, and the gate trench portion 40. The first gate trench wiring portion 512 has a gate trench, a gate insulating film 5122, and a gate conductive portion 5124 formed on the front surface 21 side. The gate insulating film 5122 is formed to cover the inner wall of the gate trench. The gate conductive portion 5124 is formed inside the gate trench and is formed on the inner side of the gate insulating film 5122. The gate insulating film 5122 insulates the gate conductive portion 5124 from the semiconductor substrate 10. The first gate trench wiring portion 512 may be covered by an interlayer insulating film 38 on the front surface 21.

[0108] The first gate trench wiring portion 512 may be provided inside the well region 17. That is, the depth of the well region 17 may be deeper than the depth of the first gate trench wiring portion 512.

[0109] The depth of the second gate trench wiring portion 514 may be the same as the depth of the first gate trench wiring portion 512, may be deeper than the depth of the first gate trench wiring portion 512, or may be shallower than the depth of the first gate trench wiring portion 512. The depth of the second gate trench wiring portion 514 in this example is the same as the depth of the first gate trench wiring portion 512.

[0110] The gate runner 520 may be connected to an end of the second gate trench wiring portion 514 in the outer periphery 150. The gate metal layer 540 may be connected to an end of the second gate trench wiring portion 514 via the gate runner 520 in the outer periphery. That is, the gate conductive portion 5144 of the second gate trench wiring portion 514, the gate runner 520, and the gate metal layer 540 may be electrically connected to one another.

[0111] In the semiconductor device 100 of this example, the gate pad 112 is electrically connected to the gate metal layer 540 and the gate runner 520 provided in the outer peripheral portion 150 of the semiconductor device 100. The gate metal layer 540 and the gate runner 520 are electrically connected to the second gate trench wiring portion 514 in the outer peripheral portion 150. The second gate trench wiring portion 514 is electrically connected to the first gate trench wiring portion 512 at the intersection portion 510. The first gate trench wiring portion 512 is electrically connected to the gate trench portion 40 of the active portion 120. In this manner, the gate pad 112 is electrically connected to the gate trench portion 40 of the active portion 120.

[0112] 2 shows an example of a view in which a trench bottom region 60 is projected onto the upper surface of the region R in FIG. 1A. The trench bottom region 60 of this example has a first trench bottom part 62 and a second trench bottom part 64 provided at a distance from the first trench bottom part 62 and connected to the well region 17. The active portion 120 of this example has a trench bottomless region 66 in which the trench bottom region 60 is not provided.

[0113] The first trench bottom portion 62 may be provided inside the active portion 120 in a top view. That is, the first trench bottom portion 62 may be provided inside the first active region 121, the second active region 122, and the third active region 123 in a top view. A trench bottomless region 66 or a second trench bottom portion 64 may be provided in a region of the active portion 120 where the first trench bottom portion 62 is not provided.

[0114] The second trench bottom portion 64 is spaced apart from the first trench bottom portion 62 and provided outside the first trench bottom portion 62. The second trench bottom portion 64 may be provided from the active portion 120 to the crossing portion 160. That is, the second trench bottom portion 64 may be provided so as to overlap the first active region 121 and the crossing portion 160, may be provided so as to overlap the second active region 122 and the crossing portion 160, or may be provided so as to overlap the third active region 123 and the crossing portion 160, in a top view.

[0115] The second trench bottom portion 64 may be provided from the active portion 120 to the outer periphery portion 150. That is, the second trench bottom portion 64 may be provided so as to overlap the first active region 121 and the outer periphery portion 150, may be provided so as to overlap the second active region 122 and the outer periphery portion 150, or may be provided so as to overlap the third active region 123 and the outer periphery portion 150, in a top view.

[0116] The emitter region 12 may be provided above the first trench bottom portion 62. The emitter region 12 does not have to be provided above the second trench bottom portion 64 or in the trench bottomless region 66. By not providing the emitter region 12 in the trench bottomless region 66, the trench bottomless region 66 becomes more likely to function as a trigger when current begins to flow.

[0117] The base region 14 may be provided above the trench bottom region 60 and in the trench bottomless region 66. By providing the base region 14 in the trench bottomless region 66, the trench bottomless region 66 can act as a trigger when current begins to flow.

[0118] The second trench bottom portion 64 may be provided beyond the dummy trench portion 30 that is closest to the outer periphery portion 150. However, the second trench bottom portion 64 only needs to be provided in connection with the well region 17, and may be provided further inward than the dummy trench portion 30 that is closest to the outer periphery portion 150.

[0119] The trench bottomless region 66 in this example is provided near the outer periphery 150 and the crossing portion 160. The trench bottomless region 66 may be provided near the center of the active portion 120, further away from the outer periphery 150 and the crossing portion 160. In this case, the emitter region 12 does not need to be provided in the trench bottomless region 66. Also, in the trench bottomless region 66, the gate trench portion 40 may not be provided, and only the dummy trench portion 30 may be provided.

[0120] 3 shows an example of an enlarged view of a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1F in that the width W1 of the first gate trench wiring portion 512 and the width W2 of the second gate trench wiring portion 514 are different. In this example, the differences from the embodiment of FIG. 1F will be particularly described, and the rest may be the same as the embodiment of FIG. 1F.

[0121] The width W2 of the second gate trench wiring portion 514 may be wider than the width W1 of the first gate trench wiring portion 512. By making the width W2 of the second gate trench wiring portion 514 wider than the width W1 of the first gate trench wiring portion 512, the cross-sectional area of ​​the gate conductive portion 5144 can be increased and the resistance value can be reduced. However, the width W2 of the second gate trench wiring portion 514 may be the same as the width W1 of the first gate trench wiring portion 512, or may be narrower than the width W1 of the first gate trench wiring portion 512.

[0122] As an example, when the width W2 of the second gate trench wiring portion 514 is narrower than the width W1 of the first gate trench wiring portion 512, the number of the multiple second gate trench wiring portions 514 provided in the traversing portion 160 may be increased. This makes it possible to increase the total cross-sectional area of ​​the gate conductive portions 5144 in the multiple second gate trench wiring portions 514, thereby making it possible to reduce the resistance value.

[0123] 4A shows an example of a view in which the trench bottom region 60 is projected onto the upper surface of the region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 2 in that the trench bottom region 60 has a third trench bottom portion 68 provided in the crossing portion 160. In this example, differences from the embodiment of FIG. 2 will be particularly described, and the rest may be the same as the embodiment of FIG. 2.

[0124] The third trench bottom portion 68 may be provided by extending from one end of the second gate trench wiring portion 514 provided in the outer peripheral portion 150 of the semiconductor device 100 to the other end of the second gate trench wiring portion 514 provided in the outer peripheral portion 150. As described above, the region including the first active region 121, the second active region 122, the crossing portion 160, and the outer peripheral portion 150 located in the +X-axis direction of the active portion 120 may also have a similar configuration that is mirror-symmetrical to the region R. That is, the third trench bottom portion 68 may be provided by extending to the region that is the object of mirroring.

[0125] The third trench bottom portion 68 of this example is provided separately from the second trench bottom portion 64 provided in the first active region 121 and the second trench bottom portion 64 provided in the second active region 122. The third trench bottom portion 68 may be provided connected to the second trench bottom portion 64 provided in the first active region 121 and the second trench bottom portion 64 provided in the second active region 122. That is, the third trench bottom portion 68, the second trench bottom portion 64 provided in the first active region 121, and the second trench bottom portion 64 provided in the second active region 122 may be provided integrally.

[0126] 4B shows an example of a dd' cross section in a modified example of the semiconductor device 100. The dd' cross section in this example is the dd' cross section of the semiconductor device 100 in FIG. 4A.

[0127] The third trench bottom portion 68 may be provided in contact with the bottom of the first gate trench wiring portion 512. The third trench bottom portion 68 may be provided in contact with the bottom of the second gate trench wiring portion 514. Thus, the third trench bottom portion 68 may be provided in contact with the bottom of the intersection portion 510. By providing the trench bottom region 60 in contact with the bottom of the intersection portion 510, it is possible to alleviate electric field concentration at the bottom of the intersection portion 510. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 100.

[0128] The third trench bottom portion 68 provided in contact with the bottom of the intersection portion 510 may be connected to the well region 17. The third trench bottom portion 68 in this example is provided inside the well region 17, and is thereby connected to the well region 17. By connecting the third trench bottom portion 68 provided in contact with the bottom of the intersection portion 510 to the well region 17, the potential of the bottom of the intersection portion 510 can be kept at the emitter potential, and electric field concentration at the bottom of the intersection portion 510 can be alleviated. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 100.

[0129] The semiconductor device 100 of this example includes a third trench bottom portion 68 and a well region 17 below the intersection portion 510. The semiconductor device 100 may include only the third trench bottom portion 68 below the intersection portion 510.

[0130] 5 shows an example of a dd' cross section in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1F in that the gate wiring portion 50 does not have a gate runner 520. In this example, differences from the embodiment of FIG. 1F will be particularly described, and the rest may be the same as the embodiment of FIG. 1F.

[0131] The gate wiring section 50 is provided in the outer periphery 150 of the semiconductor device 100, and may have a gate metal layer 540 made of metal. The gate metal layer 540 may be connected to an end of the second gate trench wiring section 514 in the outer periphery 150.

[0132] The gate wiring section 50 of this example has a gate metal layer 540 in the outer peripheral section 150 of the semiconductor device 100, but does not have a gate runner 520. Since the gate wiring section 50 does not have the gate runner 520, there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, so that full etchback is possible and the number of masks can be reduced. In addition, there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, so that the semiconductor device 100 can be planarized, and patterning accuracy can be improved even in a large diameter wafer.

[0133] 6A shows an example of an enlarged view of a region R in a modified example of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1B in that the gate wiring portion 50 has a third gate trench wiring portion 516 provided in the outer periphery 150 of the semiconductor device 100. In this example, differences from the embodiment of FIG. 1B will be particularly described, and the rest may be the same as the embodiment of FIG. 1B.

[0134] The third gate trench wiring portion 516 may be connected to an end of the second gate trench wiring portion 514 at the outer periphery 150. The third gate trench wiring portion 516 may intersect with the second gate trench wiring portion 514 at an intersection portion 510. The third gate trench wiring portion 516 may be provided to extend in a direction parallel to the end side 102.

[0135] 6B shows an example of a dd' cross section in a modified example of the semiconductor device 100. The dd' cross section in this example is the dd' cross section of the semiconductor device 100 in FIG. 6A.

[0136] The third gate trench wiring portion 516 may have the same structure as the first gate trench wiring portion 512, the second gate trench wiring portion 514, the dummy trench portion 30, and the gate trench portion 40. The third gate trench wiring portion 516 has a gate trench, a gate insulating film 5162, and a gate conductive portion 5164 formed on the front surface 21 side. The gate insulating film 5162 is formed to cover the inner wall of the gate trench. The gate conductive portion 5164 is formed inside the gate trench and is formed on the inner side of the gate insulating film 5162. The gate insulating film 5162 insulates the gate conductive portion 5164 from the semiconductor substrate 10. The third gate trench wiring portion 516 may be covered by the interlayer insulating film 38 on the front surface 21.

[0137] The intersection 510 may be provided inside the well region 17 in a cross section parallel to the depth direction of the semiconductor substrate 10, and the lower end may be shallower than the lower end of the well region 17. That is, the diffusion depth of the well region 17 may be deeper than the depths of the second gate trench wiring portion 514 and the third gate trench wiring portion 516, and may be deeper than the depth of the intersection 510. By providing the intersection 510 inside the well region 17, it is possible to alleviate electric field concentration at the bottom of the intersection 510. This makes it possible to suppress a decrease in the breakdown voltage of the semiconductor device 100.

[0138] The gate wiring section 50 of this example has a gate metal layer 540 and a third gate trench wiring section 516 in the outer peripheral section 150 of the semiconductor device 100, but does not have a gate runner 520. Since the gate wiring section 50 does not have the gate runner 520, there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, so that full etchback is possible and the number of masks can be reduced. In addition, there is no need to leave polysilicon above the semiconductor substrate 10 in the manufacturing process of the semiconductor device 100, so that the semiconductor device 100 can be planarized, and patterning accuracy can be improved even in a large diameter wafer.

[0139] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0140] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0141] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 rear surface, 24 collector electrode, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 a connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 39 oxide film, 40 gate trench portion, 42 gate insulating film, 44 gate conductive portion, 50 gate wiring portion, 52 emitter electrode, 53 plating film, 54 contact hole, 55 contact hole, 56 contact hole, 60 trench bottom region, 62 first trench a trench bottom portion, 64 a second trench bottom portion, 66 a trench bottomless region, 68 a third trench bottom portion, 100 a semiconductor device, 102 an edge, 112 a gate pad, 120 an active portion, 121 a first active region, 122 a second active region, 123 a third active region, 140 an edge termination structure portion, 150 a periphery portion, 160 a cross portion, 10 intersection portion, 512 first gate trench wiring portion, 514 second gate trench wiring portion, 516 third gate trench wiring portion, 520 gate runner, 540 gate metal layer, 5122 gate insulating film, 5124 gate conductive portion, 5142 gate insulating film, 5144 gate conductive portion, 5162 gate insulating film, 5164 gate conductive portion

Claims

1. A semiconductor device having an active portion, a drift region of a first conductivity type provided in a semiconductor substrate; a second conductivity type base region provided above the drift region; a gate pad provided above the semiconductor substrate; an emitter electrode provided above the semiconductor substrate; a gate trench portion provided on a front surface of the semiconductor substrate in the active portion; a gate wiring portion for connecting the gate pad and the gate trench portion; Equipped with The gate wiring portion is a first gate trench wiring portion extending in a predetermined direction; a second gate trench wiring portion extending in a direction different from that of the first gate trench wiring portion and intersecting with the first gate trench wiring portion at an intersection portion; having The emitter electrode is provided above the intersection. Semiconductor device.

2. a second conductivity type trench bottom region provided in contact with a bottom of the gate trench portion; The semiconductor device according to claim 1 .

3. The doping concentration of the trench bottom region is lower than the doping concentration of the base region. The semiconductor device according to claim 2 .

4. The trench bottom region is provided in contact with a bottom portion of the intersection. The semiconductor device according to claim 2 .

5. a well region of a second conductivity type provided above the drift region; The trench bottom region provided in contact with the bottom of the intersection is connected to the well region. The semiconductor device according to claim 4.

6. a well region of a second conductivity type provided above the drift region; The trench bottom region is connected to the well region. The semiconductor device according to claim 2 .

7. The trench bottom region is provided to extend from one end of the second gate trench wiring portion provided in the outer periphery of the semiconductor device to the other end of the second gate trench wiring portion provided in the outer periphery. The semiconductor device according to claim 2 .

8. a well region of a second conductivity type provided above the drift region; The trench bottom region is a first trench bottom portion; a second trench bottom portion spaced apart from the first trench bottom portion and connected to the well region; have The semiconductor device according to claim 2 .

9. a well region of a second conductivity type provided above the drift region; The intersection is provided inside the well region in a cross section parallel to a depth direction of the semiconductor substrate, and a lower end of the intersection is shallower than a lower end of the well region. The semiconductor device according to claim 1 .

10. The well region is provided so as to extend from one end of the second gate trench wiring portion provided in the outer periphery of the semiconductor device to the other end of the second gate trench wiring portion provided in the outer periphery. The semiconductor device according to claim 9.

11. the active portion has a first active region and a second active region; The emitter electrode is provided, in a top view, from the first active region to the second active region, over the second gate trench wiring portion. The semiconductor device according to claim 1 .

12. the active portion has a first active region and a second active region; The first gate trench wiring portion is provided to extend from the first active region to the second active region and connects a gate trench portion of the first active region and a gate trench portion of the second active region. The semiconductor device according to claim 1 .

13. the second gate trench wiring portion includes a plurality of second gate trench wiring portions, The plurality of second gate trench wiring portions each have an intersection with the first gate trench wiring portion. The semiconductor device according to claim 1 .

14. The width of the second gate trench wiring portion is wider than the width of the first gate trench wiring portion. The semiconductor device according to claim 1 .

15. The gate wiring portion is provided on an outer periphery of the semiconductor device, is connected to an end of the second gate trench wiring portion at the outer periphery, and has a gate metal layer made of metal. The semiconductor device according to claim 1 .

16. The gate wiring portion is provided on the outer periphery of the semiconductor device, is connected to an end of the second gate trench wiring portion at the outer periphery, and has a gate runner made of polysilicon. The semiconductor device according to claim 1 .

17. The gate wiring portion includes a third gate trench wiring portion provided on an outer periphery of the semiconductor device and connected to an end of the second gate trench wiring portion at the outer periphery. The semiconductor device according to claim 1 .

18. a plating film provided on the emitter electrode above the intersection; The semiconductor device according to claim 1 .

19. an emitter region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region; The emitter electrode is provided above the emitter region. The semiconductor device according to claim 1 .

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