Indicator

Abstract

To provide a semiconductor device with power consumption suppressed to be low.SOLUTION: A semiconductor device includes: first wiring to which first electrical potential is supplied; second wiring to which second electrical potential higher than the first electrical potential is supplied; third wiring to which third electrical potential higher than the second electrical potential is supplied; fourth wiring to which a first clock signal is supplied, the first clock signal including a sequential repetition of the second electrical potential and fourth electrical potential equal to or higher than the third electrical potential; a first transistor and a second transistor having a same polarity; and a circuit configured to control according to an input signal and a second clock signal including a sequential repetition, by the first electrical potential and the third electrical potential, of an electrical connection between a gate of the first transistor or a gate of the second transistor and the first wiring or the third wiring. One of a source and a drain of the first transistor is connected to the second wiring. One of a source and a drain of the second transistor is connected to the fourth wiring. The other of the source and the drain of the first transistor and the other of the source and the drain of the second transistor are connected to each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a unipolar transistor. and a semiconductor device, such as a sequential circuit using the sequential circuit. . [Background technology]

[0002] A semiconductor display device in which a driver circuit is composed of transistors of the same conductivity type is manufactured at a low cost. In the following Patent Documents 1 and 2, Various circuits such as inverters and shift registers used in the drive circuit are A technology for configuring a resistor is disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-325798 A [Patent Document 2] JP 2010-277652 A Summary of the Invention [Problem to be solved by the invention]

[0004] Unipolar transistors are prone to negative threshold voltage shifts due to various factors, Semiconductor display devices made up of unipolar transistors tend to be prone to becoming ionized. In the driver circuit, the threshold voltage of a transistor is set to 1 V in a sequential circuit that outputs a pulse signal. When the voltage shifts to the negative, the amplitude of the potential of the output signal becomes smaller, and the drive circuit becomes positive. Or, even if normal operation is ensured, the power consumption of the drive circuit It increases.

[0005] For example, in the circuit shown in FIG. 10 of Patent Document 2, the transistor Q2 is The source is fixed to the low potential VSS. If the transistor Q2 is normally off, When a low potential VSS is applied to the gate of transistor Q2, it becomes non-conductive (off). However, if transistor Q2 is normally on, the gate of transistor Q2 Even if a low potential VSS is applied to the gate, the voltage between the gate and source is The gate voltage remains higher than the threshold voltage of transistor Q2. Transistor Q2 does not turn off and remains conductive (ON).

[0006] If transistor Q2 is turned on when it should be off, unwanted current will flow into the circuit. Furthermore, the unnecessary current causes a potential (for example, For example, in the case of FIG. 10 of Patent Document 2, the low-level potential VSS or the clock signal CLKA The current flows through the wiring for supplying the high-level potential VDD and the low-level potential VSS. The current flowing through the wiring increases due to the resistance of the wiring. The potential of the line to which the potential VSS is supplied increases. As a result, The amplitude of the potential to be applied is greater than the ideal potential difference between the potential VDD and the potential VSS. It becomes smaller.

[0007] In addition, a transistor is used to control the electrical connection between the wiring that supplies the clock signal and the output terminal. If a transistor (for example, transistor Q1 in FIG. 10 of Patent Document 2) is normally on, Since the output terminal is charged and discharged via transistor Q1, the power consumption of the circuit increases.

[0008] In particular, in the pixel portion of a semiconductor display device, a bus line connected to a plurality of pixels is When supplying a potential output from a circuit to a wiring, such as a scanning line or a signal line, A transistor that controls the output of the potential of the A large current supply capacity is required for the transistors Q1 and Q2. The channel width W of the transistor is larger than the channel width W of the other transistors in the circuit. However, the drain current of a transistor is often designed to be smaller than the channel width W. For example, if the channel width W of a normally-on transistor is increased, When the current flowing through the transistor is to be greater than that of the other transistors, the current flowing through the transistor is to be greater than that of the other transistors. As a result, unnecessary current flowing through the circuit increases, power consumption increases, or the output current decreases. The above-mentioned phenomenon, that is, the amplitude of the signal becomes smaller, is likely to occur significantly.

[0009] In light of the above-mentioned technical background, the present invention provides a semiconductor device that can reduce power consumption. Alternatively, the present invention provides a method for reducing the amplitude of an output potential. It is an object of the present invention to provide a semiconductor device capable of preventing the above-mentioned problems. [Means for solving the problem]

[0010] In one embodiment of the present invention, a first transistor that controls the supply of a power supply potential to an output terminal; A second transistor that controls the supply of a potential of a clock signal to the terminal; The gate of the first transistor is electrically connected to a pair of wirings to which a power supply potential is supplied. A circuit for controlling the connection is provided between the source and drain of the first transistor. The power supply potential supplied to the output terminal is provided on a wiring different from the wiring to which the pair of power supply potentials are supplied. It is assumed that the signals are supplied to the sequential circuit via lines.

[0011] With the above configuration, the gate of the first transistor and the source and drain of the first transistor Therefore, the source and drain of the first transistor can be electrically isolated from one of the first and second transistors. a power supply potential supplied to one of the inputs, and a power supply potential supplied to the gate of the first transistor; By controlling each of these, the gate voltage of the first transistor is controlled so that it is turned off. Therefore, even if the first transistor is normally on, When the transistor should be off, it can be turned off.

[0012] In one embodiment of the present invention, the first transistor and the second transistor are n-channel transistors. In this case, the clock signal has two potential values, and the source and drain of the first transistor The potential closer to the power supply potential supplied to the output terminal through the input is the same as the power supply potential mentioned above. The first and second transistors are p-channel or higher. In the case of a clock signal of a clock type, the source potential of the first transistor is The potential closer to the power supply potential supplied to the output terminal through the drain and the source is the power supply potential. The rank shall be equal to or lower than that of the

[0013] With the above configuration, even if the second transistor is normally on, the second transistor can be turned off. Therefore, the output terminal This prevents the charge and discharge of the capacitor, thereby keeping the power consumption of the circuit low.

[0014] Specifically, a semiconductor device according to one aspect of the present invention includes a first potential (VSS) supplying a first potential (VSS) to the first power supply. a second wiring to which a second potential (VEE) higher than the first potential is supplied; The third wiring is supplied with a third potential (VDD) that is the highest, and the third wiring is supplied with a third potential that is equal to or higher than the third potential. A first clock signal (CLKB) in which a fourth potential (VCC) and a second potential are alternately repeated. A fourth wiring is provided, and a first transistor and a second transistor having the same polarity, and A gate of the first transistor or a gate of the second transistor, and a first wiring or a third wiring The electrical connection of the input terminals is controlled by a second clock signal in which the first potential and the third potential are alternately repeated, and an input terminal is controlled by a second clock signal in which the first potential and the third potential are alternately repeated. A circuit for controlling the source and drain of the first transistor according to a signal (Vin). One of the inputs is electrically connected to the second wiring, and the other of the inputs is connected to the source and drain of the second transistor. One of the inputs is electrically connected to the fourth wiring, and the source and drain of the first transistor The other of the input and the other of the source and drain of the second transistor are electrically connected to each other. It has been done. Effect of the Invention

[0015] In one embodiment of the present invention, a semiconductor device using transistors with the same conductivity type, which consumes less power, is Alternatively, in one aspect of the present invention, an apparatus can be provided in which the amplitude of the potential to be output is It is possible to provide a semiconductor device that can prevent the size from becoming smaller. [Brief description of the drawings]

[0016] [Figure 1] 1A and 1B are diagrams showing the configuration of a sequential circuit and diagrams showing waveforms of potentials of clock signals; [Diagram 2] FIG. 1 shows the configuration of a sequential circuit. [Diagram 3] 4 is a timing chart showing the operation of a sequential circuit. [Figure 4] FIG. 2 is a diagram showing a configuration of a shift register. [Diagram 5] 4 is a timing chart showing the operation of a shift register. [Figure 6] FIG. 2 is a schematic diagram showing a j-th sequential circuit 10_j. [Figure 7] FIG. 1 shows the configuration of a sequential circuit. [Figure 8] FIG. 1 shows the configuration of a sequential circuit. [Figure 9] FIG. 1 shows the configuration of a sequential circuit. [Figure 10] FIG. 1 is a diagram showing a configuration of a semiconductor display device. [Figure 11] Top view of a pixel. [Figure 12] FIG. [Figure 13] 1A and 1B are diagrams illustrating a cross-sectional structure of a transistor. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0018] The present invention can be applied to any device using transistors, such as integrated circuits, RF tags, and semiconductor display devices. The category includes all semiconductor devices. Control circuit, DSP (Digital Signal Processor), Microcomputer Large Scale Integrated Circuit (LSI), including the t), FPGA (Field Programmable Gate Array) and C Programmable logic circuits such as PLD (Complex PLD) The category includes semiconductor devices such as ammable logic devices. The display device includes a liquid crystal display device, a light-emitting device having a light-emitting element, typically an organic light-emitting element, in each pixel. Placement, electronic paper, DMD (Digital Micromirror Device) , PDP (Plasma Display Panel), FED (Field Emi The driving circuitry of LCDs includes circuit elements using semiconductor films, such as LCDs. Semiconductor display devices are included in this category.

[0019] In this specification, the term "semiconductor display device" refers to a display device in which display elements such as liquid crystal elements and light emitting elements are used for each screen. A panel formed as a base and a model in which ICs including a controller are mounted on the panel This category includes modules.

[0020] In this specification, the term "connection" means electrical connection, and a current, a voltage, or a potential is Therefore, the connected state corresponds to a direct connection. It does not necessarily refer to the state in which a current, voltage or potential is available or is transmitted through circuit elements such as wires, resistors, diodes, and transistors. This also includes the state where the components are electrically connected to each other.

[0021] The source of a transistor is a source region that is a part of the semiconductor film that functions as an active layer. The term "transistor" refers to a transistor region, or a source electrode electrically connected to the semiconductor film. The drain of a transistor is a drain region that is a part of a semiconductor film that functions as an active layer, or The term "gate" refers to a gate electrode electrically connected to the semiconductor film. means...

[0022] The source and drain of a transistor are determined by the channel type of the transistor and the characteristics of each terminal. The name is changed depending on the level of the potential applied. Generally, n-channel transistors are In a transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called a drain. The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Assuming that the source and drain are fixed, explain the connection relationship of the transistor. In some cases, the source and drain are named according to the above potential relationship. Replace.

[0023] Example of sequential circuit configuration FIG. 1A illustrates an example of a circuit configuration of a sequential circuit according to one embodiment of the present invention. The sequential circuit 10 shown in FIG. 1 includes a circuit 11 having a plurality of transistors, a transistor 12, and a transistor In the sequential circuit 10 shown in FIG. Transistor 12 and transistor 13 have the same polarity. 1 shows an example in which the transistor 12 and the transistor 13 are both n-channel types.

[0024] A high-level power supply potential VDD is supplied to the circuit 11 via a wiring 14, and a low-level power supply potential VDD is supplied to the circuit 11 via a wiring 15. A power supply potential VSS of the same level is supplied to the circuit 11 through a wiring 17. The potential of the input signal Vin is supplied through the plurality of wirings 18, and a plurality of clock signals CLK A potential is supplied to each.

[0025] The circuit 11 is arranged in accordance with the potential of the input signal Vin and the potentials of a plurality of clock signals CLKA. Line 14 or wiring 15, the gate of transistor 12 or the gate of transistor 13 The device has a function of controlling the electrical connection of the device.

[0026] The transistor 12 is connected to a wiring 16 to which a low-level power supply potential VEE is supplied and to an output The transistor 13 has a function of controlling an electrical connection with the terminal 20. A function of controlling the electrical connection between the wiring 19 to which the clock signal CLKB is supplied and the output terminal 20. has.

[0027] Specifically, one of the source and drain of the transistor 12 is electrically connected to the wiring 16. The other of the source and drain is electrically connected to the output terminal 20. The transistor 13 has one of the source and drain electrically connected to the wiring 19. The other of the drains is electrically connected to the output terminal 20 .

[0028] The capacitor having the function of holding the gate voltage of the transistor 13 is However, if the parasitic capacitance of the gate of the transistor 13 is If the gate voltage is large and can be maintained without providing a capacitance element, There is no need to provide a quantum element.

[0029] A signal is input from the output terminal 20 of the sequential circuit 10 to a wiring called a bus line connected to a plurality of pixels. When supplying the output potential Vout, a transistor for controlling the output of the potential Vout is provided. The current supply capability of the transistor 12 and the transistor 13 is required to be large. The channel width W of the transistor 12 and the transistor 13 is smaller than that of the transistor in the circuit 11. It is desirable to set this to a large value.

[0030] The power supply potential VEE is lower than the power supply potential VDD and higher than the power supply potential VSS. It is desirable to do so.

[0031] In one embodiment of the present invention, the clock signal CLKB has two potential values ​​repeated. The low-level potential on the side closest to the power supply potential VSS must be equal to or higher than the power supply potential VEE. FIG. 1B shows a clock in which the power supply potential VSS and the power supply potential VDD are alternately repeated. The waveform of the potential of the clock signal CLKA and the power supply potential VEE and the power supply potential V which is higher than the power supply potential VDD are shown in FIG. 10 shows an example of the waveform of the potential of the clock signal CLKB, which is a repeating clock signal CC. In 1(B), the high-level potential of the clock signal CLKB is higher than the power supply potential VDD. Although the power supply potential VCC is illustrated, the high-level potential of the clock signal CLKB It is sufficient that the potential Vdd is equal to or higher than the power supply potential VDD.

[0032] If transistor 13 is an n-channel type, then the gate of transistor 13 is connected to the When a potential higher than the power supply potential VDD is supplied, the source and drain of the transistor 13 The high-level potential VCC of the clock signal CLKB supplied to one side of the transistor Then, the output voltage Vcc of the circuit 11 is supplied to the output terminal 20 via the transistor 13. A power supply potential VSS is supplied to the gate, and a cross-connect is connected to one of the source and drain of the transistor 13. When the low level potential VEE of the clock signal CLKB is supplied, the gate of the transistor 13 The voltage is the potential VSS-VEE. The potential V is set so that the potential VSS-VEE is equal to or less than Vth. By setting the height of EE, even if transistor 13 is normally on, The transistor 13 can be turned off, and the wiring 18 can be charged and discharged through the transistor 13. This can prevent power consumption from increasing.

[0033] In addition, when the transistor 12 is an n-channel type, the transistor 12 is The gate is connected to the power supply potential VDD or the threshold voltage of the transistor used in the circuit 11. When a potential lower than the power supply potential VDD by a factor of 1 is supplied, the transistor 1 turns on. When the power supply potential VSS is supplied to the gate of the transistor 2 from the circuit 11, the gate voltage Vgs is V The potential VEE is set so that the potential VSS-VEE≦Vth. By setting this, even if the transistor 12 is normally on, the transistor 12 is turned off. This can prevent power consumption from increasing.

[0034] When the transistors of the circuit 11 are normally on like the transistor 12, A current flows through the wiring 15 via the transistor of the circuit 11, and the potential of the wiring 15 increases. The potential of the line 15 is supplied to the gate of the transistor 12 through the circuit 11. As a result of the rise in the potential of the transistor 5, the potential supplied to the gate of the transistor 12 also rises from the power supply potential VSS. The potential rises from VSS to Vα.

[0035] Even if the potential supplied to the gate of the transistor 12 increases, the gate voltage Vgs=VSS+ If Vα-VEE≦Vth, transistor 12 remains off. In order to satisfy the voltage Vgs≦Vth, the power supply potential VS If the level of S and the power supply potential VEE are determined, then even if the transistor 12 is normally on, When the transistor 12 should be off, it can be close to off.

[0036] In addition, the output terminal 2 of the sequential circuit 10 is connected to a wiring called a bus line connected to a plurality of pixels. When supplying a potential Vout output from 0, the transistors 12 and 13 A large current supply capability is required for the transistor in circuit 11. The transistor 13 does not need to have a current supply capability as large as that of the transistor 11. The channel width W of the transistor 11 is smaller than the channel width W of the transistor 12 and the transistor 13. Therefore, the transistors in the circuit 11 are normally on, Even if the gate voltage is slightly higher than the threshold voltage, the transistor in circuit 11 The current flowing through the wiring 15 is caused when the gate voltage of the transistor 12 is slightly higher than the threshold voltage. Therefore, the current flowing through the wiring 15 can be made smaller than the current flowing through the wiring 16 when the wiring 15 is turned on. It is relatively easy to keep the voltage Vα, which corresponds to the change in potential, small.

[0037] In this way, in the sequential circuit 10 according to one aspect of the present invention, the transistor 12 located on the output side A wiring 16 electrically connected to one of the source and drain of the transistor The wiring 15 electrically connected to the transistor is electrically isolated. A power supply potential VEE is supplied to one of the source and drain of the transistor 12. The power supply potential VSS supplied to the gate can be controlled separately. Therefore, even if transistor 12 is normally on, it should be turned off. The gate voltage of transistor 12 can be controlled so that it is off when Therefore, the power consumption of the sequential circuit 10 can be reduced. This makes it possible to prevent the amplitude of the output potential Vout from becoming small.

[0038] In FIG. 1A, the transistor 12 and the transistor 13 are both n-channel transistors. In this example, the transistors 12 and 13 are both p-channel transistors. However, in this case, the wiring 15 connected to the circuit 11 and the transistor The wiring 16 connected to one of the source and drain of the stator 12 has a higher Further, the potential of the wiring 16 is lower than the potential of the wiring 15. It shall be so.

[0039] <Example 1 of a sequential circuit> Next, a specific configuration example of the sequential circuit 10 will be described. 1 shows an example of a sequential circuit.

[0040] The sequential circuit 10 illustrated in FIG. 2 includes a circuit 11, a transistor 101, and a transistor 102. The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied via wirings 110 to 112, and The clock signals CLKA1 to CLKA3 are respectively supplied to the A clock signal CLKB is supplied via a wiring 116, and an input signal CLKB is supplied via a wiring 117. A signal LIN is supplied to the input circuit 111, and an input signal RIN is supplied via a wiring 118. In the circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOUT is output via the wiring 120. It is output via line 120.

[0041] In the sequential circuit 10 shown in FIG. 2, the circuit 11 includes transistors 130 to It has 139.

[0042] A shift register can be configured by connecting a plurality of stages of the sequential circuit 10.

[0043] The transistors 101 and 102, and the transistors 130 to 131 In the case where the transistor 39 is an n-channel type, specifically, the power supply potential VDD is supplied to the wiring 110. A power supply potential VSS is supplied to the wiring 111, and a power supply potential VEE is supplied to the wiring 112. An input signal LIN is supplied to a wiring 117, and an input signal RIN is supplied to a wiring 118. The input signals LIN and RIN are supplied to a sequential circuit 10 shown in FIG. This corresponds to the input signal Vin in the

[0044] Transistor 130 has its gate connected to the gates of transistors 136 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other drain is connected to one of the source and drain of the transistor 137 and the transistor 13 The transistor 136 is connected to one of the source and drain of the transistor 9. and the drain is connected to the wiring 111, and the other of the source and the drain is connected to the wiring 11 9. One of the source and drain of the transistor 101 is connected to the wiring 11 2, and the other of the source and drain is connected to the wiring 120.

[0045] The gate of the transistor 131 is connected to the wiring 117, and the source and drain of the transistor 131 are connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 13. The gate of transistor 134 is connected to the other of the source and drain of transistor 132. The source and drain of the transistor are connected to the wiring 114, and one of the source and drain of the transistor is connected to the wiring 110. The other of the source and drain is connected to one of the source and drain of a transistor 133. The transistor 135 has a gate connected to the wiring 118 and a source and a drain One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 13. 0, the gate of transistor 136, and the gate of transistor 101.

[0046] The transistor 133 has a gate connected to the wiring 115 and a source and a drain The other terminal is connected to the gates of the transistors 130, 136, and 101. The transistor 132 has its gate connected to the wiring 117 and its source One of the source and drain is connected to the wiring 111, and the other of the source and drain is connected to the transistor The gate of transistor 130 is connected to the gate of transistor 136 and to the gate of transistor 101. The transistor 137 has a gate connected to the wiring 110 and a source and a drain One is the source and drain of transistor 131, the other is the source of transistor 130 and the other of the source and drain of the transistor 138. The transistor 138 has one of its source and drain connected to a wiring. 113, and the other of the source and drain is connected to a wiring 119.

[0047] The transistor 139 has a gate connected to the wiring 110 and a source and a drain One is the source and drain of transistor 131, the other is the source of transistor 130 and the other of the source and drain of the transistor 102. The transistor 102 has a source and a drain connected to a wiring. 116 , and the other of the source and drain is connected to a wiring 120 .

[0048] The operation of the sequential circuit 10 shown in FIG. 2 will be explained with reference to the timing chart shown in FIG. Reveal.

[0049] As shown in FIG. 3, during a period t1, the clock signal CLKA1 supplied to the wiring 113 The clock signal CLKA2 supplied to the wiring 114 is at the potential VSS, the clock signal CLKA3 supplied to the wiring 114 is at the potential VDD, The clock signal CLKA3 supplied to the wiring 115 is at potential VDD, and the clock The signal CLKB is at the potential VEE, the input signal LIN supplied to the wiring 117 is at the potential VSS, The input signal RIN supplied to 118 is at the potential VSS.

[0050] Therefore, in the period t1, in the sequential circuit 10, the transistor 101 and the transistor 13 0, transistor 133, transistor 134, transistor 136, transistor 13 7, transistor 139 is turned on. Also, transistors 131 and 132 Therefore, the transistor 135, the transistor 138, and the transistor 102 are turned off. Thus, the power supply potential VEE of the wiring 112 is output from the wiring 120 as the potential of the output signal GOUT. In addition, the power supply potential VSS of the wiring 111 is input to the wiring 112 as the potential of the output signal SROUT. It is output from 119.

[0051] Next, as shown in FIG. 3, during a period t2, the clock signal C LKA1 is at the potential VSS, the clock signal CLKA2 supplied to the wiring 114 is at the potential VSS, The clock signal CLKA3 supplied to the wiring 115 is at the potential VDD, and the The clock signal CLKB is at the potential VEE, and the input signal LIN supplied to the wiring 117 is at the potential VD D. The input signal RIN supplied to the wiring 118 is at the potential VSS.

[0052] Therefore, in the period t2, in the sequential circuit 10, the transistors 131 to 1 33, transistors 137 to 139, and transistor 102 are turned on. In addition, the transistor 101, the transistor 130, the transistor 134 to the transistor Therefore, the potential VCC of the clock signal CLKB on the wiring 116 becomes The potential of the output signal GOUT is output from the wiring 120, and the clock signal CL The potential VSS of KA1 is output from the wiring 119 as the potential of the output signal SROUT.

[0053] Next, as shown in FIG. 3, during a period t3, the clock signal C LKA1 is at potential VDD, the clock signal CLKA2 supplied to the wiring 114 is at potential VSS, The clock signal CLKA3 supplied to the wiring 115 is at the potential VSS, and the wiring 116 is at the potential VSS. The clock signal CLKB is at potential VCC, and the input signal LIN supplied to the wiring 117 is at potential VD D. The input signal RIN supplied to the wiring 118 is at the potential VSS.

[0054] Therefore, in the period t3, in the sequential circuit 10, the transistors 131 and 13 2, transistor 138 and transistor 102 are turned on. Also, transistor 101 , transistor 130, transistors 133 to 137, transistor 13 9 is turned off. Therefore, the potential VCC of the clock signal CLKB on the wiring 116 is The potential of the signal GOUT is output from the wiring 120, and the clock signal CLKA The potential VDD of 1 is output from the wiring 119 as the potential of the output signal SROUT.

[0055] Next, as shown in FIG. 3, during a period t4, the clock signal C LKA1 is at potential VDD, the clock signal CLKA2 supplied to the wiring 114 is at potential VDD, The clock signal CLKA3 supplied to the wiring 115 is at the potential VSS, and the wiring 116 is at the potential VSS. The clock signal CLKB is at potential VCC, and the input signal LIN supplied to the wiring 117 is at potential VS The input signal RIN supplied to the wiring 118 is set to the potential VSS.

[0056] Therefore, in the period t4, in the sequential circuit 10, the transistors 134 and 13 8, transistor 102 is turned on. Also, transistor 101 and transistor 130 to transistors 133, transistors 135 to 137, and transistor 1 Therefore, the potential VCC of the clock signal CLKB on the wiring 116 is The potential of the input signal GOUT is output from the wiring 120, and the clock signal CLK of the wiring 113 is The potential VDD of A1 is output from the wiring 119 as the potential of the output signal SROUT.

[0057] Next, as shown in FIG. 3, during a period t5, the clock signal C LKA1 is at potential VSS, the clock signal CLKA2 supplied to the wiring 114 is at potential VDD, The clock signal CLKA3 supplied to the wiring 115 is at the potential VDD, and the The clock signal CLKB is at the potential VEE, and the input signal LIN supplied to the wiring 117 is at the potential VS S, the input signal RIN supplied to the wiring 118 is at the potential VDD.

[0058] Therefore, in the period t5, in the sequential circuit 10, the transistors 101 and 13 0, transistor 136, transistors 133 to 135, transistor 1 37 and transistor 139 are turned on. Also, transistor 131 and transistor 13 2, the transistor 138 and the transistor 102 are turned off. The power supply potential VEE is output from the wiring 120 as the potential of the output signal GOUT. The power supply potential VSS of the line 111 is output from the wiring 119 as the potential of the output signal SROUT. do.

[0059] In the above operation, the transistor 101 is turned off during the period from t2 to t4. In particular, during periods t3 and t4, the clock signal CLKB applied to the wiring 116 Since the potential VCC is at a high level, when the transistor 101 is on, the transistor A current flows between the wiring 116 and the wiring 112 via the capacitor 101 and the transistor 102. However, in one embodiment of the present invention, the gate of the transistor 101 and the source and drain Specifically, when the transistor 101 is turned off, A power supply potential VSS of the wiring 111 is applied to the gate of the transistor 101. A power supply potential VEE of the wiring 112 can be applied to one of the source and drain of the transistor 1. Therefore, even if a current flows between the wiring 116 and the wiring 112, the current The power supply potential VEE of the transistor 101 rises, and the gate voltage Vgs of the transistor 101 reaches the threshold voltage Vth. As a result, transistor 101 can finally be turned off.

[0060] In the above operation, the transistor 102 is turned off during periods t1 and t5. During these periods, the gate of the transistor 102 is supplied with the power supply potential VS of the wiring 111. However, a voltage S is supplied to one of the source and drain of the transistor 102. The potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied. The gate voltage of the transistor 102 can be made lower than the threshold voltage Vth. It is desirable that the potential VEE is higher than the potential VSS minus the threshold voltage Vth. .

[0061] FIG. 4 shows an example of a shift register formed by connecting multiple stages of the sequential circuit 10. Shown as:

[0062] The shift register shown in FIG. 4 includes sequential circuits 10_1 to 10_y (y is a natural number). The sequential circuits 10_1 to 10_y are the same as the sequential circuit 10 shown in FIG. 0. However, the wirings 113 to 115 shown in FIG. Any three of the signals CLKA1 to CLKA4 are the clock signals C The clock signals LKA1 to CLKA3 are supplied to the wiring 116. In this case, any one of the clock signals CLKB1 to CLKB4 is a clock It is supplied as the clock signal CLKB.

[0063] Specifically, in the sequential circuit 10_4m+1, the clock signal CLKA1 is input to the wiring 113, A clock signal CLKA2 is supplied to the wiring 14, and a clock signal CLKA3 is supplied to the wiring 115. In the first circuit 10_4m+2, the clock signal CLKA2 is input to the wiring 113, and the clock A clock signal CLKA3 is supplied to the sequential circuit 10, and a clock signal CLKA4 is supplied to the wiring 115. In 4m+3, the clock signal CLKA3 is applied to the wiring 113, and the clock signal CLK is applied to the wiring 114. A4, the clock signal CLKA1 is supplied to the wiring 115. , a clock signal CLKA4 is applied to the wiring 113, a clock signal CLKA1 is applied to the wiring 114, and A clock signal CLKA2 is supplied to 15. Here, m is the total number of sequential circuits 10 is y. Let be any integer such that

[0064] Specifically, in the sequential circuit 10_4m+1, the clock signal CLKB1 is input to the wiring 116. In the sequential circuit 10_4m+2, the clock signal CLKB4 is supplied to the wiring 116. In the sequential circuit 10_4m+3, the clock signal CLKB3 is supplied to the wiring 116. In the sequential circuit 10_4m+4, a clock signal CLKB2 is supplied to a wiring 116.

[0065] In the shift register shown in FIG. 4, a sequential circuit 10_j (j is a natural number equal to or smaller than y) is The positions of the wiring 113 to wiring 120 are shown in FIG. 6. As can be seen from FIG. In this way, the wiring 117 of the sequential circuit 10_j is connected to the wiring 119 of the preceding sequential circuit 10_j-1. The output signal SROUTj-1 output from the input terminal LIN is supplied as the input signal LIN. The potential of the start pulse signal SP is supplied to the wiring 117 of the first-stage sequential circuit 10_1. The configuration will be as follows.

[0066] In addition, the wiring 118 of the sequential circuit 10_j is connected to the wiring 11 of the sequential circuit 10_j+2, which is two stages behind. The output signal SROUTj+2 output from the output terminal 9 is supplied as the input signal RIN. On the other hand, an input signal RIN_y-1 is provided to the wiring 118 of the sequential circuit 10_y-1 in the y-1th stage. An input signal RIN_y is supplied to the wiring 118 of the y-th stage sequential circuit 10_y. Assuming that the input signal RIN_y-1 exists as a sequential circuit 10_y+1, In this case, assume that an output signal SROUTy+1 is to be output from the sequential circuit 10_y+1. In addition, it is assumed that the input signal RIN_y is a sequential circuit 10_y+2. When this occurs, the output signal SROUTy+2 to be output from the sequential circuit 10_y+2 is It is expected.

[0067] An output signal GOUTj is output from the wiring 120 of the sequential circuit 10_j.

[0068] FIG. 5 shows the potentials of the clock signals CLKA1 to CLKA4 and the start pulse The timing chart of the potential of the signal SP and the potentials of the output signals GOUT1 to GOUT3 The clock signals CLKA1 to CLKA4 are each The timing of the shifts shown in Figure 4 is shifted backward by a quarter period. The register operates according to the above signal. And the pulse width is half of the above clock signal. The pulse is shifted backwards by one quarter of the clock signal. The output signals GOUT1 to GOUTy each have a waveform that is softened.

[0069] For example, the shift register shown in FIG. 4 may be used to connect multiple pixels in a semiconductor display device. The output signals GOUT1 to GOUTy are provided to wiring called bus lines connected to the In this case, the output transistors of the sequential circuits 10_1 to 10_y are The stator 101 and the transistor 102 are required to have a large current supply capability. The channel width W of the transistor 101 and the transistor 102 is The channel width W of the transistor other than the transistor 102 must be designed to be larger than that of the transistor other than the transistor 102. Therefore, when the transistor 101 and the transistor 102 are normally on, , the power consumption of the shift register increases, or the output signals GOUT1 to GOUT The amplitude of the output signal GOUTy is likely to become smaller. In one embodiment of the present invention, the sequential circuits 10_1 to 10_y each have an output side Even if the transistor 101 and the transistor 102 are normally on, When the power supply 101 and the transistor 102 should be turned off, they can be turned off.

[0070] Therefore, a semiconductor device according to one embodiment of the present invention using the above shift register consumes less power. The amplitudes of the output signals GOUT1 to GOUTy are reduced. Furthermore, in the semiconductor device according to one embodiment of the present invention using the above shift register, The conductor display device has low power consumption and the amplitude of the signal supplied to the bus line is small. Therefore, it is possible to prevent display defects caused by the above.

[0071] <Specific example of sequential circuit configuration 2> Another configuration example of the sequential circuit according to one embodiment of the present invention will be described.

[0072] The sequential circuit 10 shown in FIG. 7A includes a circuit 11, a transistor 101, and a transistor 1 The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied through the wirings 110 to 112, and the wirings 113 and 11 4, the clock signal CLKA1 and the clock signal CLKA2 are respectively supplied. A clock signal CLKB is supplied via a wiring 116, and An input signal LIN is supplied through the line 112, and an input signal RIN is supplied through the line 118. In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via line 120.

[0073] In the sequential circuit 10 shown in FIG. 7A, the circuit 11 includes transistors 313 to It has a dial 319.

[0074] A shift register can be configured by connecting a plurality of stages of the sequential circuits 10.

[0075] The gate of transistor 313 is connected to the gates of transistors 314 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other drain is connected to the gate of the transistor 319 and the gate of the transistor 102. One of the source and drain of the transistor 314 is connected to the wiring 111. The other of the source and drain of the transistor 101 is connected to a wiring 119. One of the source and drain of each of the transistors is connected to the wiring 112, and the other of the source and drain of each of the transistors is connected to the wiring 112. The other end is connected to the wiring 120.

[0076] The gate of the transistor 315 is connected to the wiring 117, and the source and drain of the transistor 315 are connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 31 9 and the gate of transistor 102. Transistor 316 is The gate is connected to the wiring 114, and one of the source and drain is connected to the wiring 110. The other of the source and drain is connected to the transistor 313, the transistor 314, and The gate of transistor 317 is connected to the gate of transistor 101. The source and drain of the transistor are connected to the line 118, and one of the source and drain of the transistor is connected to the wiring 110. The other of the gates and drains is connected to the transistor 313, the transistor 314, and the transistor 1 It is connected to Gate 01.

[0077] The transistor 318 has a gate connected to the wiring 117 and a source and a drain One of the source and drain terminals is connected to the wiring 111, and the other of the source and drain terminals is connected to the transistor 313. Transistor 314 and the gate of transistor 101. 19 has its gate connected to the gate of transistor 102, and its source and drain One of the source and drain is connected to the wiring 113, and the other of the source and drain is connected to the wiring 119. The gate of transistor 102 is connected to the gate of transistor 319. One of the source and drain is connected to the wiring 116, and the other of the source and drain is connected to the wiring 116. is connected to the wiring 120.

[0078] In the sequential circuit 10 shown in FIG. 7A, all the transistors are n-channel type. Specifically, in FIG. 7A, a power supply potential VDD is supplied to the wiring 110, and When the power supply potential VSS is supplied to the line 111 and the power supply potential VEE is supplied to the line 112, The following example shows a case where

[0079] The sequential circuit 10 shown in FIG. 7A has a gate and a source of a transistor 101 on the output side, and The drain of the transistor 101 can be electrically isolated from the drain of the transistor 102. As a result, one of the source and drain of the transistor 101 is Even if the potential of the wiring 112 for supplying potential to the other side increases, the transistor 101 When it should be off, it can be turned off. One of the drains is connected to the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS. Therefore, the gate voltage of the transistor 102 is made lower than the threshold voltage Vth. Therefore, even if the transistor 102 is normally on, When 102 should be off, it can be turned off.

[0080] The sequential circuit 10 shown in FIG. 7B includes a circuit 11, a transistor 101, and a transistor 1 The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied via wirings 110 to 112, and wirings 113 to 11 5, clock signals CLKA1 to CLKA3 are supplied, respectively. A clock signal CLKB is supplied via a wiring 116, and An input signal LIN is supplied through the line 112, and an input signal RIN is supplied through the line 118. In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via line 120.

[0081] In the sequential circuit 10 shown in FIG. 7B, the circuit 11 includes transistors 344 to It has a resistor 351.

[0082] A shift register can be configured by connecting a plurality of stages of the sequential circuits 10.

[0083] The gate of transistor 344 is connected to the gates of transistors 345 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other drain is connected to the gates of the transistor 351 and the transistor 102. One of the source and drain of the transistor 345 is connected to the wiring 111. The other of the source and the drain is connected to a wiring 119. One of the source and the drain is connected to the wiring 112, and the other of the source and the drain is connected to the wiring It is connected to line 120.

[0084] The gate of the transistor 346 is connected to the wiring 117, and the source and drain of the transistor 346 are connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 35 1 and the gate of transistor 102. Transistor 347 is connected to its gate The gate is connected to the wiring 114, and one of the source and drain is connected to the wiring 110. The other of the source and drain of the transistor 344, the transistor 345, and the transistor The gate of transistor 348 is connected to the gate of wiring 115. 110, and one of its source and drain is connected to the wiring 110. The other drain is connected to the gates of transistors 344, 345, and 101. The gate of the transistor 349 is connected to the wiring 117. One of the source and drain of the A transistor 344, a transistor 345, and a transistor 101 are connected to the gates of the transistors 344, 345, and 101. is.

[0085] The transistor 350 has a gate connected to the wiring 118 and a source and a drain One of the source and drain terminals is connected to the wiring 110, and the other of the source and drain terminals is connected to the transistor 344. Transistor 345 and the gate of transistor 101. 51 has its gate connected to the gate of transistor 102, and its source and drain One of the source and drain is connected to the wiring 113, and the other of the source and drain is connected to the wiring 119. The gate of transistor 102 is connected to the gate of transistor 351. One of the source and drain is connected to the wiring 116, and the other of the source and drain is connected to the wiring 116. is connected to the wiring 120.

[0086] In the sequential circuit 10 shown in FIG. 7B, all the transistors are n-channel type. Specifically, in FIG. 7B, a power supply potential VDD is supplied to the wiring 110, and When the power supply potential VSS is supplied to the line 111 and the power supply potential VEE is supplied to the line 112, The following example shows a case where

[0087] The sequential circuit 10 shown in FIG. 7B is a transistor 101 on the output side, which is connected to a gate, a source, and a The drain of the transistor 101 can be electrically isolated from the drain of the transistor 102. As a result, one of the source and drain of the transistor 101 is Even if the potential of the wiring 112 for supplying potential to the other side increases, the transistor 101 When it should be off, it can be turned off. One of the drains is connected to the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS. Therefore, the gate voltage of the transistor 102 is made lower than the threshold voltage Vth. Therefore, even if the transistor 102 is normally on, When 102 should be off, it can be turned off.

[0088] The sequential circuit 10 shown in FIG. 8A includes a circuit 11, a transistor 101, and a transistor 1 The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied through the wirings 110 to 112, and the wirings 113 and 11 4, the clock signal CLKA1 and the clock signal CLKA2 are respectively supplied. A clock signal CLKB is supplied via a wiring 116, and An input signal LIN is supplied through the line 112, and an input signal RIN is supplied through the line 118. In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via line 120.

[0089] In the sequential circuit 10 shown in FIG. 8A, the circuit 11 includes transistors 374 to It has a resistor 381.

[0090] A shift register can be configured by connecting a plurality of stages of the sequential circuits 10.

[0091] Transistor 374 has its gate connected to the gates of transistors 375 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other of the drains is connected to one of the source and drain of the transistor 377. The transistor 375 has one of its source and drain connected to the wiring 111. The other of the source and drain is connected to a wiring 119. One of the source and drain is connected to the wiring 112, and the other of the source and drain is connected to the wiring 1 It is connected to 20.

[0092] The transistor 376 has a gate connected to the wiring 117 and a source and a drain connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 37 The gate of transistor 377 is connected to one of the source and drain of transistor 377. The other of the source and drain of the transistor 381 is connected to the wiring 110. The gate of transistor 378 is connected to the gate of wiring 11. 4, one of its source and drain is connected to the wiring 110, and its source and The other drain is connected to the transistor 374, the transistor 375, and the transistor 101. is connected to the gate.

[0093] The transistor 379 has a gate connected to the wiring 117 and a source and a drain One of the source and drain terminals is connected to the wiring 111, and the other of the source and drain terminals is connected to the transistor 374. Transistor 375 and the gate of transistor 101. 80 has its gate connected to the wiring 118 and one of its source and drain connected to the wiring 11 0, and the other of the source and drain is connected to transistor 374, transistor 37 5, and the gate of transistor 101. Transistor 381 is connected to its One of the source and drain is connected to the wiring 113, and the other of the source and drain is connected to the wiring The transistor 102 has one of its source and drain connected to a wiring 119. 116 , and the other of the source and drain is connected to a wiring 120 .

[0094] In the sequential circuit 10 shown in FIG. 8A, all the transistors are n-channel type. Specifically, in FIG. 8A, a power supply potential VDD is supplied to the wiring 110, and When the power supply potential VSS is supplied to the line 111 and the power supply potential VEE is supplied to the line 112, The following example shows a case where

[0095] The sequential circuit 10 shown in FIG. 8A has a gate and a source of a transistor 101 on the output side, and The drain of the transistor 101 can be electrically isolated from the drain of the transistor 102. As a result, one of the source and drain of the transistor 101 is Even if the potential of the wiring 112 for supplying potential to the other side increases, the transistor 101 When it should be off, it can be turned off. One of the drains is connected to the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS. Therefore, the gate voltage of the transistor 102 is made lower than the threshold voltage Vth. Therefore, even if the transistor 102 is normally on, When 102 should be off, it can be turned off.

[0096] The sequential circuit 10 shown in FIG. 8B includes a circuit 11, a transistor 101, and a transistor 1 The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied through the wirings 110 to 112, and the wirings 113 and 11 4, the clock signal CLKA1 and the clock signal CLKA2 are respectively supplied. A clock signal CLKB is supplied via a wiring 116, and An input signal LIN is supplied through the line 112, and an input signal RIN is supplied through the line 118. In the sequential circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOU T is output via line 120.

[0097] In the sequential circuit 10 shown in FIG. 8B, the circuit 11 includes transistors 414 to It has a resistor 422.

[0098] A shift register can be configured by connecting a plurality of stages of the sequential circuit 10.

[0099] The gate of transistor 414 is connected to the gates of transistors 415 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other drain is connected to one of the source and drain of the transistor 417. The transistor 415 has one of its source and drain connected to the wiring 111. The other of the source and drain is connected to a wiring 119. One of the source and drain is connected to the wiring 112, and the other of the source and drain is connected to the wiring 1 It is connected to 20.

[0100] The gate of the transistor 416 is connected to the wiring 117, and the source and drain of the transistor 416 are connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 41 The gate of transistor 417 is connected to one of the source and drain of transistor 417. The other of the source and drain is connected to the gate of the transistor 421. The transistor 418 has its gate connected to the line 114 and its source connected to the line 115. One of the source and drain is connected to the wiring 110, and the other of the source and drain is connected to the transistor. A gate of the transistor 414, a gate of the transistor 415, and a gate of the transistor 101 are connected to the The transistor 419 has a gate connected to the wiring 117 and a source and a drain One of the source and drain of the transistor 414 is connected to the wiring 111, and the other of the source and drain of the transistor 414 is connected to the wiring 111. The transistor 415 is connected to the gate of the transistor 101. 420 has its gate connected to the wiring 118 and one of its source and drain connected to the wiring 1 10, and the other of the source and drain is connected to transistor 414, transistor 4 15, and the gate of transistor 101. Transistor 421 is connected to the One of the source and the drain is connected to the wiring 113, and the other of the source and the drain is connected to the wiring Transistor 422 has its gate connected to line 110. , one of its source and drain is connected to the gate of the transistor 421, and the other is connected to the gate of the transistor 41 7, the other of which is connected to the source and drain of the transistor The source and drain of the transistor 102 are connected to the gate of the transistor 102. One of the source and drain is connected to the wiring 116, and the other of the source and drain is connected to the wiring 120. There are.

[0101] In the sequential circuit 10 shown in FIG. 8B, all the transistors are n-channel type. Specifically, in FIG. 8B, a power supply potential VDD is supplied to the wiring 110, and When the power supply potential VSS is supplied to the line 111 and the power supply potential VEE is supplied to the line 112, The following example shows a case where

[0102] The sequential circuit 10 shown in FIG. 8B has a gate and a source of the transistor 101 on the output side, and The drain of the transistor 101 can be electrically isolated from the drain of the transistor 102. As a result, one of the source and drain of the transistor 101 is Even if the potential of the wiring 112 for supplying potential to the other side increases, the transistor 101 When it should be off, it can be turned off. One of the drains is connected to the potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS. Therefore, the gate voltage of the transistor 102 is made lower than the threshold voltage Vth. Therefore, even if the transistor 102 is normally on, When 102 should be off, it can be turned off.

[0103] A sequential circuit 10 illustrated in FIG. 9 includes a circuit 11, a transistor 101, and a transistor 102. The transistor 101 corresponds to the transistor 12 in FIG. The transistor 102 corresponds to the transistor 13 in FIG. Various power supply potentials are supplied via wirings 110 to 112, and The clock signals CLKA1 and CLKA2 are respectively supplied to the A clock signal CLKB is supplied via a wiring 116, and an input signal CLKB is supplied via a wiring 117. A signal LIN is supplied to the input circuit 111, and an input signal RIN is supplied via a wiring 118. In the circuit 10, the output signal SROUT is output via the wiring 119, and the output signal GOUT is output via the wiring 120. It is output via line 120.

[0104] In the sequential circuit 10 shown in FIG. 9, the circuit 11 includes transistors 444 to It has 452.

[0105] A shift register can be configured by connecting a plurality of stages of the sequential circuit 10.

[0106] The gate of transistor 444 is connected to the gates of transistors 445 and 101. One of the source and drain of the transistor is connected to the wiring 111, and the other of the source and drain of the transistor is connected to the wiring 111. The other drain is connected to one of the source and drain of the transistor 452. The transistor 445 has one of its source and drain connected to the wiring 111. The other of the source and drain is connected to a wiring 119. One of the source and drain is connected to the wiring 112, and the other of the source and drain is connected to the wiring 1 It is connected to 20.

[0107] The transistor 446 has a gate connected to the wiring 117 and a source and a drain connected to the wiring 117. One of the inputs is connected to the wiring 110, and the other of the source and drain is connected to the transistor 45 The gate of transistor 447 is connected to one of the source and drain of transistor 2. The source and drain of the transistor are connected to the wiring 114, and one of the source and drain of the transistor is connected to the wiring 110. The other of the source and drain is a transistor 444, a transistor 445, and a transistor The gate of the transistor 448 is connected to the wiring 118. One of the source and drain is connected to the wiring 110, and the other of the source and drain is connected to the wiring 110. The other of the two inputs is connected to the gates of the transistors 444, 445, and 101. The transistor 449 has its gate connected to the wiring 117 and its source connected to the One of the source and drain is connected to the wiring 111, and the other of the source and drain is connected to the transistor. The transistors 444, 445, and 101 are connected to the gates of the transistors 444, 445, and 101. The transistor 450 has a gate connected to the wiring 110 and a source and a drain One of the inputs is connected to one of the source and drain of the transistor 452, and the other is connected to the The transistor 451 has its source and drain connected to the gate of the transistor 451. One of the inputs is connected to the wiring 113, and the other of the source and drain is connected to the wiring 119. The transistor 452 has its gate connected to the wiring 110 and its source and The other of the drains is connected to the gate of the transistor 102. One of the source and drain of each of the transistors is connected to the wiring 116, and the other of the source and drain of each of the transistors is connected to the wiring 116. The other end is connected to the wiring 120.

[0108] In the sequential circuit 10 shown in FIG. 9, all the transistors are n-channel type. Specifically, in FIG. 9, a power supply potential VDD is supplied to the wiring 110, and a power supply potential VDD is supplied to the wiring 111. A case where a power supply potential VSS is supplied and a power supply potential VEE is supplied to the wiring 112 will be illustrated. There are.

[0109] The sequential circuit 10 shown in FIG. 9 is a circuit including a gate, a source and a drain of a transistor 101 on the output side. Therefore, the transistor 101 can be electrically isolated from one of the two terminals. As a result, a current flows to one of the source and drain of the transistor 101. Even if the potential of the wiring 112 for supplying a potential rises, the transistor 101 is turned off. In addition, the source and drain of the transistor 102 can be turned off when necessary. A potential VEE of the clock signal CLKB, which is higher than the power supply potential VSS, is supplied to one of the inputs. Therefore, the gate voltage of the transistor 102 can be made lower than the threshold voltage Vth. Therefore, even if the transistor 102 is normally on, the transistor 102 can be turned off when it should be turned off.

[0110] <Configuration Example of Semiconductor Display Device> Next, a structural example of a semiconductor display device according to one embodiment of the present invention will be described.

[0111] In the semiconductor display device 70 shown in FIG. 10A, a pixel section 71 includes a plurality of pixels 55 and a pixel 5 for each row, corresponding to the bus lines GL1 to GLy (y is a natural number). A wiring GL indicated by a number (number) and a wiring SL for supplying an image signal to a selected pixel 55 1 to SLx (x is a natural number) are provided. The input of the signal is controlled by the driving circuit 72. The input of the image signal to the wiring SL is The pixel 55 is controlled by a driving circuit 73. Each of the wirings SL is connected to at least one of the wirings SL.

[0112] Specifically, the driving circuit 72 generates signals for sequentially selecting the wirings GL1 to GLy. Specifically, the driver circuit 73 has a shift register 75 which sequentially outputs a pulse. A shift register 76 generates a signal corresponding to the shift register 76. and a switch circuit 77 for controlling the supply of image signals to the wirings SL1 to SLx. .

[0113] The sequential circuit according to one embodiment of the present invention includes one of the shift register 75 and the shift register 76, Or it can be used for both.

[0114] The type and number of wirings provided in the pixel section 71 depend on the configuration, number and arrangement of the pixels 55. Specifically, in the case of the pixel section 71 shown in FIG. The pixels 55 in the row are arranged in a matrix, and the wirings SL1 to SLx and the wiring GL1 10 shows an example in which the wirings GLy are arranged inside the pixel portion 71.

[0115] In FIG. 10A, the driver circuit 72 and the driver circuit 73 are formed on a single substrate together with the pixel portion 71. The driving circuit 72 and the driving circuit 73 are formed on a substrate. It may be formed on a substrate different from that of 71 .

[0116] 10B shows an example of the configuration of a pixel 55. Each pixel 55 includes a liquid crystal element 60 a transistor 56 for controlling the supply of an image signal to the liquid crystal element 60; The liquid crystal element 60 has a capacitance element 57 for holding a voltage between the pixel electrode and the common electrode. The liquid crystal display includes a pixel electrode, a common electrode, and a liquid crystal material to which a voltage is applied between the pixel electrode and the common electrode. and a liquid crystal layer.

[0117] The transistor 56 controls whether or not the potential of the wiring SL is applied to the pixel electrode of the liquid crystal element 60. A predetermined potential is applied to the common electrode of the liquid crystal element 60.

[0118] The specific connection configuration between the transistor 56 and the liquid crystal element 60 will be described below. In B), the gate of the transistor 56 is connected to one of the wirings GL1 to GLy. One of the source and drain of the transistor 56 is connected to the wiring SL1. Lx, and the other of the source and drain of the transistor 56 is connected to the liquid crystal It is connected to the pixel electrode of the element 60 .

[0119] In the liquid crystal element 60, the voltage applied between the pixel electrode and the common electrode changes depending on the voltage contained in the liquid crystal layer. The orientation of the liquid crystal molecules contained in the liquid crystal element 60 changes, and the transmittance changes. The transmittance of the pixel is controlled by the potential of the image signal applied to the pixel, thereby displaying gray scales. In each of the pixels 55 in the pixel section 71, a liquid crystal element The gray scale of the pixel 60 is adjusted in accordance with an image signal having image information, so that an image is displayed on the pixel section 71. is displayed.

[0120] In FIG. 10B, a switch for controlling the input of an image signal to the pixel 55 is However, the case where one transistor 56 is used as a switch is illustrated. A number of transistors functioning in the same manner may be used in pixel 55.

[0121] In one embodiment of the present invention, a transistor 56 having an extremely low off-state current is used as a It is preferable to use the transistor 56 as a switch to control the input to the A small value prevents charge from leaking through transistor 56. The potential of the image signal applied to the liquid crystal element 60 and the capacitance element 57 can be more reliably held. Therefore, the transmittance of the liquid crystal element 60 changes due to leakage of electric charges within one frame period. This prevents the display of images from being blurred, thereby improving the quality of the images displayed. When the off-current of the transistor 56 is small, the charge leakage through the transistor 56 is prevented. Therefore, during the period when a still image is displayed, the driving circuits 72 and 73 With the above configuration, the supply of the image signal to the pixel section 71 may be stopped. This reduces the number of times the signal is written, thereby reducing the power consumption of the semiconductor display device.

[0122] For example, a transistor including an oxide semiconductor in a semiconductor film can significantly reduce its off-state current. Therefore, it is suitable to use this as the transistor 56.

[0123] In FIG. 10B, the transistor 56 is a single transistor that overlaps with a semiconductor film sandwiched therebetween. The semiconductor device may have a pair of gate electrodes, the pair of gate electrodes being electrically connected to each other. In one embodiment of the present invention, the above structure increases the on-state current of the transistor 56. In addition, the reliability of the transistor 56 can be improved.

[0124] Next, FIG. 10C shows another example of the pixel 55. The pixel 55 has an image signal a transistor 95 for controlling the input of a signal; a light-emitting element 98; A transistor 96 controls the current value supplied to the image sensor 8, and a capacitor 97 holds the potential of the image signal. and a capacitance element 97.

[0125] The light emitting element 98 is a light emitting diode (LED) or an organic light emitting diode (OLED). current or voltage, such as a photovoltaic (Pb) or photovoltaic (Pb) light emitting diode (Pb) The category includes devices whose luminance is controlled by the light emitting diode (ELD) layer. For example, an OLED includes an EL layer and The device has at least an anode and a cathode. The EL layer is provided between the anode and the cathode. The layer is made up of a single layer or multiple layers, each of which contains a luminescent material. It includes at least a light emitting layer.

[0126] In addition, the EL layer is turned on when the potential difference between the cathode and the anode becomes equal to or exceeds the threshold voltage of the light emitting element 98. When the current is applied, electroluminescence is obtained. There are two types of emission: fluorescence when returning from the singlet excited state to the ground state and fluorescence when returning from the triplet excited state. This includes light emission (phosphorescence) when the compound returns to the ground state.

[0127] Either the anode or the cathode of the light emitting element 98 is connected to an image signal input to the pixel 55. Therefore, the potential is controlled. The potential of the anode and the cathode is controlled according to the image signal. The electrode to be controlled is a pixel electrode, and the other electrode is a common electrode. A predetermined potential is applied to the electrode, and the brightness of the light-emitting element 98 is determined by the potential between the pixel electrode and the common electrode. Therefore, the luminance of the light emitting element 98 is determined by the potential difference between the pixel electrodes. By controlling the pixel area, it is possible to display gradations. In each of the above-mentioned embodiments, the gradation of the light-emitting element 98 is adjusted according to an image signal having image information. As a result, an image is displayed on the pixel section 71 .

[0128] Next, the transistor 95, the transistor 96, the capacitor element 97, the light emitting element 98, and the like included in the pixel 55 are The connection configuration of the element 98 will now be described.

[0129] The transistor 95 has one of a source and a drain connected to the wiring SL. The other input is connected to the gate of transistor 96. The gate of transistor 95 is , and is connected to the wiring GL. VL, and the other of the source and drain is connected to the light emitting element 98. The other of the source and drain of the transistor 96 is connected to the anode and cathode of the light emitting element 98. The light emitting element 98 is connected to either the anode or the cathode. A predetermined potential is applied to the

[0130] In FIG. 10C, a transistor 96 is a pair of gates overlapping each other with a semiconductor film sandwiched therebetween. The pair of gate electrodes may be electrically connected to each other. In one embodiment, the above-described structure increases the on-state current of the transistor 96. This can improve the reliability of Transistor 96.

[0131] Pixel Structure Next, a liquid crystal display device, which is one of the semiconductor display devices 70 shown in FIG. 10(A), will be taken as an example. Next, a configuration example of the pixel 55 will be described. FIG. 11 shows a top view of the pixel 55 as an example. In FIG. 11, various insulating films are omitted in order to clarify the layout of the pixel 55. A liquid crystal display device formed using an element substrate having pixels 55 shown in FIG. A cross-sectional view of the liquid crystal display device shown in FIG. corresponds to a cross-sectional view taken along dashed line B1-B2 in FIG.

[0132] A pixel 55 shown in FIGS. 11 and 12 includes a transistor 56 and a capacitor 57. Furthermore, the pixel 55 shown in FIG.

[0133] The transistor 56 is provided on the substrate 31 having an insulating surface, and has a function as a gate electrode. A conductive film 40 and an insulating film located on the conductive film 40, which has a function as a gate insulating film. a conductive film 40 formed on the insulating film 22; an oxide semiconductor film 41 overlapping the conductive film 40 on the insulating film 22; A conductive electrode electrically connected to the body membrane 41 and functioning as a source electrode or a drain electrode. The conductive film 40 includes a film 43 and a conductive film 44. The conductive film 40 serves as the wiring GL shown in FIG. The conductive film 43 also functions as the wiring SL shown in FIG. .

[0134] The pixel 55 also has a metal oxide film 42 on the insulating film 22. The metal oxide film 42 is The metal oxide film 42 is a conductive film that is transparent to visible light. A conductive film 61 is provided which is electrically connected to the metal film 42. The conductive film 61 is a metal oxide It functions as a wiring that supplies a predetermined potential to the film 42 .

[0135] The insulating film 22 may be made of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, Silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide One or more of: lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide The insulating film containing the acid may be used as a single layer or a laminated layer. A nitride is a material whose composition contains more oxygen than nitrogen, while a nitride oxide is a material whose composition contains more oxygen than nitrogen. It refers to a material whose composition contains more nitrogen than oxygen.

[0136] 12, the oxide semiconductor film 41, the conductive film 43, and the conductive film 44, and the metal oxide film An insulating film 26 and an insulating film 27 are provided on the insulating film 42 and the conductive film 61 in this order. The transistor 56 may include the insulating film 26 and the insulating film 27 as components. In addition, in FIG. 12, the insulating film 26 and the insulating film 27 are illustrated as being laminated in this order. Instead of the insulating film 26 and the insulating film 27, a single-layer insulating film may be used. Insulating films having three or more layers may be used.

[0137] The insulating film 26 and the insulating film 27 have an opening 58 at a position where they overlap with the metal oxide film 42. The opening 58 is formed in a region different from the oxide semiconductor film 41, the conductive film 43, and the conductive film 44. and is provided in a region overlapping with the metal oxide film 42.

[0138] 12, the metal oxide film 4 on the insulating film 26 and the insulating film 27 and in the opening 58 On the upper surface of the insulating film 2, a nitride insulating film 28 and an insulating film 29 are provided in this order.

[0139] Note that an oxide semiconductor film is formed on the insulating film 22, and a nitride By forming the insulating film 28, the electrical conductivity of the oxide semiconductor film can be increased. As a result, the oxide semiconductor film with increased conductivity can be used as the metal oxide film 42. The conductivity of the oxide semiconductor film increases when the opening 58 is formed or when the nitride insulating film 2 During the formation of the nitride insulating film 28, oxygen vacancies are formed in the oxide semiconductor film, and the oxygen diffuses from the nitride insulating film 28. This is thought to be because the hydrogen atom that is released binds to the oxygen vacancy to generate a donor. The resistivity of the metal oxide film 42 is typically 1×10 -3 Ωcm or more 1×10 4 Ωcm More preferably, the resistivity is less than 1×10 -3 Ωcm or more 1×10 -1 Less than Ωcm It would be good to do so.

[0140] The metal oxide film 42 preferably has a higher hydrogen concentration than the oxide semiconductor film 41. In the film 42, secondary ion mass spectrometry (SIMS) was used. The hydrogen concentration obtained by assemblage spectrometry was 8×10 19 atom s / cm 3 More than 1×10 20 atoms / cm 3More preferably, 5x 10 20 atoms / cm 3 The above is the case. In the oxide semiconductor film 41, the secondary ion mass The hydrogen concentration obtained by the analytical method is 5×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 below, More preferably, 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 a toms / cm 3 The following is the result.

[0141] The nitride insulating film 28 may be, for example, silicon nitride, silicon oxynitride, or aluminum nitride. The nitride insulating film using the above-mentioned material may be aluminum oxide nitride. 28 is less susceptible to external impurities than oxide insulating films such as silicon oxide and aluminum oxide. Substances such as water, alkali metals, and alkaline earth metals diffuse into the oxide semiconductor film 41. This can prevent the following:

[0142] In addition, an opening 62 is provided in the nitride insulating film 28 and the insulating film 29 at a position where the conductive film 44 overlaps. A transparent insulating film that is transparent to visible light is formed on the nitride insulating film 28 and the insulating film 29. The conductive film 45 has an opening and functions as a pixel electrode. At the opening 62, the conductive film 45 is electrically connected to the conductive film 44. At 58, the conductive film 45 overlaps with the metal oxide film 42. The overlapping portion sandwiching the oxide insulating film 28 and the insulating film 29 functions as a capacitance element 57. .

[0143] The capacitor 57 includes a metal oxide film 42 and a conductive film 45 which function as a pair of electrodes, and a dielectric The nitride insulating film 28 and the insulating film 29 functioning as a film are transparent to visible light. Therefore, the capacitor 57 is transparent to visible light, and the capacitance of the capacitor The aperture ratio of the pixel 55 can be increased compared to pixels having low translucency to visible light. This allows the capacitance required to obtain high image quality to be secured while minimizing light loss within the panel. Therefore, the power consumption of the semiconductor device can be reduced.

[0144] As described above, the insulating film 29 is not necessarily provided, but it is preferable to provide the insulating film 29 more than the nitride insulating film 28. The insulating film 29 using an insulating material having a lower relative dielectric constant than the nitride insulating film 28 is used as a dielectric film together with the nitride insulating film 28. By using the nitride insulating film 28, the dielectric constant of the dielectric film of the capacitance element 57 is increased. It is possible to adjust the value to a desired value without any need for adjustment.

[0145] On the conductive film 45, an alignment film 52 is provided.

[0146] A substrate 46 is provided so as to face the substrate 31. and a colored layer 48 that transmits visible light in a specific wavelength range. A resin film 50 is provided on the shielding film 47 and the colored layer 48. A conductive film 59 having a function as a common electrode is provided on the film 50. An alignment film 51 is provided on 59 .

[0147] Between the substrate 31 and the substrate 46, a liquid crystal layer is disposed so as to be sandwiched between the alignment film 52 and the alignment film 51. The liquid crystal element 60 includes a conductive film 45, a conductive film 59, and a liquid crystal layer 53 including a conductive film 59. and a liquid crystal layer 53 .

[0148] In addition, in FIG. 11 and FIG. 12, a TN (Twisted Nemat) liquid crystal driving method is used. The liquid crystal driving method is also called FFS (Fringe flip-flop) mode. e Field Switching) mode, STN (Super Twisted Nematic mode, VA (Vertical Alignment) mode, MV A (Multi-domain Vertical Alignment) mode, IP S (In-Plane Switching) mode, OCB (Optically C ompensated birefringence mode, blue phase mode, TBA (Transverse Bend Alignment) mode, VA-IPS mode ,ECB(Electrically Controlled Birefringen) ce) mode, FLC (Ferroelectric Liquid Crystal) Mode, AFLC (AntiFerroelectric Liquid Crysta) l) mode, PDLC (Polymer Dispersed Liquid Crystal tal) mode, PNLC (Polymer Network Liquid Crys tal) mode, guest host mode, ASV (Advanced Super Vie It is also possible to apply modes such as w).

[0149] In the liquid crystal display device according to one embodiment of the present invention, the liquid crystal layer may include, for example, a thermotropic Liquid crystal materials classified as lyotropic or lyotropic liquid crystals can be used. The liquid crystal layer may be, for example, a nematic liquid crystal, a smectic liquid crystal, a cholesteric liquid crystal, or A liquid crystal material classified as a discotic liquid crystal can be used for the liquid crystal layer. For example, liquid crystal materials classified as ferroelectric liquid crystal or antiferroelectric liquid crystal can be used. Alternatively, the liquid crystal layer may be made of, for example, a main chain type polymer liquid crystal, a side chain type polymer liquid crystal, or By using liquid crystal materials classified as polymer liquid crystals such as composite polymer liquid crystals or low molecular weight liquid crystals, Alternatively, the liquid crystal layer may be, for example, a polymer dispersed liquid crystal (PDLC). A liquid crystal material may be used.

[0150] In addition, a liquid crystal exhibiting a blue phase without using an alignment film may be used in the liquid crystal layer. When the temperature of a cholesteric liquid crystal is increased, the cholesteric phase changes to the isotropic phase. The blue phase appears only in a narrow temperature range, so The temperature range is improved by adding chiral agents and UV-curable resins. The liquid crystal composition containing the above has a short response time of 1 msec or less and is optically isotropic, so that alignment is possible. This is preferable because no processing is required and the viewing angle dependency is small.

[0151] FIG. 12 shows a liquid crystal display device that uses color filters to display color images. However, the liquid crystal display device according to one embodiment of the present invention has multiple display devices that emit light of different hues. The light sources may be sequentially turned on to display a color image.

[0152] Note that the oxide semiconductor film 41 of the transistor 56 is formed of a single oxide semiconductor film. The insulating film 13 may be formed of a plurality of stacked oxide semiconductor films. Now, let us consider a case where the oxide semiconductor film 41 is composed of three stacked oxide semiconductor films. Specifically, in a transistor 56 illustrated in FIG. 41, oxide semiconductor films 41a to 41c are arranged in this order from the insulating film 22 side. It is layered.

[0153] The oxide semiconductor film 41a and the oxide semiconductor film 41c constitute the oxide semiconductor film 41b. The element contains at least one metal element that forms an oxide. The energy of the conduction band minimum is The difference is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.05 eV or more, more preferably 0.07 eV or more, more preferably 0.1 eV or more, more preferably ... .15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, true The oxide semiconductor film 41b is an oxide film close to a vacant level. It is preferable for the compound to contain the compound to have a high carrier mobility.

[0154] Note that the oxide semiconductor film 41c is formed by arranging the conductive film 43 and the conductive film 44 as shown in FIG. It may be configured so as to overlap the insulating film 22 at the upper layer.

[0155] <Top view and cross-sectional view of semiconductor display device> Next, the appearance of a semiconductor display device according to one embodiment of the present invention will be described using a liquid crystal display device as an example. This will be described with reference to FIG. 14. FIG. 14 shows a substrate 4001 and a substrate 4006 sealed with a sealing material 40. 15 is a top view of the liquid crystal display device bonded by the method of bonding the liquid crystal display device 105 shown in FIG. This corresponds to the cross-sectional view taken along line 1-C2.

[0156] A pixel portion 4002 and a pair of driver circuits 4004 are provided on a substrate 4001. A sealing material 4005 is provided on the pixel portion 4002 and the driver circuit 4004. Therefore, the pixel portion 4002 and the driver circuit 4004 are connected to a substrate 4006. It is sealed by 4001 , a sealing material 4005 and a substrate 4006 .

[0157] In addition, the driving force is applied to an area other than the area surrounded by the sealing material 4005 on the substrate 4001. An operating circuit 4003 is implemented.

[0158] In addition, a pixel portion 4002 and a driver circuit 4004 provided on a substrate 4001 are made of transistors. In FIG. 15, a transistor 4010 included in a pixel portion 4002 is illustrated. The transistor 4010 is provided with an insulating film including various insulating films including an oxide insulating film. An insulating film 4020 and an insulating layer 4022 made of various insulating films including a nitride insulating film are provided. The transistor 4010 has an opening provided in the insulating film 4020 and the insulating layer 4022. 4022 , it is connected to a pixel electrode 4021 on an insulating film 4022 .

[0159] In addition, a resin film 4059 is provided on the substrate 4006, and a common An electrode 4060 is provided. A pixel electrode is provided between the substrate 4001 and the substrate 4006. A liquid crystal layer 4028 is provided so as to be sandwiched between the electrode 4021 and the common electrode 4060. The liquid crystal element 4023 includes a pixel electrode 4021, a common electrode 4060, and a liquid crystal layer 4028. do.

[0160] In the liquid crystal element 4023, the value of the voltage applied between the pixel electrode 4021 and the common electrode 4060 Accordingly, the orientation of the liquid crystal molecules contained in the liquid crystal layer 4028 changes, and the transmittance changes. The liquid crystal element 4023 changes its pixel voltage in response to the potential of the image signal applied to the pixel electrode 4021. By controlling the transmittance, it is possible to display gradations.

[0161] As shown in FIG. 15, in one embodiment of the present invention, the insulating film 4020 and the insulating layer 4022 are The insulating layer 4020 and the insulating layer 4022 are removed at the edge of the panel. In the removed region, a conductive film 4050 is formed. The conductive film functioning as the source or drain of the transistor 4010 is a conductive film formed by etching. It can be formed by etching.

[0162] Conductive particles 4061 having conductivity are dispersed between the substrate 4001 and the substrate 4006. The conductive film 4050 is provided with a resin film 4062 dispersed therein. That is, the common electrode 4060 and the conductive particles 4061 are electrically connected to each other. The film 4050 is electrically connected to the panel at the edge via conductive particles 4061. The resin film 4062 is made of a thermosetting resin or an ultraviolet-curing resin. The conductive particles 4061 can be made of, for example, spherical organic resin with Au, Ni, Co, etc. Particles coated with a thin film of metal such as those mentioned above can be used.

[0163] Although the alignment film is not shown in FIG. 15, the alignment film is formed on the pixel electrode 4021 and the common electrode 4 When the conductive film 4050 is provided on the common electrode 4060, the conductive particles 4061, and the conductive film 4050 are In order to electrically connect the common electrode 4060 and the alignment film, a part of the alignment film is removed from the area where the alignment film overlaps the common electrode 4060. In this case, the alignment film may be partially removed from a portion overlapping with the conductive film 4050 .

[0164] In the liquid crystal display device according to one embodiment of the present invention, a color filter is used to display a color image. An image may be displayed, or multiple light sources emitting light of different hues may be sequentially turned on. A color image may be displayed.

[0165] In addition, image signals from the driver circuit 4003 and various control signals and potentials from the FPC 4018 are 4004 or the pixel section 400 2 is given.

[0166] Semiconductor Films Impurities such as moisture or hydrogen, which act as electron donors, are reduced, and oxygen deficiencies are eliminated. The reduced amount of the oxide semiconductor is used to produce a highly purified oxide semiconductor. Since there are few carrier sources, i-type (intrinsic semiconductor) Therefore, the thickness of the oxide semiconductor film can be made as close to i-type as possible. A transistor having a channel formation region has a significantly small off-state current and is highly reliable. In addition, the threshold voltage of a transistor in which a channel formation region is formed in the oxide semiconductor film is This tends to result in poor electrical characteristics (also called normally-off characteristics).

[0167] Specifically, the present invention relates to an on-state transistor having a channel formation region in a highly purified oxide semiconductor film. The small fringe current can be proven by various experiments. For example, 0 6 Even with a device with a channel length of 10 μm, the voltage between the source and drain electrodes is In the drain voltage range of 1V to 10V, the off-state current was measured by the semiconductor parameter analyzer. Below the riser measurement limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less. In this case, the off-state current normalized by the transistor channel width is 100zA / μm or less. In addition, by connecting the capacitance element and the transistor, The off-state current is measured using a circuit that controls the charge flowing out of the capacitor with the transistor. In the measurement, a highly purified oxide semiconductor film was used as a channel of the transistor. The on / off state of the transistor is determined based on the change in the charge amount per unit time of the capacitance element. The current was measured. As a result, the voltage between the source and drain electrodes of the transistor was 3V. It was found that an even smaller off-current of several tens of yA / μm can be obtained in the case of In addition, a transistor in which a highly purified oxide semiconductor film is used for a channel formation region has an off-state current The current is significantly smaller than that of a transistor using crystalline silicon.

[0168] In the case where an oxide semiconductor film is used as the semiconductor film, the oxide semiconductor film should be at least It is preferable that the oxide semiconductor contains indium (In) or zinc (Zn). As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to these, it is preferable to have gallium (Ga). It is preferable to use hafnium (Hf) as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). It is also preferable that zirconium (Zr) is contained as a stabilizer.

[0169] Among oxide semiconductors, In-Ga-Zn oxides and In-Sn-Zn oxides are carbon Unlike silicon nitride, gallium nitride, or gallium oxide, sputtering and wet deposition methods This makes it possible to create transistors with excellent electrical characteristics, and is also suitable for mass production. Also, unlike silicon carbide, gallium nitride, or gallium oxide, The In-Ga-Zn oxide is used to form a transistor having excellent electrical characteristics on a glass substrate. It is also possible to manufacture larger substrates.

[0170] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru It may contain one or more of the elements tetraethium (Lu).

[0171] For example, oxide semiconductors include indium oxide, gallium oxide, tin oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, S n-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, I n-Hf-Zn oxide, In-La-Zn oxide, In-Pr-Zn oxide, In -Nd-Zn oxide, In-Ce-Zn oxide, In-Sm-Zn oxide, In- Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D Y-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm -Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn based oxides can be used.

[0172] For example, In-Ga-Zn oxide means an oxide containing In, Ga, and Zn. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn In-Ga-Zn oxides have a sufficiently high resistance when no electric field is present, and therefore, The flow can be made sufficiently small and the mobility is also high.

[0173] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0174] The structure of the oxide semiconductor film will be described below.

[0175] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The single crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. These include semiconductor films and CAAC-OS films.

[0176] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline component. The film is a compound semiconductor film. It does not have any crystalline parts even in a microscopic area, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0177] The microcrystalline oxide semiconductor film is, for example, a microcrystal having a size of 1 nm or more and less than 10 nm (nanocrystal). Therefore, the microcrystalline oxide semiconductor film has a lower atomic number than the amorphous oxide semiconductor film. Therefore, the microcrystalline oxide semiconductor film has a higher molecular weight than the amorphous oxide semiconductor film. Also, the defect level density is low.

[0178] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. The crystals contained in the S film are in the form of cubes with sides of less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller defect density than a microcrystalline oxide semiconductor film. The CAAC-OS film is characterized by a low density of recessed states. Observe using a transmission electron microscope. A clear boundary between the crystals, i.e., the grain boundary, was confirmed. Therefore, the CAAC-OS film has a low electron mobility due to the grain boundaries. It can be said that a decline is unlikely to occur.

[0179] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0180] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle between 80° and 100°. This includes cases where the angle is between 85° and 95°.

[0181] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0182] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0183] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, InGaZnO 4 CAAC-OS film with crystals In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal of This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0184] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is , InGaZnO 4 It is attributed to the (110) plane of the InGaZnO crystal. 4 Single crystal oxidation of In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0185] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the crystal is formed or the upper surface. Therefore, the layered arrangement confirmed by the cross-sectional TEM observation mentioned above is consistent with the above. Each layer of aligned metal atoms is a plane parallel to the ab plane of the crystal.

[0186] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it may not be parallel to the normal vector of the upper surface.

[0187] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0188] In addition, InGaZnO 4Out-of-plane synthesis of CAAC-OS films with crystallites In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0189] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0190] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0191] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0192] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the processing chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0193] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When plate- or pellet-shaped sputtered particles reach the substrate, they migrate on the substrate. Sputtering occurs and the flat surface of the sputtered particle adheres to the substrate.

[0194] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0195] As an example of the target, an In-Ga-Zn oxide target will be described below.

[0196] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. By heat treatment at a temperature between 1000 and 1500℃, polycrystalline In-Ga The target is a Zn-based oxide target. X, Y, and Z are any positive numbers. The molar ratio of the constant is, for example, InO X powder, GaO Y Powder and ZnO Z Powder is 2:2: 1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powders can be changed depending on the target to be produced. Good.

[0197] Note that alkali metals are not elements that constitute an oxide semiconductor and are therefore considered impurities. In particular, lithium-earth metals are impurities when they are not elements constituting an oxide semiconductor. Among the alkali metals, Na is preferable when the insulating film in contact with the oxide semiconductor film is an oxide. Diffusion into the insulating film + In addition, Na is an element that is contained in the oxide semiconductor film. It breaks the bond between the metal and oxygen that make up the conductor, or interrupts that bond. As a result, For example, the threshold voltage shifts in the negative direction, resulting in a normally-on state and a decrease in mobility. This causes degradation of the electrical characteristics of the transistors, such as deterioration of the electrical characteristics of the transistors, and also causes variations in the characteristics. Specifically, the measured Na concentration by secondary ion mass spectrometry was 5×10 16 / cm 3 below , preferably 1 x 10 16 / cm 3 More preferably, 1×10 15 / cm 3 The following Similarly, the measured Li concentration is 5×10 15 / cm 3 Below, preferably 1×1 0 15 / cm 3 Similarly, the measured value of K concentration should be 5×10 15 / cm 3 Below Lower, preferably 1 x 10 15 / cm 3 The following should be used.

[0198] In addition, when a metal oxide containing indium is used, the bond energy with oxygen is Silicon and carbon, which are larger than indium, break the bond between indium and oxygen, creating an oxygen vacancy. Therefore, when silicon or carbon is mixed into the oxide semiconductor film, As with alkali and alkaline earth metals, degradation of the electrical characteristics of transistors occurs. Therefore, it is preferable that the concentrations of silicon and carbon in the oxide semiconductor film be low. Specifically, the measured values ​​of C concentration or Si concentration by secondary ion mass spectrometry is 1 x 10 18 / cm 3 With the above configuration, the electrical characteristics of the transistor are preferably as follows. This makes it possible to prevent deterioration of the electrical conductivity of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0199] In addition, depending on the conductive material used for the source electrode and the drain electrode, The metal in the drain electrode may extract oxygen from the oxide semiconductor film. The region of the nitride semiconductor film that is in contact with the source electrode and the drain electrode is depleted due to the formation of oxygen vacancies. It is made n-type.

[0200] The n-type region functions as a source region or a drain region, so the oxide semiconductor The contact resistance between the film and the source and drain electrodes can be reduced. Therefore, the formation of an n-type region increases the mobility and on-current of the transistor. This makes it possible to realize high-speed operation of a semiconductor device using transistors. This can be done.

[0201] The extraction of oxygen by the metal in the source and drain electrodes This can occur when forming the drain electrode by sputtering or the like, and can occur when forming the source electrode and drain electrode. This can also occur due to a heat treatment carried out after the formation of the rain electrode.

[0202] In addition, the region to be made n-type is made of a conductive material that easily bonds with oxygen as the source electrode and the drain electrode. The conductive material is, for example, Al, C. Examples of these include R, Cu, Ta, Ti, Mo, and W.

[0203] In addition, the oxide semiconductor film is not limited to being composed of a single metal oxide film, but may be composed of a stack of metal oxide films. It may be composed of a plurality of metal oxide films. For example, the first to third metal oxide films are formed in order. In the case of a semiconductor film stacked in a layered manner, the first metal oxide film and the third metal oxide film are The metal oxide film has at least one metal element as a component thereof, and has a conduction band below The edge energy is 0.05 eV or more, 0.07 eV or more, 0. 1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less The second metal oxide film is an oxide film with a potential of 0.4 eV or less, close to the vacuum level. It is preferable that at least indium is contained since the carrier mobility is increased.

[0204] When a transistor has a semiconductor film having the above structure, a voltage is applied to a gate electrode. When an electric field is applied to the semiconductor film, the second gold layer in the semiconductor film, which has a lower energy at the bottom of the conduction band, A channel region is formed in the second metal oxide film. The third metal oxide film is provided between the first and second gate insulating films. A channel region can be formed in the metal oxide film of 2.

[0205] The third metal oxide film contains at least one of the metal elements constituting the second metal oxide film. Since the second metal oxide film and the third metal oxide film contain Therefore, the movement of carriers is not easily hindered at the interface. The field effect mobility of the transistor is increased.

[0206] In addition, when an interface state is formed at the interface between the second metal oxide film and the first metal oxide film, Since a channel region is also formed in the neighboring region, the threshold voltage of the transistor changes. However, the first metal oxide film contains at least one of the metal elements constituting the second metal oxide film. Since both of them contain one of these elements, they are formed at the interface between the second metal oxide film and the first metal oxide film. Therefore, the above-mentioned configuration reduces the threshold voltage of the transistor and the like. The variation in electrical characteristics can be reduced.

[0207] In addition, the presence of impurities between the metal oxide films causes carrier flow at the interface between the films. To prevent the formation of interfering interface states, multiple metal oxide films can be stacked. If impurities exist between the laminated metal oxide films, the metal oxide films may be formed. The continuity of the energy at the bottom of the conduction band at the interface is lost, and carriers are trapped near the interface. The impurities between the films are reduced or disappear due to recombination. By reducing the amount of the metal oxide film, a plurality of metal oxide films each having at least one metal as a main component can be obtained. Rather than simply stacking layers, continuous junctions (where the energy at the bottom of the conduction band is continuous between each film) are used. In this case, the formation of a U-shaped well structure that changes continuously is likely to occur.

[0208] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (Sputtering equipment) is used to continuously stack each film without exposing it to the air. Each chamber in the sputtering equipment must be free of impurities for oxide semiconductors. In order to remove as much water as possible, a vacuum pump of the adsorption type like a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to set the temperature to about 10 Pa. Alternatively, a turbomolecular pump and cold trap can be combined to vent the gas from the exhaust system to the chamber. It is preferable to prevent gas from flowing back into the tank.

[0209] In order to obtain a high-purity intrinsic oxide semiconductor, it is not enough to evacuate each chamber to a high vacuum. In addition, it is also important to increase the purity of the gas used in sputtering. The dew point of gas or argon gas is -40°C or less, preferably -80°C or less, more preferably - By keeping the temperature at 100°C or less and using highly purified gas, moisture and other substances are prevented from being absorbed into the oxide semiconductor film. Specifically, the second metal oxide film is In- In the case of M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), the second metal In the target used for depositing the oxide film, the atomic ratio of metal elements is In:M: Zn=x 1 :y 1 :z 1 So, 、 x 1 / y 1 is between 1 / 3 and 6, and between 1 and 6 z 1 / y 1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. It is preferable to use 1 / y 1 By setting the value of the second metal oxide film to 1 or more and 6 or less, AC-OS film is easily formed. A typical example of the atomic ratio of the metal elements in the target is , In:M:Zn=1:1:1, In:M:Zn=3:1:2, etc.

[0210] Specifically, the first metal oxide film and the third metal oxide film are In-M-Zn oxide (M is G a, Y, Zr, La, Ce, or Nd), the first metal oxide film, the third metal oxide film In the target used to deposit the metal film, the atomic ratio of metal elements is In:M:Zn =x 2 :y 2 :z 2So, 、 x 2 / y 2 <x 1 / y 1 Where z 2 / y 2 is 1 / 3 It is preferable that z is 1 or more and 6 or less, and more preferably 1 or more and 6 or less. 2 / y 2 1 to 6 By setting the following, the CAAC-OS film can be used as the first metal oxide film and the third metal oxide film. A typical example of the atomic ratio of the target metal elements is In:M:Z. n=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M :Zn=1:3:8 etc.

[0211] The thickness of the first metal oxide film and the third metal oxide film is 3 nm or more and 100 nm or less. The thickness of the second metal oxide film is preferably 3 nm or more and 50 nm or less. m is from 0.01 to 200 nm, preferably from 0.01 to 200 nm, more preferably from 0.01 to 200 nm, and even more preferably from 0.01 to 200 nm. Between 3nm and 50nm.

[0212] In the three-layered semiconductor film, the first metal oxide film, the second metal oxide film, and the third metal oxide film are amorphous or The second metal oxide on which the channel region is formed may be either amorphous or crystalline. The crystalline nature of the material film provides stable electrical characteristics to the transistor. Therefore, the second metal oxide film is preferably crystalline.

[0213] Note that the channel formation region is a region of the semiconductor film of a transistor that overlaps with a gate electrode. The channel region is the region sandwiched between the source electrode and the drain electrode. This refers to the region in the core formation region through which current mainly flows.

[0214] For example, the first metal oxide film and the third metal oxide film are formed by a sputtering method. When an In-Ga-Zn oxide film formed by the above method is used, the first metal oxide film and the third metal oxide film are The In-Ga-Zn oxide (In:Ga:Zn=1:3:2 [atomic number The film forming conditions are, for example, a film forming gas containing The gas was argon at 30 sccm and oxygen at 15 sccm, the pressure was 0.4 Pa, and the substrate temperature was The temperature is set to 200°C and the DC power is set to 0.5kW.

[0215] In addition, when the second metal oxide film is a CAAC-OS film, the second metal oxide film is formed by is an In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]), It is preferable to use a target containing a polycrystalline In-Ga-Zn oxide. For example, argon gas at 30 sccm and oxygen gas at 15 sccm are used as the deposition gas. The pressure was set to 0.4 Pa, the substrate temperature to 300° C., and the DC power to 0.5 kW. Cut.

[0216] Note that the transistor may have a structure in which the end portion of the semiconductor film is inclined. The end of the membrane may have a rounded structure.

[0217] In addition, when a semiconductor film having a plurality of stacked metal oxide films is used for a transistor, In the above structure, the regions in contact with the source electrode and the drain electrode may be n-type. The present invention provides a semiconductor device using a transistor, which has improved mobility and on-current. Furthermore, a semiconductor having a plurality of laminated metal oxide films can be used. When the conductive film is used in a transistor, the region to be made n-type is the second gold layer which becomes the channel region. The fact that the metal oxide film is reached increases the mobility and on-current of the transistor, and This is more preferable in terms of achieving higher speed operation of the device.

[0218] <Configuration Example of Electronic Device Using Semiconductor Device> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices with advanced functions (typically DVD: Digital Versatile Disc (Devices having a display capable of playing back recording media such as 3D models and displaying the images) In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used Mobile phones, handheld game consoles, personal digital assistants, e-books, video cameras, digital cameras, etc. Cameras such as TasStill cameras, goggle-type displays (head-mounted displays) ), navigation systems, audio playback devices (car audio, digital audio players) Years, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0219] FIG. 16A shows a portable game machine, which includes a housing 5001, a housing 5002, a display unit 5003, Display unit 5004, microphone 5005, speaker 5006, operation keys 5007, The display unit 5003 or the display unit 5004 and other integrated circuits A semiconductor device according to one embodiment of the present invention can be used for the semiconductor device shown in FIG. The portable game machine has two display units 5003 and 5004. The number of display units that the game machine has is not limited to this.

[0220] FIG. 16B shows a portable information terminal, which includes a first housing 5601, a second housing 5602, a first display unit, and a 5603, a second display unit 5604, a connection unit 5605, and operation keys 5606. The display unit 5603 is provided in the first housing 5601, and the second display unit 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other via a connection portion 5602. 5605, and the angle between the first housing 5601 and the second housing 5602 is The image on the first display unit 5603 can be changed by the connection unit 5 The structure is such that the switch is performed according to the angle between the first housing 5601 and the second housing 5602 at 605. The first display portion 5603 or the second display portion 5604 or other integrated circuits may be formed. In this case, the semiconductor device according to one embodiment of the present invention can be used.

[0221] FIG. 16C shows a notebook personal computer, which includes a housing 5401 and a display unit 5402. The display unit 5402 and the like include a keyboard 5403 and a pointing device 5404. The semiconductor device according to one embodiment of the present invention can be used for these and other integrated circuits.

[0222] FIG. 16D shows a wristwatch, which includes a housing 5201, a display unit 5202, an operation button 5203, and a button. The display portion 5202 and other integrated circuits according to one embodiment of the present invention may include a display unit 5202 and other integrated circuits. A semiconductor device having such a structure can be used.

[0223] FIG. 16E shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58. 03, operation keys 5804, a lens 5805, a connection part 5806, etc. 4 and a lens 5805 are provided in a first housing 5801, and a display unit 5803 is provided in a second housing. The first housing 5801 and the second housing 5802 are connected to each other via a connection portion. The first housing 5801 and the second housing 5802 are connected by a joint 5806. The video on the display unit 5803 can be changed by the video input unit 5806. , according to the angle between the first housing 5801 and the second housing 5802 at the connection portion 5806. The semiconductor device according to one embodiment of the present invention may be provided in the display portion 5803 or other integrated circuits. A body device can be used.

[0224] FIG. 16F shows a mobile phone. A housing 5901 includes a display unit 5902, a microphone 5907, and a speaker. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are provided. The semiconductor device according to one embodiment of the present invention is used for the display portion 5902 and other integrated circuits. In addition, the semiconductor device according to one embodiment of the present invention can be formed on a flexible substrate. In the case where the semiconductor device is formed in the display portion 5902 having a curved surface as shown in FIG. It is possible to apply the position. [Explanation of symbols]

[0225] 10 sequential circuits 10_j Sequential circuit 10_j-1 Sequential circuit 10_y sequential circuit 10_y-1 sequential circuit 10_1 Sequential circuit 10_4m sequential circuit 11 Circuit 12 Transistor 13. Transistor 14 Wiring 15 Wiring 16 Wiring 17 Wiring 18 Wiring 19 Wiring 20 Output terminal 22 Insulating film 26 Insulating Film 27 Insulating Film 28 Nitride insulating film 29 Insulating Film 31 Substrate 40 Conductive Film 41 Oxide Semiconductor Film 41a Oxide semiconductor film 41b Oxide semiconductor film 41c Oxide semiconductor film 42 Metal oxide film 43 Conductive Film 44 Conductive Film 45 Conductive Film 46 Substrate 47 Shielding membrane 48 Colored layer 50 Resin Film 51 Orientation film 52 Orientation film 53 Liquid crystal layer 55 pixels 56 Transistor 57 Capacitive element 58 Opening 59 Conductive Film 60 Liquid crystal element 61 Conductive Film 62 Opening 70 Semiconductor display device 71 Pixel section 72 Drive circuit 73 Drive circuit 75 Shift Register 76 Shift Register 77 Switch Circuit 95 Transistors 96 Transistors 97 Capacitive element 98 Light emitting element 101 Transistor 102 Transistor 110 Wiring 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 119 Wiring 120 Wiring 130 Transistor 131 Transistor 132 Transistor 133 Transistor 134 Transistor 135 Transistor 136 Transistor 137 Transistor 138 Transistor 139 Transistor 313 Transistor 314 Transistor 315 Transistor 316 Transistor 317 Transistor 318 Transistor 319 Transistor 344 Transistor 345 Transistor 346 Transistor 347 Transistor 348 Transistor 349 Transistor 350 Transistors 351 Transistor 374 Transistors 375 Transistors 376 Transistors 377 Transistors 378 Transistors 379 Transistor 380 Transistors 381 Transistor 414 Transistor 415 Transistor 416 Transistor 417 Transistor 418 Transistor 419 Transistor 420 Transistor 421 Transistor 422 Transistor 438 Wiring 444 Transistor 445 Transistor 446 Transistor 447 Transistor 448 Transistor 449 Transistor 450 Transistors 451 Transistor 452 Transistor 4001 Substrate 4002 Pixel section 4003 Drive circuit 4004 Drive circuit 4005 Encapsulating material 4006 Substrate 4010 Transistor 4018 FPC 4020 Insulating film 4021 Pixel electrode 4023 Liquid crystal element 4028 Liquid crystal layer 4030 Wiring 4050 Conductive film 4059 Resin film 4060 Common electrode 4061 Conductive particles 4062 Resin film 5001 Case 5002 Case 5003 Display section 5004 Display section 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5201 Case 5202 Display section 5203 Operation button 5204 Band 5401 Case 5402 Display section 5403 Keyboard 5404 Pointing Device 5601 Case 5602 Case 5603 Display section 5604 Display section 5605 Connection 5606 Operation key 5801 Case 5802 Case 5803 Display section 5804 Operation key 5805 Lens 5806 Connection 5901 Case 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

1. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; Display device.

2. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the second insulating film has a region in contact with an upper surface of the oxide semiconductor film, the second insulating film has a region in contact with an upper surface of the metal oxide film, the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; Display device.

3. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; the second conductive film does not overlap with the first region; Display device.

4. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the oxide semiconductor film overlaps with the second insulating film at a periphery of the oxide semiconductor film; the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; Display device.

5. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the second insulating film has a region in contact with an upper surface of the oxide semiconductor film, the second insulating film has a region in contact with an upper surface of the metal oxide film, the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; the second conductive film does not overlap with the first region; Display device.

6. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the second insulating film has a region in contact with an upper surface of the oxide semiconductor film, the second insulating film has a region in contact with an upper surface of the metal oxide film, the oxide semiconductor film overlaps with the second insulating film at a periphery of the oxide semiconductor film; the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; Display device.

7. A pixel includes a transistor, a display element, and a capacitor. a display device in which one of a source and a drain of the transistor is electrically connected to a pixel electrode of the display element and one of electrodes of the capacitor element, a first conductive film having a function as a gate electrode of the transistor; a first insulating film having a region disposed above the first conductive film; an oxide semiconductor film having a region located above the first insulating film and having a channel formation region of the transistor; a metal oxide film having a region disposed above the first insulating film and functioning as the other electrode of the capacitance element; a second conductive film having a region located above the oxide semiconductor film and functioning as one of a source and a drain of the transistor; a third conductive film having a region located above the oxide semiconductor film and functioning as the other of the source and the drain of the transistor; a fourth conductive film having a region disposed above the metal oxide film, electrically connected to the metal oxide film, and overlapping with the first conductive film; a second insulating film having a region disposed above the oxide semiconductor film and a region disposed above the metal oxide film; a fifth conductive film having a region disposed above the second insulating film and having a function as the pixel electrode and a function as one electrode of the capacitance element; having the second insulating film has a region in contact with an upper surface of the oxide semiconductor film, the second insulating film has a region in contact with an upper surface of the metal oxide film, the oxide semiconductor film overlaps with the second insulating film at a periphery of the oxide semiconductor film; the metal oxide film overlaps with the second insulating film at a periphery of the metal oxide film, the metal oxide film has a first region overlapping the fifth conductive film without the second insulating film therebetween and without the fourth conductive film therebetween; the second conductive film does not overlap with the first region; Display device.

8. In any one of claims 1 to 7, each of the oxide semiconductor film and the metal oxide film contains In, Ga, and Zn; Display device.

9. In any one of claims 1 to 7, each of the oxide semiconductor film and the metal oxide film contains In and Zn; Display device.

Images