Device and method for analyzing malfunction of semiconductor

Abstract

To desirably detect a malfunctioning part of a semiconductor device.SOLUTION: A controller of a semiconductor malfunction analyzer moves a chuck to a position where a first light detection unit can detect a target, and thereafter outputs an alignment order to align an optical axis of a second optical system to an optical axis of a first optical system on the basis of the target. After that, the controller applies a stimulation signal to a semiconductor device while the optical axis of the first optical system and the optical axis of the second optical axis are maintained in the same positional relation, and also outputs an analysis order to receive light emitted from the semiconductor device in response to the stimulation signal by at least one of the first light detection unit and the second light detection unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor failure analysis apparatus and a semiconductor failure analysis method. [Background technology]

[0002] Semiconductor devices are becoming increasingly miniaturized. To achieve this, it is desirable to improve the exposure and patterning techniques used to manufacture the devices. It is also important to have technology that can determine whether or not semiconductor devices manufactured using these techniques operate normally. Furthermore, when devices do not operate normally, it is also important to have technology that can determine the cause of the malfunction.

[0003] Patent Documents 1 and 2 disclose apparatus for inspecting semiconductor devices. These inspection apparatuses irradiate light onto a semiconductor device to which an electrical signal has been applied. The light irradiated onto the semiconductor device becomes reflected light according to the state of the semiconductor device. These inspection apparatuses then use the reflected light to obtain information regarding the operating state of the semiconductor device. The inspection apparatus of Patent Document 1 obtains information regarding a portion of the semiconductor device operating at a specified frequency. The inspection apparatus of Patent Document 2 obtains information regarding a heat source generated at a fault location of the semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-92514 A [Patent Document 2] International Publication No. 2016 / 056110 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technical field of semiconductor failure analysis apparatus, there is a demand for a technique for effectively detecting a failure location in a semiconductor device. Therefore, the present invention provides a semiconductor failure analysis apparatus and a semiconductor failure analysis method for effectively detecting a failure location in a semiconductor device. [Means for solving the problem]

[0006] A semiconductor failure analysis apparatus according to one embodiment of the present invention includes a first analysis unit in which a first optical detector receives light emitted from a semiconductor device via a first optical system and the first optical system is moved relative to the semiconductor device by a first drive unit, a second analysis unit in which a second optical detector receives light emitted from the semiconductor device via a second optical system and the second optical system is moved relative to the semiconductor device by a second drive unit, a device placement unit disposed between the first analysis unit and the second analysis unit, holding the semiconductor device and having a chuck provided with a target for aligning an optical axis of the first optical system with an optical axis of the second optical system, the chuck moving relative to the first analysis unit and the second analysis unit, a stimulus signal application unit that applies a stimulus signal to the semiconductor device, and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulus signal application unit. The target is detectable by the first analysis unit from one side of the target and detectable by the second analysis unit from the other side of the target. After moving the chuck to a position where the first optical detection unit can detect the target, the control unit outputs an alignment command to the second analysis unit and the device placement unit to align the optical axis of the second optical system with the optical axis of the first optical system based on the target, and outputs an analysis command to the first analysis unit, the second analysis unit, the stimulus signal application unit, and the device placement unit to apply a stimulus signal to the semiconductor device while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system, and to receive light from the semiconductor device emitted in response to the stimulus signal at least by the first optical detection unit or the second optical detection unit.

[0007] This semiconductor failure analysis apparatus applies a stimulus signal to the semiconductor device while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system, and receives light from the semiconductor device emitted in response to the stimulus signal with at least one of the first optical detection unit or the second optical detection unit. Therefore, the optical axes of the first optical system and the second optical system that receive the light from the semiconductor device are aligned, making it possible to effectively detect the fault location of the semiconductor device.

[0008] In one embodiment, an alignment command of the semiconductor failure analysis apparatus may cause the first optical detection unit to acquire a first image of the target from one side, cause the second optical detection unit to acquire a second image of the target from the other side, and move the second optical system so as to align the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images.

[0009] In one embodiment, the analysis command of the semiconductor failure analysis device may cause the chuck to be moved by a third drive unit included in the device placement unit so that the semiconductor device overlaps with the optical axis of the first optical system and the optical axis of the second optical system, and then the semiconductor device is analyzed.

[0010] In one embodiment, the target of the semiconductor failure analysis apparatus may be provided at a location different from the device holding portion of the chuck that holds the semiconductor device.

[0011] In one embodiment, a first optical detection unit of a semiconductor failure analysis apparatus may obtain a first image of a target viewed from one side, and a second optical detection unit may obtain a second image of the target viewed from the other side.

[0012] In one embodiment, the target of the semiconductor failure analysis device may include a light transmitting portion that transmits light detectable by the first light detection unit and the second light detection unit.

[0013] A semiconductor failure analysis apparatus according to another embodiment of the present invention includes a first analysis unit that irradiates a semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, a second analysis unit that irradiates a semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, a device arrangement unit that is disposed between the first analysis unit and the second analysis unit, holds the semiconductor device, and has a chuck provided with a target for aligning the center of an optical scanning region of the first optical system with the center of an optical scanning region of the second optical system, and the chuck moves relatively to the first analysis unit and the second analysis unit, an electrical signal acquisition unit that receives an electrical signal output by the semiconductor device, and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device arrangement unit, and the electrical signal acquisition unit. The target is detectable by the first analysis unit from one side of the target and is detectable by the second analysis unit from the other side of the target. After the first analysis unit has moved the chuck to a position where it can detect the target, the control unit outputs an alignment command to the second analysis unit and the device placement unit to align the center of the optical scanning area of ​​the second optical system with the center of the optical scanning area of ​​the first optical system based on the target, and outputs an analysis command to the first analysis unit, the second analysis unit, the electrical signal acquisition unit, and the device placement unit to irradiate light from at least one of the first analysis unit and the second analysis unit onto the semiconductor device while maintaining the positional relationship between the center of the optical scanning area of ​​the first optical system and the center of the optical scanning area of ​​the second optical system, and receives an electrical signal from the semiconductor device by the electrical signal acquisition unit.

[0014] A first analysis unit of a semiconductor failure analysis apparatus according to another embodiment of the present invention includes a first optical detection unit that receives light from one side of the semiconductor device, and a second analysis unit that includes a second optical detection unit that receives light from the other side of the semiconductor device, and the alignment command may include causing the first optical detection unit to acquire a first image of the target from one side and causing the second optical detection unit to acquire a second image of the target from the other side, and aligning the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images, thereby aligning the center of the scanning area of ​​the first optical system with the center of the scanning area of ​​the second optical system.

[0015] An analysis command of a semiconductor failure analysis apparatus according to another embodiment of the present invention may cause an analysis of the semiconductor device to be performed after moving the chuck by a third drive unit included in the device placement unit so that the semiconductor device overlaps the optical scanning region of the first optical system and the optical scanning region of the second optical system.

[0016] The target of the semiconductor failure analysis apparatus according to another aspect of the present invention may be provided at a location different from the device holding portion of the chuck that holds the semiconductor device.

[0017] A first analysis unit of a semiconductor failure analysis apparatus according to another embodiment of the present invention may include a first optical detection unit that receives light from one side of the semiconductor device, and a second analysis unit may include a second optical detection unit that receives light from the other side of the semiconductor device, wherein the first optical detection unit acquires a first image of the target viewed from one side, and the second optical detection unit acquires a second image of the target viewed from the other side.

[0018] In another embodiment of the present invention, the first analysis unit of a semiconductor failure analysis apparatus may include a first optical detection unit that receives light from one side of the semiconductor device, the second analysis unit may include a second optical detection unit that receives light from the other side of the semiconductor device, and the target may include a light transmitting portion that transmits light that can be detected by the first optical detection unit and the second optical detection unit.

[0019] A semiconductor failure analysis apparatus according to yet another embodiment of the present invention includes a first analysis unit that irradiates a semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, and a first response light generated from the semiconductor device in response to the light of the first light source is received by a first optical detection unit; a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, and a second response light generated from the semiconductor device in response to the light of the second light source is received by a second optical detection unit; a device placement unit that is disposed between the first analysis unit and the second analysis unit, holds the semiconductor device, and has a chuck provided with a target for aligning the center of the optical scanning region of the first optical system with the center of the optical scanning region of the second optical system, the chuck moving relatively to the first analysis unit and the second analysis unit; a stimulus signal application unit that applies a stimulus signal to the semiconductor device; and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulus signal application unit. The target is detectable by the first analysis unit from one side of the target and by the second analysis unit from the other side of the target. After the control unit moves the chuck to a position where the first light detection unit can detect the target, the control unit outputs an alignment command to the second analysis unit and the device placement unit to align the center of the light scanning area of ​​the second optical system with the center of the light scanning area of ​​the first optical system based on the target, and outputs an analysis command to the first analysis unit, the second analysis unit, the stimulus signal application unit, and the device placement unit to irradiate the semiconductor device with light from at least one of the first analysis unit and the second analysis unit while maintaining a positional relationship between the center of the light scanning area of ​​the first optical system and the center of the light scanning area of ​​the second optical system and applying a stimulus signal to the semiconductor device, and to receive at least one of the first response light and the second response light from the semiconductor device from at least one of the first light detection unit and the second light detection unit.

[0020] An alignment command of a semiconductor failure analysis apparatus according to yet another embodiment of the present invention may include causing the first optical detection unit to acquire a first image of the target from one side, causing the second optical detection unit to acquire a second image of the target from the other side, and aligning the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images, thereby aligning the center of the scanning area of ​​the first optical system with the center of the scanning area of ​​the second optical system.

[0021] An analysis command of a semiconductor failure analysis apparatus according to yet another embodiment of the present invention may cause an analysis of the semiconductor device to be performed after a chuck is moved by a third drive unit included in the device placement unit so that the semiconductor device overlaps the optical scanning region of the first optical system and the optical scanning region of the second optical system.

[0022] The target of the semiconductor failure analysis apparatus according to still another aspect of the present invention may be provided at a location in the chuck different from the device holding portion that holds the semiconductor device.

[0023] In a semiconductor failure analysis apparatus according to still another aspect of the present invention, the first optical detection unit may obtain a first image of the target viewed from one side, and the second optical detection unit may obtain a second image of the target viewed from the other side.

[0024] A target of a semiconductor failure analysis apparatus according to yet another embodiment of the present invention may include a light transmitting portion that transmits light detectable by the first light detection unit and the second light detection unit.

[0025] Yet another embodiment of the present invention is a semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus. The semiconductor failure analysis apparatus includes a first analysis unit in which a first optical detection unit receives light emitted from the semiconductor device via a first optical system and the first optical system is moved relative to the semiconductor device by a first drive unit, a second analysis unit in which a second optical detection unit receives light emitted from the semiconductor device via a second optical system and the second optical system is moved relative to the semiconductor device by a second drive unit, a device arrangement unit disposed between the first analysis unit and the second analysis unit, which holds the semiconductor device and has a chuck provided with a target for aligning the optical axis of the first optical system with the optical axis of the second optical system, and the chuck moves relative to the first analysis unit and the second analysis unit, a stimulus signal application unit that applies a stimulus signal to the semiconductor device, and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device arrangement unit, and the stimulus signal application unit. The target is detectable by the first optical detection unit from one side of the target and by the second optical detection unit from the other side of the target. The semiconductor failure analysis method includes an alignment step of aligning the optical axis of the second optical system with the optical axis of the first optical system based on the target after moving the chuck to a position where the first optical detection unit can detect the target, and an analysis step of applying a stimulus signal to the semiconductor device while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system, and receiving light from the semiconductor device in response to the stimulus signal with at least one of the first optical detection unit or the second optical detection unit.

[0026] A semiconductor failure analysis method according to still another embodiment of the present invention may further include, after the analysis step, a marking step of applying a mark indicating a failure location in the semiconductor device obtained by the first analysis unit and the second analysis unit to the semiconductor device.

[0027] Yet another embodiment of the present invention is a semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus. The semiconductor failure analysis apparatus includes a first analysis unit that irradiates the semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, a device arrangement unit that is disposed between the first analysis unit and the second analysis unit, holds the semiconductor device, and has a chuck provided with a target for aligning the center of the optical scanning area of ​​the first optical system with the center of the optical scanning area of ​​the second optical system, and the chuck moves relatively to the first analysis unit and the second analysis unit, an electrical signal acquisition unit that receives an electrical signal output by the semiconductor device, and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device arrangement unit, and the electrical signal acquisition unit. The target is detectable by the first analysis unit from one side of the target and is detectable by the second analysis unit from the other side of the target. The semiconductor failure analysis method includes an alignment step of aligning the center of the optical scanning area of ​​the second optical system with the center of the optical scanning area of ​​the first optical system using the target as a reference after moving the chuck to a position where the first analysis unit can detect the target, and an analysis step of irradiating the semiconductor device with light from at least one of the first analysis unit and the second analysis unit while maintaining the positional relationship between the center of the optical scanning area of ​​the first optical system and the center of the optical scanning area of ​​the second optical system, and receiving an electrical signal from the semiconductor device by an electrical signal acquisition unit.

[0028] A semiconductor failure analysis method according to still another embodiment of the present invention may further include, after the analysis step, a marking step of applying a mark indicating a failure location in the semiconductor device obtained by the first analysis unit and the second analysis unit to the semiconductor device.

[0029] Yet another embodiment of the present invention is a semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus. The semiconductor failure analysis apparatus includes a first analysis unit that irradiates the semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, and a first optical detection unit that receives a first response light from the semiconductor device generated in response to the light from the first light source, a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, and a second optical detection unit that receives a second response light from the semiconductor device generated in response to the light from the second light source, a device arrangement unit that is disposed between the first analysis unit and the second analysis unit, holds the semiconductor device, and has a chuck provided with a target for aligning the center of the optical scanning region of the first optical system with the center of the optical scanning region of the second optical system, and the chuck moves relatively to the first analysis unit and the second analysis unit, a stimulus signal application unit that applies a stimulus signal to the semiconductor device, and a control unit that outputs commands to the first analysis unit, the second analysis unit, the device arrangement unit, and the stimulus signal application unit. The target is detectable by the first optical detection unit from one side of the target and by the second optical detection unit from the other side of the target. The semiconductor failure analysis method includes an alignment step of aligning a center of an optical scanning region of the second optical system with a center of an optical scanning region of the first optical system based on the target after moving the chuck to a position where the first optical detection unit can detect the target, and an analysis step of irradiating the semiconductor device with light from at least one of the first analysis unit and the second analysis unit while maintaining a positional relationship between the center of the optical scanning region of the first optical system and the center of the optical scanning region of the second optical system and applying a stimulus signal to the semiconductor device, and receiving at least one of a first response light and a second response light from the semiconductor device by at least one of the first optical detection unit and the second optical detection unit.

[0030] A semiconductor failure analysis method according to still another embodiment of the present invention may further include, after the analysis step, a marking step of applying a mark indicating a failure location in the semiconductor device obtained by the first analysis unit and the second analysis unit to the semiconductor device. Effect of the Invention

[0031] According to the present invention, there is provided a semiconductor failure analysis apparatus and a semiconductor failure analysis method capable of effectively detecting a failure location in a semiconductor device. [Brief description of the drawings]

[0032] [Figure 1] FIG. 1 is a configuration diagram of a semiconductor failure analysis device according to an embodiment. [Diagram 2] Figure 2 is a diagram for explaining an image of laser marking on a semiconductor device. Figure 2(a) is a diagram showing the back surface of a laser-marked semiconductor device. Figure 2(b) is a diagram showing the front surface of a laser-marked semiconductor device. Figure 2(c) is a cross-sectional view taken along II(c)-II(c) in Figure 2(b). [Diagram 3] FIG. 3 is a diagram for explaining the marking control in the analysis device of FIG. [Figure 4] FIG. 4 is a plan view of the target. [Diagram 5] FIG. 5 is a flow chart showing main steps of a semiconductor failure analysis method using the analysis apparatus of FIG. [Figure 6] Fig. 6(a) is a diagram showing an analysis step, and Fig. 6(b) is a diagram showing one step constituting the alignment step. [Figure 7] Fig. 7(a) is a diagram showing a step constituting the alignment step following Fig. 6(b), and Fig. 7(b) is a diagram showing a step constituting the alignment step following Fig. 7(a). [Figure 8] FIG. 8 is a diagram showing a step constituting the alignment step following FIG. 7(b). [Figure 9] FIG. 9 is a configuration diagram of a semiconductor failure analysis apparatus according to the second embodiment. [Figure 10] FIG. 10 is a flow chart showing main steps of a semiconductor failure analysis method using the analysis apparatus of FIG. [Figure 11] FIG. 11 is a configuration diagram of a modified semiconductor failure analysis device. [Figure 12] FIG. 12 is a flow chart showing main steps of a semiconductor failure analysis method using the analysis apparatus of FIG. [Figure 13] FIG. 13 is a configuration diagram of a semiconductor failure analysis apparatus according to the third embodiment. [Figure 14] FIG. 14 is a flow chart showing main steps of a semiconductor failure analysis method using the analysis apparatus of FIG. [Figure 15] FIG. 15 is a configuration diagram of a semiconductor failure analysis apparatus according to the third embodiment. [Figure 16] FIG. 16 is a flow chart showing main steps of a semiconductor failure analysis method using the analysis apparatus of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] By the way, as a technique for analyzing semiconductor devices, when a fault location is identified, there is a technique for marking several points around the fault location by irradiating them with laser light. In a later process of failure analysis, the fault location can be easily identified based on the marks. Therefore, such a technique is extremely effective.

[0034] Japanese Patent Application Laid-Open No. 2016-148550 discloses an analysis device for a semiconductor device. The analysis device disclosed in Patent Document 1 has a configuration for analyzing a fault location in a semiconductor device and a configuration for attaching a mark around the fault location. The analysis device first aligns the configuration for detecting the fault location with the configuration for attaching the mark. Next, the analysis device analyzes the fault location while moving the configuration for detecting the fault location relative to the semiconductor device. When the configuration for detecting the fault location identifies the position of the fault location, the analysis device moves the configuration for attaching the mark to the position of the fault location.

[0035] In the later process of failure analysis, the position of the faulty part is identified based on the mark. Therefore, it is desirable for the mark to indicate the position of the faulty part accurately. On the other hand, even if a moving mechanism such as an XY stage that moves the components of the device is highly accurate, a slight error occurs between the position indicated by the movement command value and the actual position. Even a slight error can cause the position of the faulty part indicated by the mark to deviate from the actual position of the faulty part. In other words, the deviation between the actual position of the faulty part and the position of the faulty part indicated by the mark depends on the accuracy of the moving mechanism.

[0036] An object of the present invention is to provide a semiconductor failure analysis apparatus and a semiconductor failure analysis method capable of reducing the deviation between the location of a failure point and the location of a failure point indicated by a mark.

[0037] A semiconductor failure analysis apparatus according to one embodiment of the present invention includes an analysis unit in which a first optical detection unit receives a first light from a semiconductor device through a first optical system and the first optical system is moved relatively to the semiconductor device by a first drive unit, a marking unit in which a second optical detection unit receives a second light from the semiconductor device through a second optical system and irradiates the semiconductor device with a laser light through the second optical system and the second optical system is moved relatively to the semiconductor device by a second drive unit, a device arrangement unit disposed between the analysis unit and the marking unit, holding the semiconductor device and having a chuck provided with a target for aligning an optical axis of the first optical system with an optical axis of the second optical system, the chuck being moved relatively to the analysis unit and the marking unit by a third drive unit, and a control unit that outputs commands to the analysis unit, the marking unit, and the device arrangement unit. The target is detectable by the first optical detection unit from one side of the target and is detectable by the second optical detection unit from the other side of the target. After moving the chuck to a position where the first optical detection unit can detect the target, the control unit outputs an alignment command to the marking unit and the device placement unit to align the optical axis of the second optical system with the optical axis of the first optical system based on the target, and outputs a marking command to the marking unit and the device placement unit to irradiate laser light to a marking position set on the semiconductor device while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system.

[0038] Another aspect of the present invention is a semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus. The semiconductor failure analysis apparatus includes an analysis unit in which a first light detection unit receives a first light from the semiconductor device through a first optical system, and the first optical system is moved relatively to the semiconductor device by a first drive unit, a marking unit in which a second light detection unit receives a second light from the semiconductor device through a second optical system, and irradiates the semiconductor device with a laser light through the second optical system, and the second optical system is moved relatively to the semiconductor device by a second drive unit, a device arrangement unit that is disposed between the analysis unit and the marking unit, holds the semiconductor device, and has a chuck provided with a target for aligning the optical axis of the first optical system with the optical axis of the second optical system, and the chuck is moved relatively to the analysis unit and the marking unit by a third drive unit, and a control unit that outputs commands to the analysis unit, the marking unit, and the device arrangement unit. The target is detectable by the first light detection unit from one side of the target and detectable by the second light detection unit from the other side of the target. The semiconductor failure analysis method includes an alignment step of aligning an optical axis of a second optical system with an optical axis of a first optical system based on the target after moving the chuck to a position where a first optical detection unit can detect a target, and a marking step of irradiating a laser beam to a marking position set on the semiconductor device while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system.

[0039] In the semiconductor failure analysis device and the semiconductor failure analysis method, first, the optical axis of the second optical system of the marking unit is aligned with the optical axis of the first optical system of the analysis unit based on the target provided on the chuck. Then, while maintaining the positional relationship between the optical axis of the first optical system and the optical axis of the second optical system, the laser light is irradiated to the marking position set on the semiconductor device. In other words, after the optical axis of the first optical system is aligned with the optical axis of the second optical system, the first optical system and the second optical system do not move relative to each other. Therefore, there is no deviation between the position indicated by the movement command value and the actual position, which may occur due to the movement. As a result, it is possible to reduce the deviation of the position of the failure location indicated by the mark from the position of the failure location indicated by the analysis unit.

[0040] In one embodiment of the semiconductor failure analysis apparatus, the control unit may output an analysis command to the analysis unit before outputting the alignment command, to cause the analysis unit to analyze the failure location of the semiconductor device. Similarly, in another embodiment of the semiconductor failure analysis method, the control unit may further include an analysis step of analyzing the failure location of the semiconductor device by the analysis unit before the alignment step. With this configuration, it is possible to attach a mark that accurately indicates the position of the failure location.

[0041] In one embodiment of the semiconductor failure analysis apparatus, the marking command may cause the semiconductor device to be irradiated with laser light after the chuck is moved to the marking position by the third driving unit. Similarly, in another embodiment of the semiconductor failure analysis method, the marking step may cause the semiconductor device to be irradiated with laser light after the chuck is moved to the marking position by the third driving unit. According to this configuration, after the optical axis of the second optical system is aligned with the optical axis of the first optical system, the laser light can be irradiated to a desired position on the semiconductor device while maintaining the absolute positions as well as the relative positions of the first optical system and the second optical system. As a result, the positional deviation of the failure location indicated by the mark made by the marking unit can be further reduced.

[0042] In one embodiment of the semiconductor failure analysis device, the alignment command may include causing the first optical detection unit to acquire a first image of the target from one side, causing the second optical detection unit to acquire a second image of the target from the other side, and moving the second optical system so as to align the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images. Similarly, in another embodiment of the semiconductor failure analysis method, the alignment step may include causing the first optical detection unit to acquire a first image of the target from one side, causing the second optical detection unit to acquire a second image of the target from the other side, and moving the second drive unit so as to align the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images. With this configuration, the operation of aligning the optical axis of the second optical system with the optical axis of the first optical system can be reliably performed.

[0043] In one embodiment of the semiconductor failure analysis apparatus, the target may be provided at a location different from a device holder that holds the semiconductor device in the chuck. With this configuration, the optical axis of the second optical system can be aligned with the optical axis of the first optical system regardless of the type of semiconductor device.

[0044] In one embodiment of the semiconductor failure analysis apparatus, the first optical detection unit may obtain a first image of the target viewed from one side, and the second optical detection unit may obtain a second image of the target viewed from the other side. This configuration also ensures that the optical axis of the second optical system can be aligned with the optical axis of the first optical system.

[0045] In one embodiment of the semiconductor failure analysis apparatus, the target may include a light transmitting portion that transmits light detectable by the first light detection unit and the second light detection unit. This configuration also makes it possible to reliably perform an operation of aligning the optical axis of the second optical system with the optical axis of the first optical system.

[0046] According to the present invention, there is provided a semiconductor failure analysis apparatus and a semiconductor failure analysis method capable of reducing the deviation between the position of the failure location and the position indicated by the mark.

[0047] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0048] As shown in FIG. 1, the semiconductor failure analysis apparatus according to this embodiment analyzes a semiconductor device D, which is a device under test (DUT). In the following description, the semiconductor failure analysis apparatus according to this embodiment is simply referred to as "analysis apparatus 1." Furthermore, the analysis of the semiconductor device D includes, for example, identifying the location of a fault location contained in the semiconductor device D. Note that the analysis of the semiconductor device D is not limited to identifying the location of the fault location. The analysis of the semiconductor device D includes other analyses and inspections related to the semiconductor device D. Below, the analysis apparatus 1 of this embodiment will be described as identifying the location of a fault location contained in the semiconductor device D.

[0049] Furthermore, the analysis device 1 identifies the location of the fault and places a mark around the fault to indicate the fault. This act of placing a mark is called "marking." The mark is intended to make it easier to understand the fault location identified by the analysis device 1 in a later process of the fault analysis.

[0050] Examples of the semiconductor device D include integrated circuits (ICs) having PN junctions such as transistors, logic devices, memory devices, analog devices, which are large-scale integrated circuits (LSIs), mixed signal devices combining these, and power semiconductor devices (power devices) such as high current / high voltage MOS transistors, bipolar transistors, and IGBTs. The semiconductor device D has a layered structure including a substrate and a metal layer. For example, a silicon substrate is used as the substrate of the semiconductor device D.

[0051] The analysis device 1 includes an analysis unit 10, a marking unit 20, a device placement unit 30, and a computer 40. The analysis unit 10 identifies a fault location of a semiconductor device D. The marking unit 20 attaches a mark indicating the position of the fault location. The semiconductor device D is placed in the device placement unit 30. The analysis device 1 may be, for example, an inverted emission microscope having a laser marking function.

[0052] <Analysis Department> The analysis section 10 has a tester unit 11, a light source 12 (first light source), an observation optical system 13 (first optical system), an XYZ stage 14 (first drive section), and a two-dimensional camera 15 (first light detection section).

[0053] The tester unit 11 is electrically connected to the semiconductor device D via a cable. The tester unit 11 is a stimulus signal application section that applies a stimulus signal to the semiconductor device D. The tester unit 11 is operated by a power supply (not shown). The tester unit 11 repeatedly applies a stimulus signal such as a predetermined test pattern to the semiconductor device D. The stimulus signal output by the tester unit 11 may be a modulated current signal or a CW (continuous wave) current signal.

[0054] The tester unit 11 is electrically connected to the computer 40 via a cable. The tester unit 11 applies a stimulus signal specified by the computer 40 to the semiconductor device D. The tester unit 11 does not necessarily have to be electrically connected to the computer 40. When the tester unit 11 is not electrically connected to the computer 40, it determines a stimulus signal such as a test pattern by itself. Note that a power supply, a pulse generator, or the like may be used as the tester unit 11.

[0055] The light source 12 outputs light to the semiconductor device D. The light source 12 may be, for example, an LED (Light Emitting Diode) or an SLD (Super Luminescent Diode). Furthermore, the light source 12 may be an incoherent light source such as a lamp light source or a coherent light source such as a laser light source. The light output from the light source 12 passes through the substrate of the semiconductor device D. For example, when the substrate of the semiconductor device D is silicon, the wavelength of the light output from the light source 12 is preferably 1064 nm or more. The light output from the light source 12 is provided to an observation optical system 13.

[0056] The observation optical system 13 outputs the light output from the light source 12 to the semiconductor device D. For example, the light source 12 irradiates the back surface D1 side of the semiconductor device D with light during the marking process. The observation optical system 13 has an objective lens 13a and a beam splitter 13b. The objective lens 13a focuses the light on an observation area.

[0057] The observation optical system 13 guides the light reflected by the semiconductor device D to the two-dimensional camera 15. Specifically, the light irradiated from the observation optical system 13 passes through the substrate SiE (see FIG. 2(c)) of the semiconductor device D. Next, the light that passes through the substrate SiE is reflected by the metal layer ME (see FIG. 2(c)). Next, the light that reflects off the metal layer ME passes through the substrate SiE again. Then, the light that passes through the substrate SiE is input to the two-dimensional camera 15 via the objective lens 13a and the beam splitter 13b of the observation optical system 13. In addition, the observation optical system 13 guides light emission generated in the semiconductor device D by application of a stimulus signal to the two-dimensional camera 15. Specifically, the metal layer ME of the semiconductor device D may emit light such as emission light due to application of a stimulus signal. The light emitted by the metal layer ME is transmitted through the substrate SiE, and then enters the two-dimensional camera 15 via the objective lens 13 a and the beam splitter 13 b of the observation optical system 13 .

[0058] The observation optical system 13 is placed on an XYZ stage 14. The Z-axis direction is the optical axis direction of the objective lens 13a. The XYZ stage 14 is movable in the Z-axis direction. Furthermore, the XYZ stage 14 is also movable in the X-axis and Y-axis directions perpendicular to the Z-axis direction. The XYZ stage 14 is controlled by a control unit 41b of a computer 40, which will be described later. The observation area is determined by the position of the XYZ stage 14. The observation optical system 13 guides reflected light from the semiconductor device D in response to the irradiated light to the two-dimensional camera 15 as light from the semiconductor device D.

[0059] The two-dimensional camera 15 receives light (first light) from the semiconductor device D. The two-dimensional camera 15 outputs image data based on the received light. The light from the semiconductor device D referred to in this specification may be reflected light reflected at the semiconductor device D in response to illumination light. Also, the light from the semiconductor device D referred to in this specification may be emission light generated in response to a stimulus signal. For example, the two-dimensional camera 15 captures an image of the semiconductor device D from the substrate SiE side of the semiconductor device D during the marking process. In other words, the two-dimensional camera 15 captures an image of the semiconductor device D from the back surface D1 side of the semiconductor device D during the marking process.

[0060] The two-dimensional camera 15 receives the light reflected by the semiconductor device D. Then, the two-dimensional camera 15 outputs image data for creating a pattern image to the computer 40 based on the received light. The pattern image makes it possible to grasp the marking position. The two-dimensional camera 15 also receives emission light generated in response to the stimulus signal. The two-dimensional camera 15 outputs image data for generating an emission image to the computer 40 based on the received light. The emission image makes it possible to identify the emission location in the semiconductor device D. By identifying the emission location, it is possible to identify the failure location of the semiconductor device D.

[0061] The two-dimensional camera 15 may be an imaging device capable of detecting light of a wavelength passing through the SiE substrate of the semiconductor device D. The two-dimensional camera 15 may be a camera equipped with a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The two-dimensional camera 15 may also be an InGaAs camera or an MCT camera. Note that illumination light from the light source 12 is not required during luminescence measurement. In other words, there is no need to operate the light source 12 during luminescence measurement.

[0062] <Marking section> Next, the marking unit 20 will be described. The marking unit 20 attaches a mark indicating a fault location. The marking unit 20 has a laser light source 21, a laser marking optical system 22 (second optical system), an XYZ stage 23 (second driving unit), a probing camera 24 (second light detection unit), and an illumination light source 25.

[0063] The marking unit 20 puts a mark around the fault location identified by the analysis unit 10. As shown in FIG. 2(a) and FIG. 2(b), a marking location mp is set around the fault location fp. Four marking locations mp are illustrated in FIG. 2(a) and FIG. 2(b). When the laser marking is completed, a through hole penetrating the metal layer ME of the semiconductor device D is formed as shown in FIG. 2(c). The laser marking is performed until the through hole reaches the interface ss between the metal layer ME and the substrate SiE, exposing the surface of the substrate SiE that contacts the metal layer ME. In other words, the "mark" in this specification may mean a through hole formed in the metal layer ME. Also, the "mark" in this specification may mean the substrate SiE exposed from the through hole.

[0064] 3, the marking unit 20 irradiates a laser beam outputted by a laser light source 21 to a marking location mp of the semiconductor device D via a laser marking optical system 22. The marking unit 20 irradiates the laser beam to the marking location mp from the metal layer ME side of the semiconductor device D. Details of the marking unit 20 will be described below.

[0065] 1, the laser light source 21 outputs a laser light to be irradiated onto the semiconductor device D. The laser light forms a through hole in the metal layer ME. When an output start command is input from the computer 40, the laser light source 21 starts outputting the laser light. The laser light source 21 may be, for example, a solid-state laser light source or a semiconductor laser light source. The wavelength of the light output from the laser light source 21 is not less than 250 nm and not more than 2000 nm.

[0066] The optical system 22 for laser marking irradiates the marking location mp of the semiconductor device D with laser light. Specifically, the optical system 22 for laser marking irradiates the semiconductor device D with laser light from the metal layer ME side of the semiconductor device D. In other words, the optical system 22 for laser marking irradiates the semiconductor device D with laser light from the surface D2 side of the semiconductor device D. The optical system 22 for laser marking has an objective lens 22a and a switching unit 22b. The switching unit 22b switches the optical paths of the laser light source 21 and the probing camera 24. The objective lens 22a focuses the laser light on the marking location mp. The objective lens 22a guides the light coming from the surface of the semiconductor device D to the probing camera 24.

[0067] The laser marking optical system 22 is placed on the XYZ stage 23. The Z-axis direction of the XYZ stage 23 is the optical axis direction of the objective lens 22a. The XYZ stage 23 receives a control command from the computer 40. The XYZ stage 23 moves the laser marking optical system 22 in the Z-axis direction in response to the control command. The XYZ stage 23 also moves the laser marking optical system 22 in the X-axis direction and the Y-axis direction perpendicular to the Z-axis direction in response to the control command. The laser marking optical system 22 may have an optical scanning unit that replaces the XYZ stage 23 and focuses the laser light on the marking location mp on the surface D2 of the semiconductor device D. As the optical scanning unit, an optical scanning element such as a galvanometer mirror or a MEMS mirror may be used. The laser marking optical system 22 may also include a shutter. According to this configuration, the shutter allows or blocks the laser light from the laser light source 21 to pass under the control of the control unit 41b. As a result, the output of the laser light can be controlled.

[0068] The probing camera 24 captures an image of the metal layer ME of the semiconductor device D from the surface D2 side of the semiconductor device D. The probing camera 24 outputs the captured image to the computer 40. By checking the captured image, a user can understand the state of the laser marking viewed from the surface D2 side of the semiconductor device D. The illumination light source 25 illuminates the semiconductor device D with illumination light when capturing an image with the probing camera 24.

[0069] <Device placement section> The device placement unit 30 holds the semiconductor device D. Furthermore, the device placement unit 30 changes the position of the semiconductor device D relative to the observation optical system 13. Similarly, the device placement unit 30 changes the position of the semiconductor device D relative to the laser marking optical system 22. The device placement unit 30 has a sample stage 31, a wafer chuck 32, and an XY drive unit 33 (third drive unit).

[0070] Therefore, in the analysis device 1, the observation optical system 13, the laser marking optical system 22, and the device placement unit 30 each have a driving mechanism. That is, the analysis device 1 has three degrees of freedom. According to a configuration having three degrees of freedom, for example, the laser marking optical system 22 and the device placement unit 30 can be moved while the observation optical system 13 is fixed. Furthermore, the device placement unit 30 can also be moved while the observation optical system 13 and the laser marking optical system 22 are fixed. "Fixed" means that the position is not changed. For example, "a state in which the observation optical system 13 and the laser marking optical system 22 are fixed" refers to a state in which the relative position of the laser marking optical system 22 with respect to the observation optical system 13 is maintained.

[0071] A wafer chuck 32 is slidably placed on the sample stage 31. The wafer chuck 32 has a device holder 32a that holds a semiconductor device D. The device holder 32a includes a through hole provided in the wafer chuck 32 and a glass plate that physically covers the through hole.

[0072] The wafer chuck 32 has an alignment target 50. The alignment target 50 (see FIG. 4) is a glass plate. One surface of the glass plate is provided with a pattern extending radially from the reference point bp. This pattern is, for example, a metal film. As an example, the pattern is made of a thin aluminum film. The pattern therefore constitutes an opaque portion 50b. The glass plate transmits light of a wavelength that transmits through the substrate SiE of the semiconductor device D. As a result, the glass plate also transmits light output from the illumination light source 25 and the light source 12. Therefore, the area where the pattern is not provided constitutes a light-transmitting portion 50a. The wafer chuck 32 has a target hole 32b in which the alignment target 50 is disposed. The alignment target 50 is disposed so as to close the target hole 32b. With this arrangement, the probing camera 24 and the two-dimensional camera 15 can acquire an image of the pattern provided on one surface of the glass plate.

[0073] The alignment target 50 is provided on the wafer chuck 32. That is, the position at which the device holder 32a is provided on the wafer chuck 32 is different from the position at which the alignment target 50 is provided. When the position of the wafer chuck 32 is changed by the XY drive unit 33, the positions of the semiconductor device D and the alignment target 50 are changed simultaneously. That is, the position of the alignment target 50 with respect to the semiconductor device D attached to the wafer chuck 32 remains unchanged.

[0074] The XY drive unit 33 moves the wafer chuck 32 in the X-axis direction or the Y-axis direction in response to a control command from the computer 40. As a result, the observation area can be changed without moving the observation optical system 13. Similarly, the irradiation position of the laser light can be changed without moving the laser marking optical system 22.

[0075] The specific configuration of the device placement unit 30 is not limited to the above configuration. The device placement unit 30 may adopt a configuration that has a function of holding the semiconductor device D and a function of moving the semiconductor device D in at least one of the X-axis direction and the Y-axis direction. For example, instead of the sample stage 31 and the XY drive unit 33, an XY stage that moves the wafer chuck 32 in at least one of the X-axis direction and the Y-axis direction may be provided.

[0076] <Calculator> The calculator 40 is a computer such as a personal computer. The calculator 40 is physically configured to include memories such as RAM and ROM, a processor (arithmetic circuit) such as a CPU, a communication interface, and a storage unit such as a hard disk. Examples of the calculator 40 include a personal computer, a cloud server, and a smart device (smartphone, tablet terminal, etc.). The calculator 40 functions by executing a program stored in the memory with the CPU of a computer system. The calculator 40 has, as functional components, a condition setting unit 41a, a control unit 41b, and an image processing unit 41c.

[0077] <Condition setting section> The condition setting unit 41a sets the marking location mp based on the information indicating the fault location fp input from the input unit 41e. Several marking locations mp are set around the identified fault location fp. The several locations are, for example, four locations. When the information indicating the fault location fp is input, for example, the condition setting unit 41a automatically sets the marking locations mp at four locations around the fault location fp with the fault location fp at the center. Specifically, the condition setting unit 41a sets the marking locations mp in a cross shape with the fault location fp at the center in a plan view, for example (see FIG. 2(a) and FIG. 2(b)). Note that the marking locations mp may be set by the input unit 41e accepting input of information indicating the marking locations mp from a user who has viewed the analysis image displayed on the display unit 41d. In this case, the condition setting unit 41a does not automatically set the marking locations mp. The condition setting unit 41a sets the marking locations mp based on the information indicating the marking locations mp input from the input unit 41e. The condition setting unit 41a generates a reference image. The reference image is obtained by adding a mark indicating the fault location fp and a mark indicating the marking location mp to the analysis image. The condition setting unit 41a stores the reference image in the memory of the computer 40.

[0078] <Control Unit> The control unit 41b controls the XYZ stage 14 of the analysis unit 10 so that the observation area of ​​the failure location falls within the field of view of the two-dimensional camera 15. The control unit 41b controls the XYZ stage 23 of the marking unit 20 so that the optical axis of the laser marking optical system 22 coincides with the optical axis of the observation optical system 13. The control unit 41b controls the XY drive unit 33 of the device placement unit 30 so that the optical axis of the laser marking optical system 22 overlaps with the marking location mp.

[0079] The control unit 41b also controls the laser light source 21. When the image processing unit 41c determines that a mark image has appeared, the control unit 41b outputs an output stop signal to the laser light source 21. When the output stop signal is input, the laser light source 21 stops outputting the laser light. Therefore, the laser light source 21 continues to output the laser light from when the output start signal is input by the control unit 41b until when the output stop signal is input. As described above, the control unit 41b controls the laser light source 21 so that the laser marking is performed until the mark image formed by the laser marking appears in the pattern image. In addition, since the penetration threshold of the laser light is set, the control unit 41b controls the laser light source 21 so that the laser marking is performed until the laser light penetrates the metal layer ME.

[0080] <Image processing unit> The computer 40 is electrically connected to the two-dimensional camera 15 via a cable. The computer 40 creates a pattern image and an emission image using image data input from the two-dimensional camera 15. Here, it is difficult to identify the emission position in the pattern of the semiconductor device D using only the emission image described above. Therefore, the computer 40 generates, as an analysis image, a superimposed image in which a pattern image based on reflected light from the semiconductor device D and an emission image based on emission from the semiconductor device D are superimposed.

[0081] The image processing unit 41c creates a marking image. The marking image is a pattern image including a mark image and a light emission image superimposed on each other. The created marking image is stored in the memory of the computer 40. The image processing unit 41c also displays the marking image on the display unit 41d. The marking image allows the user to accurately grasp the marking position relative to the position of the faulty part in a later process. The image processing unit 41c also acquires marking information. The marking information is information necessary for grasping the marking position relative to the position of the faulty part. Examples of the marking information include the distance from the marking position to the faulty part, and the direction of the marking position based on the position of the faulty part. The acquired marking information may be displayed as a list. The marking information may be added to the marking image and displayed. The marking information may be output on a paper medium.

[0082] The calculator 40 outputs the analysis image to the display unit 41d. The display unit 41d is a display device such as a display for showing the analysis image, etc. to the user. The user can confirm the location of the fault from the analysis image displayed on the display unit 41d. The user also inputs information indicating the fault using the input unit 41e. The input unit 41e is an input device such as a keyboard and a mouse that accepts input from the user. The input unit 41e outputs the information indicating the fault to the calculator 40. The calculator 40, the display unit 41d, and the input unit 41e may be tablet terminals.

[0083] The image processing unit 41c may output a control command to stop the irradiation of the laser light to the control unit 41b. The control command to stop the irradiation of the laser light is generated by using a mark image that appears in the pattern image. Specifically, the image processing unit 41c sequentially generates the pattern image in parallel with the laser marking by the laser light output by the laser light source 21. A hole is formed in the metal layer ME at the marking location mp by the laser marking. When the hole in the metal layer ME is shallow, the change in the intensity of the reflected light at the marking position is small and the change in the optical reflection image is also small. In other words, when the hole formed by the laser marking is formed only in the metal layer ME and does not reach the substrate SiE, the change in the intensity of the reflected light at the marking position is small. Therefore, the change in the optical reflection image is also small. As a result, the influence of the laser marking does not appear in the pattern image. On the other hand, when the hole in the metal layer ME becomes deep, the change in at least one of the refractive index, transmittance, and reflectance of the light on the back surface D1 side becomes large. Specifically, when the hole is deep enough to reach the interface ss between the metal layer ME and the substrate SiE, at least one of the refractive index, transmittance, and reflectance of light on the back surface D1 side changes significantly. These changes cause a large change in the intensity of the reflected light at the marking position. As a result, a mark image indicating the marking location appears in the pattern image.

[0084] The image processor 41c, for example, compares the above-mentioned reference image with the pattern image. If the comparison result shows that the difference between the images is greater than a predetermined value, the image processor 41c determines that the mark image has appeared. By setting the specified value in advance, the timing at which it is determined that the mark image has appeared can be determined.

[0085] The image processor 41c may determine whether or not a mark image has appeared according to the contents of an input from the user. When the image processor 41c determines that a mark image has appeared, it compares the reference image with the pattern image. When the mark formation location of the pattern image is shifted from the marking location mp of the reference image, the image processor 41c may determine that the mark has been misaligned. In this case, laser marking may be performed again so that the mark is formed at the correct marking location mp.

[0086] Next, the marking process of the analysis device 1 will be described with reference to Fig. 5 to Fig. 8. Fig. 5 is a flow diagram showing the main steps of the marking process of the analysis device 1.

[0087] <Analysis process S10> First, a fault location of the semiconductor device D is identified (S10). The control unit 41b outputs an analysis command for step S10 to the analysis unit 10. Specifically, as shown in FIG. 6(a), the XYZ stage 14 controls the X-axis direction and the Y-axis direction to move the observation optical system 13 so that the observation optical system 13 captures an area to be observed in its field of view. Next, the XYZ stage 14 controls the Z-axis direction to move the observation optical system 13 so that the focal position of the objective lens 13a is aligned with the area to be observed. Next, the light source 12 irradiates the semiconductor device D with light. Then, the two-dimensional camera 15 receives the reflected light from the semiconductor device D. The two-dimensional camera 15 generates an optical reflection image based on the reflected light. Then, the two-dimensional camera 15 outputs the optical reflection image to the computer 40. After the optical reflection image is output, the light source 12 stops irradiating the semiconductor device D with light. Next, the tester unit 11 applies a stimulus signal to the semiconductor device D. The two-dimensional camera 15 receives the light caused by the stimulus signal. The two-dimensional camera 15 generates an emission image based on the light caused by the stimulus signal. The two-dimensional camera 15 outputs the emission image to the computer 40. The image processing unit 41c generates an analysis image in which the optical reflection image and the emission image are superimposed. Next, the failure location fp is identified using the analysis image.

[0088] As described above, during the period in which the analysis step is performed, the positional relationship of the observation optical system 13 with respect to the semiconductor device D is such that the observation area is included in the field of view of the observation optical system 13. During the period in which the analysis step is performed, the positional relationship of the observation optical system 13 with respect to the semiconductor device D is maintained. On the other hand, during the period in which the analysis step is performed, the position of the laser marking optical system 22 with respect to the semiconductor device D is not particularly limited. For example, the optical axis of the laser marking optical system 22 may or may not coincide with the optical axis of the observation optical system 13. Usually, the optical axis of the laser marking optical system 22 does not coincide with the optical axis of the observation optical system 13 unless the optical axis is aligned. In the analysis method of this embodiment, the alignment of the optical axis may be performed before the above-mentioned analysis step, but is not essential. In the analysis method of this embodiment, the alignment of the optical axis is performed after the analysis step is completed.

[0089] <Alignment process S20> Next, the observation optical system 13 and the laser marking optical system 22 are aligned (S20). The control unit 41b outputs an alignment command for step S20 to the marking unit 20 and the device placement unit 30. In the following description, a state in which the optical axis of the observation optical system 13 intersects with a defective portion of the semiconductor device D immediately before the alignment step is performed is illustrated. First, as shown in FIG. 6(b), the XY driving unit 33 controls the X-axis direction and the Y-axis direction to move the wafer chuck 32 so that the alignment target 50 is captured in the field of view of the observation optical system 13 (S21). This movement is also referred to as "evacuating the semiconductor device D". At this time, the control unit 41b stores the movement amount of the semiconductor device D (wafer chuck 32).

[0090] Next, as shown in FIG. 7(a), the XYZ stage 23 controls the X-axis direction and the Y-axis direction to move the laser marking optical system 22 so that the alignment target 50 is captured in the field of view of the laser marking optical system 22 (S22). Next, the illumination light source 25 outputs illumination light toward the alignment target 50. The illumination light passes through the light-transmitting portion 50a of the alignment target 50 and enters the observation optical system 13. The incident illumination light is captured by the two-dimensional camera 15. The two-dimensional camera 15 outputs a transmitted image to the computer 40. The illumination light is also reflected by the opaque portion 50b of the alignment target 50. The reflected light enters the laser marking optical system 22 again. The incident reflected light is then captured by the probing camera 24. The probing camera 24 outputs a reflected image to the computer 40. The image processor 41c uses the transmitted image and the reflected image to calculate the deviation of the optical axis of the laser marking optical system 22 from the optical axis of the observation optical system 13. The image processor 41c repeatedly moves the laser marking optical system 22 and checks the deviation amount until the deviation falls within the allowable range. When it is determined that the deviation falls within the allowable range, the alignment of the optical axis is completed.

[0091] After the alignment of the optical axis is completed, as shown in FIG. 7(b), the XY driving unit 33 controls the X-axis direction and the Y-axis direction to move the wafer chuck 32 so that the defective part of the semiconductor device D is captured in the field of view of the observation optical system 13 (S23). At this time, the control unit 41b may control the XY driving unit 33 based on the movement amount stored when the semiconductor device D is evacuated. Also, the relative position between the laser marking optical system 22 and the semiconductor device D may be controlled using image data output from the two-dimensional camera 15 and the probing camera 24. In this case, the object of the movement is only the semiconductor device D. The movement of the semiconductor device D in this process is also called "return of the semiconductor device D". In other words, immediately after the alignment of the optical axis is completed, the semiconductor device D is evacuated, so that the semiconductor device D does not exist in the field of view of the observation optical system 13 and the laser marking optical system 22. Therefore, after the alignment of the optical axis is completed, the semiconductor device D is accommodated in the field of view of the observation optical system 13 and the laser marking optical system 22. More specifically, the faulty part of the semiconductor device D is aligned with the optical axis of the observation optical system 13 and the optical axis of the laser marking optical system 22. In other words, what is moved after the alignment is completed is the semiconductor device D. In other words, after the alignment is completed, the observation optical system 13 and the laser marking optical system 22 are not moved. As a result, the relative positional relationship between the observation optical system 13 and the laser marking optical system 22 is maintained as a result of the alignment.

[0092] <Marking process S30> As shown in FIG. 8, laser marking is performed on the marking locations mp (S30). The control unit 41b outputs a marking command for step S30 to the marking unit 20 and the device placement unit 30. Specifically, the laser light source 21 outputs a laser light. Laser marking is performed on all of the set marking locations mp. In addition, in the output operation of the laser light to each marking location mp, the image processing unit 41c may determine whether or not a mark image appears on the pattern image. If it is determined that a mark image does not appear on the pattern image, the image processing unit 41c again performs irradiation of the laser light. In parallel with this irradiation operation of the laser light, the image processing unit 41c generates a pattern image.

[0093] The following describes the effects of the analysis device 1 of this embodiment.

[0094] In the analysis device 1 and the semiconductor failure analysis method, first, the optical axis of the laser marking optical system 22 of the marking unit 20 is aligned with the optical axis of the observation optical system 13 of the analysis unit 10 based on the alignment target 50 provided on the wafer chuck 32. Then, while maintaining the positional relationship between the optical axis of the observation optical system 13 and the optical axis of the laser marking optical system 22, the laser light is irradiated to the marking position set on the semiconductor device D. In other words, after the optical axis of the observation optical system 13 is aligned with the optical axis of the laser marking optical system 22, the observation optical system 13 and the laser marking optical system 22 do not move relative to each other. Therefore, there is no deviation between the position indicated by the movement command value and the actual position that may occur due to movement. As a result, it is possible to reduce the deviation of the position indicated by the mark given by the marking unit 20 from the position of the failure location indicated by the analysis unit 10.

[0095] Before outputting the alignment command, the control unit 41b outputs an analysis command to the analysis unit 10 to cause the analysis unit 10 to analyze the fault location of the semiconductor device D. According to this configuration, it is possible to attach a mark that indicates the position of the fault location with high accuracy.

[0096] The marking command may cause the XY drive unit 33 to move the wafer chuck 32 to a marking position, and then irradiate the semiconductor device D with laser light. According to this configuration, after the optical axis of the laser marking optical system 22 is aligned with the optical axis of the observation optical system 13, the laser light can be irradiated to a desired position on the semiconductor device D while maintaining the absolute positions as well as the relative positions of the observation optical system 13 and the laser marking optical system 22. As a result, the deviation of the position indicated by the mark made by the marking unit 20 can be further reduced.

[0097] The alignment command causes the two-dimensional camera 15 to obtain a first image of the alignment target 50 from one side, causes the probing camera 24 to obtain a second image of the alignment target 50 from the other side, and moves the second drive unit so as to align the optical axis of the laser marking optical system 22 with the optical axis of the observation optical system 13 based on the first and second images. According to this configuration, the operation of aligning the optical axis of the laser marking optical system 22 with the optical axis of the observation optical system 13 can be performed reliably.

[0098] The alignment target 50 is provided at a position on the wafer chuck 32 different from the device holding portion 32a that holds the semiconductor device D. With this configuration, the optical axis of the laser marking optical system 22 can be aligned with the optical axis of the observation optical system 13 regardless of the type of the semiconductor device D.

[0099] The two-dimensional camera 15 captures a first image of the alignment target 50 viewed from one side. The probing camera 24 captures a second image of the target viewed from the other side. This configuration also ensures that the optical axis of the observation optical system 13 and the optical axis of the laser marking optical system 22 can be aligned with each other.

[0100] The alignment target 50 includes a light transmitting portion 50a that transmits light that can be detected by the two-dimensional camera 15 and the probing camera 24. This configuration also ensures that the optical axis of the laser marking optical system 22 can be aligned with the optical axis of the observation optical system 13.

[0101] In short, the first semiconductor failure analysis apparatus includes an analysis unit in which a first light detection unit receives a first light from a semiconductor device via a first optical system, and the first optical system is moved relatively to the semiconductor device by a first drive unit; a marking unit in which a second light detection unit receives a second light from the semiconductor device via a second optical system, and irradiates the semiconductor device with laser light via the second optical system, and the second optical system is moved relatively to the semiconductor device by a second drive unit; and a device arrangement device in which the chuck is disposed between the analysis unit and the marking unit to hold the semiconductor device and is provided with a target for aligning the optical axis of the first optical system with the optical axis of the second optical system, and the chuck is moved relatively to the analysis unit and the marking unit by a third drive unit. the target is detectable by the first optical detection unit from one side of the target and by the second optical detection unit from the other side of the target, and the control unit moves the chuck to a position where the first optical detection unit can detect the target, and then outputs an alignment command to the marking unit and the device placement unit to align the optical axis of the second optical system with the optical axis of the first optical system based on the target, and outputs a marking command to the marking unit and the device placement unit to irradiate the laser light to a marking position set on the semiconductor device while maintaining a positional relationship between the optical axis of the first optical system and the optical axis of the second optical system.

[0102] The second semiconductor failure analysis apparatus outputs, to the analysis section, an analysis command for analyzing a failure location of the semiconductor device by the analysis section before the control section of the first semiconductor failure analysis apparatus outputs the alignment command.

[0103] The third semiconductor failure analysis apparatus irradiates the laser light onto the semiconductor device after the marking command of the first or second semiconductor failure analysis apparatus causes the third driving unit to move the chuck to the marking position.

[0104] The alignment command of any of the first to third semiconductor failure analysis devices causes the first optical detection unit to acquire a first image of the target from one side, causes the second optical detection unit to acquire a second image of the target from the other side, and moves the second optical system so as to align the optical axis of the second optical system with the optical axis of the first optical system based on the first image and the second image.

[0105] In a fourth semiconductor failure analysis apparatus, the target of any one of the first to third semiconductor failure analysis apparatuses is provided at a location on the chuck different from a device holding portion that holds the semiconductor device.

[0106] The fifth semiconductor failure analysis device is configured so that the first optical detection unit of any of the first to fourth semiconductor failure analysis devices acquires a first image of the target viewed from one side, and the second optical detection unit acquires a second image of the target viewed from the other side.

[0107] In a sixth semiconductor failure analysis apparatus, the target of any one of the first to fifth semiconductor failure analysis apparatuses includes a light transmitting portion that transmits light detectable by the first light detection unit and the second light detection unit.

[0108] A first semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus, the semiconductor failure analysis apparatus comprising: an analysis unit in which a first light detection unit receives a first light from the semiconductor device via a first optical system, and the first optical system is moved relatively to the semiconductor device by a first drive unit; a marking unit in which a second light detection unit receives a second light from the semiconductor device via a second optical system, and irradiates the semiconductor device with laser light via the second optical system, and the second optical system is moved relatively to the semiconductor device by a second drive unit; and a chuck disposed between the analysis unit and the marking unit to hold the semiconductor device, and provided with a target for aligning an optical axis of the first optical system with an optical axis of the second optical system; the target is detectable by the first optical detection unit from one side of the target and by the second optical detection unit from the other side of the target, and the method has an alignment step of aligning an optical axis of the second optical system with an optical axis of the first optical system based on the target after moving the chuck to a position where the first optical detection unit can detect the target, and a marking step of irradiating the laser light to a marking position set on the semiconductor device while maintaining a positional relationship between the optical axis of the first optical system and the optical axis of the second optical system.

[0109] The second semiconductor failure analysis method is the first semiconductor failure analysis method further including, before the alignment step, an analysis step of analyzing a failure location of the semiconductor device by the analysis unit.

[0110] In a third semiconductor failure analysis method, the marking step of the first or second semiconductor failure analysis method includes irradiating the semiconductor device with the laser light after the third driving unit moves the chuck to the marking position.

[0111] In a fourth semiconductor failure analysis method, the alignment step of the first to third semiconductor failure analysis methods includes causing the first optical detection unit to acquire a first image of the target from one side, causing the second optical detection unit to acquire a second image of the target from the other side, and moving the second drive unit to align the optical axis of the second optical system with the optical axis of the first optical system based on the first and second images.

[0112] Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.

[0113] For example, the laser marking has been described as being performed until the laser light penetrates the metal layer ME and the surface of the substrate SiE in contact with the metal layer ME is exposed. However, this embodiment is not limited to this. The depth of the hole by the laser marking may be such that the mark image appears in the pattern image. Specifically, for example, the laser marking may be performed further after the metal layer ME is penetrated and the surface of the substrate SiE in contact with the metal layer ME is exposed. For example, when the thickness of the metal layer ME is 10 μm and the thickness of the substrate SiE is 500 μm, the hole by the laser marking may be formed about 1 μm deeper from the surface of the substrate SiE in contact with the metal layer ME. In addition, the laser marking does not necessarily have to be performed so as to penetrate the metal layer ME. For example, when the thickness of the metal layer ME is 10 μm and the thickness of the substrate SiE is 500 μm, the thickness of the metal layer ME at the location where the hole by the laser marking is formed may be about 50 nm. In other words, the hole does not have to reach the surface of the substrate SiE in contact with the metal layer ME.

[0114] In the above description, the generation of the pattern image is performed while the laser marking is being performed. However, the present invention is not limited to this embodiment. For example, the pattern image may be generated when the output of the laser light is stopped. In this case, the output of the laser light and the stop of the laser light, i.e., the generation of the pattern image, may be alternated at a predetermined interval.

[0115] When the wavelength of the laser light output from the laser light source 21 is 1000 nanometers or more, the observation optical system 13 may have an optical filter that blocks only the laser light having a wavelength of 1000 nanometers or more. Therefore, even if the laser light output from the laser light source 21 passes through the substrate SiE of the semiconductor device D, the laser light is blocked by the observation optical system 13. As a result, it is possible to prevent the photodetector from being damaged by the laser light.

[0116] The wavelength of the laser light output from the laser light source 21 may be less than 1000 nanometers. In this case, for example, when the semiconductor device D is configured with a substrate such as a silicon substrate, the laser light is absorbed by the substrate. As a result, it is possible to prevent a photodetector such as the two-dimensional camera 15 from being damaged by the laser light without providing an optical filter or the like.

[0117] The component that applies a stimulus signal to the semiconductor device D is not limited to the tester unit 11. As a stimulus signal application unit, which is a component that applies a stimulus signal to the semiconductor device D, a device that applies a voltage or a current to the semiconductor device D may be adopted. Then, the stimulus signal may be applied to the semiconductor device D using these devices.

[0118] <Second embodiment of semiconductor failure analysis device> As shown in FIG. 9, the semiconductor failure analysis apparatus of the second embodiment (hereinafter referred to as “analysis apparatus 1A”) includes a first analysis section 10A, a second analysis section 20A, a device placement section 30, a computer 40, and a stimulus signal application section 60.

[0119] The first analysis unit 10A has a first light source 12A, a first observation optical system 13A (first optical system), an XYZ stage 14 (first driving unit), and a first camera 15A (first light detection unit). The first light source 12A has a similar configuration to the light source 12 in the first embodiment. The first observation optical system 13A has a similar configuration to the observation optical system 13 in the first embodiment. The first camera 15A has a similar configuration to the two-dimensional camera 15 in the first embodiment.

[0120] The second analysis unit 20A has a laser light source 21, a second observation optical system 22A (second optical system), an XYZ stage 23 (second driving unit), a second camera 24A (second light detection unit), and a second light source 25A. The second observation optical system 22A has a similar configuration to the laser marking optical system 22 of the first embodiment. The second camera 24A has a similar configuration to the probing camera 24 of the first embodiment. The second light source 25A has a similar configuration to the illumination light source 25 of the first embodiment.

[0121] Either the first analysis unit 10A or the second analysis unit 20A may have a function of attaching a mark indicating a fault location. That is, either the first analysis unit 10A or the second analysis unit 20A may have a laser light source for marking that the marking unit 20 of the first embodiment has. The laser light source 21 of the second analysis unit 20A may be used as a laser light source for marking.

[0122] <Second embodiment of semiconductor failure analysis method> Next, the analysis process of the analysis device 1A will be described below. Fig. 10 is a flow diagram showing the main steps of the analysis process using the analysis device 1A.

[0123] <Alignment process S100A> First, the first observation optical system 13A and the second observation optical system 22A are aligned (S100A). The control unit 41b outputs an alignment command for step S100A to the second analysis unit 20A and the device placement unit 30. The XY drive unit 33 moves the wafer chuck 32 so that the alignment target 50 is captured in the field of view of the first observation optical system 13A (S101). The control unit 41b stores the movement amount of the semiconductor device D (wafer chuck 32).

[0124] Next, the optical axis of the first observation optical system 13A is aligned with the optical axis of the second observation optical system 22A (S102). First, the XYZ stage 23 moves the second observation optical system 22A so that the alignment target 50 is captured in the field of view of the second observation optical system 22A. Next, the second light source 25A outputs illumination light toward the alignment target 50. The illumination light passes through the light-transmitting portion 50a of the alignment target 50. The first camera 15A of the first observation optical system 13A obtains a transmission image by the light that has passed through the light-transmitting portion 50a of the alignment target 50. The first camera 15A outputs the transmission image to the computer 40. The second camera 24A obtains a reflection image by the light reflected by the opaque portion 50b of the alignment target 50. Then, the second camera 24A outputs the reflection image to the computer 40. The image processor 41c calculates the deviation of the optical axis of the second observation optical system 22A from the optical axis of the first observation optical system 13A by using the transmitted image and the reflected image. The movement of the second observation optical system 22A and the confirmation of the deviation amount are repeated until the deviation falls within the allowable range. When it is determined that the deviation falls within the allowable range, the alignment of the optical axis is completed. Note that, as an operation for bringing the deviation within the allowable range, the second observation optical system 22A may be moved while the position of the first observation optical system 13A is fixed. The first observation optical system 13A may be moved while the position of the second observation optical system 22A is fixed. Furthermore, both the first observation optical system 13A and the second observation optical system 22A may be moved.

[0125] After the alignment of the optical axis is completed, the XY driving unit 33 moves the wafer chuck 32 so that the semiconductor device D is captured in the field of view of the first observation optical system 13A and the second observation optical system 22A (S103). At this time, the control unit 41b may control the XY driving unit 33 based on the movement amount stored when the semiconductor device D is evacuated. In addition, the relative positions of the first observation optical system 13A and the second observation optical system 22A and the semiconductor device D may be controlled using image data output from the first camera 15A and the second camera 24A. In this case, the only object to be moved is the semiconductor device D. Since the semiconductor device D is evacuated immediately after the alignment of the optical axis is completed, the semiconductor device D does not exist in the field of view of the first observation optical system 13A and the second observation optical system 22A. Therefore, after the alignment of the optical axis is completed, the semiconductor device D is accommodated in the field of view of the first observation optical system 13A and the second observation optical system 22A. More specifically, the semiconductor device D is placed on the optical axis of the first observation optical system 13A and the optical axis of the second observation optical system 22A. That is, what is moved after the alignment is completed is the semiconductor device D. In other words, after the alignment is completed, the first observation optical system 13A and the second observation optical system 22A are not moved. As a result, the relative positional relationship between the first observation optical system 13A and the second observation optical system 22A is maintained as a result of the alignment.

[0126] <Analysis process S110A> Next, the fault location of the semiconductor device D is identified (S110A). In the analysis step S110A, a so-called light emission analysis is performed. When performing the light emission analysis, the first camera 15A and the second camera 24A employ imaging devices capable of detecting light of a wavelength that passes through the SiE substrate of the semiconductor device D. For example, a camera equipped with a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor may be employed. Also, an InGaAs camera, an MCT camera, or the like may be employed.

[0127] First, the computer 40 stops the irradiation of illumination light from the first light source 12A and the second light source 25A. Next, the computer 40 causes the stimulus signal application unit 60 to output a stimulus signal to the semiconductor device D. When the metal layer ME of the semiconductor device D includes a faulty portion, the metal layer ME emits emission light at the faulty portion. The light emitted by the metal layer ME is incident on the first observation optical system 13A through one surface of the substrate SiE. As a result, the first camera 15A outputs an image corresponding to the incident light to the computer 40. Similarly, the light emitted by the metal layer ME is incident on the second observation optical system 22A through the other surface of the substrate SiE. As a result, the second camera 24A outputs an image corresponding to the incident light to the computer 40. The computer 40 identifies the faulty portion by identifying the light emission position from these image data.

[0128] The imaging operation of first camera 15A and second camera 24A can take a first mode and a second mode. An imaging operation refers to an operation capable of outputting image data when light is input. Therefore, "performing an imaging operation" means putting the camera in a state in which light can reach the camera and putting the camera in a state in which the camera that has received the light can output image data.

[0129] As a first mode, the imaging operation of the first camera 15A and the imaging operation of the second camera 24A may be performed in parallel. That is, while the imaging operation of the first camera 15A is being performed, the imaging operation of the second camera 24A may be performed. More specifically, the computer 40 sets the first observation optical system 13A in a state where light can reach the first camera 15A and the first camera 15A that receives the light in a state where it can output image data. Furthermore, the computer 40 sets the second observation optical system 22A in a state where light can reach the second camera 24A and the second camera 24A that receives the light in a state where it can output image data.

[0130] In the first embodiment, when light is output from both one surface and the other surface of the semiconductor device D, image data is output from both the first camera 15A and the second camera 24A. However, when emission light occurs, the emission light is not necessarily output from both one surface and the other surface of the semiconductor device D. For example, one emission light may be blocked in the wiring layer. That is, light may be output from one surface of the semiconductor device D, but not from the other surface. In the first embodiment, both the first camera 15A and the second camera 24A are in a state where they can output image data. However, since light is incident only on the first camera 15A, only the first camera 15A outputs image data. Conversely, light may be output from the other surface of the semiconductor device D, but not from one surface. In this case, only the second camera 24A outputs image data.

[0131] As a second aspect, the imaging operation of first camera 15A and the imaging operation of second camera 24A may be performed alternately. That is, the imaging operation of first camera 15A is performed in a first period. The imaging operation of second camera 24A is performed in a second period that does not overlap with the first period.

[0132] More specifically, in the first period, the computer 40 sets the first observation optical system 13A in a state where light can reach the first camera 15A, and sets the first camera 15A, which receives the light, in a state where it can output image data. Furthermore, the computer 40 sets the second observation optical system 22A in a state where light is not allowed to reach the second camera 24A, and / or sets the second camera 24A, which receives the light, in a state where it does not output image data. In the second period, the computer 40 sets the first observation optical system 13A in a state where light is not allowed to reach the first camera 15A, and / or sets the first camera 15A, which receives the light, in a state where it does not output image data. Furthermore, the computer 40 sets the second observation optical system 22A in a state where light can reach the second camera 24A, and sets the second camera 24A, which receives the light, in a state where it can output image data.

[0133] <Marking process S120A> Laser marking is performed on the marking locations mp (S120A). The control unit 41b outputs a marking command for step S120A to the second analysis unit 20A and the device placement unit 30. Specifically, the laser light source 21 outputs a laser light. Laser marking is performed on all of the set marking locations mp. In addition, in the output operation of the laser light to each marking location mp, the image processing unit 41c may determine whether or not a mark image appears on the pattern image. If it is determined that a mark image does not appear on the pattern image, the image processing unit 41c again performs irradiation of the laser light. In parallel with this irradiation operation of the laser light, the image processing unit 41c generates a pattern image.

[0134] The analysis device 1A includes a first analysis unit 10A in which a first camera 15A receives light emitted from a semiconductor device D via a first observation optical system 13A, and the first observation optical system 13A moves relatively with respect to the semiconductor device D by a first drive unit, and a second analysis unit 20A in which a second camera 24A receives light emitted from the semiconductor device D via a second observation optical system 22A, and the second observation optical system 22A moves relatively with respect to the semiconductor device D by a second drive unit, and a semiconductor device 20A is disposed between the first analysis unit 10A and the second analysis unit 20A. The apparatus further comprises a device placement section 30 that holds a semiconductor device D and has a wafer chuck 32 provided with an alignment target 50 for aligning the optical axis of a first observation optical system 13A with the optical axis of a second observation optical system 22A, the wafer chuck 32 moving relatively to the first analysis section 10A and the second analysis section 20A, a stimulus signal application section 60 that applies a stimulus signal to the semiconductor device D, and a control section 41b that outputs commands to the first analysis section 10A, the second analysis section 20A, the device placement section 30, and the stimulus signal application section 60. The alignment target 50 is detectable by the first analysis section 10A from one side of the alignment target 50 and is detectable by the second analysis section 20A from the other side of the alignment target 50. After moving the wafer chuck 32 to a position where the first camera 15A can detect the alignment target 50, the control unit 41b outputs an alignment command to the second analysis unit 20A and the device placement unit 30 to align the optical axis of the second observation optical system 22A with the optical axis of the first observation optical system 13A with reference to the alignment target 50. Furthermore, the control unit 41b outputs an analysis command to the first analysis unit 10A, the second analysis unit 20A, the stimulus signal application unit 60, and the device placement unit 30 to apply a stimulus signal to the semiconductor device D while maintaining the positional relationship between the optical axis of the first observation optical system 13A and the optical axis of the second observation optical system 22A, and to receive light from the semiconductor device D emitted in response to the stimulus signal from at least one of the first camera 15A and the second camera 24A.

[0135] A semiconductor failure analysis method for analyzing a semiconductor device D using the analysis apparatus 1A includes an alignment process (S100A) for aligning the optical axis of the second observation optical system 22A with the optical axis of the first observation optical system 13A based on the alignment target 50 after moving the wafer chuck 32 to a position where the first camera 15A can detect the alignment target 50, and an analysis process (S120A) for applying a stimulus signal to the semiconductor device D while maintaining the positional relationship between the optical axis of the first observation optical system 13A and the optical axis of the second observation optical system 22A, and receiving light from the semiconductor device D emitted in response to the stimulus signal by at least one of the first camera 15A or the second camera 24A.

[0136] The analysis apparatus 1A and the semiconductor failure analysis method apply a stimulus signal to the semiconductor device D while maintaining the positional relationship between the optical axis of the first observation optical system 13A and the optical axis of the second observation optical system 22A, and receive light from the semiconductor device D emitted in response to the stimulus signal by at least one of the first camera 15A and the second camera 24A. Therefore, the optical axes of the first observation optical system 13A and the second observation optical system 22A that receive the light from the semiconductor device D are aligned, so that the fault location of the semiconductor device D can be detected satisfactorily.

[0137] <Modification> In the analysis step, an analysis different from the light emission analysis described above may be performed. For example, a heat generation analysis may be performed in the analysis step. In this case, the stimulus signal application unit 60 applies a modulated current with a relatively low frequency as the stimulus signal. For example, if a short circuit is included inside the semiconductor device D, the short circuit generates heat due to the modulated current. As a result, a heat source is generated in the semiconductor device D. The temperature of the heat source that generates heat due to the modulated current changes periodically according to the frequency of the modulated current. The change in temperature affects the refractive index of the member around the heat source through which the irradiated light and the reflected light pass. This change in the refractive index brings about a change in the intensity of the reflected light, and as a result, the reflectance, which is the degree of the intensity of the reflected light relative to the intensity of the irradiated light, changes. The change in reflectance caused by the temperature change of the heat source is used as a response to the stimulus signal. As a result, a short circuit, which is an example of a fault location included in the semiconductor device D, can be identified.

[0138] <Modification of Semiconductor Failure Analysis Apparatus> 11, a modified semiconductor failure analysis apparatus (hereinafter referred to as "analysis apparatus 1S") includes a first analysis section 10S, a second analysis section 20S, a device placement section 30, a computer 40, and a stimulus signal application section 60. The first analysis section 10S has a first infrared camera 15S instead of the first camera 15A. Moreover, the second analysis section 20S has a second infrared camera 24S instead of the second camera 24A.

[0139] The first infrared camera 15S is a light detection unit that detects wavelengths different from visible light. The first infrared camera 15S detects, for example, light with a wavelength of 2 μm to 10 μm, which is heat rays. An InSb camera or the like may be used as the first infrared camera 15S. The first infrared camera 15S can acquire an image showing the distribution of the emissivity of the semiconductor device D. The first infrared camera 15S outputs image data by capturing an image of heat rays from the semiconductor device D. The infrared information corresponding to the image data can be used to identify a heat generating location in the semiconductor device D. By identifying the heat generating location, a fault location in the semiconductor device D can be identified. The second infrared camera 24S has a similar configuration to the first infrared camera 15S.

[0140] The image processing unit 41c of the computer 40 generates an infrared image based on the image data described above. The image processing unit 41c also generates a pattern image based on the detection signal. The image processing unit 41c then generates a superimposed image in which the infrared image is superimposed on the pattern image as an analysis image.

[0141] In addition, when detecting heat rays, unlike when obtaining a visible light image, illumination light is not required. Therefore, the analysis device 1S can omit the first light source 12A and the second light source 25A. When the first light source 12A is omitted, the first observation optical system 13A can omit the beam splitter 13b. Similarly, when the second light source 25A is omitted, the second observation optical system 22A can omit the switching unit 22b, which is a beam splitter.

[0142] <Modification of Semiconductor Failure Analysis Method> Next, the analysis process of the analysis device 1S will be described below. Fig. 12 is a flow diagram showing the main steps of the analysis process using the analysis device 1S.

[0143] <Alignment process S100S> The alignment step S100S of the modified example is similar to the alignment step S100A of the second embodiment.

[0144] <Analysis process S110S> Next, the fault location of the semiconductor device D is identified (S110S). First, the first infrared camera 15S measures heat rays from the semiconductor device D, and the image processing unit 41c generates an infrared image. It is assumed that a stimulus signal such as a test pattern is applied by the stimulus signal application unit 60. The first infrared camera 15S acquires first image data including heat generated by the semiconductor device D. The first infrared camera 15S sends a plurality of pieces of image data captured continuously at a predetermined exposure time to the computer 40 as first image data. The image processing unit 41c adds the plurality of pieces of image data. The first image data is generated by the addition process. The first image data includes information on the heat generated by the semiconductor device D and the shape of the elements forming the semiconductor device D. Next, the application of the stimulus signal by the stimulus signal application unit 60 is stopped. The first infrared camera 15S acquires image data including only information on the shape of the elements formed by the semiconductor device D. The first infrared camera 15S outputs a plurality of pieces of image data captured continuously at a predetermined exposure time to the computer 40. The image processing unit 41c adds the multiple pieces of image data. Second image data is generated by the addition process. The second image data includes only information on the shapes of the elements that form the semiconductor device D. Then, the image processing unit 41c obtains the difference between the first image data and the second image data. As a result, an infrared image including only the heat of the semiconductor device D is generated. The image processing unit 41c outputs a superimposed image in which the infrared image is superimposed on the second image data or the first image data as an analysis image. Also, the image processing unit 41c outputs the second image data as a pattern image.

[0145] The second analysis unit 20S also performs the same process as the heat generation analysis operation in the first analysis unit 10S described above. The heat generation analysis operation in the first analysis unit 10S and the heat generation analysis operation in the second analysis unit 20S may be performed in parallel. These operations may also be performed alternately.

[0146] <Marking process S120S> The marking step S120S of the modified example is similar to the marking step S120A of the second embodiment.

[0147] The analysis apparatus 1S and the semiconductor failure analysis method of the modified example also perform a process of detecting a failure location in a state where the optical axis of the first observation optical system 13S and the optical axis of the second observation optical system 22S are aligned, and the failure location of the semiconductor device D can be detected satisfactorily.

[0148] <Third embodiment of semiconductor failure analysis device> As shown in FIG. 13, the semiconductor failure analysis device of the third embodiment (hereinafter, referred to as "analysis device 1B") includes a first analysis unit 10B, a second analysis unit 20B, a device placement unit 30, a computer 40, a stimulus signal application unit 60, and an electrical signal acquisition unit 61. The analysis device 1B outputs light from the first analysis unit 10B and the second analysis unit 20B. The light output from the first analysis unit 10B is irradiated onto one surface of the substrate SiE of the semiconductor device D. The light output from the second analysis unit 20B is irradiated onto the other surface of the substrate SiE of the semiconductor device D. The analysis device 1B analyzes the failure location of the semiconductor device D by using an electrical signal generated by the irradiation of light. The semiconductor device D irradiated with light may or may not receive a stimulus signal.

[0149] The first analysis unit 10B has a first light source 12B, a first observation optical system 13B (first optical system), an XYZ stage 14 (first driving unit), and a first camera 15B (first light detection unit). The first light source 12B generates light to be irradiated onto the semiconductor device D. The details of the first light source 12B are determined according to the analysis method.

[0150] For example, in an analysis in which a semiconductor device D is irradiated with coherent light such as a laser light, a solid-state laser light source or a semiconductor laser light source may be adopted as the first light source 12B. In an analysis in which an OBIRCH (Optical Beam Induced Resistance Change) image or an SDL (Soft Defect Localization) image is acquired, the first light source 12B outputs laser light in a wavelength band in which the semiconductor device D does not generate electric charges (carriers). For example, in an analysis of a semiconductor device D made of silicon, the first light source 12B outputs laser light in a wavelength band greater than 1200 nm. The first light source 12B preferably outputs laser light in a wavelength band of about 1300 nm. In addition, in an analysis in which an OBIC image or a LADA (Laser Assisted Device Alteration) image is acquired, the first light source 12B outputs light in a wavelength band in which the semiconductor device D generates electric charges (carriers). In an analysis in which an OBIC image or a LADA image is acquired, the first light source 12B outputs light in a wavelength band of 1200 nm or less. For example, the first light source 12B outputs a laser beam in a wavelength band of about 1064 nm.

[0151] In an analysis in which the semiconductor device D is irradiated with incoherent light, a super luminescent diode (SLD), an amplified spontaneous emission (ASE), a light emitting diode (LED), or the like may be used as the first light source 12B.

[0152] The light output from the first light source 12B is guided to the first observation optical system 13B via a polarization-preserving single mode optical coupler (not shown) and a polarization-preserving single mode optical fiber for the probe light. The first observation optical system 13B has an objective lens 13a, a beam splitter 13b, and a first optical scanning unit 13s. The first optical scanning unit 13s scans an irradiation spot on the back surface of the semiconductor device D. The first optical scanning unit 13s is composed of an optical scanning element such as a galvanometer mirror or a MEMS mirror. The objective lens 13a focuses the light guided by the first optical scanning unit 13s on the irradiation spot. The first optical scanning unit 13s is controlled by the control unit 41b of the computer 40.

[0153] The first camera 15B detects the reflected light of the semiconductor device D in response to the laser light. The first camera 15B outputs a detection signal to the computer 40. The first camera 15B is, for example, a photodiode, an avalanche photodiode, a photomultiplier tube, an area image sensor, or the like.

[0154] The second analysis unit 20B has a second light source 21B, a second observation optical system 22B (second optical system), and a second camera 24B (second light detection unit). The second light source 21B has a configuration similar to that of the first light source 12B. The second observation optical system 22B has an objective lens 22a, a switching unit 22b (beam splitter), and a second optical scanning unit 22s. The second optical scanning unit 22s has a configuration similar to that of the first optical scanning unit 13s. The second camera 24B has a configuration similar to that of the probing camera 24 of the first embodiment.

[0155] The electrical signal acquiring unit 61 is electrically connected to the semiconductor device D. The electrical signal acquiring unit 61 detects an electrical signal generated in the semiconductor device D in response to the laser light. The electrical signal acquiring unit 61 outputs to the computer 40 an electrical signal characteristic value in response to the detected electrical signal.

[0156] The image processing unit 41c of the computer 40 outputs an electric signal image based on the electric signal characteristic value. The electric signal image is an image obtained by associating the electric signal characteristic value with the scanning positions of the laser light by the first optical scanning unit 13s and the second optical scanning unit 22s. The image processing unit 41c also outputs an optical reflection image based on the detection signal. Then, the image processing unit 41c superimposes the electric signal image on the optical reflection image. As a result, the image processing unit 41c outputs a superimposed image in which the electric signal image is superimposed on the optical reflection image as an analysis image.

[0157] The electric signal image is, for example, an OBIC image which is a photovoltaic current image, an OBIRCH image which is an electric quantity change image, an SDL image which is a correct / incorrect information image, and a LADA image.

[0158] The OBIC image is based on the photoelectric current generated by laser irradiation, and is an image of the current value or current change value of the photoelectric current as an electrical signal characteristic value.

[0159] The OBIRCH image is based on the resistance value occurring at the position where the semiconductor device D is irradiated with the laser light. A constant current is applied to the semiconductor device D irradiated with the laser light. The change in the resistance value can be obtained as a voltage value or a change in voltage. The OBIRCH image is an image of the voltage value or an electrical signal characteristic value indicating the change in voltage. Note that when the OBIRCH image is obtained, a constant voltage may be applied to the semiconductor device D irradiated with the laser light. In this case, the change in the resistance value at the irradiated position in the semiconductor device D can be obtained as a change in current value. The OBIRCH image is an image of the electrical signal characteristic value indicating the change in current value.

[0160] An SDL image is an image of information related to a malfunction state (e.g., a PASS / FAIL signal). A semiconductor device D to which a stimulus signal such as a test pattern has been applied is irradiated with laser light. This laser light has a wavelength at which carriers are not excited. By applying the stimulus signal and irradiating the laser light, a malfunction state can be detected. Then, the information related to the malfunction is obtained as a brightness value. An SDL image is an image based on the brightness value.

[0161] LADA images are also images of information related to malfunction states (e.g., PASS / FAIL signals). However, the analysis for obtaining LADA images differs from the analysis for obtaining SDL images in that the semiconductor device D is irradiated with laser light having a wavelength that excites carriers. Similar to SDL images, information related to malfunctions is obtained as brightness values ​​by applying a stimulus signal and irradiating with laser light, and image data is generated based on the brightness values.

[0162] Either the first analysis unit 10B or the second analysis unit 20B may have a function of attaching a mark indicating a fault location. In other words, either the first analysis unit 10B or the second analysis unit 20B may have a laser light source for marking that the marking unit 20 of the first embodiment has.

[0163] <Semiconductor failure analysis method according to the third embodiment> Next, the analysis process of the analysis device 1B will be described below. Fig. 14 is a flow diagram showing the main steps of the analysis process using the analysis device 1B.

[0164] <Alignment process S100B> First, the first observation optical system 13B and the second observation optical system 22B are aligned (S100B). The alignment here means that the optical axis of the first observation optical system 13B and the optical axis of the second observation optical system 22B are aligned to eliminate the misalignment between the center of the first optical scanning area related to the first observation optical system 13B and the center of the second optical scanning area related to the second observation optical system 22B. The control unit 41b outputs an alignment command for step S100B to the second analysis unit 20B and the device placement unit 30. The XY drive unit 33 moves the wafer chuck 32 so that the alignment target 50 is captured in the field of view of the first observation optical system 13B (S101). The control unit 41b stores the movement amount of the semiconductor device D. The movement amount may be that of the wafer chuck 32.

[0165] Next, the first optical scanning region of the first observation optical system 13B and the second optical scanning region of the second observation optical system 22B are aligned (S102B). This means that the optical axis of the first observation optical system 13B and the optical axis of the second observation optical system 22B are aligned to align the center of the first optical scanning region related to the first observation optical system 13B with the center of the second optical scanning region related to the second observation optical system 22B. First, the XYZ stage 23 moves the second observation optical system 22B so that the alignment target 50 is captured in the field of view of the second observation optical system 22B. Next, the second light source 25B outputs illumination light toward the alignment target 50. The illumination light passes through the light transmitting portion 50a of the alignment target 50. The first camera 15B of the first observation optical system 13B obtains a transmission image by the light that has passed through the light transmitting portion 50a of the alignment target 50. The first camera 15B outputs the transmission image to the computer 40. The second camera 24B obtains a reflected image by the light reflected by the opaque portion 50b of the alignment target 50. The second camera 24B then outputs the reflected image to the computer 40. The image processor 41c calculates the deviation of the optical axis of the second observation optical system 22B from the optical axis of the first observation optical system 13B using the transmitted image and the reflected image. The second observation optical system 22B is moved and the deviation amount is confirmed repeatedly until the deviation falls within the allowable range. When it is determined that the deviation falls within the allowable range, the alignment of the optical axis is completed. This allows the center of the first optical scanning area related to the first observation optical system 13B to be aligned with the center of the second optical scanning area related to the second observation optical system 22B. Note that, as an operation for bringing the deviation within the allowable range, the second observation optical system 22B may be moved while the position of the first observation optical system 13B is fixed. The first observation optical system 13B may be moved while the position of the second observation optical system 22B is fixed. Furthermore, both the first observation optical system 13B and the second observation optical system 22B may be moved.

[0166] After the alignment of the optical scanning area is completed, the XY driving unit 33 controls the X-axis direction and the Y-axis direction to move the wafer chuck 32 so that the semiconductor device D is captured in the field of view of the first observation optical system 13B and the second observation optical system 22B (S103). At this time, the control unit 41b may control the XY driving unit 33 based on the movement amount stored when the semiconductor device D is evacuated. In addition, the relative positions of the first observation optical system 13B and the second observation optical system 22B and the semiconductor device D may be controlled using image data output from the first camera 15B and the second camera 24B. In this case, the only object to be moved is the semiconductor device D. Immediately after the alignment of the scanning area is completed, the semiconductor device D is evacuated, so that the semiconductor device D does not exist in the field of view of the first observation optical system 13B and the second observation optical system 22B. Therefore, after the alignment of the scanning area is completed, the semiconductor device D is placed in the field of view of the first observation optical system 13B and the second observation optical system 22B. More specifically, the semiconductor device D is placed in the first optical scanning region of the first observation optical system 13B and the second optical scanning region of the second observation optical system 22B. That is, what is moved after the alignment is completed is the semiconductor device D. In other words, after the alignment is completed, the first observation optical system 13B and the second observation optical system 22B are not moved. As a result, the relative positional relationship between the first optical scanning region of the first observation optical system 13B and the second optical scanning region of the second observation optical system 22B is maintained as a result of the alignment.

[0167] <Analysis process S110B> Next, the fault location of the semiconductor device D is identified (S110B). In the analysis step S110B, a signal analysis is performed by light irradiation. The first observation optical system 13B irradiates one surface of the semiconductor device D with the first laser light. The second observation optical system 22B irradiates the other surface of the semiconductor device D with the second laser light. The irradiation of the first laser light and the second laser light may be performed in parallel in time. That is, the period during which the first laser light is irradiated may have an overlapping portion with the period during which the second laser light is irradiated. Also, the period during which the first laser light is irradiated may not overlap with the period during which the second laser light is irradiated. That is, the irradiation of the second laser light may be started after the irradiation of the first laser light is stopped. In the analysis step S110B, several electrical signal images can be obtained according to the characteristics of the first laser light and the second laser light and the state of the semiconductor device D irradiated with the laser light. The electric signal image is, for example, an OBIC image which is a photovoltaic current image, an OBIRCH image which is an electric quantity change image, an SDL image which is a correct / incorrect information image, and a LADA image.

[0168] As a first analysis, the semiconductor device D is irradiated with a first laser light and a second laser light. In the first analysis, the stimulus signal application unit 60 does not apply a stimulus signal to the semiconductor device D. When the semiconductor device D receives the laser light, a photo-induced current may be generated. The electrical signal acquisition unit 61 outputs the current value or the current change value of the photo-induced current as an electrical signal characteristic value. An electrical signal image based on the electrical signal characteristic value obtained in the first analysis is an OBIC image.

[0169] For the second analysis, the first laser light and the second laser light are irradiated onto the semiconductor device D. In the second analysis, the stimulus signal application unit 60 applies a constant current, which is a stimulus signal, to the semiconductor device D. The stimulus signal may be a constant voltage. When the semiconductor device D that has received the stimulus signal is irradiated with laser light, the resistance value at the irradiated position on the semiconductor device D changes. The electrical signal acquisition unit 61 outputs a voltage value or a change in voltage corresponding to the change in resistance value as an electrical signal characteristic value. An electrical signal image based on the electrical signal characteristic value obtained in the second analysis is an OBIRCH image.

[0170] In the third analysis, the semiconductor device D is irradiated with a first laser light and a second laser light. In the third analysis, lasers having wavelengths that do not excite carriers are used as the first laser light and the second laser light. Furthermore, in the third analysis, the stimulus signal application unit 60 applies a stimulus signal such as a test pattern. When the semiconductor device D that has received the stimulus signal is irradiated with laser light having a wavelength that does not excite carriers, a malfunction state of the semiconductor device D can be detected. The electrical signal acquisition unit 61 outputs information related to the malfunction state (e.g., a PASS / FAIL signal) as an electrical signal characteristic value. An image obtained by converting the electrical signal characteristic value obtained in the third analysis into a brightness value is an SDL image.

[0171] In the fourth analysis, the semiconductor device D is irradiated with a first laser light and a second laser light. In the fourth analysis, lasers having a wavelength at which carriers are excited are used as the first laser light and the second laser light. Furthermore, in the fourth analysis, the stimulus signal application unit 60 applies a stimulus signal such as a test pattern. When the semiconductor device D that has received the stimulus signal is irradiated with a laser light having a wavelength at which carriers are excited, a malfunction state of the semiconductor device D can be detected. The electrical signal acquisition unit 61 outputs information related to the malfunction state (e.g., a PASS / FAIL signal) as an electrical signal characteristic value. An image obtained by converting the electrical signal characteristic value obtained in the fourth analysis into a brightness value is a LADA image.

[0172] <Marking process S120B> The marking step S120B of the third embodiment is similar to the marking step S120A of the second embodiment. When marking is performed by the second observation optical system 22B, the second observation optical system 22B may include a laser light source for marking, an XYZ stage, and an illumination light source.

[0173] The analysis device 1B includes a first analysis unit 10B that irradiates the semiconductor device D with light generated by a first light source 12B via a first observation optical system 13B having a first optical scanning unit 13s, a second analysis unit 20B that irradiates the semiconductor device D with light generated by a second light source 21B via a second observation optical system 22B having a second optical scanning unit 22s, and a second analysis unit 20B that is disposed between the first analysis unit 10B and the second analysis unit 20B to hold the semiconductor device D and to be aligned in a light scanning region of the first observation optical system 13B. The apparatus includes a device placement unit 30 having a wafer chuck 32 provided with an alignment target 50 for alignment with the optical scanning region of the second observation optical system 22B, the wafer chuck 32 moving relatively to the first analysis unit 10B and the second analysis unit 20B, an electrical signal acquisition unit 61 receiving an electrical signal output by the semiconductor device D, and a control unit 41b outputting commands to the first analysis unit 10B, the second analysis unit 20B, the device placement unit 30, and the electrical signal acquisition unit 61. The alignment target 50 is detectable by the first analysis unit 10B from one side of the alignment target 50, and is detectable by the second analysis unit 20B from the other side of the alignment target 50. After the first analysis unit 10B moves the wafer chuck 32 to a position where the alignment target 50 can be detected, the control unit 41b outputs an alignment command to the second analysis unit 20B and the device placement unit 30 to align the optical scanning region of the second observation optical system 22B with the optical scanning region of the first observation optical system 13B with reference to the alignment target 50. Furthermore, the control unit 41b outputs an analysis command to the first analysis unit 10B, the second analysis unit 20B, the electrical signal acquisition unit 61, and the device placement unit 30 to irradiate light from at least one of the first analysis unit 10B and the second analysis unit 20B to the semiconductor device D while maintaining the positional relationship between the optical scanning region of the first observation optical system 13B and the optical scanning region of the second observation optical system 22B, and to receive an electrical signal from the semiconductor device D by the electrical signal acquisition unit 61.

[0174] A semiconductor failure analysis method for analyzing a semiconductor device D using the analysis apparatus 1B includes an alignment step (S100B) of aligning the optical scanning region of the second observation optical system 22B with the optical scanning region of the first observation optical system 13B based on the alignment target 50 after the first analysis unit 10B moves the wafer chuck 32 to a position where the alignment target 50 can be detected, and an analysis step (S110B) of irradiating the semiconductor device D with light from at least one of the first analysis unit 10B and the second analysis unit 20B while maintaining the positional relationship between the optical scanning region of the first observation optical system 13B and the optical scanning region of the second observation optical system 22B, and receiving an electrical signal from the semiconductor device D by the electrical signal acquisition unit 61.

[0175] The analysis device 1B irradiates light onto the semiconductor device D while maintaining the positional relationship between the optical scanning region of the first observation optical system 13B and the optical scanning region of the second observation optical system 22B. Therefore, the optical scanning regions of the first observation optical system 13B and the second observation optical system 22B coincide with each other, so that the defective portion of the semiconductor device D can be detected satisfactorily.

[0176] <Fourth embodiment of semiconductor failure analysis device> The semiconductor failure analysis device according to the fourth embodiment identifies the failure location by an optical probing technique called EOP or EOFM (Electro-Optical Frequency Mapping). In addition, optical probed thermo-reflectance image mapping (OPTIM) may be performed using EOFM. The optical probing technique identifies the position of a circuit operating at a target frequency. In the optical probing technique, light emitted from a light source is irradiated onto an integrated circuit. The light reflected by the integrated circuit is detected by an optical sensor. A signal component having a target frequency is extracted from the detection signal output from the optical sensor. The amplitude energy of the extracted signal component is displayed as a time lapse. In addition, the amplitude energy of the extracted signal component is displayed as a two-dimensional mapping.

[0177] That is, the optical probing technique analyzes failures in the semiconductor device D based on the intensity modulation of light from the semiconductor device D during operation. The semiconductor failure analysis device applies an electric signal having a predetermined modulation frequency to the semiconductor device D. In this case, the modulation frequency is often higher than the frequency of the stimulus signal used in the analysis to identify the heat source position. For example, the semiconductor failure analysis device applies a drive current having the same frequency as the drive signal of the semiconductor device D as the stimulus signal.

[0178] 15, the semiconductor failure analysis apparatus of the fourth embodiment (hereinafter referred to as "analysis apparatus 1C") includes a first analysis section 10C, a second analysis section 20C, a device placement section 30, a computer 40, and a stimulus signal application section 60. That is, the analysis apparatus 1C of the fourth embodiment does not include the electrical signal acquisition section 61 that the analysis apparatus 1B of the third embodiment has.

[0179] The first analysis unit 10C has a first light source 12C, a first observation optical system 13C (first optical system), an XYZ stage 14 (first driving unit), and a first camera 15C (first light detection unit). The first light source 12C is similar to the first light source 12B in the second embodiment. The first observation optical system 13C is similar to the first observation optical system 13B in the second embodiment. The first camera 15C is similar to the first camera 15B in the second embodiment.

[0180] The second analysis unit 20C has a second light source 21C, a second observation optical system 22C (second optical system), and a second camera 24C (second light detection unit). The second light source 21C is similar to the second light source 21B in the second embodiment. The second observation optical system 22C is similar to the second observation optical system 22B in the second embodiment. The second camera 24C is similar to the second camera 24B in the second embodiment.

[0181] Either the first analysis unit 10C or the second analysis unit 20C may have a function of attaching a mark indicating a fault location. That is, either the first analysis unit 10C or the second analysis unit 20C may have a laser light source for marking that the marking unit 20 of the first embodiment has.

[0182] <Semiconductor failure analysis according to the fourth embodiment> Next, the analysis process of the analysis device 1C will be described below with reference to Fig. 16, which is a flow chart showing the main steps of the analysis process using the analysis device 1C.

[0183] <Alignment process S100C> The alignment step S100C of the fourth embodiment is similar to the alignment step S100B of the third embodiment. Therefore, the step (S102C) of aligning the optical scanning region included in the alignment step S100C of the fourth embodiment is similar to the step S102B of the third embodiment.

[0184] <Analysis process S110C> Next, the fault location of the semiconductor device D is identified (S110C). The first analysis unit 10C irradiates the semiconductor device D with light from the first light source 12C by the first optical scanning unit 13s. The light output from the first light source 12C is, for example, light in a wavelength band of 530 nm or more. The light output from the first light source 12C is preferably light in a wavelength band of 1064 nm or more. The light is reflected on the surface of the semiconductor device D. The reflected light is incident on the first analysis unit 10C. The incident light is detected by the first camera 15C. The first camera 15C outputs information based on the reflected light to the computer 40. The image processing unit 41c of the computer 40 generates an optical reflection image using the information output by the first camera 15C. In this operation, the stimulus signal application unit 60 does not output a stimulus signal.

[0185] Next, the stimulus signal applying unit 60 outputs a stimulus signal such as a test pattern to the semiconductor device D. The first analyzing unit 10C irradiates the semiconductor device D that has received the stimulus signal with light from the first light source 12C. In this operation, the light from the first light source 12C is irradiated to an irradiation position selected by the user. The user may input the irradiation position to the computer 40 using the input unit 41e while viewing the optical reflection image displayed on the display unit 41d. The first camera 15C detects the reflected light from the semiconductor device D that has received the stimulus signal. Then, the first camera 15C outputs information based on the reflected light to the computer 40.

[0186] The semiconductor device D receiving the stimulus signal operates elements that constitute the semiconductor device D. The reflected light from the semiconductor device D whose elements are operating is modulated in accordance with the operation of the elements.

[0187] The image processor 41c of the computer 40 uses the detection signal output by the first camera 15C to generate a signal waveform. The image processor 41c displays the signal waveform on the display unit 41d. Then, while changing the irradiation position based on the optical reflection image described above, the computer 40 acquires the detection signal and generates a signal waveform. The generated signal waveform can be used to identify the fault location.

[0188] The image processor 41c may generate an electro-optical frequency mapping image (EOFM image). An EOFM image is an image of phase difference information between a detection signal and a stimulus signal such as a test pattern, associated with an irradiation position. In this case, the phase difference information can be obtained from an AC component extracted from the detection signal. An optical reflection image can be obtained by imaging a DC component extracted simultaneously with the AC component, associated with the irradiation position. Then, a superimposed image obtained by superimposing an EOFM image on the optical reflection image can be used as an analysis image.

[0189] The second analysis unit 20C also performs the same process as the analysis operation in the first analysis unit 10C described above. The analysis operation in the first analysis unit 10C and the analysis operation in the second analysis unit 20C may be performed in parallel. These operations may also be performed alternately.

[0190] <Marking process S120C> The marking step S120C of the fourth embodiment is similar to the marking step S120A of the second embodiment. When marking is performed by the second observation optical system 22C, the second observation optical system 22B may include a laser light source for marking, an XYZ stage, and an illumination light source.

[0191] The analysis device 1C includes a first analysis unit 10C that irradiates the semiconductor device D with light generated by a first light source 12C via a first observation optical system 13C having a first optical scanning unit 13s, and receives a first response light from the semiconductor device D generated in response to the light from the first light source 12C with a first camera 15C, and a second analysis unit 20C that irradiates the semiconductor device D with light generated by a second light source 21C via a second observation optical system 22C having a second optical scanning unit 22s, and receives a second response light from the semiconductor device D generated in response to the light from the second light source 21C with a second camera 24C. The apparatus further comprises a device placement section 30, which is disposed between the first analysis section 10C and the second analysis section 20C and holds a semiconductor device D, and has a wafer chuck 32 provided with an alignment target 50 for aligning an optical scanning region of the first observation optical system 13C and an optical scanning region of the second observation optical system 22C, and the wafer chuck 32 moves relatively to the first analysis section 10C and the second analysis section 20C, a stimulus signal application section 60 that applies a stimulus signal to the semiconductor device D, and a control section 41b that outputs commands to the first analysis section 10C, the second analysis section 20C, the device placement section 30, and the stimulus signal application section 60. The alignment target 50 is detectable by the first analysis section 10C from one side of the alignment target 50, and is detectable by the second analysis section 20C from the other side of the alignment target 50. After moving the wafer chuck 32 to a position where the first camera 15C can detect the alignment target 50, the control unit 41b outputs an alignment command to the second analysis unit 20C and the device placement unit 30 to align the optical scanning region of the second observation optical system 22C with the optical scanning region of the first observation optical system 13C with reference to the alignment target 50. Furthermore, the control unit 41b outputs an analysis command to the first analysis unit 10C, the second analysis unit 20C, the stimulus signal application unit 60, and the device placement unit 30 to irradiate light from at least one of the first analysis unit 10C and the second analysis unit 20C to the semiconductor device D while maintaining the positional relationship between the optical scanning region of the first observation optical system 13C and the optical scanning region of the second observation optical system 22C and applying a stimulus signal to the semiconductor device D, and to receive at least one of the first response light and the second response light from the semiconductor device D from at least one of the first camera 15C and the second camera 24C.

[0192] A semiconductor failure analysis method for analyzing a semiconductor device using the analysis apparatus 1C includes an alignment step (S100C) of aligning the optical scanning region of the second observation optical system 22C with the optical scanning region of the first observation optical system 13C based on the alignment target 50 after moving the wafer chuck 32 to a position where the first camera 15C can detect the alignment target 50, and an analysis step (S110C) of irradiating the semiconductor device D with light from at least one of the first analysis unit 10C and the second analysis unit 20C while maintaining the positional relationship between the optical scanning region of the first observation optical system 13C and the optical scanning region of the second observation optical system 22C and applying a stimulus signal to the semiconductor device D, and receiving at least one of the first response light and the second response light from the semiconductor device D by at least one of the first camera 15C and the second camera 24C.

[0193] The analysis device 1C irradiates light onto the semiconductor device D while maintaining the positional relationship between the optical scanning region of the first observation optical system 13C and the optical scanning region of the second observation optical system 22C. Therefore, the optical scanning regions of the first observation optical system 13C and the second observation optical system 22C coincide with each other, so that the defective portion of the semiconductor device D can be detected satisfactorily. [Explanation of symbols]

[0194] 1, 1A, 1B, 1C, 1S...analysis device (semiconductor failure analysis device), 10...analysis section, 10A, 10B, 10C...first analysis section, 11...tester unit, 12...light source, 13...observation optical system (first optical system), 14...XYZ stage (first drive section), 15...two-dimensional camera (first light detection section), 20...marking section, 20A, 20B, 20C...second analysis section, 21...laser light source, 22...laser marking optical system (second optical system), 23...XYZ stage (second drive section), 24...probing camera mera (second light detection unit), 25...illumination light source, 30...device placement unit, 31...sample stage, 32...wafer chuck, 33...XY drive unit (third drive unit), 32a...device holding unit, 32b...target hole, 40...computer, 41a...condition setting unit, 41b...control unit, 41c...image processing unit, 41e...input unit, 41d...display unit, 50...alignment target, 50a...light-transmitting unit, 50b...opaque unit, D...semiconductor device, ME...metal layer, fp...failure area, mp...marking area.

Claims

1. a first analysis unit in which a first light detection unit receives light emitted from a semiconductor device via a first optical system, and the first optical system is moved relatively to the semiconductor device by a first drive unit; a second analysis unit in which a second light detection unit receives light emitted from the semiconductor device via a second optical system, and the second optical system is moved relatively to the semiconductor device by a second drive unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; a stimulus signal application unit that applies a stimulus signal to the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulation signal application unit, the control unit applies the stimulus signal to the semiconductor device, and outputs an analysis command to the first analysis unit, the second analysis unit, the stimulus signal application unit, and the device placement unit to receive light from the semiconductor device emitted in response to the stimulus signal, to at least one of the first light detection unit or the second light detection unit.

2. 2. The semiconductor failure analysis apparatus according to claim 1, wherein the analysis command causes an analysis of the semiconductor device to be performed after the chuck is moved by a third drive unit included in the device placement unit so that the semiconductor device overlaps with an optical axis of the first optical system and an optical axis of the second optical system.

3. 3. The semiconductor failure analysis apparatus according to claim 1, wherein the first light detection section is a first infrared camera, and the second light detection section is a second infrared camera.

4. 4. The semiconductor failure analysis device according to claim 3, wherein the first infrared camera and the second infrared camera detect light having a wavelength of not less than 2 [mu]m and not more than 10 [mu]m.

5. 5. The semiconductor failure analysis apparatus according to claim 1, wherein the control unit outputs an analysis command to the first analysis unit and the second analysis unit to receive light from the semiconductor device emitted in response to the stimulus signal at both the first light detection unit and the second light detection unit.

6. a first analysis unit that irradiates the semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit; a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; an electrical signal acquiring unit that receives an electrical signal output from the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the electrical signal acquisition unit, The control unit irradiates the semiconductor device with light from at least one of the first analysis unit and the second analysis unit, and outputs an analysis command to the first analysis unit, the second analysis unit, the electrical signal acquisition unit, and the device placement unit to receive an electrical signal from the semiconductor device by the electrical signal acquisition unit.

7. 7. The semiconductor failure analysis apparatus according to claim 6, wherein the analysis command causes an analysis of the semiconductor device to be performed after the chuck is moved by a third drive unit included in the device placement unit so that the semiconductor device overlaps an optical scanning region of the first optical system and an optical scanning region of the second optical system.

8. 8. The semiconductor failure analysis apparatus according to claim 6, wherein the first light source and the second light source output laser light in a wavelength band in which the semiconductor device does not generate electric charges.

9. 9. The semiconductor failure analysis apparatus according to claim 6, wherein the control unit causes light to be irradiated from both the first analysis unit and the second analysis unit to the semiconductor device, and outputs an analysis command to the first analysis unit, the second analysis unit, the electrical signal acquisition unit, and the device placement unit to receive an electrical signal from the semiconductor device by the electrical signal acquisition unit.

10. a first analysis unit that irradiates a semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, and receives a first response light from the semiconductor device that is generated in response to the light from the first light source using a first optical detection unit; a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, and receives second response light from the semiconductor device that is generated in response to the light from the second light source using a second optical detection unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; a stimulus signal application unit that applies a stimulus signal to the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulation signal application unit, the control unit, while applying the stimulus signal to the semiconductor device, irradiates the semiconductor device with light from at least one of the first analysis unit and the second analysis unit, and outputs an analysis command to the first analysis unit, the second analysis unit, the stimulus signal application unit, and the device placement unit to receive at least one of the first response light and the second response light from the semiconductor device from at least one of the first light detection unit and the second light detection unit.

11. 11. The semiconductor failure analysis apparatus according to claim 10, wherein the analysis command causes an analysis of the semiconductor device to be performed after the chuck is moved by a third drive unit included in the device placement unit so that the semiconductor device overlaps an optical scanning region of the first optical system and an optical scanning region of the second optical system.

12. the stimulus signal application unit applies the stimulus signal having a predetermined modulation frequency to the semiconductor device; 12. The semiconductor failure analysis apparatus according to claim 10, wherein the control unit extracts a signal component having a predetermined frequency based on at least one of the first response light and the second response light, and displays the signal component as a time progression or a two-dimensional mapping of the signal component.

13. 13. The semiconductor failure analysis apparatus according to claim 10, wherein the control unit, while applying the stimulus signal to the semiconductor device, irradiates the semiconductor device with light from both the first analysis unit and the second analysis unit, and outputs an analysis command to the first analysis unit, the second analysis unit, the stimulus signal application unit, and the device placement unit to receive at least one of the first response light and the second response light from the semiconductor device from at least one of the first light detection unit and the second light detection unit.

14. A semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus, comprising: The semiconductor failure analysis apparatus includes: a first analysis unit in which a first light detection unit receives light emitted from a semiconductor device via a first optical system, and the first optical system is moved relatively to the semiconductor device by a first drive unit; a second analysis unit in which a second light detection unit receives light emitted from the semiconductor device via a second optical system, and the second optical system is moved relatively to the semiconductor device by a second drive unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; a stimulus signal application unit that applies a stimulus signal to the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulation signal application unit, applying the stimulus signal to the semiconductor device; receiving light from the semiconductor device in response to the stimulus signal by at least one of the first light detection unit or the second light detection unit.

15. 15. The semiconductor failure analysis method of claim 14, further comprising, prior to the step of applying the stimulus signal, a step of moving the chuck by a third drive unit included in the device placement unit so that the semiconductor device overlaps with the optical axis of the first optical system and the optical axis of the second optical system.

16. 16. The semiconductor failure analysis method according to claim 14, wherein in the step of receiving light from the semiconductor device, the light from the semiconductor device is received by a first infrared camera which is the first light detection unit and a second infrared camera which is the second light detection unit.

17. The semiconductor failure analysis method according to any one of claims 14 to 16, wherein in the step of receiving light from the semiconductor device, a first infrared camera which is the first light detection unit and a second infrared camera which is the second light detection unit detect light having a wavelength of 2 μm or more and 10 μm or less.

18. The semiconductor failure analysis method according to any one of claims 14 to 17, wherein in the step of receiving light from the semiconductor device, light emitted from the semiconductor device in response to the stimulus signal is received by both the first light detection unit and the second light detection unit.

19. A semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus, comprising: The semiconductor failure analysis apparatus includes: a first analysis unit that irradiates the semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit; a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; an electrical signal acquiring unit that receives an electrical signal output from the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the electrical signal acquisition unit, irradiating the semiconductor device with light from at least one of the first analysis unit and the second analysis unit; receiving an electrical signal from the semiconductor device by the electrical signal acquisition unit.

20. 20. The semiconductor failure analysis method according to claim 19, further comprising, prior to the step of irradiating the semiconductor device with light, a step of moving the chuck by a third drive unit included in the device placement unit so that the semiconductor device overlaps an optical scanning region of the first optical system and an optical scanning region of the second optical system.

21. 21. The semiconductor failure analysis method according to claim 19, wherein in the step of irradiating the semiconductor device with light, the first light source and the second light source output laser light in a wavelength band in which the semiconductor device does not generate electric charges.

22. In the step of irradiating the semiconductor device with light, the semiconductor device is irradiated with light from both the first analysis unit and the second analysis unit, 22. The semiconductor failure analysis method according to claim 19, wherein in the step of receiving an electrical signal from the semiconductor device, the electrical signal is received from the semiconductor device by the electrical signal acquisition section.

23. A semiconductor failure analysis method for analyzing a semiconductor device using a semiconductor failure analysis apparatus, comprising: The semiconductor failure analysis apparatus includes: a first analysis unit that irradiates a semiconductor device with light generated by a first light source via a first optical system having a first optical scanning unit, and receives a first response light from the semiconductor device that is generated in response to the light from the first light source using a first optical detection unit; a second analysis unit that irradiates the semiconductor device with light generated by a second light source via a second optical system having a second optical scanning unit, and receives second response light from the semiconductor device that is generated in response to the light from the second light source using a second optical detection unit; a device placement section that is disposed between the first analysis section and the second analysis section and has a chuck that holds the semiconductor device, the chuck moving relatively with respect to the first analysis section and the second analysis section; a stimulus signal application unit that applies a stimulus signal to the semiconductor device; a control unit that outputs commands to the first analysis unit, the second analysis unit, the device placement unit, and the stimulation signal application unit, irradiating the semiconductor device with light from at least one of the first analysis unit and the second analysis unit while applying the stimulus signal to the semiconductor device; receiving at least one of the first response light and the second response light from the semiconductor device by at least one of the first light detection unit and the second light detection unit.

24. 24. The semiconductor failure analysis method according to claim 23, further comprising, before the step of irradiating the semiconductor device with light, a step of moving the chuck by a third drive unit included in the device placement unit so that the semiconductor device overlaps an optical scanning region of the first optical system and an optical scanning region of the second optical system.

25. applying a stimulus signal having a predetermined modulation frequency to the semiconductor device prior to the step of irradiating the semiconductor device with light; 25. The semiconductor failure analysis method according to claim 23, further comprising the step of: after the step of receiving at least one of the first response light and the second response light from the semiconductor device, extracting a signal component having a predetermined frequency based on at least one of the first response light and the second response light, and displaying the signal component as a time progression or a two-dimensional mapping of the signal component.

26. 26. The semiconductor failure analysis method according to claim 23, wherein in the step of irradiating the semiconductor device with light, the semiconductor device is irradiated with light from both the first analysis section and the second analysis section.

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