DC / DC converter and controller circuit thereof

Abstract

To provide a controller circuit of a DC / DC converter in an improved current mode.SOLUTION: An error amplifier 210 generates an error signal EOUT by amplifying error between output voltage VOUT of a DC / DC converter 100 and a target voltage thereof. A pulse modulator 220 in a current mode generates a pulse signal TON based on the error signal EOUT and a current detection signal CSNS indicating coil current IL of the DC / DC converter 100. A current ripple detection circuit 240 generates a peak current detection signal PEAK indicating a peak of the coil current IL and a valley current detection signal VALLEY indicating a bottom of the coil current IL.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a DC / DC converter (switching regulator). [Background technology]

[0002] A variety of electronic devices, including consumer devices such as smartphones and tablet computers, in-vehicle devices, office equipment, and industrial equipment, are equipped with circuit components that require a power supply voltage that is lower or higher than the battery voltage or external power supply voltage. Step-down DC / DC converters (Buck converters) and step-up DC / DC converters are used to supply an appropriate power supply voltage to such circuit components.

[0003] Current mode control is one of the control methods for DC / DC converters. In current mode control, the error between the output voltage and the target voltage of the DC / DC converter is amplified by an error amplifier, and the coil current is stabilized close to the current amount determined by the output voltage of the error amplifier (called the error voltage). In other words, the error voltage indicates the target value of the coil current, and changes according to the load current of the DC / DC converter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-113636 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors have come to recognize the following problems when introducing constant-on-time (COT) control or constant-off-time control into a current-mode DC / DC converter.

[0006] Here, an example will be described in which a current-mode step-down converter is combined with COT control.

[0007] In COT control, the detection value of the coil current V CS is compared with the error voltage EOUT, which is the output of the error amplifier. The detected coil current V CS When becomes lower than the error voltage EOUT, the switching transistor turns on, and after a certain on-time has elapsed, the switching transistor turns off.

[0008] In this control, the error voltage EOUT defines the bottom level (valley current) of the coil current. Therefore, in a current-mode converter, it is possible to limit the current by clamping the error voltage EOUT.

[0009] Here, the coil current has ripples, and the width of the ripples varies depending on the input voltage and output voltage of the DC / DC converter. Therefore, when the error voltage EOUT is clamped at a certain voltage level VCL, the valley current is limited to a current level according to the voltage level VCL, but the average value (effective value) of the coil current at that time varies depending on the ripple width, making application design difficult.

[0010] The present disclosure has been made in this context, and it is an exemplary purpose of an embodiment thereof to provide an improved controller circuit for a current-mode DC / DC converter. [Means for solving the problem]

[0011] An embodiment of the present disclosure relates to a controller circuit for a DC / DC converter, the controller circuit including: an error amplifier that generates an error signal by amplifying an error between an output voltage of the DC / DC converter and a target voltage thereof, a current-mode pulse modulator that generates a pulse signal based on the error signal and a current detection signal indicating a coil current of the DC / DC converter, and a current ripple detection circuit that generates a peak current detection signal indicating a peak of the coil current and a valley current detection signal indicating a bottom of the coil current.

[0012] Any combination of the above components, and mutual substitution of components or expressions between methods, devices, systems, etc. are also valid aspects of the present invention. Effect of the Invention

[0013] Certain aspects of the present disclosure enable an improved current-mode DC / DC converter controller circuit. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a circuit diagram of a DC / DC converter according to a comparative technique. [Diagram 2] FIG. 2 is an operational waveform diagram of the DC / DC converter of FIG. [Diagram 3] FIG. 3 is a block diagram of a DC / DC converter including a controller circuit according to an embodiment. [Figure 4] FIG. 4 is an operational waveform diagram of the DC / DC converter of FIG. [Diagram 5] FIG. 5 is a block diagram of a current ripple detection circuit. [Figure 6] FIG. 6 is a circuit diagram of a current-mode COT DC / DC converter including a controller circuit according to an embodiment. [Figure 7] FIG. 7 is a circuit diagram of a portion of a controller circuit according to one embodiment. [Figure 8] FIG. 8 is an operation waveform diagram of the current ripple detection circuit of FIG. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of a current ripple detection circuit according to the first modification. [Figure 10] FIG. 10 is an operational waveform diagram of the current ripple detection circuit according to the first modification. [Figure 11] FIG. 11 is a circuit diagram of a current ripple detection circuit according to the second modification. [Figure 12] FIG. 12 is a circuit diagram of a controller circuit according to the third modification. [Figure 13] FIG. 13 is an operation waveform diagram of the controller circuit of FIG. [Figure 14] FIG. 14 is a circuit diagram of a DC / DC converter according to the fourth modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified summary of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. Furthermore, this summary is not intended to be a comprehensive overview of all possible embodiments, nor is it intended to limit essential components of the embodiments. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0016] This summary is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

[0017] A controller circuit of a DC / DC converter according to one embodiment includes an error amplifier that amplifies the error between the output voltage of the DC / DC converter and its target voltage to generate an error signal, a current-mode pulse modulator that generates a pulse signal based on the error signal and a current detection signal indicative of the coil current of the DC / DC converter, and a current ripple detection circuit that generates a peak current detection signal indicative of the peak of the coil current and a valley current detection signal indicative of the bottom of the coil current.

[0018] According to this embodiment, by generating a peak current detection signal and a valley current detection signal, information on the ripple current, which is the difference between the peak current detection signal and the valley current detection signal, can be used to control the DC / DC converter.

[0019] In one embodiment, the pulse modulator may set the pulse signal to a first level when a signal obtained by combining the error signal with a signal multiplied by a predetermined coefficient of a ripple detection signal based on the difference between the peak current detection signal and the valley current detection signal becomes equal to the current detection signal, and set the pulse signal to a second level after a predetermined time has elapsed. With this configuration, the average value of the coil current can be controlled based on the error signal.

[0020] In one embodiment, the DC / DC converter may be a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor. The current ripple detection circuit may generate a peak current detection signal by sampling and holding a current detection signal indicating a coil current, triggered by a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off, and may generate a valley current detection signal by sampling and holding the current detection signal, triggered by a transition of the pulse signal from an off level to an on level.

[0021] In one embodiment, the current detection signal may include a first voltage generated at a first end and a second voltage generated at a second end of an impedance element provided on a path of a current to be detected.

[0022] In one embodiment, the current ripple detection circuit may include a timing generator that generates a first sample and hold signal that is asserted for a predetermined time after a pulse signal transitions from an on level to an off level and a second sample and hold signal that is asserted for a predetermined time after the pulse signal transitions from the off level to the on level, a first sample and hold circuit that samples and holds the current detection signal in response to the first sample and hold signal to generate a peak current detection signal, and a second sample and hold circuit that samples and holds the current detection signal in response to the second sample and hold signal to generate a valley current detection signal.

[0023] In one embodiment, the current ripple detection circuit may further include at least one switched capacitor filter connected to a downstream stage of the first sample and hold circuit, and at least one switched capacitor filter connected to a downstream stage of the second sample and hold circuit.

[0024] In one embodiment, the DC / DC converter may be a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor. The current ripple detection circuit may generate a peak current detection signal by sampling and holding a current detection signal indicating a coil current, triggered by a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off, track the current detection signal in a section where the pulse signal is at the off level, and hold the current detection signal when the pulse signal transitions to the on level to generate a valley current detection signal.

[0025] In one embodiment, the current ripple detection circuit may include a timing generator that generates a first sample and hold signal that is asserted for a predetermined time after a pulse signal transitions from an on level to an off level and a second sample and hold signal that is asserted in an interval where the pulse signal is at the off level, a first sample and hold circuit that samples and holds the current detection signal in response to the first sample and hold signal to generate a peak current detection signal, and a second sample and hold circuit that tracks and holds the current detection signal in response to the second sample and hold signal to generate a valley current detection signal.

[0026] In one embodiment, the current ripple detection circuit may further include a switched capacitor filter connected to a downstream stage of the first sample and hold circuit, and a switched capacitor filter connected to a downstream stage of the second sample and hold circuit.

[0027] In one embodiment, the pulse modulator may include a gm amplifier that converts the error signal into a differential current, a first resistor connected between a first output of the gm amplifier and one end of an impedance element provided on the path of the coil current, a second resistor connected between a second output of the gm amplifier and the other end of the impedance element, and a comparison circuit configured to receive the first output and second output of the gm amplifier, the peak current detection signal, and the valley current detection signal, and to compare the differential voltage between the first output and the second output of the gm amplifier with a signal that is 1 / 2 times the difference between the peak current detection signal and the valley current detection signal.

[0028] In one embodiment, the comparison circuit may include an inverter and a plurality of gm amplifiers, each having an output commonly connected to the inverter.

[0029] In one embodiment, the controller circuit may be monolithically integrated on a single semiconductor substrate. "Monolithic integration" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are monolithically integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting the circuit constants. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0030] (Embodiment) Hereinafter, the present disclosure will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are not intended to limit the invention or disclosure, but are merely examples, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention or disclosure.

[0031] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0032] Similarly, "a state in which component C is connected between components A and B" includes not only a case in which components A and C, or components B and C, are directly connected to each other, but also a case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0033] First, problems that arise when COT (Constant On-Time) control is incorporated into a current-mode DC / DC converter will be described with reference to a comparative technique.

[0034] 1 is a circuit diagram of a DC / DC converter 100R according to a comparative technique. The DC / DC converter 100R is a synchronous rectification type step-down converter that steps down an input voltage VIN on an input line 102 and generates an output voltage VOUT stabilized at a target voltage level on an output line 104.

[0035] The DC / DC converter 100R includes a controller circuit 600 and its peripheral circuits. The peripheral circuits include an inductor L1, an output capacitor C1, and resistors R11 and R12.

[0036] Resistors R11 and R12 divide the output voltage VOUT and supply it to a feedback pin FB. An error amplifier 610 amplifies the error between the voltage of the FB pin (feedback voltage FB) and a reference voltage VREF1, and generates an error signal EOUT.

[0037] The pulse modulator 620 generates a pulse signal TON by COT control based on the error signal EOUT and a current detection signal CSNS indicating the coil current IL flowing through the inductor L1. The pulse modulator 620 may include a comparator 622 and a one-shot circuit 624. The comparator 622 compares the error signal EOUT with the current detection signal CSNS, and asserts a comparison signal COMP when the current detection signal CNS becomes as low as the error signal EOUT. The one-shot circuit 624 generates a pulse signal TON based on the comparison signal COMP. In response to the assertion of the comparison signal COMP, the pulse signal TON transitions to an ON level instructing M1 to be ON and M2 to be OFF, and after a predetermined ON time has elapsed, transitions to an OFF level instructing M1 to be OFF and M2 to be ON.

[0038] The driver circuit 630 drives the high-side transistor M1 and the low-side transistor M2 based on the pulse signal TON.

[0039] Fig. 2 is an operation waveform diagram of the DC / DC converter 100R of Fig. 1. Fig. 2 shows an input voltage VIN, a coil current IL, and a pulse signal TON. In current-mode COT control, the bottom level (valley current Ivalley) of the coil current IL is determined by an error signal EOUT. The error signal EOUT is feedback-controlled so that the output voltage VOUT approaches a target level. In this example, the length ton of the on-section is adjusted according to the input voltage VIN so that the frequency of the pulse signal TON is constant, but it may be constant regardless of the input voltage VIN.

[0040] Here, the coil current IL has ripples, and the ripple width changes depending on the input voltage VIN of the DC / DC converter. Therefore, the average value Idc of the coil current IL depends not only on the error voltage EOUT but also on the input voltage VIN. This characteristic makes application design complicated.

[0041] For example, in current mode COT control, the error voltage EOUT determines the bottom level (valley current) of the coil current, so it is possible to limit the current by clamping the error voltage EOUT. However, when the input voltage VIN changes, the average value Idc and peak of the coil current IL change, so it is not possible to set a substantial clamp level for the coil current IL.

[0042] Furthermore, if the circuit is configured so that the error signal EOUT indicates the average coil current Idc, current limitation based on the error signal EOUT will be accurate and easy. Alternatively, the load current (output current of the DC / DC converter) can be accurately monitored based on the error signal EOUT.

[0043] Next, the controller circuit 200 according to the embodiment will be described.

[0044] 3 is a block diagram of a DC / DC converter 100 including a controller circuit 200 according to an embodiment. The controller circuit 200 includes an error amplifier 210, a pulse modulator 220, a driver circuit 230, and a current ripple detection circuit 240.

[0045] Resistors R11 and R12 divide the output voltage VOUT and supply it to a feedback pin FB. An error amplifier 210 amplifies the error between the voltage of the FB pin (feedback voltage FB) and a reference voltage VREF1, and generates an error signal EOUT. The error amplifier 210 may include a gm amplifier (transconductance amplifier) ​​212 and a phase compensation circuit 214.

[0046] The pulse modulator 220 generates a pulse signal TON by COT control based on the error signal EOUT and a current detection signal CSNS indicating the coil current IL flowing through the inductor L1.

[0047] The driver circuit 230 drives the high-side transistor M1 and the low-side transistor M2 based on the pulse signal TON.

[0048] The current ripple detection circuit 240 generates a peak current detection signal PEAK indicating the peak (peak current) of the current detection signal CSNS, and a valley current detection signal VALLEY indicating the bottom (valley current) of the current detection signal CSNS. The difference between the peak current detection signal PEAK and the valley current detection signal VALLEY indicates the ripple width Iripple of the coil current IL. In other words, the current ripple detection circuit 240 is capable of generating ripple information RIPPLE of the coil current IL. This ripple information RIPPLE is used to control the pulse modulator 220. The current ripple detection circuit 240 may calculate the difference between the peak current detection signal PEAK and the valley current detection signal VALLEY, generate the current ripple information RIPPLE, and supply it to the pulse modulator 220. Alternatively, the current ripple detection circuit 240 may supply the peak current detection signal PEAK and the valley current detection signal VALLEY to the pulse modulator 220, which may calculate the difference between the peak current detection signal PEAK and the valley current detection signal VALLEY to generate the current ripple information RIPPLE.

[0049] When a signal obtained by combining the error signal EOUT with a signal RIPPLE×α multiplied by a predetermined coefficient (α<1) of the current ripple information RIPPLE becomes equal to the current detection signal CSNS, the pulse modulator 220 transitions the pulse signal TON to a first level, and then transitions it to a second level after a predetermined time has elapsed.

[0050] The pulse modulator 220 may perform current mode COT control (bottom detection on-time fixed control). In this case, when the value obtained by subtracting the signal RIPPLE×α from the error signal EOUT becomes equal to the value of the current detection signal CSNS, the pulse modulator 220 transitions the pulse signal TON to a first level (on level) that instructs the high-side transistor M1 to be on, and after a predetermined time ton has elapsed, transitions the pulse signal TON to a second level (off level) that instructs the high-side transistor M1 to be off. The predetermined time ton may be a fixed length or may vary depending on the input voltage VIN. α is preferably 1 / 2, but a value deviated from 1 / 2 may be used.

[0051] That is, the pulse modulator 220 monitors whether the following relational expression is satisfied based on the three signals EOUT, CSNS, and RIPPLE, and when this relational expression is satisfied, transitions the pulse signal TON to the on level. EOUT-RIPPLE×α>CSNS …(1)

[0052] Thus, pulse modulator 220 may (i) compare EOUT-RIPPLE x α to CSNS, (ii) compare EOUT to RIPPLE x α + CSNS, (iii) compare CSNS-EOUT to -RIPPLE x α, or (iv) compare EOUT-CSNS to RIPPLE x α, all of which are equivalent.

[0053] The above is the configuration of the controller circuit 200. Next, the operation of the controller circuit 200 will be described.

[0054] Fig. 4 is an operation waveform diagram of the DC / DC converter 100 in Fig. 3. In the controller circuit 200, at the timing when the relational expression (1) is satisfied, the pulse signal TON becomes the on level, and the high-side transistor M1 is turned on. When α=1 / 2, the signal EOUT2, which is lower than the error signal EOUT by 1 / 2×Iripple, defines the valley current Ivalley. At this time, the original error signal EOUT indicates the average value Idc of the coil current IL. In other words, the average value Idc of the coil current IL can be controlled by the error signal EOUT.

[0055] Thereby, for example, when current limiting is performed by clamping the error signal EOUT to a predetermined level, the clamp level can be determined with respect to the average value of the coil current IL.

[0056] Alternatively, since the error signal EOUT indicates the average value of the coil current IL, it becomes possible to indirectly monitor the load current IOUT based on the error signal EOUT.

[0057] Next, the configuration of the current ripple detection circuit 240 will be described.

[0058] 5 is a block diagram of the current ripple detection circuit 240. The current ripple detection circuit 240 includes a timing generator 242, a first sample-and-hold circuit 244, and a second sample-and-hold circuit 246.

[0059] The current ripple detection circuit 240 generates a peak current detection signal PEAK by sampling and holding the current detection signal CSNS using a transition of the pulse signal TON from an on level to an off level as a trigger, and also generates a valley current detection signal VALLEY by sampling and holding the current detection signal CSNS using a transition of the pulse signal TON from an off level to an on level as a trigger.

[0060] In this example, the current detection signal CSNS includes a first voltage CSP generated at a first terminal of an impedance element RSNS provided on a path of a current to be detected, and a second voltage CSN generated at a second terminal. The impedance element RSNS may be a sense resistor connected in series with the inductor L1, or may be a sense resistor connected in series with the low-side transistor M2. Alternatively, the on-resistance of the low-side transistor M2 may be used as the impedance element RSNS.

[0061] The timing generator 242 generates a first sample-and-hold signal SH1 and a second sample-and-hold signal SH2 based on the pulse signal TON. Specifically, the timing generator 242 asserts the first sample-and-hold signal SH1 for a predetermined time after the pulse signal TON transitions from an on level to an off level. Also, the timing generator 242 asserts the second sample-and-hold signal SH2 for a predetermined time after the pulse signal TON transitions from an off level to an on level.

[0062] The first sample-and-hold circuit 244 samples and holds the current detection signal CSNS in response to the first sample-and-hold signal SH1 to generate a peak current detection signal PEAK, and the second sample-and-hold circuit 246 samples and holds the current detection signal CSNS in response to the second sample-and-hold signal SH2 to generate a valley current detection signal VALLEY.

[0063] Next, a configuration example of the pulse modulator 220 will be described.

[0064] 6 is a circuit diagram of a current-mode COT DC / DC converter 100 including a controller circuit 200 according to an embodiment. In this example, an impedance element (sense resistor) RSNS for current detection is connected in series with an inductor L1. The CSP pin and CSN pin of the controller circuit 200 are connected to both ends of the sense resistor RSNS.

[0065] The pulse modulator 220 includes a comparator 222 and a one-shot circuit 224. The comparator 222 monitors whether the relational expression (1) is satisfied based on the three signals EOUT, CSNS, and RIPPLE, and asserts a comparison signal COMP when the relational expression is satisfied. EOUT-RIPPLE×α>CSNS …(1)

[0066] The one-shot circuit 224 generates a pulse signal TON that is at an on level (for example, high) for an on-time ton after the comparison signal COMP is asserted.

[0067] A comparator 222 compares EOUT-CSNS with RIPPLE×α.

[0068] The comparator 222 includes a gm amplifier 226, resistors R21 and R22, and a comparison circuit 228. The gm amplifier 226 converts the error signal EOUT into a differential current Idiff. The resistor R21 is connected between one output of the gm amplifier 226 and the CPS pin, and the resistor R22 is connected between the other output of the gm amplifier 226 and the CPN pin. The resistors R21 and R22 have the same resistance value R.

[0069] A differential voltage ΔV equivalent to EOUT-CSNS is generated at the output of the gm amplifier 226. The comparison circuit 228 receives the differential voltage ΔV and the current ripple information RIPPLE, and asserts a comparison signal COMP when the differential voltage ΔV becomes equal to RIPPLE / 2.

[0070] Next, examples of the configuration of the current ripple detection circuit 240 and the comparison circuit 228 will be described.

[0071] FIG. 7 is a circuit diagram of a portion of a controller circuit 200A according to one embodiment.

[0072] Refer to the current ripple detection circuit 240A. The first sample-and-hold circuit 244A includes capacitors C1P, C1N and switches SW1P, SW1N. The switches SW1P, SW1N are on during the period when the first sample-and-hold signal SH1 is asserted, and off during the period when the first sample-and-hold signal SH1 is negated. The second sample-and-hold circuit 246A includes capacitors C2P, C2N and switches SW2P, SW2N. The switches SW2P, SW2N are on during the period when the second sample-and-hold signal SH2 is asserted, and off during the period when the second sample-and-hold signal SH2 is negated.

[0073] Fig. 8 is an operation waveform diagram of the current ripple detection circuit 240A of Fig. 7. The difference between the voltage INP1 of the capacitor C1P and the voltage INN1 of the capacitor C1N is the peak current detection signal PEAK. The difference between the voltage INP2 of the capacitor C2P and the voltage INN2 of the capacitor C2N is the valley current detection signal VALLEY.

[0074] Returning to FIG. 7, the comparison circuit 228A includes a first gm amplifier gm1, a second gm amplifier gm2, a third gm amplifier gm3, and a buffer (inverter) 229. The first gm amplifier gm1 generates a current signal Igm1 according to the differential voltage ΔV. The second gm amplifier gm2 generates a current signal Igm2 according to the peak current detection signal PEAK. The third gm amplifier gm3 generates a current signal Igm3 according to the valley current detection signal VALLEY. The inputs to the gm amplifiers gm1 and gm3 are input with opposite polarity, and the current signals Igm1 and Igm3 flow in the opposite direction to gm2. The transconductance of the second gm amplifier gm2 and the third gm amplifier gm3 is set to 1 / 2 the transconductance of the first gm amplifier gm1.

[0075] At the input node of the CMOS buffer 229, a voltage is generated according to the amount of output current Igm1, Igm2, and Igm3 of the three gm amplifiers gm1 to gm3. Specifically, when -Igm1+(Igm2-Igm3) / 2 is positive, the input voltage of the CMOS buffer 229 rises and becomes higher than the threshold voltage of the CMOS buffer 229, and the comparison signal COMP transitions to a high level (asserted). Igm1 corresponds to ΔV=EOUT-CSNS, and Igm2-Igm3 corresponds to RIPPLE. That is, the comparison circuit 228A can compare EOUT-CSNS with RIPPLE / 2.

[0076] Next, a modification of the controller circuit 200 will be described.

[0077] (Variation 1) 8, a current needs to flow through the impedance element RSNS even when the low-side transistor M2 is off. Therefore, there are restrictions on where the impedance element RSNS can be placed, and it is not possible to place the impedance element RSNS in series with the low-side transistor M2 or to use the on-resistance of the low-side transistor M2 as the impedance element RSNS.

[0078] When it is desired to provide an impedance element RSNS in series with the low-side transistor M2 or to use the on-resistance of the low-side transistor M2 as the impedance element RSNS, the first modification can be adopted.

[0079] 9 is a circuit diagram showing a configuration example of a current ripple detection circuit 240B according to Modification 1. The current ripple detection circuit 240B tracks the current detection signal CSNS in an interval where the pulse signal TON is at an off level, and holds the pulse signal TON when it transitions to an on level to generate a valley current detection signal VALLEY. In this modification, the timing generator 242B asserts the second sample and hold signal SH2 in an interval where the pulse signal TON is at an off level.

[0080] The current ripple detection circuit 240B includes a switched capacitor filter 248B in addition to a first sample and hold circuit 244B and a second sample and hold circuit 246B. The switched capacitor filter 248B is controlled in response to an inverted signal / SH2 of the second sample and hold signal SH2.

[0081] 10 is an operation waveform diagram of the current ripple detection circuit 240B according to Modification 1. By making the capacitance value of the capacitor of the switched capacitor filter 248 sufficiently smaller than the capacitance value of the capacitor of the second sample-and-hold circuit 246, the difference INP2-INN2 of the outputs of the switched capacitor filter 248 indicates the valley current detection signal VALLEY.

[0082] (Variation 2) The peak current detection signal PEAK and the valley current detection signal VALLEY generated by the current ripple detection circuit 240 (240A, 240B) described above are based on the current in the immediately preceding cycle. If the pulse signal TON is generated based on the current information thus obtained, very large corrections are repeated for the response of the DC / DC converter, which may cause the circuit operation to become unstable.

[0083] Therefore, it is preferable to insert a filter for smoothing the detection signal after the first sample-and-hold circuit 244 and the second sample-and-hold circuit 246. The filter may be an analog filter such as an RC filter or a switched capacitor filter.

[0084] 11 is a circuit diagram of a current ripple detection circuit 240C according to the second modification. The current ripple detection circuit 240C includes a first sample-and-hold circuit 244, a second sample-and-hold circuit 246, and switched capacitor filters 250, 252, 254, and 256. The switched capacitor filters 250 and 254 are controlled by an inverted signal / SH2 of the second sample-and-hold signal SH2, and the switched capacitor filters 252 and 256 are controlled by the second sample-and-hold signal SH2. The cutoff frequency of the filter circuit becomes lower as the number of stages of the switched capacitor filters increases, and also becomes lower as the capacitance value of the capacitor of the final-stage switched capacitor filters 252 and 256 increases.

[0085] (Variation 3) FIG. 12 is a circuit diagram of a controller circuit 200D according to the third modification. The basic configuration of the current ripple detection circuit 240D is the same as that of the current ripple detection circuit 240C of FIG. 11, but the configurations of the sample-and-hold circuit and the switched capacitor filter are different. Specifically, the sample-and-hold circuit 244D includes one capacitor C21 and two switches SW1P, SW1N. The switched capacitor filter 250D includes one capacitor C22 and two switches SW2P, SW2N. The switched capacitor filter 252D includes one capacitor C22 and one switch SW2P. The second sample-and-hold circuit 246D and the switched capacitor filters 254D and 256D are also configured in the same manner.

[0086] The comparison circuit 228D includes a first gm amplifier gm1, a fourth gm amplifier gm4, and a CMOS buffer 229. The fourth gm amplifier gm4 is a combination of the second gm amplifier gm2 and the third gm amplifier gm3 in FIG.

[0087] Fig. 13 is an operation waveform diagram of the controller circuit 200D of Fig. 12. CSP-CSN corresponds to the current detection signal CSNS. In addition, INN2-INP2 corresponds to ΔV=EOUT-CSNS. In addition, INN1-INP1 corresponds to ripple information RIPPLE (=PEAK-VALLEY).

[0088] The coil current IL is converted to a voltage in the sense resistor RSNS, and a voltage drop CSP-CSN occurs. The difference in current flowing through resistors R21 and R22 is proportional to the transconductance gm0 of the gm amplifier 226, gm0×(EOUT-VREF2) Therefore, INN2-INP2=CSP-CNS-gm0×(EOUT-VREF2) This signal is compared with 0.5 × (INP1-INN1), so (INN2-INP2)+0.5×(INP1-INN1)<0 twist, gm0×R×(EOUT-VREF2)>(CSP-CNS)+0.5×(INN1-INP1) is satisfied, the comparison signal COMP is asserted, and the pulse signal TON goes to the on level. This turns the high-side transistor M1 on and the low-side transistor M2 off, causing the switching node SW to go high, and the coil current IL increases.

[0089] At the moment when the switching node SW changes from low to high, valley current information is stored in CSP-CSN, and information on the smoothed ripple current Iripple is stored in INN1-INP1, so it can be seen that the average coil current can be controlled by the differential voltage EOUT-VREF2.

[0090] (Variation 4) 14 is a circuit diagram of a DC / DC converter 100E according to Modification 4. In a controller circuit 200E according to Modification 4, a sense resistor RSNS is connected in series with a low-side transistor M2. The rest is the same as in FIG.

[0091] (Variation 5) In the above description, the bottom detection on-time fixed control has been described, but the present disclosure is not limited thereto and can be applied to the peak detection off-time fixed control. Also, the present disclosure can be applied not only to the step-down converter but also to the step-up converter and the step-up / step-down converter. Also, the high-side transistor M1 and the low-side transistor M2 may be external discrete components.

[0092] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various variations in the combination of each component and each treatment process, and that such variations are also included in the present disclosure and may constitute the scope of the present invention.

[0093] (Additional Note) The present specification discloses the following techniques:

[0094] (Item 1) A controller circuit for a DC / DC converter, comprising: an error amplifier that amplifies an error between an output voltage of the DC / DC converter and a target voltage thereof to generate an error signal; a current-mode pulse modulator that generates a pulse signal based on the error signal and a current detection signal indicating a coil current of the DC / DC converter; a current ripple detection circuit that generates a peak current detection signal indicating a peak of the coil current and a valley current detection signal indicating a bottom of the coil current; A controller circuit comprising:

[0095] (Item 2) The controller circuit described in item 1, wherein the pulse modulator sets the pulse signal to a first level when a signal obtained by combining the error signal with a signal multiplied by a predetermined coefficient of a ripple detection signal based on the difference between the peak current detection signal and the valley current detection signal becomes equal to the current detection signal, and sets the pulse signal to a second level after a predetermined time has elapsed.

[0096] (Item 3) the DC / DC converter is a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor, The current ripple detection circuit includes: a current detection signal indicating the coil current is sampled and held using a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off as a trigger, and the peak current detection signal is generated; The controller circuit of item 1, wherein the transition of the pulse signal from the off level to the on level is used as a trigger to sample and hold the current detection signal to generate the valley current detection signal.

[0097] (Item 4) The current ripple detection circuit includes: a timing generator that generates a first sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the on level to the off level, and a second sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the off level to the on level; a first sample-and-hold circuit that samples and holds the current detection signal in response to the first sample-and-hold signal to generate the peak current detection signal; a second sample-and-hold circuit configured to sample and hold the current detection signal in response to the second sample-and-hold signal to generate the valley current detection signal; 4. The controller circuit of item 3, comprising:

[0098] (Item 5) The current ripple detection circuit includes: at least one switched capacitor filter connected to a downstream of the first sample and hold circuit; at least one switched capacitor filter connected to a downstream stage of the second sample and hold circuit; 5. The controller circuit of item 4, further comprising:

[0099] (Item 6) the DC / DC converter is a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor, The current ripple detection circuit includes: a current detection signal indicating the coil current is sampled and held using a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off as a trigger, and the peak current detection signal is generated; 2. The controller circuit of item 1, further comprising: a controller circuit for tracking the current detection signal during an interval in which the pulse signal is at the off level; and a controller circuit for holding the current detection signal when the pulse signal transitions to the on level to generate the valley current detection signal.

[0100] (Item 7) The current ripple detection circuit includes: a timing generator that generates a first sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the on level to the off level, and a second sample-and-hold signal that is asserted during an interval in which the pulse signal is at the off level; a first sample-and-hold circuit that samples and holds the current detection signal in response to the first sample-and-hold signal to generate the peak current detection signal; a second sample-and-hold circuit configured to track and hold the current detection signal in response to the second sample-and-hold signal to generate the valley current detection signal; 7. The controller circuit of item 6, comprising:

[0101] (Item 8) The current ripple detection circuit includes: a switched capacitor filter connected to a downstream stage of the first sample and hold circuit; a switched capacitor filter connected to a downstream stage of the second sample and hold circuit; 8. The controller circuit of item 7, further comprising:

[0102] (Item 9) The pulse modulator includes: a gm amplifier for converting the error signal into a differential current; a first resistor connected between a first output of the gm amplifier and one end of an impedance element provided on a path of a coil current; a second resistor connected between a second output of the gm amplifier and the other end of the impedance element; a comparison circuit configured to receive the first output and the second output of the gm amplifier, the peak current detection signal, and the valley current detection signal, and to compare a differential voltage between the first output and the second output of the gm amplifier with a signal that is 1 / 2 the difference between the peak current detection signal and the valley current detection signal; 3. The controller circuit of item 2, comprising:

[0103] (Item 10) The comparison circuit includes: An inverter; A plurality of gm amplifiers, each having an output commonly connected to the inverter; 10. The controller circuit of item 9, comprising:

[0104] (Item 11) 11. The controller circuit according to any one of items 1 to 10, which is monolithically integrated on a single semiconductor substrate.

[0105] (Item 12) 12. A DC / DC converter comprising a controller circuit according to any one of items 1 to 11. [Explanation of symbols]

[0106] 100 DC / DC Converter 102 input lines 104 Output Line M1 High-side transistor M2 Low-side transistor L1 Inductor C1 Output capacitor 200 Controller Circuit 210 Error Amplifier 212 gm amplifier 214 Phase compensation circuit 220 Pulse Modulator 222 Comparator 224 One-shot circuit 226 gm amplifier R21,R22 resistance 228 Comparison circuit 230 Driver circuit 240 Current ripple detection circuit 242 Timing Generator 244 First sample and hold circuit 246 Second sample and hold circuit 248,250,252,254 Switched Capacitor Filters

Claims

1. A controller circuit for a DC / DC converter, comprising: an error amplifier that amplifies an error between an output voltage of the DC / DC converter and a target voltage thereof to generate an error signal; a current-mode pulse modulator that generates a pulse signal based on the error signal and a current detection signal indicating a coil current of the DC / DC converter; a current ripple detection circuit that generates a peak current detection signal indicating a peak of the coil current and a valley current detection signal indicating a bottom of the coil current; A controller circuit comprising:

2. 2. The controller circuit according to claim 1, wherein the pulse modulator sets the pulse signal to a first level when a signal obtained by combining the error signal with a signal multiplied by a predetermined coefficient of a ripple detection signal based on a difference between the peak current detection signal and the valley current detection signal becomes equal to the current detection signal, and sets the pulse signal to a second level after a predetermined time has elapsed.

3. the DC / DC converter is a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor, The current ripple detection circuit includes: a current detection signal indicating the coil current is sampled and held using a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off as a trigger, and the peak current detection signal is generated; The controller circuit according to claim 1 , wherein the controller circuit generates the valley current detection signal by sampling and holding the current detection signal using a transition of the pulse signal from the off level to the on level as a trigger.

4. The current ripple detection circuit includes: a timing generator that generates a first sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the on level to the off level, and a second sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the off level to the on level; a first sample-and-hold circuit configured to sample and hold the current detection signal in response to the first sample-and-hold signal to generate the peak current detection signal; a second sample-and-hold circuit configured to sample and hold the current detection signal in response to the second sample-and-hold signal to generate the valley current detection signal; 4. The controller circuit of claim 3, comprising:

5. The current ripple detection circuit includes: at least one switched capacitor filter connected to a downstream stage of the first sample and hold circuit; at least one switched capacitor filter connected to a downstream stage of the second sample and hold circuit; The controller circuit of claim 4 further comprising:

6. the DC / DC converter is a synchronous rectification type step-down converter including a high-side transistor and a low-side transistor, The current ripple detection circuit includes: a current detection signal indicating the coil current is sampled and held using a transition of the pulse signal from an on level instructing the high-side transistor to be on to an off level instructing the high-side transistor to be off as a trigger, and the peak current detection signal is generated; 2. The controller circuit of claim 1, further comprising: a controller circuit for tracking the current detection signal during an interval in which the pulse signal is at the off level; and a controller circuit for holding the current detection signal when the pulse signal transitions to the on level, to generate the valley current detection signal.

7. The current ripple detection circuit includes: a timing generator that generates a first sample-and-hold signal that is asserted for a predetermined time after the pulse signal transitions from the on level to the off level, and a second sample-and-hold signal that is asserted during an interval in which the pulse signal is at the off level; a first sample-and-hold circuit configured to sample and hold the current detection signal in response to the first sample-and-hold signal to generate the peak current detection signal; a second sample-and-hold circuit configured to track and hold the current detection signal in response to the second sample-and-hold signal to generate the valley current detection signal; 7. The controller circuit of claim 6, comprising:

8. The current ripple detection circuit includes: a switched capacitor filter connected to a downstream stage of the first sample and hold circuit; a switched capacitor filter connected to a downstream stage of the second sample-and-hold circuit; The controller circuit of claim 7 further comprising:

9. The pulse modulator includes: a gm amplifier for converting the error signal into a differential current; a first resistor connected between a first output of the gm amplifier and one end of an impedance element provided on a path of a coil current; a second resistor connected between a second output of the gm amplifier and the other end of the impedance element; a comparison circuit configured to receive the first output and the second output of the gm amplifier, the peak current detection signal, and the valley current detection signal, and to compare a difference voltage between the first output and the second output of the gm amplifier with a signal that is 1 / 2 the difference between the peak current detection signal and the valley current detection signal; The controller circuit of claim 2 , comprising:

10. The comparison circuit includes: An inverter; A plurality of gm amplifiers, each having an output commonly connected to the inverter; 10. The controller circuit of claim 9, comprising:

11. The controller circuit according to claim 1 , which is monolithically integrated on a single semiconductor substrate.

12. A DC / DC converter comprising a controller circuit according to any one of claims 1 to 10.

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