Semiconductor device and manufacturing method of semiconductor device

Abstract

To reduce the cost of a semiconductor device while improving the reliability.SOLUTION: A semiconductor device includes a semiconductor substrate 10, a first metal layer 21 provided on the semiconductor substrate 10, a second metal layer 22 provided on the first metal layer 21, and a protective film 40 having an opening 41 and provided on the second metal layer 22, the protective film 40 is in contact with the second metal layer 22 and made of a resin material, each of the first metal layer 21 and the second metal layer 22 is provided over an area that includes the opening 41 in a planar view, and the second metal layer 22 has a portion interposed between the first metal layer 21 and the protective film 40.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] Semiconductor devices, such as power semiconductor devices, may have electrodes soldered to conductors such as leads or terminal pins. For example, in the semiconductor device described in Patent Document 1, an emitter electrode soldered is provided on one surface of a semiconductor substrate. Here, the emitter electrode includes a first metal layer, a second metal layer, and an oxidation prevention layer. A first protective film having a first opening is provided on the first metal layer so as to cover an end of the first metal layer. The second metal layer is provided on the first metal layer at the first opening. The oxidation prevention layer is provided on the second metal layer at the first opening.

[0003] In Patent Document 1, a second protective film having a second opening is provided so as to cover the end of the oxidation prevention layer and the first protective film, thereby preventing the occurrence of cracks due to thermal stress at the boundary between the first protective film and the second metal layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-201160 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor device described in Patent Document 1, because a part of the first protective film is interposed between the first metal layer and the second metal layer, there is a risk that the second metal layer will peel off from the first metal layer due to thermal expansion of the first protective film. In addition, because the second protective film is required in addition to the first protective film, the manufacturing process becomes complicated, which results in an issue of high costs.

[0006] In consideration of the above circumstances, an object of one aspect of the present disclosure is to reduce the cost of a semiconductor device while improving its reliability. [Means for solving the problem]

[0007] In order to solve the above problems, a semiconductor device according to a preferred embodiment of the present disclosure comprises a semiconductor substrate, a first metal layer provided on the substrate, a second metal layer provided on the first metal layer, and a protective film having an opening and provided on the second metal layer, the protective film being in contact with the second metal layer and being made of a resin material, each of the first metal layer and the second metal layer being provided over an area that includes the opening in a planar view, and the second metal layer having a portion interposed between the first metal layer and the protective film.

[0008] A manufacturing method of a semiconductor device according to a preferred embodiment of the present disclosure is a manufacturing method of a semiconductor device comprising a semiconductor substrate, a first metal layer provided on the substrate, a second metal layer provided on the first metal layer, and a protective film having an opening and provided on the second metal layer, the method including a metal layer formation step of forming the first metal layer and the second metal layer, and a protective film formation step of forming the protective film, wherein the protective film is in contact with the second metal layer and is made of a resin material, each of the first metal layer and the second metal layer is provided over an area that includes the opening in a planar view, and the second metal layer has a portion interposed between the first metal layer and the protective film. Effect of the Invention

[0009] The present disclosure makes it possible to reduce the cost of a semiconductor device while improving its reliability. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line AA′ in FIG. 1. [Diagram 3]1 is a partially enlarged cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 11 is a partially enlarged cross-sectional view of a semiconductor device according to a reference example. [Diagram 5] 2A to 2C are diagrams showing a flow of a manufacturing method of a semiconductor device according to the first embodiment. [Figure 6] FIG. 11 is a diagram for explaining a substrate preparation step. [Figure 7] FIG. 13 is a diagram for explaining a first film forming step in a metal layer forming step. [Figure 8] FIG. 13 is a view for explaining a second film forming step in the metal layer forming step. [Figure 9] FIG. 13 is a diagram for explaining an etching step in the metal layer forming step. [Figure 10] 11A to 11C are diagrams for explaining a protective film forming step. [Figure 11] FIG. 11 is a partially enlarged cross-sectional view of a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is a partially enlarged cross-sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present disclosure will be described with reference to the drawings. Note that in the drawings, some parts are shown diagrammatically to facilitate understanding. In addition, the scope of the present disclosure is not limited to these embodiments unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0012] 1. Embodiment 1-1. Overall configuration of semiconductor device Fig. 1 is a plan view of a semiconductor device 1 according to a first embodiment. Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1. Fig. 1 shows the front surface of the semiconductor device 1. Note that, for ease of viewing, solder 60, which will be described later, is omitted from Fig. 1.

[0013] The semiconductor device 1 is, for example, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a trench gate structure. As shown in Figures 1 and 2, the semiconductor device 1 includes a semiconductor substrate 10, an interlayer insulating film 114, an insulating film 123, and a gate runner 130, which will be described later, as well as a source pad 20, a gate pad 30, a protective film 40, and a drain pad 50.

[0014] Hereinafter, first, an outline of each part of the semiconductor device 1 will be sequentially described based on FIG. 1 and FIG. 2. For convenience, the following description will be made using the X-axis, Y-axis, and Z-axis that are mutually orthogonal. The Z-axis is an axis parallel to the thickness direction of the semiconductor device 1. Hereinafter, one direction along the X-axis is the X1 direction, and the direction opposite to the X1 direction is the X2 direction. One direction along the Y-axis is the Y1 direction, and the direction opposite to the Y1 direction is the Y2 direction. One direction along the Z-axis is the Z1 direction, and the direction opposite to the Z1 direction is the Z2 direction. The relationship between these directions and the vertical direction is not particularly limited and is arbitrary. Hereinafter, a view along the Z-axis may be referred to as a "planar view", a surface facing the Z1 direction may be referred to as a "front surface", and a surface facing the Z2 direction may be referred to as a "rear surface".

[0015] The semiconductor substrate 10 is a substrate made of a semiconductor such as silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), and has a vertical MOSFET structure.

[0016] 1, semiconductor substrate 10 is a rectangle having a pair of sides along the X-axis and a pair of sides along the Y-axis in a plan view. Semiconductor substrate 10 is divided into active region 10a and edge termination region 10b, as shown in FIG.

[0017] The active region 10a includes an effective region through which a drift current flows as a main current when the MOSFET is in an on-state. In the example shown in Fig. 1, the active region 10a forms a rectangle along the outer edge of the semiconductor substrate 10 on the inner side in a plan view.

[0018] In the active region 10a, a plurality of trenches 16 for a vertical MOSFET are provided, and an inter-trench p+ type region 17 is provided between adjacent trenches 16. A region between adjacent trenches is defined as a unit cell 110, and a plurality of unit cells 110 are provided in the active region 10a. For convenience of explanation, FIG. 2 shows elements such as a vertical MOSFET provided in the semiconductor substrate 10 in a schematic manner. Note that, hereinafter, an example of the configuration of the semiconductor substrate 10 will be described with reference to FIGS. 1 and 2, but the configuration of the semiconductor substrate 10 is not limited to the example shown in FIGS. 1 and 2.

[0019] In the following description, + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same n and n are attached to a semiconductor region, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0020] Here, the semiconductor substrate 10 has at least an n+ type starting substrate 11, an n- type drift layer 12, a p-type well layer 14, and an n-type source region 15, and may also have an n-type region 13 and a p++-type contact region 18.

[0021] The semiconductor substrate 10 is formed by laminating an n- type drift layer 12 and an n- type region 13 in this order in the Z1 direction on an n+ type starting substrate 11. The p-type well layer 14 may be formed by ion implanting a p-type impurity such as Al into the surface of the n-type region 13, or may be formed by laminating a p-type epitaxial layer. The n-type source region 15 is formed by ion implanting an n-type impurity into the p-type well layer 14.

[0022] The n+ type starting substrate 11 is a substrate made of a semiconductor such as n-type silicon carbide. The n- type drift layer 12 is a layer made of a semiconductor such as n-type silicon carbide having a lower impurity concentration than the n+ type starting substrate 11. The n- type region 13 is a so-called current spreading layer (CSL) that has a lower impurity concentration than the n+ type starting substrate 11 and a higher impurity concentration than the n- type drift layer 12. The n- type region 13 does not necessarily have to be provided. When the n- type region 13 is not provided, the upper surface of the n- type drift layer 12 may be in contact with the lower surface of the p-type well layer 14 described later.

[0023] The p-type well layer 14 is a layer made of a semiconductor such as p-type silicon carbide, and includes a base region. The n-type source region 15 has an impurity concentration lower than that of the n+ type starting substrate 11 and higher than that of the n- type drift layer 12. + The source region is a layer comprised of a semiconductor such as silicon carbide of the type IGBT.

[0024] On the front surface of such a semiconductor substrate 10, a plurality of trenches 16 are provided in the active region 10a, penetrating the p-type well layer 14 and the n-type source region 15. The ends of the trenches 16 in the Z2 direction reach the n-type region 13, and reach the n-type drift layer 12 if the n-type region 13 is not provided. The n-type source region 15 and the p-type well layer 14 contact the side surfaces of each trench 16. A large number of trenches 16 are arranged at intervals from each other in the direction along the Y axis. Each trench 16 may have a planar pattern extending in a striped shape in the direction along the X axis, or may have a planar pattern like dots.

[0025] A gate insulating film 111 is provided along the bottom surface and both side surfaces of each trench 16. A gate electrode 112 is provided inside the trench 16 via the gate insulating film 111. The gate insulating film 111 may be, for example, any one of a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, a single layer film or a composite film in which a plurality of these films are laminated.

[0026] As the gate electrode 112, for example, a polysilicon layer (doped polysilicon layer) doped with a high impurity concentration of p-type impurities or n-type impurities, or a high melting point metal such as titanium (Ti), tungsten (W) or nickel (Ni) can be used. A p+ type region 113 is provided in the n-type region 13 (or the n- type drift layer 12 if no n- type impurity is provided). The end of each trench 16 in the Z2 direction may or may not be in contact with the p+ type region 113. The p+ type region 113 is provided under the trench 16 and is a region made of a semiconductor such as p-type silicon carbide. The p+ type region 113 has a function of relaxing the electric field concentrated at the end of the gate insulating film 111 in the Z2 direction. The width of the p+ type region 113 may be the same as or wider than the width of the trench 16. In addition, an interlayer insulating film 114 is provided on the front surface of the semiconductor substrate 10 so as to cover the gate electrode 112. The interlayer insulating film 114 is a film made of an insulating material such as PSG (Phospho Silicate Glass).

[0027] The inter-trench p+ type region 17 is provided between adjacent trenches 16 and separated from the p+ type region 113 and the trench 16. The inter-trench p+ type region 17 contacts the p-type well layer 14 at the upper surface and is electrically connected to the first metal layer 21 via the p-type well layer 14. The inter-trench p+ type region 17 may be formed as two adjacent layers, an upper inter-trench p+ type region 131 formed on the front surface side inside the n-type region 13 and a lower inter-trench p+ type region 132 formed on the lower surface side inside the n-type region 13, or may be formed as a single layer simultaneously.

[0028] The p+ type region 113 and the inter-trench p+ type region 17 are fixed to the potential of the first metal layer 21, and are depleted when the semiconductor device 1 is turned off, which has the effect of alleviating the electric field applied to the gate insulating film 111. The p+ type region 113 is provided away from the p-type well layer 14, and faces the bottom surface of the trench 16 in the depth direction. The p+ type region 113 has a portion (not shown) that is connected to the inter-trench p+ type region 17, and is electrically connected to the first metal layer 21.

[0029] Edge termination region 10b is a region between active region 10a and the outer edge of semiconductor substrate 10 in plan view. In the example shown in FIG. 1, edge termination region 10b forms a frame surrounding active region 10a. Edge termination region 10b is a region in which p++-type contact region 18, p-type well layer 14, and n-type source region 15 are not provided. In addition, edge termination region 10b is provided with breakdown voltage structure 120 including JTE (Junction Termination Extension) structure 121 and FLR (Field Limiting Ring) structure 122. Breakdown voltage structure 120 has a function of maintaining a breakdown voltage by relaxing the electric field on the front surface side of semiconductor substrate 10. Here, breakdown voltage is the maximum voltage at which the MOSFET does not malfunction or break down.

[0030] In the example shown in FIG. 2, the JTE structure 121 is a plurality of p-type junctions arranged at intervals around the entire periphery of the edge termination region 10b on the front surface of the semiconductor substrate 10. ++ p containing the type domain --The FLR structure 122 is a plurality of p-type regions that are spaced apart from each other and provided around the entire periphery of the edge termination region 10b on the front surface of the semiconductor substrate 10, closer to the outer edge of the semiconductor substrate 10 than the JTE structure 121. -- The semiconductor substrate 10 is configured with a die region. An insulating film 123 is provided on the front surface of the semiconductor substrate 10 so as to cover the voltage-resistant structure 120. The insulating film 123 may be formed together with the above-mentioned interlayer insulating film 114. The configuration of the voltage-resistant structure 120 is not limited to the example shown in FIG. 2, but may be any configuration, and various known structures may be appropriately adopted.

[0031] In the semiconductor substrate 10, p++ type contact region 18, p-type well layer 14, upper p+ type region 131, and lower p+ type region 132 are provided adjacent to each other in the depth direction from the front surface side of the semiconductor substrate in n-type region 13 (in n-type drift layer 12 if n-type region 13 is not provided), on the outer edge side of trench 16 provided in the outermost periphery of active region 10a and on the inner side of edge termination region 10b. These regions are regions in which p++ type contact region 18, p-type well layer 14, and inter-trench p+ type region 17 of active region 10a are extended. The above-mentioned multiple p-type regions may be formed to surround active region 10a. The above-mentioned multiple p-type regions are regions for drawing out hole current, which is generated in n-type drift layer 12 of edge termination region 10b when the semiconductor device is off and flows toward the center of active region 10a, to first metal layer 21.

[0032] A gate runner 130 is provided on the front surface of the semiconductor substrate 10, on the outer edge side of the semiconductor substrate 10 from the trench 16 provided at the outermost periphery and on the inside of the breakdown voltage structure 120, via an insulating film 123. The gate runner 130 is disposed above the semiconductor substrate 10 so as to surround the active region 10a, and includes, for example, wiring made of polysilicon (Poly-Si). The gate runner 130 may have a laminated structure of wiring made of polysilicon and wiring made of metal. Although not shown, the gate runner 130 is electrically connected to all the gate electrodes 112 provided in the active region 10a. The gate runner 130 is also electrically connected to the gate pad 30. That is, the gate runner 130 electrically connects all the gate electrodes 112 provided in the active region 10a and the gate pad 30 to each other.

[0033] On the front surface of the semiconductor substrate 10 described above, in the active region 10a, a source pad 20 and a gate pad 30 are provided with an interlayer insulating film 114 interposed therebetween.

[0034] In the active region 10a, the source pad 20 and the gate pad 30 are each provided on an interlayer insulating film (not shown) on the front surface of the semiconductor substrate 10. Here, the source pad 20 and the gate pad 30 are arranged with a gap between them.

[0035] The source pad 20 is electrically connected to the source region and base region constituting the MOS gate through a contact hole penetrating the interlayer insulating film. In the example shown in Fig. 1, the source pad 20 is provided over the entire area of ​​the opening 41 in a plan view. Here, the gate pad 30 has a rectangular shape in a plan view, and is provided over the entire area of ​​the opening 42. Note that the plan view shapes of the source pad 20 and the gate pad 30 are not limited to the example shown in Fig. 1, and may be arbitrary.

[0036] The source pad 20 and the gate pad 30 may have the same layer structure and may be formed collectively by the same film formation process. In Fig. 2, the layer structure of the source pad 20 is representatively illustrated. As shown in Fig. 2, the source pad 20 may have a first metal layer 21 provided on the interlayer insulating film 114 and a second metal layer 22 provided on the first metal layer 21.

[0037] Details of the first metal layer 21 and the second metal layer 22 will be described later with reference to FIG. 3, but as shown in FIG. 2, the outer peripheral surface 21a of the first metal layer 21 and the outer peripheral surface 22a of the second metal layer 22 are continuously connected to each other. In the example shown in FIG. 2, the outer peripheral surface 21a and the outer peripheral surface 22a are inclined so as to widen toward the Z2 direction. Then, the outer peripheral surface 21a in the Z1 direction and the outer peripheral surface 22a in the Z2 direction are connected to each other so that they coincide with each other. Here, the difference in the inclination angle of the outer peripheral surfaces 21a and 22a is due to the difference in etching rate between the first metal film 210 and the second metal film 220 in the etching step S23 described later.

[0038] In this way, at least a part of the outer edge of the second metal layer 22 coincides with the outer edge of the first metal layer 21 in a plan view. Here, "coincidence" includes not only strict coincidence but also substantial coincidence with a difference due to manufacturing error or the like. This difference includes a difference caused by the difference in etching rate between the first metal film 210 and the second metal film 220 in the etching step S23 described below.

[0039] In this manner, in an embodiment in which at least a part of the outer edge of the second metal layer 22 coincides with the outer edge of the first metal layer 21 in a plan view, the adhesion between the first metal layer 21 and the second metal layer 22 can be improved compared to an embodiment in which the second metal layer 22 is provided only in the vicinity of the opening 41. As a result, the reliability of the semiconductor device 1 is further improved. In addition, when the outer edges of the first metal layer 21 and the second metal layer 22 coincide with each other in a plan view, the first metal layer 21 and the second metal layer 22 can be formed collectively by the same etching process. Therefore, the cost of the semiconductor device 1 can be reduced compared to an embodiment in which the first metal layer 21 and the second metal layer 22 are formed by separate etching processes.

[0040] In the example shown in FIG. 2, each of outer circumferential surfaces 21a, 22a is located near the boundary between active region 10a and edge termination region 10b.

[0041] The portion of source pad 20 covered by protective film 40 may have a layer configuration different from that of the portion exposed from opening 41 of source pad 20. For example, a layer made of a metal such as AlSi different from the metal constituting second metal layer 22 may be interposed between second metal layer 22 and protective film 40. In this case, the adhesion between second metal layer 22 and protective film 40 can be improved.

[0042] A protective film 40 is provided on such source pad 20 and gate pad 30. That is, the protective film 40 is provided on the second metal layer 22 and is in contact with the second metal layer 22. The protective film 40 is made of a resin material such as polyimide.

[0043] The protective film 40 has openings 41 and 42. The opening 41 penetrates the protective film 40 in the thickness direction, and exposes a portion of the source pad 20. This allows solder bonding to the source pad 20 with solder 60 through the opening 41. The opening 42 penetrates the protective film 40 in the thickness direction, and exposes a portion of the gate pad 30. This allows solder bonding to the gate pad 30 through the opening 42.

[0044] The solder 60 is not particularly limited, but may be, for example, a lead-free solder such as SnAg-based, SnAgCu-based, SnBi-based, SnZnBi-based, SnCu-based, SnAgBi-based, or SnZnAl-based.

[0045] Moreover, the opening 41 is located inside the outer peripheral surface 21a of the first metal layer 21 and the outer peripheral surface 22a of the second metal layer 22 in a plan view. Therefore, each of the first metal layer 21 and the second metal layer 22 is provided over an area that includes the opening 41 in a plan view. Therefore, the first metal layer 21 is covered by the second metal layer 22 in the opening 41. Moreover, the second metal layer 22 has a portion SD interposed between the first metal layer 21 and the protective film 40.

[0046] On the other hand, a drain pad 50 is provided as a drain electrode over the entire back surface of the semiconductor substrate 10. The drain pad 50 has a layered structure in which, for example, a Ti film, a nickel (Ni) film, and a gold (Au) film are layered in this order.

[0047] 1-2. First metal layer and second metal layer Fig. 3 is a partially enlarged cross-sectional view of the semiconductor device 1 according to the first embodiment. The first metal layer 21 and the second metal layer 22 will be described in detail below with reference to Fig. 3. Note that, although the source pad 20 will be described below as a representative example, the actions and effects of the first metal layer 21 and the second metal layer 22 are similarly exerted on the gate pad 30.

[0048] As shown in FIG. 3, the second metal layer 22 has a portion SD interposed between the first metal layer 21 and the protective film 40. Therefore, even if two protective films as described in Patent Document 1 are not provided, the first metal layer 21 can be reliably prevented from being exposed from the opening 41. Therefore, contact between the solder 60 and the first metal layer 21 due to solder connection is prevented, so that the occurrence of cracks due to thermal stress of the first metal layer 21 can be reduced. As a result, the reliability of the semiconductor device 1 can be improved. In addition, since there is no need to provide two protective films as described in Patent Document 1, the manufacturing process can be simplified compared to the device described in Patent Document 1. As a result, the cost of the semiconductor device 1 can also be reduced.

[0049] Here, the first metal layer 21 is made of, for example, aluminum (Al) alone, or an Al alloy such as aluminum silicon (AlSi), aluminum silicon copper (AlSiCu), or aluminum copper (AlCu).

[0050] In this way, when first metal layer 21 is made of Al or an Al alloy, optimizing the film formation conditions can improve the embeddability of first metal layer 21. Therefore, even if unevenness is formed on the front surface of semiconductor substrate 10 as described above, first metal layer 21 can be easily planarized.

[0051] The thickness T1 of the first metal layer 21 is not particularly limited, but is greater than the thicknesses of the interlayer insulating film 114, the insulating film 123, and the gate runner 130 described above.

[0052] On the other hand, the second metal layer 22 is made of a metal different from that of the first metal layer 21. Specifically, the second metal layer 22 is made of a metal having excellent wettability with the solder 60, for example, nickel (Ni) alone, a nickel alloy such as a nickel-phosphorus alloy or a nickel-tin-phosphorus alloy, or gold (Au) alone.

[0053] In this way, when the second metal layer 22 is composed of Ni, a Ni alloy or Au, it is possible to improve the adhesion between the first metal layer 21 and the second metal layer 22 while improving the wettability of the solder 60 to the solder joint.

[0054] The second metal layer 22 may be composed of a single layer or may be composed of a laminate of multiple layers. When the second metal layer 22 is composed of a laminate of multiple layers, it is preferable that the second metal layer 22 includes, for example, a Ni layer in contact with the first metal layer 21 and an Au layer provided on the Ni layer. In this case, the wettability of the solder 60 to the solder joint can be improved while improving the adhesion between the first metal layer 21 and the second metal layer 22.

[0055] In this embodiment, the thickness T2 of the second metal layer 22 is preferably within a range of 1 μm to 5 μm. In this case, it is possible to reduce the stress of the second metal layer 22 and prevent the solder 60 from reaching the first metal layer 21 due to solder erosion of the second metal layer 22, without providing the third metal layer 23 as in the second embodiment.

[0056] In contrast, if thickness T2 is too thin, depending on the constituent material of solder 60, there is a possibility that solder 60 may reach first metal layer 21 due to solder erosion of second metal layer 22. On the other hand, if thickness T2 is too thick, depending on the constituent material of second metal layer 22, the stress of second metal layer 22 may become excessive, resulting in many problems in manufacturing semiconductor device 1.

[0057] 4 is a partially enlarged cross-sectional view of a semiconductor device 1X according to a reference example. The semiconductor device 1X has the same structure as the semiconductor device 1 described above, except that the second metal layer 22 is omitted.

[0058] In the semiconductor device 1X, as shown in Fig. 4, the solder 1060 is provided on the first metal layer 1021. Therefore, the solder 1060, the first metal layer 1021, and the protective film 1040 contact each other at a position P near the opening 1041 of the protective film 1040. Due to thermal stress caused by the difference in linear expansion coefficients among the solder 1060, the first metal layer 1021, and the protective film 1040, cracks may occur in the first metal layer 1021 as shown by the arrows in Fig. 4. These cracks are likely to reach the interface between the semiconductor substrate 1010 and the first metal layer 1021, which reduces the reliability of the semiconductor device 1X.

[0059] In Patent Document 1, in order to prevent this cracking, a Ni layer is provided on the first metal layer 1021 within the opening 1041, and a protective film made of a resin such as polyimide is added on the protective film 1040 so as to cover the outer edge of this Ni layer.

[0060] However, in this configuration, because a part of protective film 1040 is interposed between first metal layer 1021 and the Ni layer, there is a risk that the Ni layer will peel off from the first metal layer due to thermal expansion of protective film 1040. In addition, because an additional protective film is required in addition to protective film 1040, the manufacturing process becomes complicated, which results in a problem of increased costs.

[0061] In contrast, in the above-mentioned semiconductor device 1, the first metal layer 21 can be reliably prevented from being exposed from the opening 41 without providing an additional protective film. Therefore, contact between the solder 60 and the first metal layer 21 due to solder connection is prevented, so that the occurrence of cracks due to thermal stress of the first metal layer 21 can be reduced. This can increase the power cycle resistance of the semiconductor device 1. In addition, since the protective film 40 is not interposed between the first metal layer 21 and the second metal layer 22, the problem of peeling of the second metal layer 22 as in Patent Document 1 does not occur, so that the reliability of the semiconductor device 1 can be improved. In addition, since there is no need to provide an additional protective film, the manufacturing process can be simplified compared to the device described in Patent Document 1. As a result, the cost of the semiconductor device 1 can also be reduced.

[0062] 1-3. Manufacturing method of semiconductor device 5 is a diagram showing a flow of a manufacturing method for the semiconductor device 1 according to the first embodiment. As shown in FIG. 5, the manufacturing method includes a substrate preparation step S10, a metal layer formation step S20, and a protective film formation step S30, in this order.

[0063] In the substrate preparation step S10, an interlayer insulating film 114, an insulating film 123, and a polysilicon gate runner 130 are formed on the semiconductor substrate 10. In the metal layer formation step S20, a first metal layer 21 and a second metal layer 22 are formed. In this embodiment, the metal layer formation step S20 includes a first film formation step S21, a second film formation step S22, and an etching step S23 in this order. In the first film formation step S21, a first metal film 210 for the first metal layer 21 is formed. In the second film formation step S22, a second metal film 220 for the second metal layer 22 is formed. In the etching step S23, the first metal layer 21 and the second metal layer 22 are formed by etching the first metal film 210 and the second metal film 220 at once. In the protective film formation step S30, a protective film 40 is formed.

[0064] Each step will now be described in detail.

[0065] Fig. 6 is a diagram for explaining the substrate preparation step S10. In the substrate preparation step S10, as shown in Fig. 6, a semiconductor substrate 10, an interlayer insulating film 114, an insulating film 123, and a polysilicon gate runner 130 are formed and prepared. The method for manufacturing the semiconductor substrate 10 is not particularly limited, and a known method can be used. In Fig. 6, the semiconductor substrate 10 includes a drain pad 50. Note that the drain pad 50 may be formed after the substrate preparation step S10.

[0066] Fig. 7 is a diagram for explaining the first film formation step S21 of the metal layer formation step S20. In the first film formation step S21, as shown in Fig. 7, a first metal film 210 is formed on the semiconductor substrate 10 by sputtering or the like. The first metal film 210 is a film that becomes the first metal layer 21 through an etching step S23 described below, and is made of, for example, Al or an Al alloy. In the example shown in Fig. 7, the first metal film 210 is formed over the entire front surface of the semiconductor substrate 10.

[0067] FIG. 8 is a diagram for explaining the second film-forming step S22 of the metal layer forming step S20. In the second film-forming step S22, as shown in FIG. 8, the second metal film 220 is formed on the first metal film 210 by sputtering. The second metal film 220 is a film that becomes the second metal layer 22 through the etching step S23 described later, and is made of, for example, Ni, Ni alloy, or Au. The second metal film 220 may also be formed by sputtering solder. The sputtering solder is formed by sputtering using a solder material as a target. In the example shown in FIG. 8, the second metal film 220 is formed over the entire area of ​​the first metal film 210.

[0068] 9 is a diagram for explaining the etching step S23 of the metal layer forming step S20. In the etching step S23, the first metal film 210 and the second metal film 220 are etched at the same time. As a result, the first metal layer 21 and the second metal layer 22 are formed as shown in FIG. The etching method in the etching step S23 is not particularly limited, and may be wet etching or dry etching. The etching step S23 is performed in a state where a photomask is appropriately formed on the second metal film 220.

[0069] In the etching step S23, it is preferable that the etching rate for the second metal film 220 is faster than the etching rate for the first metal film 210. As a result, as described above, each of the outer peripheral surface 21a and the outer peripheral surface 22a is inclined so as to widen in the Z2 direction. As a result, in the protective film forming step S30, the protective film 40 can be easily adhered to the first metal layer 21 and the second metal layer 22 without any gaps.

[0070] Fig. 10 is a diagram for explaining the protective film forming step S30. In the protective film forming step S30, a protective film 40 is formed as shown in Fig. 10. Specifically, in the protective film forming step S30, for example, a polyimide film is formed over the entire front surface of the semiconductor substrate 10, and then the polyimide film is selectively removed by photolithography and etching to form the protective film 40 having an opening 41.

[0071] Thereafter, although not shown, the semiconductor substrate 10 is diced into individual chips, and then solder 60 is formed on the second metal layer 22 in the opening 41 to solder the terminals and the like to the source pad 20. In this way, the semiconductor device 1 is obtained.

[0072] The above-described method for manufacturing the semiconductor device 1 allows the semiconductor device 1, which has excellent reliability, to be manufactured at low cost. In addition, in this embodiment, as described above, the metal layer formation step S20 includes the first film formation step S21, the second film formation step S22, and the etching step S23, and therefore the manufacturing cost can be reduced compared to an embodiment in which the first metal film 210 and the second metal film 220 are etched separately.

[0073] 2. Second embodiment A second embodiment of the present disclosure will be described below. In the following example, for elements having the same actions and functions as those in the above embodiment, the reference numerals used in the description of the above embodiment will be used and detailed descriptions of each will be omitted as appropriate.

[0074] 11 is a partially enlarged cross-sectional view of a semiconductor device 1A according to the second embodiment. The semiconductor device 1A has the same configuration as the semiconductor device 1A of the first embodiment, except that a third metal layer 23 is added.

[0075] The third metal layer 23 is provided on the second metal layer 22, and is located within the opening 41 in a plan view. The third metal layer 23 is, for example, made of nickel (Ni) alone, or made of a nickel alloy such as a nickel-phosphorus alloy or a nickel-tin-phosphorus alloy, or made of gold (Au) alone. Preferably, the third metal layer 23 is made of gold (Au). The third metal layer 23 is formed by plating. The material constituting the third metal layer 23 may be the same as or different from the material constituting the second metal layer 22.

[0076] In this way, the semiconductor device 1A includes the third metal layer 23, and thus it is possible to further improve the wettability of the solder 60 to the solder joints. Also, by providing the third metal layer 23, it is possible to reduce the thickness of the second metal layer 22.

[0077] In this embodiment, the thickness T2 of the second metal layer 22 is preferably within a range of 1 μm to 2 μm. In this case, even if the third metal layer 23 is provided, the overall stress of the second metal layer 22 and the third metal layer 23 can be reduced, and the solder 60 can be suitably prevented from reaching the first metal layer 21 due to solder erosion of the second metal layer 22 and the third metal layer 23.

[0078] Furthermore, the thickness T3 of the third metal layer 23 is preferably within a range of 0.1 μm to 1 μm. In this case, even if the third metal layer 23 is provided, the overall stress of the second metal layer 22 and the third metal layer 23 can be reduced, and the solder 60 can be suitably prevented from reaching the first metal layer 21 due to solder erosion of the second metal layer 22 and the third metal layer 23.

[0079] According to the second embodiment described above, the reliability of the semiconductor device 1A can be improved while reducing the cost.

[0080] 3. Third embodiment The third embodiment of the present disclosure will be described below. In the following exemplary embodiment, the elements having the same actions and functions as those in the above-described embodiment will be designated by the same reference numerals as those in the above-described embodiment, and detailed descriptions thereof will be omitted as appropriate.

[0081] 12 is a partially enlarged cross-sectional view of a semiconductor device 1B according to a third embodiment. The semiconductor device 1B has the same configuration as the semiconductor device 1 of the first embodiment, except that the second metal layer 22 is replaced with a second metal layer 22B.

[0082] The second metal layer 22B is configured similarly to the second metal layer 22 of the second embodiment, except that it has a through hole 22b. The through hole 22b is disposed at a position overlapping the protective film 40 in a plan view. Therefore, a part of the protective film 40 enters the through hole 22b, and the adhesion between the protective film 40 and the second metal layer 22 can be improved by an anchor effect. As a result, the reliability of the semiconductor device 1B is further improved.

[0083] As long as the through-hole 22b is covered with the protective film 40, the shape, position, size, area, and other aspects of the through-hole 22b are not particularly limited and may be arbitrarily determined.

[0084] According to the above third embodiment, the reliability of the semiconductor device 1B can be improved while reducing the cost.

[0085] 4. Variations The present disclosure is not limited to the above-described embodiment, and various modifications are possible. In addition, the embodiment and the modifications may be combined as appropriate.

[0086] 4-1. Variation 1 For example, the second embodiment and the third embodiment may be combined. That is, the second metal layer 22 of the second embodiment may be the second metal layer 22B of the third embodiment, and the semiconductor device 1B of the third embodiment may include the third metal layer 23 of the second embodiment.

[0087] 4-2. Variation 2 In the above embodiment, the source pad 20 and the gate pad 30 each have the first metal layer 21 and the second metal layer 22, but are not limited to this. When the semiconductor device has a diode, the pad of the diode may have the same configuration as the source pad 20 and the gate pad 30. [Explanation of symbols]

[0088] 1...semiconductor device, 1A...semiconductor device, 1B...semiconductor device, 1X...semiconductor device, 10...semiconductor substrate, 10a...active region, 10b...edge termination region, 11...n+ type starting substrate, 12...drift layer, 13...n-type region, 14...p-type well layer, 15...n-type source region, 16...trench, 20...source pad, 21...first metal layer, 21a...peripheral surface, 22...second metal layer, 22B...second metal layer, 22a...peripheral surface, 22b...through hole, 23...third metal layer, 30...gate pad, 40...protective film, 41...opening, 42...opening, 50...drain pad , 60...solder, 110...unit cell, 111...gate insulating film, 112...gate electrode, 113...p-type region, 114...interlayer insulating film, 120...voltage-resistant structure, 121...JTE structure, 122...FLR structure, 123...insulating film, 130...gate runner, 131...p-type region, 210...first metal film, 220...second metal film, P...position, SD...portion, S10...substrate preparation process, S20...metal layer formation process, S21...first film formation process, S22...second film formation process, S23...etching process, S30...protective film formation process, T1...thickness, T2...thickness, T3...thickness.

Claims

1. A semiconductor substrate; a first metal layer provided on the semiconductor substrate; a second metal layer provided on the first metal layer; a protective film having an opening and provided on the second metal layer; the protective film is in contact with the second metal layer and is made of a resin material; each of the first metal layer and the second metal layer is provided over an area including the opening in a plan view; the second metal layer has a portion interposed between the first metal layer and the protective film; Semiconductor device.

2. In a plan view, at least a part of an outer edge of the second metal layer coincides with an outer edge of the first metal layer. The semiconductor device according to claim 1 .

3. the second metal layer has a through hole at a position overlapping the protective film in a plan view; 3. The semiconductor device according to claim 1 or 2.

4. The second metal layer is composed of Ni, a Ni alloy, or Au. The semiconductor device according to claim 1 .

5. The thickness of the second metal layer is in the range of 1 μm to 5 μm. The semiconductor device according to claim 4.

6. a third metal layer provided on the second metal layer and positioned within the opening in a plan view; The third metal layer is composed of Ni, a Ni alloy, or Au. The semiconductor device according to claim 4.

7. The thickness of the second metal layer is in the range of 1 μm to 2 μm. The semiconductor device according to claim 6.

8. The thickness of the third metal layer is in the range of 1 μm to 3 μm.

8. The semiconductor device according to claim 6 or 7.

9. The first metal layer is composed of Al or an Al alloy.

6. The semiconductor device according to claim 4.

10. A semiconductor substrate; a first metal layer provided on the semiconductor substrate; a second metal layer provided on the first metal layer; a protective film having an opening and provided on the second metal layer, a metal layer forming step of forming the first metal layer and the second metal layer; A protective film forming step of forming the protective film, the protective film is in contact with the second metal layer and is made of a resin material; each of the first metal layer and the second metal layer is provided over an area including the opening in a plan view; the second metal layer has a portion interposed between the first metal layer and the protective film; A method for manufacturing a semiconductor device.

11. The metal layer forming step includes: a first film formation step of forming a first metal film on the semiconductor substrate; a second film formation step of forming a second metal film on the first metal film; and an etching step of forming the first metal layer and the second metal layer by simultaneously etching the first metal film and the second metal film. The method for manufacturing a semiconductor device according to claim 10.

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